From: Thierry Reding <thierry.reding@gmail.com>
To: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Prathamesh Shete <pshete@nvidia.com>,
Linus Walleij <linus.walleij@linaro.org>,
Jonathan Hunter <jonathanh@nvidia.com>,
linux-gpio <linux-gpio@vger.kernel.org>,
linux-tegra <linux-tegra@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>,
smangipudi@nvidia.com
Subject: Re: [PATCH v3 2/2] arm64: tegra: GPIO Interrupt entries
Date: Wed, 22 Sep 2021 15:25:26 +0200 [thread overview]
Message-ID: <YUsuxvLWgVZpjNpE@orome.fritz.box> (raw)
In-Reply-To: <CAMpxmJWyepTvUQEAVDB2b=uocFTq49=yRiCXrxnwyLMe7LY_1Q@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 6200 bytes --]
On Wed, Sep 22, 2021 at 11:29:21AM +0200, Bartosz Golaszewski wrote:
> On Tue, Sep 7, 2021 at 9:32 AM Prathamesh Shete <pshete@nvidia.com> wrote:
> >
> > From: pshete <pshete@nvidia.com>
> >
> > Tegra19x supports 8 entries for GPIO controller.
> > This change adds the required interrupt entires for all GPIO controllers.
> >
> > Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
> > ---
> > arch/arm64/boot/dts/nvidia/tegra194.dtsi | 49 +++++++++++++++++++++++-
> > 1 file changed, 47 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> > index b7d532841390..c681a79c44ec 100644
> > --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> > +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> > @@ -34,11 +34,53 @@
> > reg = <0x2200000 0x10000>,
> > <0x2210000 0x10000>;
> > interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
> > <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
> > <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
> > <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
> > <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
> > + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
> > #interrupt-cells = <2>;
> > interrupt-controller;
> > #gpio-cells = <2>;
> > @@ -1273,7 +1315,10 @@
> > reg-names = "security", "gpio";
> > reg = <0xc2f0000 0x1000>,
> > <0xc2f1000 0x1000>;
> > - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> > gpio-controller;
> > #gpio-cells = <2>;
> > interrupt-controller;
> > --
> > 2.17.1
> >
>
> Prathamesh: what are the changes between the three versions of this
> patch I have in my inbox? Please always include a brief list of
> updates when resending.
>
> Thierry: does this make sense to you?
Hi Bartosz,
the following patches from me that you applied earlier:
[PATCH 1/2] gpio: tegra186: Force one interrupt per bank
[PATCH 2/2] gpio: tegra186: Support multiple interrupts per bank
are replacements for patch 1 in this series, so that should no longer be
needed. Patch 2 of this series (the DT change) I plan to pick up into
the Tegra tree for v5.16.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
next prev parent reply other threads:[~2021-09-22 13:25 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-03 10:15 [PATCH v2 0/2] gpio: tegra: add multiple interrupt support Prathamesh Shete
2021-09-03 10:15 ` [PATCH v2 1/2] " Prathamesh Shete
2021-09-06 4:51 ` Thierry Reding
2021-09-07 7:23 ` Prathamesh Shete
2021-09-07 7:30 ` [PATCH v2 0/2] " Prathamesh Shete
2021-09-07 7:30 ` [PATCH v2 1/2] " Prathamesh Shete
2021-09-07 7:30 ` [PATCH v2 2/2] arm64: tegra: GPIO Interrupt entries Prathamesh Shete
2021-09-07 7:32 ` [PATCH v3 0/2] gpio: tegra: add multiple interrupt support Prathamesh Shete
2021-09-07 7:32 ` [PATCH v3 1/2] " Prathamesh Shete
2021-09-17 10:47 ` Thierry Reding
2021-09-07 7:32 ` [PATCH v3 2/2] arm64: tegra: GPIO Interrupt entries Prathamesh Shete
2021-09-22 9:29 ` Bartosz Golaszewski
2021-09-22 13:25 ` Thierry Reding [this message]
2021-09-24 14:37 ` Thierry Reding
2021-09-03 10:15 ` [PATCH v2 " Prathamesh Shete
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YUsuxvLWgVZpjNpE@orome.fritz.box \
--to=thierry.reding@gmail.com \
--cc=bgolaszewski@baylibre.com \
--cc=jonathanh@nvidia.com \
--cc=linus.walleij@linaro.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-tegra@vger.kernel.org \
--cc=pshete@nvidia.com \
--cc=smangipudi@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).