* [PATCH v2 0/6] UFS support on SM6350 & FP4 @ 2022-03-21 13:33 Luca Weiss 2022-03-21 13:33 ` [PATCH v2 4/6] pinctrl: qcom: sm6350: fix order of UFS & SDC pins Luca Weiss 0 siblings, 1 reply; 5+ messages in thread From: Luca Weiss @ 2022-03-21 13:33 UTC (permalink / raw) To: linux-arm-msm Cc: ~postmarketos/upstreaming, phone-devel, Luca Weiss, Alim Akhtar, Andy Gross, AngeloGioacchino Del Regno, Avri Altman, Bjorn Andersson, devicetree, Konrad Dybcio, Linus Walleij, linux-gpio, linux-kernel, linux-phy, linux-scsi, Vinod Koul This series adds support for UFS on SM6350 which is used for internal storage. Changes in v2: - see individual patches Luca Weiss (6): scsi: ufs: dt-bindings: Add SM6350 compatible string dt-bindings: phy: qcom,qmp: Add SM6350 UFS PHY bindings phy: qcom-qmp: Add SM6350 UFS PHY support pinctrl: qcom: sm6350: fix order of UFS & SDC pins arm64: dts: qcom: sm6350: Add UFS nodes arm64: dts: qcom: sm7225-fairphone-fp4: Enable UFS .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 + .../devicetree/bindings/ufs/qcom,ufs.yaml | 2 + arch/arm64/boot/dts/qcom/sm6350.dtsi | 77 +++++++++++++++++++ .../boot/dts/qcom/sm7225-fairphone-fp4.dts | 18 +++++ drivers/phy/qualcomm/phy-qcom-qmp.c | 3 + drivers/pinctrl/qcom/pinctrl-sm6350.c | 16 ++-- 6 files changed, 110 insertions(+), 8 deletions(-) -- 2.35.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 4/6] pinctrl: qcom: sm6350: fix order of UFS & SDC pins 2022-03-21 13:33 [PATCH v2 0/6] UFS support on SM6350 & FP4 Luca Weiss @ 2022-03-21 13:33 ` Luca Weiss 2022-03-21 14:15 ` Bjorn Andersson 2022-04-17 23:42 ` Linus Walleij 0 siblings, 2 replies; 5+ messages in thread From: Luca Weiss @ 2022-03-21 13:33 UTC (permalink / raw) To: linux-arm-msm Cc: ~postmarketos/upstreaming, phone-devel, Luca Weiss, Andy Gross, Bjorn Andersson, Linus Walleij, AngeloGioacchino Del Regno, Konrad Dybcio, linux-gpio, linux-kernel In other places the SDC and UFS pins have been swapped but this was missed in the PINCTRL_PIN definitions. Fix that. Fixes: 7d74b55afd27 ("pinctrl: qcom: Add SM6350 pinctrl driver") Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> --- Changes in v2: - nothing drivers/pinctrl/qcom/pinctrl-sm6350.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350.c b/drivers/pinctrl/qcom/pinctrl-sm6350.c index 4d37b817b232..a91a86628f2f 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6350.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6350.c @@ -264,14 +264,14 @@ static const struct pinctrl_pin_desc sm6350_pins[] = { PINCTRL_PIN(153, "GPIO_153"), PINCTRL_PIN(154, "GPIO_154"), PINCTRL_PIN(155, "GPIO_155"), - PINCTRL_PIN(156, "SDC1_RCLK"), - PINCTRL_PIN(157, "SDC1_CLK"), - PINCTRL_PIN(158, "SDC1_CMD"), - PINCTRL_PIN(159, "SDC1_DATA"), - PINCTRL_PIN(160, "SDC2_CLK"), - PINCTRL_PIN(161, "SDC2_CMD"), - PINCTRL_PIN(162, "SDC2_DATA"), - PINCTRL_PIN(163, "UFS_RESET"), + PINCTRL_PIN(156, "UFS_RESET"), + PINCTRL_PIN(157, "SDC1_RCLK"), + PINCTRL_PIN(158, "SDC1_CLK"), + PINCTRL_PIN(159, "SDC1_CMD"), + PINCTRL_PIN(160, "SDC1_DATA"), + PINCTRL_PIN(161, "SDC2_CLK"), + PINCTRL_PIN(162, "SDC2_CMD"), + PINCTRL_PIN(163, "SDC2_DATA"), }; #define DECLARE_MSM_GPIO_PINS(pin) \ -- 2.35.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 4/6] pinctrl: qcom: sm6350: fix order of UFS & SDC pins 2022-03-21 13:33 ` [PATCH v2 4/6] pinctrl: qcom: sm6350: fix order of UFS & SDC pins Luca Weiss @ 2022-03-21 14:15 ` Bjorn Andersson 2022-03-21 14:21 ` Luca Weiss 2022-04-17 23:42 ` Linus Walleij 1 sibling, 1 reply; 5+ messages in thread From: Bjorn Andersson @ 2022-03-21 14:15 UTC (permalink / raw) To: Luca Weiss Cc: linux-arm-msm, ~postmarketos/upstreaming, phone-devel, Andy Gross, Linus Walleij, AngeloGioacchino Del Regno, Konrad Dybcio, linux-gpio, linux-kernel On Mon 21 Mar 08:33 CDT 2022, Luca Weiss wrote: > In other places the SDC and UFS pins have been swapped but this was > missed in the PINCTRL_PIN definitions. Fix that. > > Fixes: 7d74b55afd27 ("pinctrl: qcom: Add SM6350 pinctrl driver") > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Your proposed change looks good, but when I look at 7d74b55afd27 it already has these entries in the correct order. Can you please confirm that this is still applicable. Or help me see what I am missing. Regards, Bjorn > --- > Changes in v2: > - nothing > > drivers/pinctrl/qcom/pinctrl-sm6350.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350.c b/drivers/pinctrl/qcom/pinctrl-sm6350.c > index 4d37b817b232..a91a86628f2f 100644 > --- a/drivers/pinctrl/qcom/pinctrl-sm6350.c > +++ b/drivers/pinctrl/qcom/pinctrl-sm6350.c > @@ -264,14 +264,14 @@ static const struct pinctrl_pin_desc sm6350_pins[] = { > PINCTRL_PIN(153, "GPIO_153"), > PINCTRL_PIN(154, "GPIO_154"), > PINCTRL_PIN(155, "GPIO_155"), > - PINCTRL_PIN(156, "SDC1_RCLK"), > - PINCTRL_PIN(157, "SDC1_CLK"), > - PINCTRL_PIN(158, "SDC1_CMD"), > - PINCTRL_PIN(159, "SDC1_DATA"), > - PINCTRL_PIN(160, "SDC2_CLK"), > - PINCTRL_PIN(161, "SDC2_CMD"), > - PINCTRL_PIN(162, "SDC2_DATA"), > - PINCTRL_PIN(163, "UFS_RESET"), > + PINCTRL_PIN(156, "UFS_RESET"), > + PINCTRL_PIN(157, "SDC1_RCLK"), > + PINCTRL_PIN(158, "SDC1_CLK"), > + PINCTRL_PIN(159, "SDC1_CMD"), > + PINCTRL_PIN(160, "SDC1_DATA"), > + PINCTRL_PIN(161, "SDC2_CLK"), > + PINCTRL_PIN(162, "SDC2_CMD"), > + PINCTRL_PIN(163, "SDC2_DATA"), > }; > > #define DECLARE_MSM_GPIO_PINS(pin) \ > -- > 2.35.1 > ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 4/6] pinctrl: qcom: sm6350: fix order of UFS & SDC pins 2022-03-21 14:15 ` Bjorn Andersson @ 2022-03-21 14:21 ` Luca Weiss 0 siblings, 0 replies; 5+ messages in thread From: Luca Weiss @ 2022-03-21 14:21 UTC (permalink / raw) To: Bjorn Andersson Cc: linux-arm-msm, ~postmarketos/upstreaming, phone-devel, Andy Gross, Linus Walleij, AngeloGioacchino Del Regno, Konrad Dybcio, linux-gpio, linux-kernel Hi Bjorn, On Mon Mar 21, 2022 at 3:15 PM CET, Bjorn Andersson wrote: > On Mon 21 Mar 08:33 CDT 2022, Luca Weiss wrote: > > > In other places the SDC and UFS pins have been swapped but this was > > missed in the PINCTRL_PIN definitions. Fix that. > > > > Fixes: 7d74b55afd27 ("pinctrl: qcom: Add SM6350 pinctrl driver") > > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> > > Your proposed change looks good, but when I look at 7d74b55afd27 it > already has these entries in the correct order. > > Can you please confirm that this is still applicable. Or help me see > what I am missing. There are 3 times where number and description should match. For this UFS pin on sm6350 only 2/3 match. 2x the number is 156, 1x it's 163 $ grep -i ufs_reset drivers/pinctrl/qcom/pinctrl-sm6350.c PINCTRL_PIN(163, "UFS_RESET"), static const unsigned int ufs_reset_pins[] = { 156 }; [156] = UFS_RESET(ufs_reset, 0xae000), Does that help? Regards Luca > > Regards, > Bjorn > > > --- > > Changes in v2: > > - nothing > > > > drivers/pinctrl/qcom/pinctrl-sm6350.c | 16 ++++++++-------- > > 1 file changed, 8 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/pinctrl/qcom/pinctrl-sm6350.c b/drivers/pinctrl/qcom/pinctrl-sm6350.c > > index 4d37b817b232..a91a86628f2f 100644 > > --- a/drivers/pinctrl/qcom/pinctrl-sm6350.c > > +++ b/drivers/pinctrl/qcom/pinctrl-sm6350.c > > @@ -264,14 +264,14 @@ static const struct pinctrl_pin_desc sm6350_pins[] = { > > PINCTRL_PIN(153, "GPIO_153"), > > PINCTRL_PIN(154, "GPIO_154"), > > PINCTRL_PIN(155, "GPIO_155"), > > - PINCTRL_PIN(156, "SDC1_RCLK"), > > - PINCTRL_PIN(157, "SDC1_CLK"), > > - PINCTRL_PIN(158, "SDC1_CMD"), > > - PINCTRL_PIN(159, "SDC1_DATA"), > > - PINCTRL_PIN(160, "SDC2_CLK"), > > - PINCTRL_PIN(161, "SDC2_CMD"), > > - PINCTRL_PIN(162, "SDC2_DATA"), > > - PINCTRL_PIN(163, "UFS_RESET"), > > + PINCTRL_PIN(156, "UFS_RESET"), > > + PINCTRL_PIN(157, "SDC1_RCLK"), > > + PINCTRL_PIN(158, "SDC1_CLK"), > > + PINCTRL_PIN(159, "SDC1_CMD"), > > + PINCTRL_PIN(160, "SDC1_DATA"), > > + PINCTRL_PIN(161, "SDC2_CLK"), > > + PINCTRL_PIN(162, "SDC2_CMD"), > > + PINCTRL_PIN(163, "SDC2_DATA"), > > }; > > > > #define DECLARE_MSM_GPIO_PINS(pin) \ > > -- > > 2.35.1 > > ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 4/6] pinctrl: qcom: sm6350: fix order of UFS & SDC pins 2022-03-21 13:33 ` [PATCH v2 4/6] pinctrl: qcom: sm6350: fix order of UFS & SDC pins Luca Weiss 2022-03-21 14:15 ` Bjorn Andersson @ 2022-04-17 23:42 ` Linus Walleij 1 sibling, 0 replies; 5+ messages in thread From: Linus Walleij @ 2022-04-17 23:42 UTC (permalink / raw) To: Luca Weiss Cc: linux-arm-msm, ~postmarketos/upstreaming, phone-devel, Andy Gross, Bjorn Andersson, AngeloGioacchino Del Regno, Konrad Dybcio, linux-gpio, linux-kernel On Mon, Mar 21, 2022 at 2:33 PM Luca Weiss <luca.weiss@fairphone.com> wrote: > In other places the SDC and UFS pins have been swapped but this was > missed in the PINCTRL_PIN definitions. Fix that. > > Fixes: 7d74b55afd27 ("pinctrl: qcom: Add SM6350 pinctrl driver") > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> > --- > Changes in v2: > - nothing Since no changes I assume it was OK I applied v1. Yours, Linus Walleij ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-04-17 23:43 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-03-21 13:33 [PATCH v2 0/6] UFS support on SM6350 & FP4 Luca Weiss 2022-03-21 13:33 ` [PATCH v2 4/6] pinctrl: qcom: sm6350: fix order of UFS & SDC pins Luca Weiss 2022-03-21 14:15 ` Bjorn Andersson 2022-03-21 14:21 ` Luca Weiss 2022-04-17 23:42 ` Linus Walleij
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