From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Linus Walleij <linus.walleij@linaro.org>,
linux-gpio@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v2] pinctrl: renesas: checker: Rework drive and bias pin iteration
Date: Fri, 15 Apr 2022 09:48:19 +0200 [thread overview]
Message-ID: <YlkjQ2+O0h8jDTqq@shikoro> (raw)
In-Reply-To: <1848e56e6496b8d5ed50fd6adc8ef2078b454ce4.1649944305.git.geert+renesas@glider.be>
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On Thu, Apr 14, 2022 at 03:57:36PM +0200, Geert Uytterhoeven wrote:
> The checker code to iterate over all drive strength and bias register
> description items is cumbersome, due to the repeated calculation of
> indices, and the use of hardcoded array sizes. The latter was done
> under the assumption they would never need to be changed, which turned
> out to be false.
>
> Increase readability by introducing helper macros to access drive
> strength and bias register description items.
> Increase maintainability by replacing hardcoded numbers by array sizes
> calculated at compile-time.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cool, this makes the code much more readable!
In general, I am fine with it, maybe one tiny addition to make it even
more readable?
> +#define drive_nfields ARRAY_SIZE(drive_regs->fields)
Let's have here:
#define drive_ofs(i) drive_regs[(i) / drive_nfields]
> +#define drive_reg(i) drive_regs[(i) / drive_nfields].reg
and here
#define drive_reg(i) drive_ofs(i).reg
> +#define drive_bit(i) ((i) % drive_nfields)
> +#define drive_field(i) drive_regs[(i) / drive_nfields].fields[drive_bit(i)]
and here
drive_field(i) drv_ofs(i).fields[drive_bit(i)]
?
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prev parent reply other threads:[~2022-04-15 7:48 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-14 13:57 [PATCH v2] pinctrl: renesas: checker: Rework drive and bias pin iteration Geert Uytterhoeven
2022-04-15 7:48 ` Wolfram Sang [this message]
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