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From: "J. Neuschäfer" <j.ne@posteo.net>
To: Rob Herring <robh@kernel.org>
Cc: "J. Neuschäfer" <j.ne@posteo.net>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Bartosz Golaszewski" <brgl@bgdev.pl>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Maxime Ripard" <mripard@kernel.org>,
	linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/4] dt-bindings: gpio: fairchild,74hc595: Add latch-gpios property
Date: Thu, 19 Dec 2024 12:44:42 +0000	[thread overview]
Message-ID: <Z2QVOk2YiIJPMhIl@probook> (raw)
In-Reply-To: <20241217152522.GA1813602-robh@kernel.org>

On Tue, Dec 17, 2024 at 09:25:22AM -0600, Rob Herring wrote:
> On Fri, Dec 13, 2024 at 06:32:48PM +0100, J. Neuschäfer wrote:
> > The Fairchild MM74HC595 and other compatible parts have a latch clock
> > input (also known as storage register clock input), which must be
> > clocked once in order to apply any value that was serially shifted in.
> 
> That sounds like all the existing parts have the signal and it is 
> required to operate? Or just needed to write settings, but not read GPIO 
> input state for example?

These parts are output-only (so, "GPO"s, arguably).

The situation with the latch signal is weirder, as I found out in the
meantime: These parts don't have a chip-select built in, but the
rising-edge triggered latch clock can be reinterpreted as an active-low
chip-select, because that would also rise after the appropriate number
of bits has been shifted through the SPI bus.

                     _   _       _   _
 shift clock    ____| |_| |_..._| |_| |_________

 latch clock                           * trigger
                ___                     ________
 chip select#      |___________________|



So, I now think that no additional signal and no binding change is
actually needed, just perhaps an explanatory comment.


> 
> If the new parts are usable without latch, then they should have a 
> fallback compatible. If they aren't usable, then it should be 1 binding 
> patch.

AFAICT, the new part (onnn,74hc595a) behaves the same at the existing
(fairchild,74hc595 and nxp,74lvc594), with regards to the latch signal,
so my two binding patches are independent of other.
In other words, this one can be dropped, but the other still stands.



Best regards
 -- jn

  reply	other threads:[~2024-12-19 12:44 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-13 17:32 [PATCH 0/4] gpio: 74HC595 / 74x164 shift register improvements J. Neuschäfer via B4 Relay
2024-12-13 17:32 ` [PATCH 1/4] dt-bindings: gpio: fairchild,74hc595: Add On Semi MC74HC595A compat J. Neuschäfer via B4 Relay
2024-12-20 12:53   ` Linus Walleij
2024-12-13 17:32 ` [PATCH 2/4] dt-bindings: gpio: fairchild,74hc595: Add latch-gpios property J. Neuschäfer via B4 Relay
2024-12-17 15:25   ` Rob Herring
2024-12-19 12:44     ` J. Neuschäfer [this message]
2024-12-13 17:32 ` [PATCH 3/4] gpio: 74x164: Add On Semi MC74HC595A compat J. Neuschäfer via B4 Relay
2024-12-20 12:54   ` Linus Walleij
2024-12-13 17:32 ` [PATCH 4/4] gpio: 74x164: Add latch GPIO support J. Neuschäfer via B4 Relay
2024-12-16 18:20   ` J. Neuschäfer
2024-12-22  8:58   ` Linus Walleij
2024-12-24  7:26     ` J. Neuschäfer

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