From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 199F7C6FD1B for ; Mon, 6 Mar 2023 23:36:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229483AbjCFXgG (ORCPT ); Mon, 6 Mar 2023 18:36:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229534AbjCFXgF (ORCPT ); Mon, 6 Mar 2023 18:36:05 -0500 Received: from fgw21-7.mail.saunalahti.fi (fgw21-7.mail.saunalahti.fi [62.142.5.82]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A96D34DE0E for ; Mon, 6 Mar 2023 15:36:02 -0800 (PST) Received: from localhost (88-113-24-128.elisa-laajakaista.fi [88.113.24.128]) by fgw21.mail.saunalahti.fi (Halon) with ESMTP id a5ff45a6-bc77-11ed-abf4-005056bdd08f; Tue, 07 Mar 2023 01:36:00 +0200 (EET) From: andy.shevchenko@gmail.com Date: Tue, 7 Mar 2023 01:35:58 +0200 To: Biju Das Cc: Linus Walleij , Philipp Zabel , Geert Uytterhoeven , Thierry Reding , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Chris Paterson , Prabhakar Mahadev Lad Subject: Re: [PATCH v6 06/13] drivers: pinctrl: renesas: Add RZ/G2L POEG driver support Message-ID: References: <20230306090014.128732-1-biju.das.jz@bp.renesas.com> <20230306090014.128732-7-biju.das.jz@bp.renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230306090014.128732-7-biju.das.jz@bp.renesas.com> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Mon, Mar 06, 2023 at 09:00:07AM +0000, Biju Das kirjoitti: > The output pins of the RZ/G2L general PWM timer (GPT) can be disabled > by using the port output enabling function for the GPT (POEG). > > Add basic support using s/w control through generic pincontrol sysfs to > enable/disable output from GPT by registering with RZ/G2L pincontrol > driver. You have wrong Subject prefix. ... > +static void rzg2l_poeg_write(struct rzg2l_poeg_chip *chip, u32 data) > +{ > + iowrite32(data, chip->mmio); > +} > + > +static u32 rzg2l_poeg_read(struct rzg2l_poeg_chip *chip) > +{ > + return ioread32(chip->mmio); > +} Why not regmap MMIO? ... > +static struct platform_driver rzg2l_poeg_driver = { > + .driver = { > + .name = "rzg2l-poeg", > + .of_match_table = of_match_ptr(rzg2l_poeg_of_table), Why do you need of_match_ptr()? > + }, > + .probe = rzg2l_poeg_probe, > + .remove = rzg2l_poeg_remove, > +}; -- With Best Regards, Andy Shevchenko