From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 836A5EB64DD for ; Thu, 20 Jul 2023 20:10:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230456AbjGTUKe (ORCPT ); Thu, 20 Jul 2023 16:10:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229663AbjGTUKd (ORCPT ); Thu, 20 Jul 2023 16:10:33 -0400 Received: from fgw23-7.mail.saunalahti.fi (fgw23-7.mail.saunalahti.fi [62.142.5.84]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2905B2706 for ; Thu, 20 Jul 2023 13:10:29 -0700 (PDT) Received: from localhost (88-113-24-87.elisa-laajakaista.fi [88.113.24.87]) by fgw23.mail.saunalahti.fi (Halon) with ESMTP id 73e5902b-2739-11ee-b972-005056bdfda7; Thu, 20 Jul 2023 23:10:20 +0300 (EEST) From: andy.shevchenko@gmail.com Date: Thu, 20 Jul 2023 23:10:20 +0300 To: Naresh Solanki Cc: Patrick Rudolph , Linus Walleij , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 2/2] pinctrl: cy8c95x0: Add reset support Message-ID: References: <20230714081902.2621771-1-Naresh.Solanki@9elements.com> <20230714081902.2621771-2-Naresh.Solanki@9elements.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230714081902.2621771-2-Naresh.Solanki@9elements.com> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Fri, Jul 14, 2023 at 10:19:01AM +0200, Naresh Solanki kirjoitti: > From: Patrick Rudolph > > This patch adds support for an optional "reset" GPIO pin in the cy8c95x0 Find "This patch" in the Submitting Patches documentation and modify this accordingly. > pinctrl driver. On probe, the reset pin is pulled low to bring chip out > of reset. The reset pin has an internal pull-down and can be left > floating if not required. > > The datasheet doesn't mention any timing related to the reset pin. > > Based on empirical tests, it was found that the chip requires a > delay of 250 milliseconds before accepting I2C transfers after driving > the reset pin low. Therefore, a delay of 250ms is added before > proceeding with I2C transfers. ... > + /* bring the chip out of reset if reset pin is provided */ > + chip->gpio_reset = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH); &client->dev > + if (IS_ERR(chip->gpio_reset)) { > + ret = dev_err_probe(chip->dev, PTR_ERR(chip->gpio_reset), chip->dev Why inconsistent? > + "Failed to get GPIO 'reset'\n"); > + goto err_exit; I haven't looked at the context, but this seems like a smoke, we usually don't have such in devm-enabled drivers. > + } else if (chip->gpio_reset) { > + usleep_range(1000, 2000); > + gpiod_set_value_cansleep(chip->gpio_reset, 0); > + usleep_range(250000, 300000); This is incorrect use of usleep_range(). Please, read documentation Documentation/timers/timers-howto.rst on the topic. The fix can be switching to fsleep() in both branches. > + gpiod_set_consumer_name(chip->gpio_reset, "CY8C95X0 RESET"); This can be done uncoditionally before toggling the reset. > + } ... This change wasn't Cc'ed to me, however I was contributing a lot into this driver. I would recommend to use my "smart" script [1] to send patches. It has some heuristics which works well in 98% of the cases for me. [1]: https://github.com/andy-shev/home-bin-tools/blob/master/ge2maintainer.sh -- With Best Regards, Andy Shevchenko