* [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver
@ 2023-09-08 5:51 Linhua Xu
2023-09-08 5:51 ` [PATCH V2 1/6] pinctrl: sprd: Modify the probe function parameters Linhua Xu
` (6 more replies)
0 siblings, 7 replies; 22+ messages in thread
From: Linhua Xu @ 2023-09-08 5:51 UTC (permalink / raw)
To: Linus Walleij
Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Linhua Xu, Zhirong Qiu, Xiongpeng Wu
From: Linhua Xu <Linhua.Xu@unisoc.com>
Recently, some bugs have been discovered during use, and patch2 and patch3
are bug fixes. Also, this patchset add new features: patch1 is for
compatibility with more platforms, patch4 add pinctrl support for UMS512,
patch5 Increase the range of register values, patch6 add pinctrl support
for UMS9621.
change in V2
-Add comment for common_pin_offset and misc_pin_offset
-Remove cast commits
-Modify the mask definition into GENMASK form
-Delete the three-speed configuration that modifies the original parameters
-Add 1.8K resistor configuration
-Delete depends on OF
-Modify the format of sprd_pinctrl_of_match
-Drop trailing comma in the terminator entry
-Add bits.h header file
-Add kernel.h header file
Linhua Xu (6):
pinctrl: sprd: Modify the probe function parameters
pinctrl: sprd: Fix the incorrect mask and shift definition
pinctrl: sprd: Modify pull-up parameters
pinctrl: sprd: Add pinctrl support for UMS512
pinctrl: sprd: Increase the range of register values
pinctrl: sprd: Add pinctrl support for UMS9621
drivers/pinctrl/sprd/Kconfig | 22 +
drivers/pinctrl/sprd/Makefile | 2 +
drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c | 7 +-
drivers/pinctrl/sprd/pinctrl-sprd-ums512.c | 878 +++++++++++++++
drivers/pinctrl/sprd/pinctrl-sprd-ums9621.c | 1117 +++++++++++++++++++
drivers/pinctrl/sprd/pinctrl-sprd.c | 49 +-
drivers/pinctrl/sprd/pinctrl-sprd.h | 33 +-
7 files changed, 2071 insertions(+), 37 deletions(-)
create mode 100644 drivers/pinctrl/sprd/pinctrl-sprd-ums512.c
create mode 100644 drivers/pinctrl/sprd/pinctrl-sprd-ums9621.c
--
2.17.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH V2 1/6] pinctrl: sprd: Modify the probe function parameters
2023-09-08 5:51 [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linhua Xu
@ 2023-09-08 5:51 ` Linhua Xu
2023-09-11 9:46 ` Andy Shevchenko
2023-09-12 8:13 ` Baolin Wang
2023-09-08 5:51 ` [PATCH V2 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition Linhua Xu
` (5 subsequent siblings)
6 siblings, 2 replies; 22+ messages in thread
From: Linhua Xu @ 2023-09-08 5:51 UTC (permalink / raw)
To: Linus Walleij
Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Linhua Xu, Zhirong Qiu, Xiongpeng Wu
From: Linhua Xu <Linhua.Xu@unisoc.com>
For UNISOC pin controller, the offset values of the common register and
misc register will be different. Thus put these in the probe function
parameters.
Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
---
drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c | 7 +++++-
drivers/pinctrl/sprd/pinctrl-sprd.c | 27 +++++++++++++---------
drivers/pinctrl/sprd/pinctrl-sprd.h | 3 ++-
3 files changed, 24 insertions(+), 13 deletions(-)
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c
index d14f382f2392..05158c71ad77 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c
+++ b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c
@@ -10,6 +10,9 @@
#include "pinctrl-sprd.h"
+#define PINCTRL_REG_OFFSET 0x20
+#define PINCTRL_REG_MISC_OFFSET 0x4020
+
enum sprd_sc9860_pins {
/* pin global control register 0 */
SC9860_VIO28_0_IRTE = SPRD_PIN_INFO(0, GLOBAL_CTRL_PIN, 11, 1, 0),
@@ -926,7 +929,9 @@ static struct sprd_pins_info sprd_sc9860_pins_info[] = {
static int sprd_pinctrl_probe(struct platform_device *pdev)
{
return sprd_pinctrl_core_probe(pdev, sprd_sc9860_pins_info,
- ARRAY_SIZE(sprd_sc9860_pins_info));
+ ARRAY_SIZE(sprd_sc9860_pins_info),
+ PINCTRL_REG_OFFSET,
+ PINCTRL_REG_MISC_OFFSET);
}
static const struct of_device_id sprd_pinctrl_of_match[] = {
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c
index ca9659f4e4b1..25fb9ce9ad78 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.c
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.c
@@ -30,8 +30,6 @@
#include "pinctrl-sprd.h"
#define PINCTRL_BIT_MASK(width) (~(~0UL << (width)))
-#define PINCTRL_REG_OFFSET 0x20
-#define PINCTRL_REG_MISC_OFFSET 0x4020
#define PINCTRL_REG_LEN 0x4
#define PIN_FUNC_MASK (BIT(4) | BIT(5))
@@ -148,12 +146,16 @@ struct sprd_pinctrl_soc_info {
* @pctl: pointer to the pinctrl handle
* @base: base address of the controller
* @info: pointer to SoC's pins description information
+ * @common_pin_offset: offset value of common register
+ * @misc_pin_offset: offset value of misc register
*/
struct sprd_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
struct sprd_pinctrl_soc_info *info;
+ u32 common_pin_offset;
+ u32 misc_pin_offset;
};
#define SPRD_PIN_CONFIG_CONTROL (PIN_CONFIG_END + 1)
@@ -1023,12 +1025,12 @@ static int sprd_pinctrl_add_pins(struct sprd_pinctrl *sprd_pctl,
ctrl_pin++;
} else if (pin->type == COMMON_PIN) {
pin->reg = (unsigned long)sprd_pctl->base +
- PINCTRL_REG_OFFSET + PINCTRL_REG_LEN *
+ sprd_pctl->common_pin_offset + PINCTRL_REG_LEN *
(i - ctrl_pin);
com_pin++;
} else if (pin->type == MISC_PIN) {
pin->reg = (unsigned long)sprd_pctl->base +
- PINCTRL_REG_MISC_OFFSET + PINCTRL_REG_LEN *
+ sprd_pctl->misc_pin_offset + PINCTRL_REG_LEN *
(i - ctrl_pin - com_pin);
}
}
@@ -1045,7 +1047,9 @@ static int sprd_pinctrl_add_pins(struct sprd_pinctrl *sprd_pctl,
int sprd_pinctrl_core_probe(struct platform_device *pdev,
struct sprd_pins_info *sprd_soc_pin_info,
- int pins_cnt)
+ int pins_cnt,
+ u32 common_pin_offset,
+ u32 misc_pin_offset)
{
struct sprd_pinctrl *sprd_pctl;
struct sprd_pinctrl_soc_info *pinctrl_info;
@@ -1069,6 +1073,8 @@ int sprd_pinctrl_core_probe(struct platform_device *pdev,
sprd_pctl->info = pinctrl_info;
sprd_pctl->dev = &pdev->dev;
+ sprd_pctl->common_pin_offset = common_pin_offset;
+ sprd_pctl->misc_pin_offset = misc_pin_offset;
platform_set_drvdata(pdev, sprd_pctl);
ret = sprd_pinctrl_add_pins(sprd_pctl, sprd_soc_pin_info, pins_cnt);
@@ -1077,12 +1083,6 @@ int sprd_pinctrl_core_probe(struct platform_device *pdev,
return ret;
}
- ret = sprd_pinctrl_parse_dt(sprd_pctl);
- if (ret) {
- dev_err(&pdev->dev, "fail to parse dt properties\n");
- return ret;
- }
-
pin_desc = devm_kcalloc(&pdev->dev,
pinctrl_info->npins,
sizeof(struct pinctrl_pin_desc),
@@ -1100,6 +1100,11 @@ int sprd_pinctrl_core_probe(struct platform_device *pdev,
sprd_pinctrl_desc.name = dev_name(&pdev->dev);
sprd_pinctrl_desc.npins = pinctrl_info->npins;
+ ret = sprd_pinctrl_parse_dt(sprd_pctl);
+ if (ret) {
+ dev_err(&pdev->dev, "fail to parse dt properties\n");
+ return ret;
+ }
sprd_pctl->pctl = pinctrl_register(&sprd_pinctrl_desc,
&pdev->dev, (void *)sprd_pctl);
if (IS_ERR(sprd_pctl->pctl)) {
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.h b/drivers/pinctrl/sprd/pinctrl-sprd.h
index 69544a3cd635..a696f81ce663 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.h
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.h
@@ -52,7 +52,8 @@ struct sprd_pins_info {
int sprd_pinctrl_core_probe(struct platform_device *pdev,
struct sprd_pins_info *sprd_soc_pin_info,
- int pins_cnt);
+ int pins_cnt, u32 common_pin_offset,
+ u32 misc_pin_offset);
int sprd_pinctrl_remove(struct platform_device *pdev);
void sprd_pinctrl_shutdown(struct platform_device *pdev);
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V2 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition
2023-09-08 5:51 [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linhua Xu
2023-09-08 5:51 ` [PATCH V2 1/6] pinctrl: sprd: Modify the probe function parameters Linhua Xu
@ 2023-09-08 5:51 ` Linhua Xu
2023-09-11 9:50 ` Andy Shevchenko
` (2 more replies)
2023-09-08 5:51 ` [PATCH V2 3/6] pinctrl: sprd: Modify pull-up parameters Linhua Xu
` (4 subsequent siblings)
6 siblings, 3 replies; 22+ messages in thread
From: Linhua Xu @ 2023-09-08 5:51 UTC (permalink / raw)
To: Linus Walleij
Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Linhua Xu, Zhirong Qiu, Xiongpeng Wu
From: Linhua Xu <Linhua.Xu@unisoc.com>
Pull-up and pull-down are mutually exclusive. When setting one of them,
the bit of the other needs to be clear. Now, there are cases where pull-up
and pull-down are set at the same time in the code, thus fix them.
Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
---
drivers/pinctrl/sprd/pinctrl-sprd.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c
index 25fb9ce9ad78..5b9126b2cde2 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.c
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.c
@@ -58,21 +58,21 @@
#define DRIVE_STRENGTH_SHIFT 19
#define SLEEP_PULL_DOWN BIT(2)
-#define SLEEP_PULL_DOWN_MASK 0x1
+#define SLEEP_PULL_DOWN_MASK GENMASK(1, 0)
#define SLEEP_PULL_DOWN_SHIFT 2
#define PULL_DOWN BIT(6)
-#define PULL_DOWN_MASK 0x1
+#define PULL_DOWN_MASK (GENMASK(1, 0) | BIT(6))
#define PULL_DOWN_SHIFT 6
#define SLEEP_PULL_UP BIT(3)
-#define SLEEP_PULL_UP_MASK 0x1
-#define SLEEP_PULL_UP_SHIFT 3
+#define SLEEP_PULL_UP_MASK GENMASK(1, 0)
+#define SLEEP_PULL_UP_SHIFT 2
#define PULL_UP_4_7K (BIT(12) | BIT(7))
#define PULL_UP_20K BIT(7)
-#define PULL_UP_MASK 0x21
-#define PULL_UP_SHIFT 7
+#define PULL_UP_MASK (GENMASK(1, 0) | BIT(6))
+#define PULL_UP_SHIFT 6
#define INPUT_SCHMITT BIT(11)
#define INPUT_SCHMITT_MASK 0x1
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V2 3/6] pinctrl: sprd: Modify pull-up parameters
2023-09-08 5:51 [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linhua Xu
2023-09-08 5:51 ` [PATCH V2 1/6] pinctrl: sprd: Modify the probe function parameters Linhua Xu
2023-09-08 5:51 ` [PATCH V2 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition Linhua Xu
@ 2023-09-08 5:51 ` Linhua Xu
2023-09-11 9:51 ` Andy Shevchenko
2023-09-12 8:22 ` Baolin Wang
2023-09-08 5:51 ` [PATCH V2 4/6] pinctrl: sprd: Add pinctrl support for UMS512 Linhua Xu
` (3 subsequent siblings)
6 siblings, 2 replies; 22+ messages in thread
From: Linhua Xu @ 2023-09-08 5:51 UTC (permalink / raw)
To: Linus Walleij
Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Linhua Xu, Zhirong Qiu, Xiongpeng Wu
From: Linhua Xu <Linhua.Xu@unisoc.com>
For UNISOC pin controller, there are three different configurations of
pull-up drive current. Modify the 20K pull-up resistor configuration and
add the 1.8K pull-up resistor configuration.
Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
---
drivers/pinctrl/sprd/pinctrl-sprd.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c
index 5b9126b2cde2..6c75e6b8d2ca 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.c
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.c
@@ -69,7 +69,8 @@
#define SLEEP_PULL_UP_MASK GENMASK(1, 0)
#define SLEEP_PULL_UP_SHIFT 2
-#define PULL_UP_4_7K (BIT(12) | BIT(7))
+#define PULL_UP_1_8K (BIT(12) | BIT(7))
+#define PULL_UP_4_7K BIT(12)
#define PULL_UP_20K BIT(7)
#define PULL_UP_MASK (GENMASK(1, 0) | BIT(6))
#define PULL_UP_SHIFT 6
@@ -499,7 +500,7 @@ static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id,
break;
case PIN_CONFIG_BIAS_DISABLE:
if ((reg & (SLEEP_PULL_DOWN | SLEEP_PULL_UP)) ||
- (reg & (PULL_DOWN | PULL_UP_4_7K | PULL_UP_20K)))
+ (reg & (PULL_DOWN | PULL_UP_1_8K)))
return -EINVAL;
arg = 1;
@@ -701,6 +702,8 @@ static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id,
val |= PULL_UP_20K;
else if (arg == 4700)
val |= PULL_UP_4_7K;
+ else if (arg == 1800)
+ val |= PULL_UP_1_8K;
mask = PULL_UP_MASK;
shift = PULL_UP_SHIFT;
@@ -712,8 +715,7 @@ static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id,
mask = SLEEP_PULL_DOWN | SLEEP_PULL_UP;
} else {
val = shift = 0;
- mask = PULL_DOWN | PULL_UP_20K |
- PULL_UP_4_7K;
+ mask = PULL_DOWN | PULL_UP_1_8K;
}
break;
case PIN_CONFIG_SLEEP_HARDWARE_STATE:
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V2 4/6] pinctrl: sprd: Add pinctrl support for UMS512
2023-09-08 5:51 [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linhua Xu
` (2 preceding siblings ...)
2023-09-08 5:51 ` [PATCH V2 3/6] pinctrl: sprd: Modify pull-up parameters Linhua Xu
@ 2023-09-08 5:51 ` Linhua Xu
2023-09-09 1:56 ` kernel test robot
2023-09-11 9:53 ` Andy Shevchenko
2023-09-08 5:51 ` [PATCH V2 5/6] pinctrl: sprd: Increase the range of register values Linhua Xu
` (2 subsequent siblings)
6 siblings, 2 replies; 22+ messages in thread
From: Linhua Xu @ 2023-09-08 5:51 UTC (permalink / raw)
To: Linus Walleij
Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Linhua Xu, Zhirong Qiu, Xiongpeng Wu
From: Linhua Xu <Linhua.Xu@unisoc.com>
Add the pin control driver for UNISOC UMS512 platform.
Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
---
drivers/pinctrl/sprd/Kconfig | 11 +
drivers/pinctrl/sprd/Makefile | 1 +
drivers/pinctrl/sprd/pinctrl-sprd-ums512.c | 878 +++++++++++++++++++++
3 files changed, 890 insertions(+)
create mode 100644 drivers/pinctrl/sprd/pinctrl-sprd-ums512.c
diff --git a/drivers/pinctrl/sprd/Kconfig b/drivers/pinctrl/sprd/Kconfig
index eef35d01b770..a2a653c63137 100644
--- a/drivers/pinctrl/sprd/Kconfig
+++ b/drivers/pinctrl/sprd/Kconfig
@@ -19,3 +19,14 @@ config PINCTRL_SPRD_SC9860
select PINCTRL_SPRD
help
Say Y here to enable Spreadtrum SC9860 pinctrl driver
+
+config PINCTRL_SPRD_UMS512
+ tristate "Spreadtrum ums512 pinctrl driver"
+ depends on ARCH_SPRD || COMPILE_TEST
+ select PINCTRL_SPRD
+ help
+ Say Y here to enable Spreadtrum ums512 pinctrl driver
+ Support pin function switching
+ Support pin drive capability configuration
+ Support pin pull-up and pull-down configuration
+ Support pin pull-up and pull-down configuration during sleep
diff --git a/drivers/pinctrl/sprd/Makefile b/drivers/pinctrl/sprd/Makefile
index 3d4989057739..e3509c2515c9 100644
--- a/drivers/pinctrl/sprd/Makefile
+++ b/drivers/pinctrl/sprd/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_PINCTRL_SPRD) += pinctrl-sprd.o
obj-$(CONFIG_PINCTRL_SPRD_SC9860) += pinctrl-sprd-sc9860.o
+obj-$(CONFIG_PINCTRL_SPRD_UMS512) += pinctrl-sprd-ums512.o
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd-ums512.c b/drivers/pinctrl/sprd/pinctrl-sprd-ums512.c
new file mode 100644
index 000000000000..58ca0eb9d33e
--- /dev/null
+++ b/drivers/pinctrl/sprd/pinctrl-sprd-ums512.c
@@ -0,0 +1,878 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Unisoc ums512 pinctrl driver
+ *
+ * Copyright (C) 2020 Unisoc, Inc.
+ * Author: linhua xu <linhua.xu@unisoc.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-sprd.h"
+
+#define PINCTRL_REG_OFFSET 0x34
+#define PINCTRL_REG_MISC_OFFSET 0x434
+
+enum sprd_ums512_pins {
+ /* UART_MATRIX_MTX_CFG */
+ UMS512_UART_INF6_SYS_SEL = SPRD_PIN_INFO(0, GLOBAL_CTRL_PIN, 28, 4, 1),
+ UMS512_UART_INF5_SYS_SEL = SPRD_PIN_INFO(1, GLOBAL_CTRL_PIN, 24, 4, 1),
+ UMS512_UART_INF4_SYS_SEL = SPRD_PIN_INFO(2, GLOBAL_CTRL_PIN, 20, 4, 1),
+ UMS512_UART_INF3_SYS_SEL = SPRD_PIN_INFO(3, GLOBAL_CTRL_PIN, 16, 4, 1),
+ UMS512_UART_INF2_INF3_LOOP = SPRD_PIN_INFO(4, GLOBAL_CTRL_PIN, 15, 1, 1),
+ UMS512_UART_INF2_INF4_LOOP = SPRD_PIN_INFO(5, GLOBAL_CTRL_PIN, 14, 1, 1),
+ UMS512_UART_INF2_SYS_SEL = SPRD_PIN_INFO(6, GLOBAL_CTRL_PIN, 10, 4, 1),
+ UMS512_UART_INF1_INF4_LOOP = SPRD_PIN_INFO(7, GLOBAL_CTRL_PIN, 9, 1, 1),
+ UMS512_UART_INF1_INF3_LOOP = SPRD_PIN_INFO(8, GLOBAL_CTRL_PIN, 8, 1, 1),
+ UMS512_UART_INF1_SYS_SEL = SPRD_PIN_INFO(9, GLOBAL_CTRL_PIN, 4, 4, 1),
+ UMS512_UART_INF0_SYS_SEL = SPRD_PIN_INFO(10, GLOBAL_CTRL_PIN, 0, 4, 1),
+
+ /* UART_MATRIX_MTX_CFG1 */
+ UMS512_UART_INF9_SYS_SEL = SPRD_PIN_INFO(11, GLOBAL_CTRL_PIN, 9, 4, 2),
+ UMS512_UART_INF8_SYS_SEL = SPRD_PIN_INFO(12, GLOBAL_CTRL_PIN, 5, 4, 2),
+ UMS512_UART_INF7_INF8_LOOP = SPRD_PIN_INFO(13, GLOBAL_CTRL_PIN, 4, 1, 2),
+ UMS512_UART_INF7_SYS_SEL = SPRD_PIN_INFO(14, GLOBAL_CTRL_PIN, 0, 4, 2),
+
+ /* IIS_MATRIX_MTX_CFG */
+ UMS512_IIS_INF4_INF3_LOOP = SPRD_PIN_INFO(15, GLOBAL_CTRL_PIN, 23, 1, 3),
+ UMS512_IIS_INF4_SYS_SEL = SPRD_PIN_INFO(16, GLOBAL_CTRL_PIN, 19, 4, 3),
+ UMS512_IIS_INF3_SYS_SEL = SPRD_PIN_INFO(17, GLOBAL_CTRL_PIN, 15, 4, 3),
+ UMS512_IIS_INF2_SYS_SEL = SPRD_PIN_INFO(18, GLOBAL_CTRL_PIN, 11, 4, 3),
+ UMS512_IIS_INF1_INF2_LOOP = SPRD_PIN_INFO(19, GLOBAL_CTRL_PIN, 10, 1, 3),
+ UMS512_IIS_INF1_SYS_SEL = SPRD_PIN_INFO(20, GLOBAL_CTRL_PIN, 6, 4, 3),
+ UMS512_IIS_INF0_INF2_LOOP = SPRD_PIN_INFO(21, GLOBAL_CTRL_PIN, 5, 1, 3),
+ UMS512_IIS_INF0_INF1_LOOP = SPRD_PIN_INFO(22, GLOBAL_CTRL_PIN, 4, 1, 3),
+ UMS512_IIS_INF0_SYS_SEL = SPRD_PIN_INFO(23, GLOBAL_CTRL_PIN, 0, 4, 3),
+
+ /* SIM_MATRIX_MTX_CFG */
+ UMS512_SIM_INF2_SYS_SEL = SPRD_PIN_INFO(24, GLOBAL_CTRL_PIN, 2, 1, 4),
+ UMS512_SIM_INF1_SYS_SEL = SPRD_PIN_INFO(25, GLOBAL_CTRL_PIN, 1, 1, 4),
+ UMS512_SIM_INFO_SYS_SEL = SPRD_PIN_INFO(26, GLOBAL_CTRL_PIN, 0, 1, 4),
+
+ /* SPI_MATRIX_MTX_CFG */
+ UMS512_SPI_INF3_SYS_SEL = SPRD_PIN_INFO(27, GLOBAL_CTRL_PIN, 3, 1, 5),
+ UMS512_SPI_INF2_SYS_SEL = SPRD_PIN_INFO(28, GLOBAL_CTRL_PIN, 2, 1, 5),
+ UMS512_SPI_INF1_SYS_SEL = SPRD_PIN_INFO(29, GLOBAL_CTRL_PIN, 1, 1, 5),
+ UMS512_SPI_INF0_SYS_SEL = SPRD_PIN_INFO(30, GLOBAL_CTRL_PIN, 0, 1, 5),
+
+ /* IIC_MATRIX_MTX_CFG */
+ UMS512_IIC_INF7_SYS_SEL = SPRD_PIN_INFO(31, GLOBAL_CTRL_PIN, 21, 3, 6),
+ UMS512_IIC_INF6_SYS_SEL = SPRD_PIN_INFO(32, GLOBAL_CTRL_PIN, 18, 3, 6),
+ UMS512_IIC_INF5_SYS_SEL = SPRD_PIN_INFO(33, GLOBAL_CTRL_PIN, 15, 3, 6),
+ UMS512_IIC_INF4_SYS_SEL = SPRD_PIN_INFO(34, GLOBAL_CTRL_PIN, 12, 3, 6),
+ UMS512_IIC_INF3_SYS_SEL = SPRD_PIN_INFO(35, GLOBAL_CTRL_PIN, 9, 3, 6),
+ UMS512_IIC_INF2_SYS_SEL = SPRD_PIN_INFO(36, GLOBAL_CTRL_PIN, 6, 3, 6),
+ UMS512_IIC_INF1_SYS_SEL = SPRD_PIN_INFO(37, GLOBAL_CTRL_PIN, 3, 3, 6),
+ UMS512_IIC_INF0_SYS_SEL = SPRD_PIN_INFO(38, GLOBAL_CTRL_PIN, 0, 3, 6),
+
+ /* PIN_CTRL_REG0 */
+ UMS512_PIN_CTRL_REG0 = SPRD_PIN_INFO(39, GLOBAL_CTRL_PIN, 0, 1, 7),
+
+ /* PIN_CTRL_REG1 */
+ UMS512_PIN_CTRL_REG1 = SPRD_PIN_INFO(40, GLOBAL_CTRL_PIN, 28, 4, 8),
+
+ /* PIN_CTRL_REG2 */
+ UMS512_UART_USB_PHY_SEL = SPRD_PIN_INFO(41, GLOBAL_CTRL_PIN, 31, 1, 9),
+ UMS512_USB_PHY_DM_OE = SPRD_PIN_INFO(42, GLOBAL_CTRL_PIN, 30, 1, 9),
+ UMS512_USB_PHY_DP_OE = SPRD_PIN_INFO(43, GLOBAL_CTRL_PIN, 29, 1, 9),
+
+ /* PIN_CTRL_REG3 */
+ UMS512_SP_EIC_DPAD3 = SPRD_PIN_INFO(44, GLOBAL_CTRL_PIN, 24, 8, 10),
+ UMS512_SP_EIC_DPAD2 = SPRD_PIN_INFO(45, GLOBAL_CTRL_PIN, 16, 8, 10),
+ UMS512_SP_EIC_DPAD1 = SPRD_PIN_INFO(46, GLOBAL_CTRL_PIN, 8, 8, 10),
+ UMS512_SP_EIC_DPAD0 = SPRD_PIN_INFO(47, GLOBAL_CTRL_PIN, 0, 8, 10),
+
+ /* PIN_CTRL_REG4 */
+ UMS512_SP_EIC_DPAD7 = SPRD_PIN_INFO(48, GLOBAL_CTRL_PIN, 24, 8, 11),
+ UMS512_SP_EIC_DPAD6 = SPRD_PIN_INFO(49, GLOBAL_CTRL_PIN, 16, 8, 11),
+ UMS512_SP_EIC_DPAD5 = SPRD_PIN_INFO(50, GLOBAL_CTRL_PIN, 8, 8, 11),
+ UMS512_SP_EIC_DPAD4 = SPRD_PIN_INFO(51, GLOBAL_CTRL_PIN, 0, 8, 11),
+
+ /* PIN_CTRL_REG5 */
+ UMS512_VBC_IIS_INF_SYS_SEL = SPRD_PIN_INFO(52, GLOBAL_CTRL_PIN, 20, 1, 12),
+ UMS512_CARD_DET_SEL = SPRD_PIN_INFO(53, GLOBAL_CTRL_PIN, 17, 3, 12),
+ UMS512_SIM0_DET_SEL = SPRD_PIN_INFO(54, GLOBAL_CTRL_PIN, 16, 1, 12),
+ UMS512_AP_SIM0_BD_EB = SPRD_PIN_INFO(55, GLOBAL_CTRL_PIN, 15, 1, 12),
+ UMS512_AP_EMMC_BD_EB = SPRD_PIN_INFO(56, GLOBAL_CTRL_PIN, 14, 1, 12),
+ UMS512_AP_SDIO2_BD_EB = SPRD_PIN_INFO(57, GLOBAL_CTRL_PIN, 13, 1, 12),
+ UMS512_AP_SDIO1_BD_EB = SPRD_PIN_INFO(58, GLOBAL_CTRL_PIN, 12, 1, 12),
+ UMS512_AP_SDIO0_BD_EB = SPRD_PIN_INFO(59, GLOBAL_CTRL_PIN, 11, 1, 12),
+ UMS512_PUBCP_SDIO_BD_EB = SPRD_PIN_INFO(60, GLOBAL_CTRL_PIN, 10, 1, 12),
+ UMS512_PUBCP_SIM1_BD_EB = SPRD_PIN_INFO(61, GLOBAL_CTRL_PIN, 9, 1, 12),
+ UMS512_PUBCP_SIM0_BD_EB = SPRD_PIN_INFO(62, GLOBAL_CTRL_PIN, 8, 1, 12),
+
+ /* Common pin registers definitions */
+ UMS512_EMMC_RST = SPRD_PIN_INFO(63, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_CMD = SPRD_PIN_INFO(64, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_D0 = SPRD_PIN_INFO(65, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_D3 = SPRD_PIN_INFO(66, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_D2 = SPRD_PIN_INFO(67, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_D5 = SPRD_PIN_INFO(68, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_CLK = SPRD_PIN_INFO(69, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_DS = SPRD_PIN_INFO(70, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_D1 = SPRD_PIN_INFO(71, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_D4 = SPRD_PIN_INFO(72, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_D6 = SPRD_PIN_INFO(73, COMMON_PIN, 0, 0, 0),
+ UMS512_EMMC_D7 = SPRD_PIN_INFO(74, COMMON_PIN, 0, 0, 0),
+ UMS512_LCM_RSTN = SPRD_PIN_INFO(75, COMMON_PIN, 0, 0, 0),
+ UMS512_DSI_TE = SPRD_PIN_INFO(76, COMMON_PIN, 0, 0, 0),
+ UMS512_DCDC_ARM1_EN = SPRD_PIN_INFO(77, COMMON_PIN, 0, 0, 0),
+ UMS512_PTEST = SPRD_PIN_INFO(78, COMMON_PIN, 0, 0, 0),
+ UMS512_EXT_RST_B = SPRD_PIN_INFO(79, COMMON_PIN, 0, 0, 0),
+ UMS512_ADI_SCLK = SPRD_PIN_INFO(80, COMMON_PIN, 0, 0, 0),
+ UMS512_CLK_32K = SPRD_PIN_INFO(81, COMMON_PIN, 0, 0, 0),
+ UMS512_ANA_INT = SPRD_PIN_INFO(82, COMMON_PIN, 0, 0, 0),
+ UMS512_ADI_D = SPRD_PIN_INFO(83, COMMON_PIN, 0, 0, 0),
+ UMS512_AUD_SCLK = SPRD_PIN_INFO(84, COMMON_PIN, 0, 0, 0),
+ UMS512_DCDC_ARM0_EN = SPRD_PIN_INFO(85, COMMON_PIN, 0, 0, 0),
+ UMS512_AUD_ADD0 = SPRD_PIN_INFO(86, COMMON_PIN, 0, 0, 0),
+ UMS512_XTL_EN0 = SPRD_PIN_INFO(87, COMMON_PIN, 0, 0, 0),
+ UMS512_AUD_ADSYNC = SPRD_PIN_INFO(88, COMMON_PIN, 0, 0, 0),
+ UMS512_AUD_DAD0 = SPRD_PIN_INFO(89, COMMON_PIN, 0, 0, 0),
+ UMS512_XTL_EN1 = SPRD_PIN_INFO(90, COMMON_PIN, 0, 0, 0),
+ UMS512_AUD_DASYNC = SPRD_PIN_INFO(91, COMMON_PIN, 0, 0, 0),
+ UMS512_AUD_DAD1 = SPRD_PIN_INFO(92, COMMON_PIN, 0, 0, 0),
+ UMS512_CHIP_SLEEP = SPRD_PIN_INFO(93, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMCLK2 = SPRD_PIN_INFO(94, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMDA2 = SPRD_PIN_INFO(95, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMRST2 = SPRD_PIN_INFO(96, COMMON_PIN, 0, 0, 0),
+ UMS512_SD0_CMD = SPRD_PIN_INFO(97, COMMON_PIN, 0, 0, 0),
+ UMS512_SD0_D0 = SPRD_PIN_INFO(98, COMMON_PIN, 0, 0, 0),
+ UMS512_SD0_D1 = SPRD_PIN_INFO(99, COMMON_PIN, 0, 0, 0),
+ UMS512_SD0_CLK = SPRD_PIN_INFO(100, COMMON_PIN, 0, 0, 0),
+ UMS512_SD0_D2 = SPRD_PIN_INFO(101, COMMON_PIN, 0, 0, 0),
+ UMS512_SD0_D3 = SPRD_PIN_INFO(102, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMCLK0 = SPRD_PIN_INFO(103, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMDA0 = SPRD_PIN_INFO(104, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMRST0 = SPRD_PIN_INFO(105, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMCLK1 = SPRD_PIN_INFO(106, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMDA1 = SPRD_PIN_INFO(107, COMMON_PIN, 0, 0, 0),
+ UMS512_SIMRST1 = SPRD_PIN_INFO(108, COMMON_PIN, 0, 0, 0),
+ UMS512_SD2_CMD = SPRD_PIN_INFO(109, COMMON_PIN, 0, 0, 0),
+ UMS512_SD2_D0 = SPRD_PIN_INFO(110, COMMON_PIN, 0, 0, 0),
+ UMS512_SD2_D1 = SPRD_PIN_INFO(111, COMMON_PIN, 0, 0, 0),
+ UMS512_SD2_CLK = SPRD_PIN_INFO(112, COMMON_PIN, 0, 0, 0),
+ UMS512_SD2_D2 = SPRD_PIN_INFO(113, COMMON_PIN, 0, 0, 0),
+ UMS512_SD2_D3 = SPRD_PIN_INFO(114, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL0 = SPRD_PIN_INFO(115, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL1 = SPRD_PIN_INFO(116, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL2 = SPRD_PIN_INFO(117, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL3 = SPRD_PIN_INFO(118, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL4 = SPRD_PIN_INFO(119, COMMON_PIN, 0, 0, 0),
+ UMS512_DNS_D0 = SPRD_PIN_INFO(120, COMMON_PIN, 0, 0, 0),
+ UMS512_DNS_D1 = SPRD_PIN_INFO(121, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS3DI = SPRD_PIN_INFO(122, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS3DO = SPRD_PIN_INFO(123, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS3CLK = SPRD_PIN_INFO(124, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS3LRCK = SPRD_PIN_INFO(125, COMMON_PIN, 0, 0, 0),
+ UMS512_GPIO116 = SPRD_PIN_INFO(126, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL5 = SPRD_PIN_INFO(127, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL6 = SPRD_PIN_INFO(128, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL7 = SPRD_PIN_INFO(129, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL8 = SPRD_PIN_INFO(130, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL9 = SPRD_PIN_INFO(131, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL10 = SPRD_PIN_INFO(132, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL11 = SPRD_PIN_INFO(133, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL12 = SPRD_PIN_INFO(134, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL13 = SPRD_PIN_INFO(135, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL14 = SPRD_PIN_INFO(136, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL15 = SPRD_PIN_INFO(137, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL16 = SPRD_PIN_INFO(138, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL17 = SPRD_PIN_INFO(139, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL18 = SPRD_PIN_INFO(140, COMMON_PIN, 0, 0, 0),
+ UMS512_RFCTL19 = SPRD_PIN_INFO(141, COMMON_PIN, 0, 0, 0),
+ UMS512_RFSCK0 = SPRD_PIN_INFO(142, COMMON_PIN, 0, 0, 0),
+ UMS512_RFSDA0 = SPRD_PIN_INFO(143, COMMON_PIN, 0, 0, 0),
+ UMS512_RFSEN0 = SPRD_PIN_INFO(144, COMMON_PIN, 0, 0, 0),
+ UMS512_RFSCK1 = SPRD_PIN_INFO(145, COMMON_PIN, 0, 0, 0),
+ UMS512_RFSDA1 = SPRD_PIN_INFO(146, COMMON_PIN, 0, 0, 0),
+ UMS512_RFSEN1 = SPRD_PIN_INFO(147, COMMON_PIN, 0, 0, 0),
+ UMS512_RFFE0_SCK = SPRD_PIN_INFO(148, COMMON_PIN, 0, 0, 0),
+ UMS512_RFFE0_SDA = SPRD_PIN_INFO(149, COMMON_PIN, 0, 0, 0),
+ UMS512_RFFE1_SCK = SPRD_PIN_INFO(150, COMMON_PIN, 0, 0, 0),
+ UMS512_RFFE1_SDA = SPRD_PIN_INFO(151, COMMON_PIN, 0, 0, 0),
+ UMS512_U1TXD = SPRD_PIN_INFO(152, COMMON_PIN, 0, 0, 0),
+ UMS512_U1RXD = SPRD_PIN_INFO(153, COMMON_PIN, 0, 0, 0),
+ UMS512_SCL6 = SPRD_PIN_INFO(154, COMMON_PIN, 0, 0, 0),
+ UMS512_SDA6 = SPRD_PIN_INFO(155, COMMON_PIN, 0, 0, 0),
+ UMS512_MTCK_ARM = SPRD_PIN_INFO(156, COMMON_PIN, 0, 0, 0),
+ UMS512_MTMS_ARM = SPRD_PIN_INFO(157, COMMON_PIN, 0, 0, 0),
+ UMS512_PWMC = SPRD_PIN_INFO(158, COMMON_PIN, 0, 0, 0),
+ UMS512_KEYOUT0 = SPRD_PIN_INFO(159, COMMON_PIN, 0, 0, 0),
+ UMS512_KEYOUT1 = SPRD_PIN_INFO(160, COMMON_PIN, 0, 0, 0),
+ UMS512_KEYOUT2 = SPRD_PIN_INFO(161, COMMON_PIN, 0, 0, 0),
+ UMS512_KEYIN0 = SPRD_PIN_INFO(162, COMMON_PIN, 0, 0, 0),
+ UMS512_KEYIN1 = SPRD_PIN_INFO(163, COMMON_PIN, 0, 0, 0),
+ UMS512_KEYIN2 = SPRD_PIN_INFO(164, COMMON_PIN, 0, 0, 0),
+ UMS512_SCL0 = SPRD_PIN_INFO(165, COMMON_PIN, 0, 0, 0),
+ UMS512_SDA0 = SPRD_PIN_INFO(166, COMMON_PIN, 0, 0, 0),
+ UMS512_SDA1 = SPRD_PIN_INFO(167, COMMON_PIN, 0, 0, 0),
+ UMS512_SCL1 = SPRD_PIN_INFO(168, COMMON_PIN, 0, 0, 0),
+ UMS512_CMMCLK0 = SPRD_PIN_INFO(169, COMMON_PIN, 0, 0, 0),
+ UMS512_CMMCLK1 = SPRD_PIN_INFO(170, COMMON_PIN, 0, 0, 0),
+ UMS512_CMRST0 = SPRD_PIN_INFO(171, COMMON_PIN, 0, 0, 0),
+ UMS512_CMRST1 = SPRD_PIN_INFO(172, COMMON_PIN, 0, 0, 0),
+ UMS512_CMPD0 = SPRD_PIN_INFO(173, COMMON_PIN, 0, 0, 0),
+ UMS512_CMPD1 = SPRD_PIN_INFO(174, COMMON_PIN, 0, 0, 0),
+ UMS512_CMMCLK2 = SPRD_PIN_INFO(175, COMMON_PIN, 0, 0, 0),
+ UMS512_CMPD2 = SPRD_PIN_INFO(176, COMMON_PIN, 0, 0, 0),
+ UMS512_CMRST2 = SPRD_PIN_INFO(177, COMMON_PIN, 0, 0, 0),
+ UMS512_GPIO84 = SPRD_PIN_INFO(178, COMMON_PIN, 0, 0, 0),
+ UMS512_GPIO85 = SPRD_PIN_INFO(179, COMMON_PIN, 0, 0, 0),
+ UMS512_GPIO86 = SPRD_PIN_INFO(180, COMMON_PIN, 0, 0, 0),
+ UMS512_GPIO87 = SPRD_PIN_INFO(181, COMMON_PIN, 0, 0, 0),
+ UMS512_GPIO88 = SPRD_PIN_INFO(182, COMMON_PIN, 0, 0, 0),
+ UMS512_SPI0_CSN = SPRD_PIN_INFO(183, COMMON_PIN, 0, 0, 0),
+ UMS512_SPI0_DO = SPRD_PIN_INFO(184, COMMON_PIN, 0, 0, 0),
+ UMS512_SPI0_DI = SPRD_PIN_INFO(185, COMMON_PIN, 0, 0, 0),
+ UMS512_SPI0_CLK = SPRD_PIN_INFO(186, COMMON_PIN, 0, 0, 0),
+ UMS512_EXTINT9 = SPRD_PIN_INFO(187, COMMON_PIN, 0, 0, 0),
+ UMS512_EXTINT10 = SPRD_PIN_INFO(188, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS1DI = SPRD_PIN_INFO(189, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS1DO = SPRD_PIN_INFO(190, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS1CLK = SPRD_PIN_INFO(191, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS1LRCK = SPRD_PIN_INFO(192, COMMON_PIN, 0, 0, 0),
+ UMS512_SCL2 = SPRD_PIN_INFO(193, COMMON_PIN, 0, 0, 0),
+ UMS512_SDA2 = SPRD_PIN_INFO(194, COMMON_PIN, 0, 0, 0),
+ UMS512_MEMS_MIC_CLK0 = SPRD_PIN_INFO(195, COMMON_PIN, 0, 0, 0),
+ UMS512_MEMS_MIC_DATA0 = SPRD_PIN_INFO(196, COMMON_PIN, 0, 0, 0),
+ UMS512_MEMS_MIC_CLK1 = SPRD_PIN_INFO(197, COMMON_PIN, 0, 0, 0),
+ UMS512_MEMS_MIC_DATA1 = SPRD_PIN_INFO(198, COMMON_PIN, 0, 0, 0),
+ UMS512_SPI2_CSN = SPRD_PIN_INFO(199, COMMON_PIN, 0, 0, 0),
+ UMS512_SPI2_DO = SPRD_PIN_INFO(200, COMMON_PIN, 0, 0, 0),
+ UMS512_SPI2_DI = SPRD_PIN_INFO(201, COMMON_PIN, 0, 0, 0),
+ UMS512_SPI2_CLK = SPRD_PIN_INFO(202, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS0DI = SPRD_PIN_INFO(203, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS0DO = SPRD_PIN_INFO(204, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS0CLK = SPRD_PIN_INFO(205, COMMON_PIN, 0, 0, 0),
+ UMS512_IIS0LRCK = SPRD_PIN_INFO(206, COMMON_PIN, 0, 0, 0),
+ UMS512_U5TXD = SPRD_PIN_INFO(207, COMMON_PIN, 0, 0, 0),
+ UMS512_U5RXD = SPRD_PIN_INFO(208, COMMON_PIN, 0, 0, 0),
+ UMS512_CLK_AUX0 = SPRD_PIN_INFO(209, COMMON_PIN, 0, 0, 0),
+ UMS512_U0TXD = SPRD_PIN_INFO(210, COMMON_PIN, 0, 0, 0),
+ UMS512_U0RXD = SPRD_PIN_INFO(211, COMMON_PIN, 0, 0, 0),
+ UMS512_U0CTS = SPRD_PIN_INFO(212, COMMON_PIN, 0, 0, 0),
+ UMS512_U0RTS = SPRD_PIN_INFO(213, COMMON_PIN, 0, 0, 0),
+ UMS512_U4TXD = SPRD_PIN_INFO(214, COMMON_PIN, 0, 0, 0),
+ UMS512_U4RXD = SPRD_PIN_INFO(215, COMMON_PIN, 0, 0, 0),
+ UMS512_U4CTS = SPRD_PIN_INFO(216, COMMON_PIN, 0, 0, 0),
+ UMS512_U4RTS = SPRD_PIN_INFO(217, COMMON_PIN, 0, 0, 0),
+ UMS512_SD1_CMD = SPRD_PIN_INFO(218, COMMON_PIN, 0, 0, 0),
+ UMS512_SD1_D0 = SPRD_PIN_INFO(219, COMMON_PIN, 0, 0, 0),
+ UMS512_SD1_D1 = SPRD_PIN_INFO(220, COMMON_PIN, 0, 0, 0),
+ UMS512_SD1_CLK = SPRD_PIN_INFO(221, COMMON_PIN, 0, 0, 0),
+ UMS512_SD1_D2 = SPRD_PIN_INFO(222, COMMON_PIN, 0, 0, 0),
+ UMS512_SD1_D3 = SPRD_PIN_INFO(223, COMMON_PIN, 0, 0, 0),
+ UMS512_EXTINT0 = SPRD_PIN_INFO(224, COMMON_PIN, 0, 0, 0),
+ UMS512_EXTINT1 = SPRD_PIN_INFO(225, COMMON_PIN, 0, 0, 0),
+ UMS512_SDA3 = SPRD_PIN_INFO(226, COMMON_PIN, 0, 0, 0),
+ UMS512_SCL3 = SPRD_PIN_INFO(227, COMMON_PIN, 0, 0, 0),
+
+ /* MSIC pin registers definitions */
+ UMS512_EMMC_RST_MISC = SPRD_PIN_INFO(228, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_CMD_MISC = SPRD_PIN_INFO(229, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_D0_MISC = SPRD_PIN_INFO(230, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_D3_MISC = SPRD_PIN_INFO(231, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_D2_MISC = SPRD_PIN_INFO(232, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_D5_MISC = SPRD_PIN_INFO(233, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_CLK_MISC = SPRD_PIN_INFO(234, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_DS_MISC = SPRD_PIN_INFO(235, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_D1_MISC = SPRD_PIN_INFO(236, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_D4_MISC = SPRD_PIN_INFO(237, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_D6_MISC = SPRD_PIN_INFO(238, MISC_PIN, 0, 0, 0),
+ UMS512_EMMC_D7_MISC = SPRD_PIN_INFO(239, MISC_PIN, 0, 0, 0),
+ UMS512_LCM_RSTN_MISC = SPRD_PIN_INFO(240, MISC_PIN, 0, 0, 0),
+ UMS512_DSI_TE_MISC = SPRD_PIN_INFO(241, MISC_PIN, 0, 0, 0),
+ UMS512_DCDC_ARM1_EN_MISC = SPRD_PIN_INFO(242, MISC_PIN, 0, 0, 0),
+ UMS512_PTEST_MISC = SPRD_PIN_INFO(243, MISC_PIN, 0, 0, 0),
+ UMS512_EXT_RST_B_MISC = SPRD_PIN_INFO(244, MISC_PIN, 0, 0, 0),
+ UMS512_ADI_SCLK_MISC = SPRD_PIN_INFO(245, MISC_PIN, 0, 0, 0),
+ UMS512_CLK_32K_MISC = SPRD_PIN_INFO(246, MISC_PIN, 0, 0, 0),
+ UMS512_ANA_INT_MISC = SPRD_PIN_INFO(247, MISC_PIN, 0, 0, 0),
+ UMS512_ADI_D_MISC = SPRD_PIN_INFO(248, MISC_PIN, 0, 0, 0),
+ UMS512_AUD_SCLK_MISC = SPRD_PIN_INFO(249, MISC_PIN, 0, 0, 0),
+ UMS512_DCDC_ARM0_EN_MISC = SPRD_PIN_INFO(250, MISC_PIN, 0, 0, 0),
+ UMS512_AUD_ADD0_MISC = SPRD_PIN_INFO(251, MISC_PIN, 0, 0, 0),
+ UMS512_XTL_EN0_MISC = SPRD_PIN_INFO(252, MISC_PIN, 0, 0, 0),
+ UMS512_AUD_ADSYNC_MISC = SPRD_PIN_INFO(253, MISC_PIN, 0, 0, 0),
+ UMS512_AUD_DAD0_MISC = SPRD_PIN_INFO(254, MISC_PIN, 0, 0, 0),
+ UMS512_XTL_EN1_MISC = SPRD_PIN_INFO(255, MISC_PIN, 0, 0, 0),
+ UMS512_AUD_DASYNC_MISC = SPRD_PIN_INFO(256, MISC_PIN, 0, 0, 0),
+ UMS512_AUD_DAD1_MISC = SPRD_PIN_INFO(257, MISC_PIN, 0, 0, 0),
+ UMS512_CHIP_SLEEP_MISC = SPRD_PIN_INFO(258, MISC_PIN, 0, 0, 0),
+ UMS512_SIMCLK2_MISC = SPRD_PIN_INFO(259, MISC_PIN, 0, 0, 0),
+ UMS512_SIMDA2_MISC = SPRD_PIN_INFO(260, MISC_PIN, 0, 0, 0),
+ UMS512_SIMRST2_MISC = SPRD_PIN_INFO(261, MISC_PIN, 0, 0, 0),
+ UMS512_SD0_CMD_MISC = SPRD_PIN_INFO(262, MISC_PIN, 0, 0, 0),
+ UMS512_SD0_D0_MISC = SPRD_PIN_INFO(263, MISC_PIN, 0, 0, 0),
+ UMS512_SD0_D1_MISC = SPRD_PIN_INFO(264, MISC_PIN, 0, 0, 0),
+ UMS512_SD0_CLK_MISC = SPRD_PIN_INFO(265, MISC_PIN, 0, 0, 0),
+ UMS512_SD0_D2_MISC = SPRD_PIN_INFO(266, MISC_PIN, 0, 0, 0),
+ UMS512_SD0_D3_MISC = SPRD_PIN_INFO(267, MISC_PIN, 0, 0, 0),
+ UMS512_SIMCLK0_MISC = SPRD_PIN_INFO(268, MISC_PIN, 0, 0, 0),
+ UMS512_SIMDA0_MISC = SPRD_PIN_INFO(269, MISC_PIN, 0, 0, 0),
+ UMS512_SIMRST0_MISC = SPRD_PIN_INFO(270, MISC_PIN, 0, 0, 0),
+ UMS512_SIMCLK1_MISC = SPRD_PIN_INFO(271, MISC_PIN, 0, 0, 0),
+ UMS512_SIMDA1_MISC = SPRD_PIN_INFO(272, MISC_PIN, 0, 0, 0),
+ UMS512_SIMRST1_MISC = SPRD_PIN_INFO(273, MISC_PIN, 0, 0, 0),
+ UMS512_SD2_CMD_MISC = SPRD_PIN_INFO(274, MISC_PIN, 0, 0, 0),
+ UMS512_SD2_D0_MISC = SPRD_PIN_INFO(275, MISC_PIN, 0, 0, 0),
+ UMS512_SD2_D1_MISC = SPRD_PIN_INFO(276, MISC_PIN, 0, 0, 0),
+ UMS512_SD2_CLK_MISC = SPRD_PIN_INFO(277, MISC_PIN, 0, 0, 0),
+ UMS512_SD2_D2_MISC = SPRD_PIN_INFO(278, MISC_PIN, 0, 0, 0),
+ UMS512_SD2_D3_MISC = SPRD_PIN_INFO(279, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL0_MISC = SPRD_PIN_INFO(280, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL1_MISC = SPRD_PIN_INFO(281, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL2_MISC = SPRD_PIN_INFO(282, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL3_MISC = SPRD_PIN_INFO(283, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL4_MISC = SPRD_PIN_INFO(284, MISC_PIN, 0, 0, 0),
+ UMS512_DNS_D0_MISC = SPRD_PIN_INFO(285, MISC_PIN, 0, 0, 0),
+ UMS512_DNS_D1_MISC = SPRD_PIN_INFO(286, MISC_PIN, 0, 0, 0),
+ UMS512_IIS3DI_MISC = SPRD_PIN_INFO(287, MISC_PIN, 0, 0, 0),
+ UMS512_IIS3DO_MISC = SPRD_PIN_INFO(288, MISC_PIN, 0, 0, 0),
+ UMS512_IIS3CLK_MISC = SPRD_PIN_INFO(289, MISC_PIN, 0, 0, 0),
+ UMS512_IIS3LRCK_MISC = SPRD_PIN_INFO(290, MISC_PIN, 0, 0, 0),
+ UMS512_GPIO116_MISC = SPRD_PIN_INFO(291, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL5_MISC = SPRD_PIN_INFO(292, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL6_MISC = SPRD_PIN_INFO(293, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL7_MISC = SPRD_PIN_INFO(294, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL8_MISC = SPRD_PIN_INFO(295, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL9_MISC = SPRD_PIN_INFO(296, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL10_MISC = SPRD_PIN_INFO(297, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL11_MISC = SPRD_PIN_INFO(298, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL12_MISC = SPRD_PIN_INFO(299, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL13_MISC = SPRD_PIN_INFO(300, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL14_MISC = SPRD_PIN_INFO(301, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL15_MISC = SPRD_PIN_INFO(302, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL16_MISC = SPRD_PIN_INFO(303, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL17_MISC = SPRD_PIN_INFO(304, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL18_MISC = SPRD_PIN_INFO(305, MISC_PIN, 0, 0, 0),
+ UMS512_RFCTL19_MISC = SPRD_PIN_INFO(306, MISC_PIN, 0, 0, 0),
+ UMS512_RFSCK0_MISC = SPRD_PIN_INFO(307, MISC_PIN, 0, 0, 0),
+ UMS512_RFSDA0_MISC = SPRD_PIN_INFO(308, MISC_PIN, 0, 0, 0),
+ UMS512_RFSEN0_MISC = SPRD_PIN_INFO(309, MISC_PIN, 0, 0, 0),
+ UMS512_RFSCK1_MISC = SPRD_PIN_INFO(310, MISC_PIN, 0, 0, 0),
+ UMS512_RFSDA1_MISC = SPRD_PIN_INFO(311, MISC_PIN, 0, 0, 0),
+ UMS512_RFSEN1_MISC = SPRD_PIN_INFO(312, MISC_PIN, 0, 0, 0),
+ UMS512_RFFE0_SCK_MISC = SPRD_PIN_INFO(313, MISC_PIN, 0, 0, 0),
+ UMS512_RFFE0_SDA_MISC = SPRD_PIN_INFO(314, MISC_PIN, 0, 0, 0),
+ UMS512_RFFE1_SCK_MISC = SPRD_PIN_INFO(315, MISC_PIN, 0, 0, 0),
+ UMS512_RFFE1_SDA_MISC = SPRD_PIN_INFO(316, MISC_PIN, 0, 0, 0),
+ UMS512_U1TXD_MISC = SPRD_PIN_INFO(317, MISC_PIN, 0, 0, 0),
+ UMS512_U1RXD_MISC = SPRD_PIN_INFO(318, MISC_PIN, 0, 0, 0),
+ UMS512_SCL6_MISC = SPRD_PIN_INFO(319, MISC_PIN, 0, 0, 0),
+ UMS512_SDA6_MISC = SPRD_PIN_INFO(320, MISC_PIN, 0, 0, 0),
+ UMS512_MTCK_ARM_MISC = SPRD_PIN_INFO(321, MISC_PIN, 0, 0, 0),
+ UMS512_MTMS_ARM_MISC = SPRD_PIN_INFO(322, MISC_PIN, 0, 0, 0),
+ UMS512_PWMC_MISC = SPRD_PIN_INFO(323, MISC_PIN, 0, 0, 0),
+ UMS512_KEYOUT0_MISC = SPRD_PIN_INFO(324, MISC_PIN, 0, 0, 0),
+ UMS512_KEYOUT1_MISC = SPRD_PIN_INFO(325, MISC_PIN, 0, 0, 0),
+ UMS512_KEYOUT2_MISC = SPRD_PIN_INFO(326, MISC_PIN, 0, 0, 0),
+ UMS512_KEYIN0_MISC = SPRD_PIN_INFO(327, MISC_PIN, 0, 0, 0),
+ UMS512_KEYIN1_MISC = SPRD_PIN_INFO(328, MISC_PIN, 0, 0, 0),
+ UMS512_KEYIN2_MISC = SPRD_PIN_INFO(329, MISC_PIN, 0, 0, 0),
+ UMS512_SCL0_MISC = SPRD_PIN_INFO(330, MISC_PIN, 0, 0, 0),
+ UMS512_SDA0_MISC = SPRD_PIN_INFO(331, MISC_PIN, 0, 0, 0),
+ UMS512_SDA1_MISC = SPRD_PIN_INFO(332, MISC_PIN, 0, 0, 0),
+ UMS512_SCL1_MISC = SPRD_PIN_INFO(333, MISC_PIN, 0, 0, 0),
+ UMS512_CMMCLK0_MISC = SPRD_PIN_INFO(334, MISC_PIN, 0, 0, 0),
+ UMS512_CMMCLK1_MISC = SPRD_PIN_INFO(335, MISC_PIN, 0, 0, 0),
+ UMS512_CMRST0_MISC = SPRD_PIN_INFO(336, MISC_PIN, 0, 0, 0),
+ UMS512_CMRST1_MISC = SPRD_PIN_INFO(337, MISC_PIN, 0, 0, 0),
+ UMS512_CMPD0_MISC = SPRD_PIN_INFO(338, MISC_PIN, 0, 0, 0),
+ UMS512_CMPD1_MISC = SPRD_PIN_INFO(339, MISC_PIN, 0, 0, 0),
+ UMS512_CMMCLK2_MISC = SPRD_PIN_INFO(340, MISC_PIN, 0, 0, 0),
+ UMS512_CMPD2_MISC = SPRD_PIN_INFO(341, MISC_PIN, 0, 0, 0),
+ UMS512_CMRST2_MISC = SPRD_PIN_INFO(342, MISC_PIN, 0, 0, 0),
+ UMS512_GPIO84_MISC = SPRD_PIN_INFO(343, MISC_PIN, 0, 0, 0),
+ UMS512_GPIO85_MISC = SPRD_PIN_INFO(344, MISC_PIN, 0, 0, 0),
+ UMS512_GPIO86_MISC = SPRD_PIN_INFO(345, MISC_PIN, 0, 0, 0),
+ UMS512_GPIO87_MISC = SPRD_PIN_INFO(346, MISC_PIN, 0, 0, 0),
+ UMS512_GPIO88_MISC = SPRD_PIN_INFO(347, MISC_PIN, 0, 0, 0),
+ UMS512_SPI0_CSN_MISC = SPRD_PIN_INFO(348, MISC_PIN, 0, 0, 0),
+ UMS512_SPI0_DO_MISC = SPRD_PIN_INFO(349, MISC_PIN, 0, 0, 0),
+ UMS512_SPI0_DI_MISC = SPRD_PIN_INFO(350, MISC_PIN, 0, 0, 0),
+ UMS512_SPI0_CLK_MISC = SPRD_PIN_INFO(351, MISC_PIN, 0, 0, 0),
+ UMS512_EXTINT9_MISC = SPRD_PIN_INFO(352, MISC_PIN, 0, 0, 0),
+ UMS512_EXTINT10_MISC = SPRD_PIN_INFO(353, MISC_PIN, 0, 0, 0),
+ UMS512_IIS1DI_MISC = SPRD_PIN_INFO(354, MISC_PIN, 0, 0, 0),
+ UMS512_IIS1DO_MISC = SPRD_PIN_INFO(355, MISC_PIN, 0, 0, 0),
+ UMS512_IIS1CLK_MISC = SPRD_PIN_INFO(356, MISC_PIN, 0, 0, 0),
+ UMS512_IIS1LRCK_MISC = SPRD_PIN_INFO(357, MISC_PIN, 0, 0, 0),
+ UMS512_SCL2_MISC = SPRD_PIN_INFO(358, MISC_PIN, 0, 0, 0),
+ UMS512_SDA2_MISC = SPRD_PIN_INFO(359, MISC_PIN, 0, 0, 0),
+ UMS512_MEMS_MIC_CLK0_MISC = SPRD_PIN_INFO(360, MISC_PIN, 0, 0, 0),
+ UMS512_MEMS_MIC_DATA0_MISC = SPRD_PIN_INFO(361, MISC_PIN, 0, 0, 0),
+ UMS512_MEMS_MIC_CLK1_MISC = SPRD_PIN_INFO(362, MISC_PIN, 0, 0, 0),
+ UMS512_MEMS_MIC_DATA1_MISC = SPRD_PIN_INFO(363, MISC_PIN, 0, 0, 0),
+ UMS512_SPI2_CSN_MISC = SPRD_PIN_INFO(364, MISC_PIN, 0, 0, 0),
+ UMS512_SPI2_DO_MISC = SPRD_PIN_INFO(365, MISC_PIN, 0, 0, 0),
+ UMS512_SPI2_DI_MISC = SPRD_PIN_INFO(366, MISC_PIN, 0, 0, 0),
+ UMS512_SPI2_CLK_MISC = SPRD_PIN_INFO(367, MISC_PIN, 0, 0, 0),
+ UMS512_IIS0DI_MISC = SPRD_PIN_INFO(368, MISC_PIN, 0, 0, 0),
+ UMS512_IIS0DO_MISC = SPRD_PIN_INFO(369, MISC_PIN, 0, 0, 0),
+ UMS512_IIS0CLK_MISC = SPRD_PIN_INFO(370, MISC_PIN, 0, 0, 0),
+ UMS512_IIS0LRCK_MISC = SPRD_PIN_INFO(371, MISC_PIN, 0, 0, 0),
+ UMS512_U5TXD_MISC = SPRD_PIN_INFO(372, MISC_PIN, 0, 0, 0),
+ UMS512_U5RXD_MISC = SPRD_PIN_INFO(373, MISC_PIN, 0, 0, 0),
+ UMS512_CLK_AUX0_MISC = SPRD_PIN_INFO(374, MISC_PIN, 0, 0, 0),
+ UMS512_U0TXD_MISC = SPRD_PIN_INFO(375, MISC_PIN, 0, 0, 0),
+ UMS512_U0RXD_MISC = SPRD_PIN_INFO(376, MISC_PIN, 0, 0, 0),
+ UMS512_U0CTS_MISC = SPRD_PIN_INFO(377, MISC_PIN, 0, 0, 0),
+ UMS512_U0RTS_MISC = SPRD_PIN_INFO(378, MISC_PIN, 0, 0, 0),
+ UMS512_U4TXD_MISC = SPRD_PIN_INFO(379, MISC_PIN, 0, 0, 0),
+ UMS512_U4RXD_MISC = SPRD_PIN_INFO(380, MISC_PIN, 0, 0, 0),
+ UMS512_U4CTS_MISC = SPRD_PIN_INFO(381, MISC_PIN, 0, 0, 0),
+ UMS512_U4RTS_MISC = SPRD_PIN_INFO(382, MISC_PIN, 0, 0, 0),
+ UMS512_SD1_CMD_MISC = SPRD_PIN_INFO(383, MISC_PIN, 0, 0, 0),
+ UMS512_SD1_D0_MISC = SPRD_PIN_INFO(384, MISC_PIN, 0, 0, 0),
+ UMS512_SD1_D1_MISC = SPRD_PIN_INFO(385, MISC_PIN, 0, 0, 0),
+ UMS512_SD1_CLK_MISC = SPRD_PIN_INFO(386, MISC_PIN, 0, 0, 0),
+ UMS512_SD1_D2_MISC = SPRD_PIN_INFO(387, MISC_PIN, 0, 0, 0),
+ UMS512_SD1_D3_MISC = SPRD_PIN_INFO(388, MISC_PIN, 0, 0, 0),
+ UMS512_EXTINT0_MISC = SPRD_PIN_INFO(389, MISC_PIN, 0, 0, 0),
+ UMS512_EXTINT1_MISC = SPRD_PIN_INFO(390, MISC_PIN, 0, 0, 0),
+ UMS512_SDA3_MISC = SPRD_PIN_INFO(391, MISC_PIN, 0, 0, 0),
+ UMS512_SCL3_MISC = SPRD_PIN_INFO(392, MISC_PIN, 0, 0, 0),
+};
+
+static struct sprd_pins_info sprd_ums512_pins_info[] = {
+ SPRD_PINCTRL_PIN(UMS512_UART_INF6_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF5_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF4_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF3_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF2_INF3_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF2_INF4_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF1_INF4_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF1_INF3_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS512_UART_INF9_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF8_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF7_INF8_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_UART_INF7_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF4_INF3_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF4_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF3_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF1_INF2_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF0_INF2_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF0_INF1_LOOP),
+ SPRD_PINCTRL_PIN(UMS512_IIS_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS512_SIM_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_SIM_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_SIM_INFO_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS512_SPI_INF3_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_SPI_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_SPI_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_SPI_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS512_IIC_INF7_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIC_INF6_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIC_INF5_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIC_INF4_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIC_INF3_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIC_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIC_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_IIC_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS512_PIN_CTRL_REG0),
+
+ SPRD_PINCTRL_PIN(UMS512_PIN_CTRL_REG1),
+
+ SPRD_PINCTRL_PIN(UMS512_UART_USB_PHY_SEL),
+ SPRD_PINCTRL_PIN(UMS512_USB_PHY_DM_OE),
+ SPRD_PINCTRL_PIN(UMS512_USB_PHY_DP_OE),
+
+ SPRD_PINCTRL_PIN(UMS512_SP_EIC_DPAD3),
+ SPRD_PINCTRL_PIN(UMS512_SP_EIC_DPAD2),
+ SPRD_PINCTRL_PIN(UMS512_SP_EIC_DPAD1),
+ SPRD_PINCTRL_PIN(UMS512_SP_EIC_DPAD0),
+
+ SPRD_PINCTRL_PIN(UMS512_SP_EIC_DPAD7),
+ SPRD_PINCTRL_PIN(UMS512_SP_EIC_DPAD6),
+ SPRD_PINCTRL_PIN(UMS512_SP_EIC_DPAD5),
+ SPRD_PINCTRL_PIN(UMS512_SP_EIC_DPAD4),
+
+ SPRD_PINCTRL_PIN(UMS512_VBC_IIS_INF_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS512_CARD_DET_SEL),
+ SPRD_PINCTRL_PIN(UMS512_SIM0_DET_SEL),
+ SPRD_PINCTRL_PIN(UMS512_AP_SIM0_BD_EB),
+ SPRD_PINCTRL_PIN(UMS512_AP_EMMC_BD_EB),
+ SPRD_PINCTRL_PIN(UMS512_AP_SDIO2_BD_EB),
+ SPRD_PINCTRL_PIN(UMS512_AP_SDIO1_BD_EB),
+ SPRD_PINCTRL_PIN(UMS512_AP_SDIO0_BD_EB),
+ SPRD_PINCTRL_PIN(UMS512_PUBCP_SDIO_BD_EB),
+ SPRD_PINCTRL_PIN(UMS512_PUBCP_SIM1_BD_EB),
+ SPRD_PINCTRL_PIN(UMS512_PUBCP_SIM0_BD_EB),
+
+ SPRD_PINCTRL_PIN(UMS512_EMMC_RST),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_CMD),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D0),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D3),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D2),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D5),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_CLK),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_DS),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D1),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D4),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D6),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D7),
+ SPRD_PINCTRL_PIN(UMS512_LCM_RSTN),
+ SPRD_PINCTRL_PIN(UMS512_DSI_TE),
+ SPRD_PINCTRL_PIN(UMS512_DCDC_ARM1_EN),
+ SPRD_PINCTRL_PIN(UMS512_PTEST),
+ SPRD_PINCTRL_PIN(UMS512_EXT_RST_B),
+ SPRD_PINCTRL_PIN(UMS512_ADI_SCLK),
+ SPRD_PINCTRL_PIN(UMS512_CLK_32K),
+ SPRD_PINCTRL_PIN(UMS512_ANA_INT),
+ SPRD_PINCTRL_PIN(UMS512_ADI_D),
+ SPRD_PINCTRL_PIN(UMS512_AUD_SCLK),
+ SPRD_PINCTRL_PIN(UMS512_DCDC_ARM0_EN),
+ SPRD_PINCTRL_PIN(UMS512_AUD_ADD0),
+ SPRD_PINCTRL_PIN(UMS512_XTL_EN0),
+ SPRD_PINCTRL_PIN(UMS512_AUD_ADSYNC),
+ SPRD_PINCTRL_PIN(UMS512_AUD_DAD0),
+ SPRD_PINCTRL_PIN(UMS512_XTL_EN1),
+ SPRD_PINCTRL_PIN(UMS512_AUD_DASYNC),
+ SPRD_PINCTRL_PIN(UMS512_AUD_DAD1),
+ SPRD_PINCTRL_PIN(UMS512_CHIP_SLEEP),
+ SPRD_PINCTRL_PIN(UMS512_SIMCLK2),
+ SPRD_PINCTRL_PIN(UMS512_SIMDA2),
+ SPRD_PINCTRL_PIN(UMS512_SIMRST2),
+ SPRD_PINCTRL_PIN(UMS512_SD0_CMD),
+ SPRD_PINCTRL_PIN(UMS512_SD0_D0),
+ SPRD_PINCTRL_PIN(UMS512_SD0_D1),
+ SPRD_PINCTRL_PIN(UMS512_SD0_CLK),
+ SPRD_PINCTRL_PIN(UMS512_SD0_D2),
+ SPRD_PINCTRL_PIN(UMS512_SD0_D3),
+ SPRD_PINCTRL_PIN(UMS512_SIMCLK0),
+ SPRD_PINCTRL_PIN(UMS512_SIMDA0),
+ SPRD_PINCTRL_PIN(UMS512_SIMRST0),
+ SPRD_PINCTRL_PIN(UMS512_SIMCLK1),
+ SPRD_PINCTRL_PIN(UMS512_SIMDA1),
+ SPRD_PINCTRL_PIN(UMS512_SIMRST1),
+ SPRD_PINCTRL_PIN(UMS512_SD2_CMD),
+ SPRD_PINCTRL_PIN(UMS512_SD2_D0),
+ SPRD_PINCTRL_PIN(UMS512_SD2_D1),
+ SPRD_PINCTRL_PIN(UMS512_SD2_CLK),
+ SPRD_PINCTRL_PIN(UMS512_SD2_D2),
+ SPRD_PINCTRL_PIN(UMS512_SD2_D3),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL0),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL1),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL2),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL3),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL4),
+ SPRD_PINCTRL_PIN(UMS512_DNS_D0),
+ SPRD_PINCTRL_PIN(UMS512_DNS_D1),
+ SPRD_PINCTRL_PIN(UMS512_IIS3DI),
+ SPRD_PINCTRL_PIN(UMS512_IIS3DO),
+ SPRD_PINCTRL_PIN(UMS512_IIS3CLK),
+ SPRD_PINCTRL_PIN(UMS512_IIS3LRCK),
+ SPRD_PINCTRL_PIN(UMS512_GPIO116),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL5),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL6),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL7),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL8),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL9),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL10),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL11),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL12),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL13),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL14),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL15),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL16),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL17),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL18),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL19),
+ SPRD_PINCTRL_PIN(UMS512_RFSCK0),
+ SPRD_PINCTRL_PIN(UMS512_RFSDA0),
+ SPRD_PINCTRL_PIN(UMS512_RFSEN0),
+ SPRD_PINCTRL_PIN(UMS512_RFSCK1),
+ SPRD_PINCTRL_PIN(UMS512_RFSDA1),
+ SPRD_PINCTRL_PIN(UMS512_RFSEN1),
+ SPRD_PINCTRL_PIN(UMS512_RFFE0_SCK),
+ SPRD_PINCTRL_PIN(UMS512_RFFE0_SDA),
+ SPRD_PINCTRL_PIN(UMS512_RFFE1_SCK),
+ SPRD_PINCTRL_PIN(UMS512_RFFE1_SDA),
+ SPRD_PINCTRL_PIN(UMS512_U1TXD),
+ SPRD_PINCTRL_PIN(UMS512_U1RXD),
+ SPRD_PINCTRL_PIN(UMS512_SCL6),
+ SPRD_PINCTRL_PIN(UMS512_SDA6),
+ SPRD_PINCTRL_PIN(UMS512_MTCK_ARM),
+ SPRD_PINCTRL_PIN(UMS512_MTMS_ARM),
+ SPRD_PINCTRL_PIN(UMS512_PWMC),
+ SPRD_PINCTRL_PIN(UMS512_KEYOUT0),
+ SPRD_PINCTRL_PIN(UMS512_KEYOUT1),
+ SPRD_PINCTRL_PIN(UMS512_KEYOUT2),
+ SPRD_PINCTRL_PIN(UMS512_KEYIN0),
+ SPRD_PINCTRL_PIN(UMS512_KEYIN1),
+ SPRD_PINCTRL_PIN(UMS512_KEYIN2),
+ SPRD_PINCTRL_PIN(UMS512_SCL0),
+ SPRD_PINCTRL_PIN(UMS512_SDA0),
+ SPRD_PINCTRL_PIN(UMS512_SDA1),
+ SPRD_PINCTRL_PIN(UMS512_SCL1),
+ SPRD_PINCTRL_PIN(UMS512_CMMCLK0),
+ SPRD_PINCTRL_PIN(UMS512_CMMCLK1),
+ SPRD_PINCTRL_PIN(UMS512_CMRST0),
+ SPRD_PINCTRL_PIN(UMS512_CMRST1),
+ SPRD_PINCTRL_PIN(UMS512_CMPD0),
+ SPRD_PINCTRL_PIN(UMS512_CMPD1),
+ SPRD_PINCTRL_PIN(UMS512_CMMCLK2),
+ SPRD_PINCTRL_PIN(UMS512_CMPD2),
+ SPRD_PINCTRL_PIN(UMS512_CMRST2),
+ SPRD_PINCTRL_PIN(UMS512_GPIO84),
+ SPRD_PINCTRL_PIN(UMS512_GPIO85),
+ SPRD_PINCTRL_PIN(UMS512_GPIO86),
+ SPRD_PINCTRL_PIN(UMS512_GPIO87),
+ SPRD_PINCTRL_PIN(UMS512_GPIO88),
+ SPRD_PINCTRL_PIN(UMS512_SPI0_CSN),
+ SPRD_PINCTRL_PIN(UMS512_SPI0_DO),
+ SPRD_PINCTRL_PIN(UMS512_SPI0_DI),
+ SPRD_PINCTRL_PIN(UMS512_SPI0_CLK),
+ SPRD_PINCTRL_PIN(UMS512_EXTINT9),
+ SPRD_PINCTRL_PIN(UMS512_EXTINT10),
+ SPRD_PINCTRL_PIN(UMS512_IIS1DI),
+ SPRD_PINCTRL_PIN(UMS512_IIS1DO),
+ SPRD_PINCTRL_PIN(UMS512_IIS1CLK),
+ SPRD_PINCTRL_PIN(UMS512_IIS1LRCK),
+ SPRD_PINCTRL_PIN(UMS512_SCL2),
+ SPRD_PINCTRL_PIN(UMS512_SDA2),
+ SPRD_PINCTRL_PIN(UMS512_MEMS_MIC_CLK0),
+ SPRD_PINCTRL_PIN(UMS512_MEMS_MIC_DATA0),
+ SPRD_PINCTRL_PIN(UMS512_MEMS_MIC_CLK1),
+ SPRD_PINCTRL_PIN(UMS512_MEMS_MIC_DATA1),
+ SPRD_PINCTRL_PIN(UMS512_SPI2_CSN),
+ SPRD_PINCTRL_PIN(UMS512_SPI2_DO),
+ SPRD_PINCTRL_PIN(UMS512_SPI2_DI),
+ SPRD_PINCTRL_PIN(UMS512_SPI2_CLK),
+ SPRD_PINCTRL_PIN(UMS512_IIS0DI),
+ SPRD_PINCTRL_PIN(UMS512_IIS0DO),
+ SPRD_PINCTRL_PIN(UMS512_IIS0CLK),
+ SPRD_PINCTRL_PIN(UMS512_IIS0LRCK),
+ SPRD_PINCTRL_PIN(UMS512_U5TXD),
+ SPRD_PINCTRL_PIN(UMS512_U5RXD),
+ SPRD_PINCTRL_PIN(UMS512_CLK_AUX0),
+ SPRD_PINCTRL_PIN(UMS512_U0TXD),
+ SPRD_PINCTRL_PIN(UMS512_U0RXD),
+ SPRD_PINCTRL_PIN(UMS512_U0CTS),
+ SPRD_PINCTRL_PIN(UMS512_U0RTS),
+ SPRD_PINCTRL_PIN(UMS512_U4TXD),
+ SPRD_PINCTRL_PIN(UMS512_U4RXD),
+ SPRD_PINCTRL_PIN(UMS512_U4CTS),
+ SPRD_PINCTRL_PIN(UMS512_U4RTS),
+ SPRD_PINCTRL_PIN(UMS512_SD1_CMD),
+ SPRD_PINCTRL_PIN(UMS512_SD1_D0),
+ SPRD_PINCTRL_PIN(UMS512_SD1_D1),
+ SPRD_PINCTRL_PIN(UMS512_SD1_CLK),
+ SPRD_PINCTRL_PIN(UMS512_SD1_D2),
+ SPRD_PINCTRL_PIN(UMS512_SD1_D3),
+ SPRD_PINCTRL_PIN(UMS512_EXTINT0),
+ SPRD_PINCTRL_PIN(UMS512_EXTINT1),
+ SPRD_PINCTRL_PIN(UMS512_SDA3),
+ SPRD_PINCTRL_PIN(UMS512_SCL3),
+
+ SPRD_PINCTRL_PIN(UMS512_EMMC_RST_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_CMD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D3_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D5_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_DS_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D4_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D6_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EMMC_D7_MISC),
+ SPRD_PINCTRL_PIN(UMS512_LCM_RSTN_MISC),
+ SPRD_PINCTRL_PIN(UMS512_DSI_TE_MISC),
+ SPRD_PINCTRL_PIN(UMS512_DCDC_ARM1_EN_MISC),
+ SPRD_PINCTRL_PIN(UMS512_PTEST_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EXT_RST_B_MISC),
+ SPRD_PINCTRL_PIN(UMS512_ADI_SCLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CLK_32K_MISC),
+ SPRD_PINCTRL_PIN(UMS512_ANA_INT_MISC),
+ SPRD_PINCTRL_PIN(UMS512_ADI_D_MISC),
+ SPRD_PINCTRL_PIN(UMS512_AUD_SCLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_DCDC_ARM0_EN_MISC),
+ SPRD_PINCTRL_PIN(UMS512_AUD_ADD0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_XTL_EN0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_AUD_ADSYNC_MISC),
+ SPRD_PINCTRL_PIN(UMS512_AUD_DAD0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_XTL_EN1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_AUD_DASYNC_MISC),
+ SPRD_PINCTRL_PIN(UMS512_AUD_DAD1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CHIP_SLEEP_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMCLK2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMDA2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMRST2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD0_CMD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD0_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD0_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD0_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD0_D2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD0_D3_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMCLK0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMDA0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMRST0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMCLK1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMDA1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SIMRST1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD2_CMD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD2_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD2_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD2_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD2_D2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD2_D3_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL3_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL4_MISC),
+ SPRD_PINCTRL_PIN(UMS512_DNS_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_DNS_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS3DI_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS3DO_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS3CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS3LRCK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_GPIO116_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL5_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL6_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL7_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL8_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL9_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL10_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL11_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL12_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL13_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL14_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL15_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL16_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL17_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL18_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFCTL19_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFSCK0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFSDA0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFSEN0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFSCK1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFSDA1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFSEN1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFFE0_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFFE0_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFFE1_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_RFFE1_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U1TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U1RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SCL6_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SDA6_MISC),
+ SPRD_PINCTRL_PIN(UMS512_MTCK_ARM_MISC),
+ SPRD_PINCTRL_PIN(UMS512_MTMS_ARM_MISC),
+ SPRD_PINCTRL_PIN(UMS512_PWMC_MISC),
+ SPRD_PINCTRL_PIN(UMS512_KEYOUT0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_KEYOUT1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_KEYOUT2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_KEYIN0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_KEYIN1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_KEYIN2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SCL0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SDA0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SDA1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SCL1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMMCLK0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMMCLK1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMRST0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMRST1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMPD0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMPD1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMMCLK2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMPD2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CMRST2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_GPIO84_MISC),
+ SPRD_PINCTRL_PIN(UMS512_GPIO85_MISC),
+ SPRD_PINCTRL_PIN(UMS512_GPIO86_MISC),
+ SPRD_PINCTRL_PIN(UMS512_GPIO87_MISC),
+ SPRD_PINCTRL_PIN(UMS512_GPIO88_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SPI0_CSN_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SPI0_DO_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SPI0_DI_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SPI0_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EXTINT9_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EXTINT10_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS1DI_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS1DO_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS1CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS1LRCK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SCL2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SDA2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_MEMS_MIC_CLK0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_MEMS_MIC_DATA0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_MEMS_MIC_CLK1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_MEMS_MIC_DATA1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SPI2_CSN_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SPI2_DO_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SPI2_DI_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SPI2_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS0DI_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS0DO_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS0CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_IIS0LRCK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U5TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U5RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_CLK_AUX0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U0TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U0RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U0CTS_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U0RTS_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U4TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U4RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U4CTS_MISC),
+ SPRD_PINCTRL_PIN(UMS512_U4RTS_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD1_CMD_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD1_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD1_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD1_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD1_D2_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SD1_D3_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EXTINT0_MISC),
+ SPRD_PINCTRL_PIN(UMS512_EXTINT1_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SDA3_MISC),
+ SPRD_PINCTRL_PIN(UMS512_SCL3_MISC),
+};
+
+static int sprd_pinctrl_probe(struct platform_device *pdev)
+{
+ return sprd_pinctrl_core_probe(pdev, sprd_ums512_pins_info,
+ ARRAY_SIZE(sprd_ums512_pins_info),
+ PINCTRL_REG_OFFSET,
+ PINCTRL_REG_MISC_OFFSET);
+}
+
+static const struct of_device_id sprd_pinctrl_of_match[] = {
+ { .compatible = "sprd,ums512-pinctrl", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, sprd_pinctrl_of_match);
+
+static struct platform_driver sprd_pinctrl_driver = {
+ .driver = {
+ .name = "sprd-pinctrl",
+ .of_match_table = sprd_pinctrl_of_match,
+ },
+ .probe = sprd_pinctrl_probe,
+ .remove = sprd_pinctrl_remove,
+ .shutdown = sprd_pinctrl_shutdown,
+};
+module_platform_driver(sprd_pinctrl_driver);
+
+MODULE_DESCRIPTION("UNISOC Pin Controller Driver");
+MODULE_AUTHOR("linhua xu <linhua.xu@unisoc.com>");
+MODULE_LICENSE("GPL");
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V2 5/6] pinctrl: sprd: Increase the range of register values
2023-09-08 5:51 [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linhua Xu
` (3 preceding siblings ...)
2023-09-08 5:51 ` [PATCH V2 4/6] pinctrl: sprd: Add pinctrl support for UMS512 Linhua Xu
@ 2023-09-08 5:51 ` Linhua Xu
2023-09-11 9:55 ` Andy Shevchenko
2023-09-12 8:37 ` Baolin Wang
2023-09-08 5:51 ` [PATCH V2 6/6] pinctrl: sprd: Add pinctrl support for UMS9621 Linhua Xu
2023-09-11 13:41 ` [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linus Walleij
6 siblings, 2 replies; 22+ messages in thread
From: Linhua Xu @ 2023-09-08 5:51 UTC (permalink / raw)
To: Linus Walleij
Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Linhua Xu, Zhirong Qiu, Xiongpeng Wu
From: Linhua Xu <Linhua.Xu@unisoc.com>
As the UNISOC pin controller version iterates, more registers are required
to meet new functional requirements. Thus modify them.
Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
---
drivers/pinctrl/sprd/pinctrl-sprd.h | 30 +++++++++++++++--------------
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.h b/drivers/pinctrl/sprd/pinctrl-sprd.h
index a696f81ce663..5357874186fd 100644
--- a/drivers/pinctrl/sprd/pinctrl-sprd.h
+++ b/drivers/pinctrl/sprd/pinctrl-sprd.h
@@ -7,30 +7,32 @@
#ifndef __PINCTRL_SPRD_H__
#define __PINCTRL_SPRD_H__
+#include <linux/bits.h>
+
struct platform_device;
-#define NUM_OFFSET (20)
-#define TYPE_OFFSET (16)
-#define BIT_OFFSET (8)
-#define WIDTH_OFFSET (4)
+#define NUM_OFFSET 22
+#define TYPE_OFFSET 18
+#define BIT_OFFSET 10
+#define WIDTH_OFFSET 6
#define SPRD_PIN_INFO(num, type, offset, width, reg) \
- (((num) & 0xFFF) << NUM_OFFSET | \
- ((type) & 0xF) << TYPE_OFFSET | \
- ((offset) & 0xFF) << BIT_OFFSET | \
- ((width) & 0xF) << WIDTH_OFFSET | \
- ((reg) & 0xF))
+ (((num) & GENMASK(10, 0)) << NUM_OFFSET | \
+ ((type) & GENMASK(3, 0)) << TYPE_OFFSET | \
+ ((offset) & GENMASK(7, 0)) << BIT_OFFSET | \
+ ((width) & GENMASK(3, 0)) << WIDTH_OFFSET | \
+ ((reg) & GENMASK(5, 0)))
#define SPRD_PINCTRL_PIN(pin) SPRD_PINCTRL_PIN_DATA(pin, #pin)
#define SPRD_PINCTRL_PIN_DATA(a, b) \
{ \
.name = b, \
- .num = (((a) >> NUM_OFFSET) & 0xfff), \
- .type = (((a) >> TYPE_OFFSET) & 0xf), \
- .bit_offset = (((a) >> BIT_OFFSET) & 0xff), \
- .bit_width = ((a) >> WIDTH_OFFSET & 0xf), \
- .reg = ((a) & 0xf) \
+ .num = (((a) & GENMASK(31, 22)) >> NUM_OFFSET), \
+ .type = (((a) & GENMASK(21, 18)) >> TYPE_OFFSET), \
+ .bit_offset = (((a) & GENMASK(17, 10)) >> BIT_OFFSET), \
+ .bit_width = (((a) & GENMASK(9, 6)) >> WIDTH_OFFSET), \
+ .reg = ((a) & GENMASK(5, 0)) \
}
enum pin_type {
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH V2 6/6] pinctrl: sprd: Add pinctrl support for UMS9621
2023-09-08 5:51 [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linhua Xu
` (4 preceding siblings ...)
2023-09-08 5:51 ` [PATCH V2 5/6] pinctrl: sprd: Increase the range of register values Linhua Xu
@ 2023-09-08 5:51 ` Linhua Xu
2023-09-11 9:56 ` Andy Shevchenko
2023-09-11 13:41 ` [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linus Walleij
6 siblings, 1 reply; 22+ messages in thread
From: Linhua Xu @ 2023-09-08 5:51 UTC (permalink / raw)
To: Linus Walleij
Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Linhua Xu, Zhirong Qiu, Xiongpeng Wu
From: Linhua Xu <Linhua.Xu@unisoc.com>
Add the pin control driver for UNISOC UMS9621 platform.
Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
---
drivers/pinctrl/sprd/Kconfig | 11 +
drivers/pinctrl/sprd/Makefile | 1 +
drivers/pinctrl/sprd/pinctrl-sprd-ums9621.c | 1117 +++++++++++++++++++
3 files changed, 1129 insertions(+)
create mode 100644 drivers/pinctrl/sprd/pinctrl-sprd-ums9621.c
diff --git a/drivers/pinctrl/sprd/Kconfig b/drivers/pinctrl/sprd/Kconfig
index a2a653c63137..b57f0555dfa6 100644
--- a/drivers/pinctrl/sprd/Kconfig
+++ b/drivers/pinctrl/sprd/Kconfig
@@ -30,3 +30,14 @@ config PINCTRL_SPRD_UMS512
Support pin drive capability configuration
Support pin pull-up and pull-down configuration
Support pin pull-up and pull-down configuration during sleep
+
+config PINCTRL_SPRD_UMS9621
+ tristate "Spreadtrum ums9621 pinctrl driver"
+ depends on ARCH_SPRD || COMPILE_TEST
+ select PINCTRL_SPRD
+ help
+ Say Y here to enable Spreadtrum ums512 pinctrl driver
+ Support pin function switching
+ Support pin drive capability configuration
+ Support pin pull-up and pull-down configuration
+ Support pin pull-up and pull-down configuration during sleep
diff --git a/drivers/pinctrl/sprd/Makefile b/drivers/pinctrl/sprd/Makefile
index e3509c2515c9..6c1946c664b7 100644
--- a/drivers/pinctrl/sprd/Makefile
+++ b/drivers/pinctrl/sprd/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_PINCTRL_SPRD) += pinctrl-sprd.o
obj-$(CONFIG_PINCTRL_SPRD_SC9860) += pinctrl-sprd-sc9860.o
obj-$(CONFIG_PINCTRL_SPRD_UMS512) += pinctrl-sprd-ums512.o
+obj-$(CONFIG_PINCTRL_SPRD_UMS9621) += pinctrl-sprd-ums9621.o
diff --git a/drivers/pinctrl/sprd/pinctrl-sprd-ums9621.c b/drivers/pinctrl/sprd/pinctrl-sprd-ums9621.c
new file mode 100644
index 000000000000..01d2e4d7ab28
--- /dev/null
+++ b/drivers/pinctrl/sprd/pinctrl-sprd-ums9621.c
@@ -0,0 +1,1117 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Unisoc ums9621 pinctrl driver
+ *
+ * Copyright (C) 2021 Unisoc, Inc.
+ * Author: zhirong.qiu <zhirong.qiu@unisoc.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-sprd.h"
+
+#define PINCTRL_REG_OFFSET 0x44
+#define PINCTRL_REG_MISC_OFFSET 0x444
+
+enum sprd_ums9621_pins {
+ /*sim_matrix_mtx_cfg*/
+ UMS9621_SIM_INF1_SYS_SEL = SPRD_PIN_INFO(0, GLOBAL_CTRL_PIN, 1, 1, 1),
+ UMS9621_SIM_INF0_SYS_SEL = SPRD_PIN_INFO(1, GLOBAL_CTRL_PIN, 0, 1, 1),
+
+ /*dmic_matrix_mtx_cfg*/
+ UMS9621_DMIC_INF2_SYS_SEL = SPRD_PIN_INFO(2, GLOBAL_CTRL_PIN, 2, 1, 2),
+ UMS9621_DMIC_INF1_SYS_SEL = SPRD_PIN_INFO(3, GLOBAL_CTRL_PIN, 1, 1, 2),
+ UMS9621_DMIC_INF0_SYS_SEL = SPRD_PIN_INFO(4, GLOBAL_CTRL_PIN, 0, 1, 2),
+
+ /*uart_matrix_mtx_cfg*/
+ UMS9621_UART_INF6_SYS_SEL = SPRD_PIN_INFO(5, GLOBAL_CTRL_PIN, 28, 4, 3),
+ UMS9621_UART_INF5_SYS_SEL = SPRD_PIN_INFO(6, GLOBAL_CTRL_PIN, 24, 4, 3),
+ UMS9621_UART_INF4_SYS_SEL = SPRD_PIN_INFO(7, GLOBAL_CTRL_PIN, 20, 4, 3),
+ UMS9621_UART_INF3_SYS_SEL = SPRD_PIN_INFO(8, GLOBAL_CTRL_PIN, 16, 4, 3),
+ UMS9621_UART_INF2_INF3_LOOP = SPRD_PIN_INFO(9, GLOBAL_CTRL_PIN, 15, 1, 3),
+ UMS9621_UART_INF2_INF4_LOOP = SPRD_PIN_INFO(10, GLOBAL_CTRL_PIN, 14, 1, 3),
+ UMS9621_UART_INF2_SYS_SEL = SPRD_PIN_INFO(11, GLOBAL_CTRL_PIN, 10, 4, 3),
+ UMS9621_UART_INF1_INF4_LOOP = SPRD_PIN_INFO(12, GLOBAL_CTRL_PIN, 9, 1, 3),
+ UMS9621_UART_INF1_INF3_LOOP = SPRD_PIN_INFO(13, GLOBAL_CTRL_PIN, 8, 1, 3),
+ UMS9621_UART_INF1_SYS_SEL = SPRD_PIN_INFO(14, GLOBAL_CTRL_PIN, 4, 4, 3),
+ UMS9621_UART_INF0_SYS_SEL = SPRD_PIN_INFO(15, GLOBAL_CTRL_PIN, 0, 4, 3),
+
+ /*uart_matrix_mtx_cfg1*/
+ UMS9621_UART_INF8_SYS_SEL = SPRD_PIN_INFO(16, GLOBAL_CTRL_PIN, 4, 4, 4),
+ UMS9621_UART_INF7_SYS_SEL = SPRD_PIN_INFO(17, GLOBAL_CTRL_PIN, 0, 4, 4),
+
+ /*iis_matrix_mtx_cfg*/
+ UMS9621_IIS_INF4_SYS_SEL = SPRD_PIN_INFO(18, GLOBAL_CTRL_PIN, 23, 5, 5),
+ UMS9621_IIS_INF3_SYS_SEL = SPRD_PIN_INFO(19, GLOBAL_CTRL_PIN, 18, 5, 5),
+ UMS9621_IIS_INF2_SYS_SEL = SPRD_PIN_INFO(20, GLOBAL_CTRL_PIN, 13, 5, 5),
+ UMS9621_IIS_INF1_INF2_LOOP = SPRD_PIN_INFO(21, GLOBAL_CTRL_PIN, 12, 1, 5),
+ UMS9621_IIS_INF1_SYS_SEL = SPRD_PIN_INFO(22, GLOBAL_CTRL_PIN, 7, 5, 5),
+ UMS9621_IIS_INF0_INF2_LOOP = SPRD_PIN_INFO(23, GLOBAL_CTRL_PIN, 6, 1, 5),
+ UMS9621_IIS_INF0_INF1_LOOP = SPRD_PIN_INFO(24, GLOBAL_CTRL_PIN, 5, 1, 5),
+ UMS9621_IIS_INF0_SYS_SEL = SPRD_PIN_INFO(25, GLOBAL_CTRL_PIN, 0, 5, 5),
+
+ /*iis_matrix_mtx_cfg1*/
+ UMS9621_IIS_INF6_SYS_SEL = SPRD_PIN_INFO(26, GLOBAL_CTRL_PIN, 5, 1, 6),
+ UMS9621_IIS_INF5_SYS_SEL = SPRD_PIN_INFO(27, GLOBAL_CTRL_PIN, 0, 5, 6),
+
+ /*spi_matrix_mtx_cfg*/
+ UMS9621_SPI_INF3_SYS_SEL = SPRD_PIN_INFO(28, GLOBAL_CTRL_PIN, 6, 2, 7),
+ UMS9621_SPI_INF2_SYS_SEL = SPRD_PIN_INFO(29, GLOBAL_CTRL_PIN, 4, 2, 7),
+ UMS9621_SPI_INF1_SYS_SEL = SPRD_PIN_INFO(30, GLOBAL_CTRL_PIN, 2, 2, 7),
+ UMS9621_SPI_INF0_SYS_SEL = SPRD_PIN_INFO(31, GLOBAL_CTRL_PIN, 0, 2, 7),
+
+ /*iic_matrix_mtx_cfg*/
+ UMS9621_IIC_INF7_SYS_SEL = SPRD_PIN_INFO(32, GLOBAL_CTRL_PIN, 28, 4, 8),
+ UMS9621_IIC_INF6_SYS_SEL = SPRD_PIN_INFO(33, GLOBAL_CTRL_PIN, 24, 4, 8),
+ UMS9621_IIC_INF5_SYS_SEL = SPRD_PIN_INFO(34, GLOBAL_CTRL_PIN, 20, 4, 8),
+ UMS9621_IIC_INF4_SYS_SEL = SPRD_PIN_INFO(35, GLOBAL_CTRL_PIN, 16, 4, 8),
+ UMS9621_IIC_INF3_SYS_SEL = SPRD_PIN_INFO(36, GLOBAL_CTRL_PIN, 12, 4, 8),
+ UMS9621_IIC_INF2_SYS_SEL = SPRD_PIN_INFO(37, GLOBAL_CTRL_PIN, 8, 4, 8),
+ UMS9621_IIC_INF1_SYS_SEL = SPRD_PIN_INFO(38, GLOBAL_CTRL_PIN, 4, 4, 8),
+ UMS9621_IIC_INF0_SYS_SEL = SPRD_PIN_INFO(39, GLOBAL_CTRL_PIN, 0, 4, 8),
+
+ /*iic_matrix_mtx_cfg1*/
+ UMS9621_IIC_INF9_SYS_SEL = SPRD_PIN_INFO(40, GLOBAL_CTRL_PIN, 4, 4, 9),
+ UMS9621_IIC_INF8_SYS_SEL = SPRD_PIN_INFO(41, GLOBAL_CTRL_PIN, 0, 4, 9),
+
+ /*hot_plug_matrix_mtx_cfg*/
+ UMS9621_HOT_PLUG_DET_INF2_SYS_SEL = SPRD_PIN_INFO(42, GLOBAL_CTRL_PIN, 4, 2, 10),
+ UMS9621_HOT_PLUG_DET_INF1_SYS_SEL = SPRD_PIN_INFO(43, GLOBAL_CTRL_PIN, 2, 2, 10),
+ UMS9621_HOT_PLUG_DET_INF0_SYS_SEL = SPRD_PIN_INFO(44, GLOBAL_CTRL_PIN, 0, 2, 10),
+
+ /*PIN_CTRL_REG0*/
+ UMS9621_PIN_CTRL_REG0_FUNC_CFG = SPRD_PIN_INFO(45, GLOBAL_CTRL_PIN, 0, 1, 11),
+
+ /*PIN_CTRL_REG1*/
+ UMS9621_PIN_CTRL_REG1_FUNC_CFG = SPRD_PIN_INFO(46, GLOBAL_CTRL_PIN, 0, 0, 12),
+
+ /*PIN_CTRL_REG2*/
+ UMS9621_UART_USB_PHY_SEL = SPRD_PIN_INFO(47, GLOBAL_CTRL_PIN, 29, 3, 13),
+
+
+ /*PIN_CTRL_REG3*/
+ UMS9621_CH_EIC_DPAD3 = SPRD_PIN_INFO(48, GLOBAL_CTRL_PIN, 24, 8, 14),
+ UMS9621_CH_EIC_DPAD2 = SPRD_PIN_INFO(49, GLOBAL_CTRL_PIN, 16, 8, 14),
+ UMS9621_CH_EIC_DPAD1 = SPRD_PIN_INFO(50, GLOBAL_CTRL_PIN, 8, 8, 14),
+ UMS9621_CH_EIC_DPAD0 = SPRD_PIN_INFO(51, GLOBAL_CTRL_PIN, 0, 8, 14),
+
+ /*PIN_CTRL_REG4*/
+ UMS9621_CH_EIC_DPAD7 = SPRD_PIN_INFO(52, GLOBAL_CTRL_PIN, 24, 8, 15),
+ UMS9621_CH_EIC_DPAD6 = SPRD_PIN_INFO(53, GLOBAL_CTRL_PIN, 16, 8, 15),
+ UMS9621_CH_EIC_DPAD5 = SPRD_PIN_INFO(54, GLOBAL_CTRL_PIN, 8, 8, 15),
+ UMS9621_CH_EIC_DPAD4 = SPRD_PIN_INFO(55, GLOBAL_CTRL_PIN, 0, 8, 15),
+
+ /*PIN_CTRL_REG5*/
+ UMS9621_CORE_OUT_WDGRST_SOUR_SEL = SPRD_PIN_INFO(56, GLOBAL_CTRL_PIN, 28, 4, 16),
+ UMS9621_VBC_IIS_INF_SYS_SEL = SPRD_PIN_INFO(57, GLOBAL_CTRL_PIN, 20, 1, 16),
+ UMS9621_VAD_DIN_SEL = SPRD_PIN_INFO(58, GLOBAL_CTRL_PIN, 19, 1, 16),
+ UMS9621_TF_DET_SW = SPRD_PIN_INFO(59, GLOBAL_CTRL_PIN, 10, 1, 16),
+ UMS9621_CORE_IN_TF_DET_MUX = SPRD_PIN_INFO(60, GLOBAL_CTRL_PIN, 8, 2, 16),
+ UMS9621_SIM1_DET_SW = SPRD_PIN_INFO(61, GLOBAL_CTRL_PIN, 6, 1, 16),
+ UMS9621_CORE_IN_SIM1_DET_MUX = SPRD_PIN_INFO(62, GLOBAL_CTRL_PIN, 4, 2, 16),
+ UMS9621_SIM0_DET_SW = SPRD_PIN_INFO(63, GLOBAL_CTRL_PIN, 2, 1, 16),
+ UMS9621_CORE_IN_SIM0_DET_MUX = SPRD_PIN_INFO(64, GLOBAL_CTRL_PIN, 0, 2, 16),
+
+ /* Common pin registers definitions */
+ UMS9621_SD1_CMD = SPRD_PIN_INFO(65, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD1_D0 = SPRD_PIN_INFO(66, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD1_D1 = SPRD_PIN_INFO(67, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD1_CLK = SPRD_PIN_INFO(68, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD1_D2 = SPRD_PIN_INFO(69, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD1_D3 = SPRD_PIN_INFO(70, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_RST = SPRD_PIN_INFO(71, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_CMD = SPRD_PIN_INFO(72, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_D0 = SPRD_PIN_INFO(73, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_D3 = SPRD_PIN_INFO(74, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_D2 = SPRD_PIN_INFO(75, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_D5 = SPRD_PIN_INFO(76, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_CLK = SPRD_PIN_INFO(77, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_DS = SPRD_PIN_INFO(78, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_D1 = SPRD_PIN_INFO(79, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_D4 = SPRD_PIN_INFO(80, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_D6 = SPRD_PIN_INFO(81, COMMON_PIN, 0, 0, 0),
+ UMS9621_EMMC_D7 = SPRD_PIN_INFO(82, COMMON_PIN, 0, 0, 0),
+ UMS9621_DNS_D0 = SPRD_PIN_INFO(83, COMMON_PIN, 0, 0, 0),
+ UMS9621_DNS_D1 = SPRD_PIN_INFO(84, COMMON_PIN, 0, 0, 0),
+ UMS9621_LCM0_RSTN = SPRD_PIN_INFO(85, COMMON_PIN, 0, 0, 0),
+ UMS9621_DSI0_TE = SPRD_PIN_INFO(86, COMMON_PIN, 0, 0, 0),
+ UMS9621_PWMA = SPRD_PIN_INFO(87, COMMON_PIN, 0, 0, 0),
+ UMS9621_EXTINT0 = SPRD_PIN_INFO(88, COMMON_PIN, 0, 0, 0),
+ UMS9621_EXTINT1 = SPRD_PIN_INFO(89, COMMON_PIN, 0, 0, 0),
+ UMS9621_SDA3 = SPRD_PIN_INFO(90, COMMON_PIN, 0, 0, 0),
+ UMS9621_SCL3 = SPRD_PIN_INFO(91, COMMON_PIN, 0, 0, 0),
+ UMS9621_DCDC_ARM1_EN = SPRD_PIN_INFO(92, COMMON_PIN, 0, 0, 0),
+ UMS9621_PTEST = SPRD_PIN_INFO(93, COMMON_PIN, 0, 0, 0),
+ UMS9621_EXT_RST_B = SPRD_PIN_INFO(94, COMMON_PIN, 0, 0, 0),
+ UMS9621_ADI_SCLK = SPRD_PIN_INFO(95, COMMON_PIN, 0, 0, 0),
+ UMS9621_CLK_32K = SPRD_PIN_INFO(96, COMMON_PIN, 0, 0, 0),
+ UMS9621_ANA_INT1 = SPRD_PIN_INFO(97, COMMON_PIN, 0, 0, 0),
+ UMS9621_ANA_INT0 = SPRD_PIN_INFO(98, COMMON_PIN, 0, 0, 0),
+ UMS9621_ANA_INT2 = SPRD_PIN_INFO(99, COMMON_PIN, 0, 0, 0),
+ UMS9621_ADI_D = SPRD_PIN_INFO(100, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_SCLK = SPRD_PIN_INFO(101, COMMON_PIN, 0, 0, 0),
+ UMS9621_DCDC_ARM0_EN = SPRD_PIN_INFO(102, COMMON_PIN, 0, 0, 0),
+ UMS9621_DCDC_ARM2_EN = SPRD_PIN_INFO(103, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_ADD0 = SPRD_PIN_INFO(104, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_ADD1 = SPRD_PIN_INFO(105, COMMON_PIN, 0, 0, 0),
+ UMS9621_XTL_EN0 = SPRD_PIN_INFO(106, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_ADSYNC = SPRD_PIN_INFO(107, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_DAD0 = SPRD_PIN_INFO(108, COMMON_PIN, 0, 0, 0),
+ UMS9621_XTL_EN1 = SPRD_PIN_INFO(109, COMMON_PIN, 0, 0, 0),
+ UMS9621_XTL_EN2 = SPRD_PIN_INFO(110, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_DASYNC = SPRD_PIN_INFO(111, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_DAD1 = SPRD_PIN_INFO(112, COMMON_PIN, 0, 0, 0),
+ UMS9621_CHIP_SLEEP = SPRD_PIN_INFO(113, COMMON_PIN, 0, 0, 0),
+ UMS9621_CHG_TYPE = SPRD_PIN_INFO(114, COMMON_PIN, 0, 0, 0),
+ UMS9621_SIMCLK0 = SPRD_PIN_INFO(115, COMMON_PIN, 0, 0, 0),
+ UMS9621_SIMDA0 = SPRD_PIN_INFO(116, COMMON_PIN, 0, 0, 0),
+ UMS9621_SIMRST0 = SPRD_PIN_INFO(117, COMMON_PIN, 0, 0, 0),
+ UMS9621_SIMCLK1 = SPRD_PIN_INFO(118, COMMON_PIN, 0, 0, 0),
+ UMS9621_SIMDA1 = SPRD_PIN_INFO(119, COMMON_PIN, 0, 0, 0),
+ UMS9621_SIMRST1 = SPRD_PIN_INFO(120, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD0_CMD = SPRD_PIN_INFO(121, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD0_D_0 = SPRD_PIN_INFO(122, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD0_D_1 = SPRD_PIN_INFO(123, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD0_CLK = SPRD_PIN_INFO(124, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD0_D_2 = SPRD_PIN_INFO(125, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD0_D_3 = SPRD_PIN_INFO(126, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD2_CLK = SPRD_PIN_INFO(127, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD2_D1 = SPRD_PIN_INFO(128, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD2_CMD = SPRD_PIN_INFO(129, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD2_D0 = SPRD_PIN_INFO(130, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD2_D2 = SPRD_PIN_INFO(131, COMMON_PIN, 0, 0, 0),
+ UMS9621_SD2_D3 = SPRD_PIN_INFO(132, COMMON_PIN, 0, 0, 0),
+ UMS9621_SIM_DET0 = SPRD_PIN_INFO(133, COMMON_PIN, 0, 0, 0),
+ UMS9621_SIM_DET1 = SPRD_PIN_INFO(134, COMMON_PIN, 0, 0, 0),
+ UMS9621_TF_DET = SPRD_PIN_INFO(135, COMMON_PIN, 0, 0, 0),
+ UMS9621_BAT_DET = SPRD_PIN_INFO(136, COMMON_PIN, 0, 0, 0),
+ UMS9621_SCL4 = SPRD_PIN_INFO(137, COMMON_PIN, 0, 0, 0),
+ UMS9621_SDA4 = SPRD_PIN_INFO(138, COMMON_PIN, 0, 0, 0),
+ UMS9621_CLK_AUX1 = SPRD_PIN_INFO(139, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS1DI = SPRD_PIN_INFO(140, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS1DO = SPRD_PIN_INFO(141, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS1CLK = SPRD_PIN_INFO(142, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS1LRCK = SPRD_PIN_INFO(143, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS3DI = SPRD_PIN_INFO(144, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS3DO = SPRD_PIN_INFO(145, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS3LRCK = SPRD_PIN_INFO(146, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS3CLK = SPRD_PIN_INFO(147, COMMON_PIN, 0, 0, 0),
+ UMS9621_CLK_AUX2 = SPRD_PIN_INFO(148, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_0 = SPRD_PIN_INFO(149, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_1 = SPRD_PIN_INFO(150, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_2 = SPRD_PIN_INFO(151, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_3 = SPRD_PIN_INFO(152, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_4 = SPRD_PIN_INFO(153, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_5 = SPRD_PIN_INFO(154, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_6 = SPRD_PIN_INFO(155, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_7 = SPRD_PIN_INFO(156, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_8 = SPRD_PIN_INFO(157, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_9 = SPRD_PIN_INFO(158, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_10 = SPRD_PIN_INFO(159, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_11 = SPRD_PIN_INFO(160, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_12 = SPRD_PIN_INFO(161, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_13 = SPRD_PIN_INFO(162, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_14 = SPRD_PIN_INFO(163, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFCTL_15 = SPRD_PIN_INFO(164, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE0_SCK = SPRD_PIN_INFO(165, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE0_SDA = SPRD_PIN_INFO(166, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE1_SCK = SPRD_PIN_INFO(167, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE1_SDA = SPRD_PIN_INFO(168, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE2_SCK = SPRD_PIN_INFO(169, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE2_SDA = SPRD_PIN_INFO(170, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE3_SCK = SPRD_PIN_INFO(171, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE3_SDA = SPRD_PIN_INFO(172, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE4_SCK = SPRD_PIN_INFO(173, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE4_SDA = SPRD_PIN_INFO(174, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE5_SCK = SPRD_PIN_INFO(175, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE5_SDA = SPRD_PIN_INFO(176, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE6_SCK = SPRD_PIN_INFO(177, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE6_SDA = SPRD_PIN_INFO(178, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE7_SCK = SPRD_PIN_INFO(179, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFFE7_SDA = SPRD_PIN_INFO(180, COMMON_PIN, 0, 0, 0),
+ UMS9621_LVDSRF_ADDAC0_ON = SPRD_PIN_INFO(181, COMMON_PIN, 0, 0, 0),
+ UMS9621_LVDSRF_ADDAC1_ON = SPRD_PIN_INFO(182, COMMON_PIN, 0, 0, 0),
+ UMS9621_LVDSRF_ADDAC2_ON = SPRD_PIN_INFO(183, COMMON_PIN, 0, 0, 0),
+ UMS9621_LVDSRF_ADDAC3_ON = SPRD_PIN_INFO(184, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SDA0 = SPRD_PIN_INFO(185, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SDA1 = SPRD_PIN_INFO(186, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SDA2 = SPRD_PIN_INFO(187, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SDA3 = SPRD_PIN_INFO(188, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SCK = SPRD_PIN_INFO(189, COMMON_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SEN = SPRD_PIN_INFO(190, COMMON_PIN, 0, 0, 0),
+ UMS9621_SCL6 = SPRD_PIN_INFO(191, COMMON_PIN, 0, 0, 0),
+ UMS9621_SDA6 = SPRD_PIN_INFO(192, COMMON_PIN, 0, 0, 0),
+ UMS9621_VDSP_TDO = SPRD_PIN_INFO(193, COMMON_PIN, 0, 0, 0),
+ UMS9621_VDSP_TDI = SPRD_PIN_INFO(194, COMMON_PIN, 0, 0, 0),
+ UMS9621_VDSP_TMS = SPRD_PIN_INFO(195, COMMON_PIN, 0, 0, 0),
+ UMS9621_VDSP_TCK = SPRD_PIN_INFO(196, COMMON_PIN, 0, 0, 0),
+ UMS9621_VDSP_RTCK = SPRD_PIN_INFO(197, COMMON_PIN, 0, 0, 0),
+ UMS9621_DMIC_CLK2 = SPRD_PIN_INFO(198, COMMON_PIN, 0, 0, 0),
+ UMS9621_DMIC_DATA2 = SPRD_PIN_INFO(199, COMMON_PIN, 0, 0, 0),
+ UMS9621_DMIC_CLK0 = SPRD_PIN_INFO(200, COMMON_PIN, 0, 0, 0),
+ UMS9621_DMIC_DATA0 = SPRD_PIN_INFO(201, COMMON_PIN, 0, 0, 0),
+ UMS9621_DMIC_CLK1 = SPRD_PIN_INFO(202, COMMON_PIN, 0, 0, 0),
+ UMS9621_DMIC_DATA1 = SPRD_PIN_INFO(203, COMMON_PIN, 0, 0, 0),
+ UMS9621_U2TXD = SPRD_PIN_INFO(204, COMMON_PIN, 0, 0, 0),
+ UMS9621_U2RXD = SPRD_PIN_INFO(205, COMMON_PIN, 0, 0, 0),
+ UMS9621_U1TXD = SPRD_PIN_INFO(206, COMMON_PIN, 0, 0, 0),
+ UMS9621_U1RXD = SPRD_PIN_INFO(207, COMMON_PIN, 0, 0, 0),
+ UMS9621_U7TXD = SPRD_PIN_INFO(208, COMMON_PIN, 0, 0, 0),
+ UMS9621_U7RXD = SPRD_PIN_INFO(209, COMMON_PIN, 0, 0, 0),
+ UMS9621_U6TXD = SPRD_PIN_INFO(210, COMMON_PIN, 0, 0, 0),
+ UMS9621_U6RXD = SPRD_PIN_INFO(211, COMMON_PIN, 0, 0, 0),
+ UMS9621_MTCK_ARM = SPRD_PIN_INFO(212, COMMON_PIN, 0, 0, 0),
+ UMS9621_MTMS_ARM = SPRD_PIN_INFO(213, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_TDO = SPRD_PIN_INFO(214, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_RTCK = SPRD_PIN_INFO(215, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_TDI = SPRD_PIN_INFO(216, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_TCK = SPRD_PIN_INFO(217, COMMON_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_TMS = SPRD_PIN_INFO(218, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMMCLK0 = SPRD_PIN_INFO(219, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMMCLK1 = SPRD_PIN_INFO(220, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMMCLK2 = SPRD_PIN_INFO(221, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMMCLK3 = SPRD_PIN_INFO(222, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMRST0 = SPRD_PIN_INFO(223, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMRST1 = SPRD_PIN_INFO(224, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMRST2 = SPRD_PIN_INFO(225, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMRST3 = SPRD_PIN_INFO(226, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMRST4 = SPRD_PIN_INFO(227, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMRST5 = SPRD_PIN_INFO(228, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMPD0 = SPRD_PIN_INFO(229, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMPD1 = SPRD_PIN_INFO(230, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMPD2 = SPRD_PIN_INFO(231, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMPD3 = SPRD_PIN_INFO(232, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMPD4 = SPRD_PIN_INFO(233, COMMON_PIN, 0, 0, 0),
+ UMS9621_CMPD5 = SPRD_PIN_INFO(234, COMMON_PIN, 0, 0, 0),
+ UMS9621_SCL0 = SPRD_PIN_INFO(235, COMMON_PIN, 0, 0, 0),
+ UMS9621_SDA0 = SPRD_PIN_INFO(236, COMMON_PIN, 0, 0, 0),
+ UMS9621_SCL1 = SPRD_PIN_INFO(237, COMMON_PIN, 0, 0, 0),
+ UMS9621_SDA1 = SPRD_PIN_INFO(238, COMMON_PIN, 0, 0, 0),
+ UMS9621_SCL8 = SPRD_PIN_INFO(239, COMMON_PIN, 0, 0, 0),
+ UMS9621_SDA8 = SPRD_PIN_INFO(240, COMMON_PIN, 0, 0, 0),
+ UMS9621_SCL9 = SPRD_PIN_INFO(241, COMMON_PIN, 0, 0, 0),
+ UMS9621_SDA9 = SPRD_PIN_INFO(242, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI2_CSN = SPRD_PIN_INFO(243, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI2_DO = SPRD_PIN_INFO(244, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI2_DI = SPRD_PIN_INFO(245, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI2_CLK = SPRD_PIN_INFO(246, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI3_CSN = SPRD_PIN_INFO(247, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI3_CLK = SPRD_PIN_INFO(248, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI3_DI = SPRD_PIN_INFO(249, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI3_DO = SPRD_PIN_INFO(250, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI0_CSN = SPRD_PIN_INFO(251, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI0_DO = SPRD_PIN_INFO(252, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI0_DI = SPRD_PIN_INFO(253, COMMON_PIN, 0, 0, 0),
+ UMS9621_SPI0_CLK = SPRD_PIN_INFO(254, COMMON_PIN, 0, 0, 0),
+ UMS9621_SCL2 = SPRD_PIN_INFO(255, COMMON_PIN, 0, 0, 0),
+ UMS9621_SDA2 = SPRD_PIN_INFO(256, COMMON_PIN, 0, 0, 0),
+ UMS9621_KEYOUT1 = SPRD_PIN_INFO(257, COMMON_PIN, 0, 0, 0),
+ UMS9621_KEYOUT0 = SPRD_PIN_INFO(258, COMMON_PIN, 0, 0, 0),
+ UMS9621_KEYOUT2 = SPRD_PIN_INFO(259, COMMON_PIN, 0, 0, 0),
+ UMS9621_EXTINT9 = SPRD_PIN_INFO(260, COMMON_PIN, 0, 0, 0),
+ UMS9621_EXTINT10 = SPRD_PIN_INFO(261, COMMON_PIN, 0, 0, 0),
+ UMS9621_KEYIN0 = SPRD_PIN_INFO(262, COMMON_PIN, 0, 0, 0),
+ UMS9621_KEYIN1 = SPRD_PIN_INFO(263, COMMON_PIN, 0, 0, 0),
+ UMS9621_KEYIN2 = SPRD_PIN_INFO(264, COMMON_PIN, 0, 0, 0),
+ UMS9621_U5TXD = SPRD_PIN_INFO(265, COMMON_PIN, 0, 0, 0),
+ UMS9621_U5RXD = SPRD_PIN_INFO(266, COMMON_PIN, 0, 0, 0),
+ UMS9621_CLK_AUX0 = SPRD_PIN_INFO(267, COMMON_PIN, 0, 0, 0),
+ UMS9621_U0TXD = SPRD_PIN_INFO(268, COMMON_PIN, 0, 0, 0),
+ UMS9621_U0RXD = SPRD_PIN_INFO(269, COMMON_PIN, 0, 0, 0),
+ UMS9621_U0CTS = SPRD_PIN_INFO(270, COMMON_PIN, 0, 0, 0),
+ UMS9621_U0RTS = SPRD_PIN_INFO(271, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS0DI = SPRD_PIN_INFO(272, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS0DO = SPRD_PIN_INFO(273, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS0CLK = SPRD_PIN_INFO(274, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS0LRCK = SPRD_PIN_INFO(275, COMMON_PIN, 0, 0, 0),
+ UMS9621_PWMC = SPRD_PIN_INFO(276, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS4DO = SPRD_PIN_INFO(277, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS4DI = SPRD_PIN_INFO(278, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS4CLK = SPRD_PIN_INFO(279, COMMON_PIN, 0, 0, 0),
+ UMS9621_IIS4LRCK = SPRD_PIN_INFO(280, COMMON_PIN, 0, 0, 0),
+ UMS9621_U4TXD = SPRD_PIN_INFO(281, COMMON_PIN, 0, 0, 0),
+ UMS9621_U4RXD = SPRD_PIN_INFO(282, COMMON_PIN, 0, 0, 0),
+ UMS9621_U4CTS = SPRD_PIN_INFO(283, COMMON_PIN, 0, 0, 0),
+ UMS9621_U4RTS = SPRD_PIN_INFO(284, COMMON_PIN, 0, 0, 0),
+
+ /* MSIC pin registers definitions */
+ UMS9621_SD1_CMD_MISC = SPRD_PIN_INFO(285, MISC_PIN, 0, 0, 0),
+ UMS9621_SD1_D0_MISC = SPRD_PIN_INFO(286, MISC_PIN, 0, 0, 0),
+ UMS9621_SD1_D1_MISC = SPRD_PIN_INFO(287, MISC_PIN, 0, 0, 0),
+ UMS9621_SD1_CLK_MISC = SPRD_PIN_INFO(288, MISC_PIN, 0, 0, 0),
+ UMS9621_SD1_D2_MISC = SPRD_PIN_INFO(289, MISC_PIN, 0, 0, 0),
+ UMS9621_SD1_D3_MISC = SPRD_PIN_INFO(290, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_RST_MISC = SPRD_PIN_INFO(291, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_CMD_MISC = SPRD_PIN_INFO(292, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_D0_MISC = SPRD_PIN_INFO(293, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_D3_MISC = SPRD_PIN_INFO(294, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_D2_MISC = SPRD_PIN_INFO(295, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_D5_MISC = SPRD_PIN_INFO(296, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_CLK_MISC = SPRD_PIN_INFO(297, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_DS_MISC = SPRD_PIN_INFO(298, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_D1_MISC = SPRD_PIN_INFO(299, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_D4_MISC = SPRD_PIN_INFO(300, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_D6_MISC = SPRD_PIN_INFO(301, MISC_PIN, 0, 0, 0),
+ UMS9621_EMMC_D7_MISC = SPRD_PIN_INFO(302, MISC_PIN, 0, 0, 0),
+ UMS9621_DNS_D0_MISC = SPRD_PIN_INFO(303, MISC_PIN, 0, 0, 0),
+ UMS9621_DNS_D1_MISC = SPRD_PIN_INFO(304, MISC_PIN, 0, 0, 0),
+ UMS9621_LCM0_RSTN_MISC = SPRD_PIN_INFO(305, MISC_PIN, 0, 0, 0),
+ UMS9621_DSI0_TE_MISC = SPRD_PIN_INFO(306, MISC_PIN, 0, 0, 0),
+ UMS9621_PWMA_MISC = SPRD_PIN_INFO(307, MISC_PIN, 0, 0, 0),
+ UMS9621_EXTINT0_MISC = SPRD_PIN_INFO(308, MISC_PIN, 0, 0, 0),
+ UMS9621_EXTINT1_MISC = SPRD_PIN_INFO(309, MISC_PIN, 0, 0, 0),
+ UMS9621_SDA3_MISC = SPRD_PIN_INFO(310, MISC_PIN, 0, 0, 0),
+ UMS9621_SCL3_MISC = SPRD_PIN_INFO(311, MISC_PIN, 0, 0, 0),
+ UMS9621_DCDC_ARM1_EN_MISC = SPRD_PIN_INFO(312, MISC_PIN, 0, 0, 0),
+ UMS9621_PTEST_MISC = SPRD_PIN_INFO(313, MISC_PIN, 0, 0, 0),
+ UMS9621_EXT_RST_B_MISC = SPRD_PIN_INFO(314, MISC_PIN, 0, 0, 0),
+ UMS9621_ADI_SCLK_MISC = SPRD_PIN_INFO(315, MISC_PIN, 0, 0, 0),
+ UMS9621_CLK_32K_MISC = SPRD_PIN_INFO(316, MISC_PIN, 0, 0, 0),
+ UMS9621_ANA_INT1_MISC = SPRD_PIN_INFO(317, MISC_PIN, 0, 0, 0),
+ UMS9621_ANA_INT0_MISC = SPRD_PIN_INFO(318, MISC_PIN, 0, 0, 0),
+ UMS9621_ANA_INT2_MISC = SPRD_PIN_INFO(319, MISC_PIN, 0, 0, 0),
+ UMS9621_ADI_D_MISC = SPRD_PIN_INFO(320, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_SCLK_MISC = SPRD_PIN_INFO(321, MISC_PIN, 0, 0, 0),
+ UMS9621_DCDC_ARM0_EN_MISC = SPRD_PIN_INFO(322, MISC_PIN, 0, 0, 0),
+ UMS9621_DCDC_ARM2_EN_MISC = SPRD_PIN_INFO(323, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_ADD0_MISC = SPRD_PIN_INFO(324, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_ADD1_MISC = SPRD_PIN_INFO(325, MISC_PIN, 0, 0, 0),
+ UMS9621_XTL_EN0_MISC = SPRD_PIN_INFO(326, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_ADSYNC_MISC = SPRD_PIN_INFO(327, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_DAD0_MISC = SPRD_PIN_INFO(328, MISC_PIN, 0, 0, 0),
+ UMS9621_XTL_EN1_MISC = SPRD_PIN_INFO(329, MISC_PIN, 0, 0, 0),
+ UMS9621_XTL_EN2_MISC = SPRD_PIN_INFO(330, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_DASYNC_MISC = SPRD_PIN_INFO(331, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_DAD1_MISC = SPRD_PIN_INFO(332, MISC_PIN, 0, 0, 0),
+ UMS9621_CHIP_SLEEP_MISC = SPRD_PIN_INFO(333, MISC_PIN, 0, 0, 0),
+ UMS9621_CHG_TYPE_MISC = SPRD_PIN_INFO(334, MISC_PIN, 0, 0, 0),
+ UMS9621_SIMCLK0_MISC = SPRD_PIN_INFO(335, MISC_PIN, 0, 0, 0),
+ UMS9621_SIMDA0_MISC = SPRD_PIN_INFO(336, MISC_PIN, 0, 0, 0),
+ UMS9621_SIMRST0_MISC = SPRD_PIN_INFO(337, MISC_PIN, 0, 0, 0),
+ UMS9621_SIMCLK1_MISC = SPRD_PIN_INFO(338, MISC_PIN, 0, 0, 0),
+ UMS9621_SIMDA1_MISC = SPRD_PIN_INFO(339, MISC_PIN, 0, 0, 0),
+ UMS9621_SIMRST1_MISC = SPRD_PIN_INFO(340, MISC_PIN, 0, 0, 0),
+ UMS9621_SD0_CMD_MISC = SPRD_PIN_INFO(341, MISC_PIN, 0, 0, 0),
+ UMS9621_SD0_D_0_MISC = SPRD_PIN_INFO(342, MISC_PIN, 0, 0, 0),
+ UMS9621_SD0_D_1_MISC = SPRD_PIN_INFO(343, MISC_PIN, 0, 0, 0),
+ UMS9621_SD0_CLK_MISC = SPRD_PIN_INFO(344, MISC_PIN, 0, 0, 0),
+ UMS9621_SD0_D_2_MISC = SPRD_PIN_INFO(345, MISC_PIN, 0, 0, 0),
+ UMS9621_SD0_D_3_MISC = SPRD_PIN_INFO(346, MISC_PIN, 0, 0, 0),
+ UMS9621_SD2_CLK_MISC = SPRD_PIN_INFO(347, MISC_PIN, 0, 0, 0),
+ UMS9621_SD2_D1_MISC = SPRD_PIN_INFO(348, MISC_PIN, 0, 0, 0),
+ UMS9621_SD2_CMD_MISC = SPRD_PIN_INFO(349, MISC_PIN, 0, 0, 0),
+ UMS9621_SD2_D0_MISC = SPRD_PIN_INFO(350, MISC_PIN, 0, 0, 0),
+ UMS9621_SD2_D2_MISC = SPRD_PIN_INFO(351, MISC_PIN, 0, 0, 0),
+ UMS9621_SD2_D3_MISC = SPRD_PIN_INFO(352, MISC_PIN, 0, 0, 0),
+ UMS9621_SIM_DET0_MISC = SPRD_PIN_INFO(353, MISC_PIN, 0, 0, 0),
+ UMS9621_SIM_DET1_MISC = SPRD_PIN_INFO(354, MISC_PIN, 0, 0, 0),
+ UMS9621_TF_DET_MISC = SPRD_PIN_INFO(355, MISC_PIN, 0, 0, 0),
+ UMS9621_BAT_DET_MISC = SPRD_PIN_INFO(356, MISC_PIN, 0, 0, 0),
+ UMS9621_SCL4_MISC = SPRD_PIN_INFO(357, MISC_PIN, 0, 0, 0),
+ UMS9621_SDA4_MISC = SPRD_PIN_INFO(358, MISC_PIN, 0, 0, 0),
+ UMS9621_CLK_AUX1_MISC = SPRD_PIN_INFO(359, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS1DI_MISC = SPRD_PIN_INFO(360, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS1DO_MISC = SPRD_PIN_INFO(361, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS1CLK_MISC = SPRD_PIN_INFO(362, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS1LRCK_MISC = SPRD_PIN_INFO(363, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS3DI_MISC = SPRD_PIN_INFO(364, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS3DO_MISC = SPRD_PIN_INFO(365, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS3LRCK_MISC = SPRD_PIN_INFO(366, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS3CLK_MISC = SPRD_PIN_INFO(367, MISC_PIN, 0, 0, 0),
+ UMS9621_CLK_AUX2_MISC = SPRD_PIN_INFO(368, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_0_MISC = SPRD_PIN_INFO(369, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_1_MISC = SPRD_PIN_INFO(370, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_2_MISC = SPRD_PIN_INFO(371, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_3_MISC = SPRD_PIN_INFO(372, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_4_MISC = SPRD_PIN_INFO(373, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_5_MISC = SPRD_PIN_INFO(374, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_6_MISC = SPRD_PIN_INFO(375, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_7_MISC = SPRD_PIN_INFO(376, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_8_MISC = SPRD_PIN_INFO(377, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_9_MISC = SPRD_PIN_INFO(378, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_10_MISC = SPRD_PIN_INFO(379, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_11_MISC = SPRD_PIN_INFO(380, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_12_MISC = SPRD_PIN_INFO(381, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_13_MISC = SPRD_PIN_INFO(382, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_14_MISC = SPRD_PIN_INFO(383, MISC_PIN, 0, 0, 0),
+ UMS9621_RFCTL_15_MISC = SPRD_PIN_INFO(384, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE0_SCK_MISC = SPRD_PIN_INFO(385, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE0_SDA_MISC = SPRD_PIN_INFO(386, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE1_SCK_MISC = SPRD_PIN_INFO(387, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE1_SDA_MISC = SPRD_PIN_INFO(388, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE2_SCK_MISC = SPRD_PIN_INFO(389, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE2_SDA_MISC = SPRD_PIN_INFO(390, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE3_SCK_MISC = SPRD_PIN_INFO(391, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE3_SDA_MISC = SPRD_PIN_INFO(392, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE4_SCK_MISC = SPRD_PIN_INFO(393, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE4_SDA_MISC = SPRD_PIN_INFO(394, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE5_SCK_MISC = SPRD_PIN_INFO(395, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE5_SDA_MISC = SPRD_PIN_INFO(396, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE6_SCK_MISC = SPRD_PIN_INFO(397, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE6_SDA_MISC = SPRD_PIN_INFO(398, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE7_SCK_MISC = SPRD_PIN_INFO(399, MISC_PIN, 0, 0, 0),
+ UMS9621_RFFE7_SDA_MISC = SPRD_PIN_INFO(400, MISC_PIN, 0, 0, 0),
+ UMS9621_LVDSRF_ADDAC0_ON_MISC = SPRD_PIN_INFO(401, MISC_PIN, 0, 0, 0),
+ UMS9621_LVDSRF_ADDAC1_ON_MISC = SPRD_PIN_INFO(402, MISC_PIN, 0, 0, 0),
+ UMS9621_LVDSRF_ADDAC2_ON_MISC = SPRD_PIN_INFO(403, MISC_PIN, 0, 0, 0),
+ UMS9621_LVDSRF_ADDAC3_ON_MISC = SPRD_PIN_INFO(404, MISC_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SDA0_MISC = SPRD_PIN_INFO(405, MISC_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SDA1_MISC = SPRD_PIN_INFO(406, MISC_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SDA2_MISC = SPRD_PIN_INFO(407, MISC_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SDA3_MISC = SPRD_PIN_INFO(408, MISC_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SCK_MISC = SPRD_PIN_INFO(409, MISC_PIN, 0, 0, 0),
+ UMS9621_RFSPI_SEN_MISC = SPRD_PIN_INFO(410, MISC_PIN, 0, 0, 0),
+ UMS9621_SCL6_MISC = SPRD_PIN_INFO(411, MISC_PIN, 0, 0, 0),
+ UMS9621_SDA6_MISC = SPRD_PIN_INFO(412, MISC_PIN, 0, 0, 0),
+ UMS9621_VDSP_TDO_MISC = SPRD_PIN_INFO(413, MISC_PIN, 0, 0, 0),
+ UMS9621_VDSP_TDI_MISC = SPRD_PIN_INFO(414, MISC_PIN, 0, 0, 0),
+ UMS9621_VDSP_TMS_MISC = SPRD_PIN_INFO(415, MISC_PIN, 0, 0, 0),
+ UMS9621_VDSP_TCK_MISC = SPRD_PIN_INFO(416, MISC_PIN, 0, 0, 0),
+ UMS9621_VDSP_RTCK_MISC = SPRD_PIN_INFO(417, MISC_PIN, 0, 0, 0),
+ UMS9621_DMIC_CLK2_MISC = SPRD_PIN_INFO(418, MISC_PIN, 0, 0, 0),
+ UMS9621_DMIC_DATA2_MISC = SPRD_PIN_INFO(419, MISC_PIN, 0, 0, 0),
+ UMS9621_DMIC_CLK0_MISC = SPRD_PIN_INFO(420, MISC_PIN, 0, 0, 0),
+ UMS9621_DMIC_DATA0_MISC = SPRD_PIN_INFO(421, MISC_PIN, 0, 0, 0),
+ UMS9621_DMIC_CLK1_MISC = SPRD_PIN_INFO(422, MISC_PIN, 0, 0, 0),
+ UMS9621_DMIC_DATA1_MISC = SPRD_PIN_INFO(423, MISC_PIN, 0, 0, 0),
+ UMS9621_U2TXD_MISC = SPRD_PIN_INFO(424, MISC_PIN, 0, 0, 0),
+ UMS9621_U2RXD_MISC = SPRD_PIN_INFO(425, MISC_PIN, 0, 0, 0),
+ UMS9621_U1TXD_MISC = SPRD_PIN_INFO(426, MISC_PIN, 0, 0, 0),
+ UMS9621_U1RXD_MISC = SPRD_PIN_INFO(427, MISC_PIN, 0, 0, 0),
+ UMS9621_U7TXD_MISC = SPRD_PIN_INFO(428, MISC_PIN, 0, 0, 0),
+ UMS9621_U7RXD_MISC = SPRD_PIN_INFO(429, MISC_PIN, 0, 0, 0),
+ UMS9621_U6TXD_MISC = SPRD_PIN_INFO(430, MISC_PIN, 0, 0, 0),
+ UMS9621_U6RXD_MISC = SPRD_PIN_INFO(431, MISC_PIN, 0, 0, 0),
+ UMS9621_MTCK_ARM_MISC = SPRD_PIN_INFO(432, MISC_PIN, 0, 0, 0),
+ UMS9621_MTMS_ARM_MISC = SPRD_PIN_INFO(433, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_TDO_MISC = SPRD_PIN_INFO(434, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_RTCK_MISC = SPRD_PIN_INFO(435, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_TDI_MISC = SPRD_PIN_INFO(436, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_TCK_MISC = SPRD_PIN_INFO(437, MISC_PIN, 0, 0, 0),
+ UMS9621_AUD_DSP_TMS_MISC = SPRD_PIN_INFO(438, MISC_PIN, 0, 0, 0),
+ UMS9621_CMMCLK0_MISC = SPRD_PIN_INFO(439, MISC_PIN, 0, 0, 0),
+ UMS9621_CMMCLK1_MISC = SPRD_PIN_INFO(440, MISC_PIN, 0, 0, 0),
+ UMS9621_CMMCLK2_MISC = SPRD_PIN_INFO(441, MISC_PIN, 0, 0, 0),
+ UMS9621_CMMCLK3_MISC = SPRD_PIN_INFO(442, MISC_PIN, 0, 0, 0),
+ UMS9621_CMRST0_MISC = SPRD_PIN_INFO(443, MISC_PIN, 0, 0, 0),
+ UMS9621_CMRST1_MISC = SPRD_PIN_INFO(444, MISC_PIN, 0, 0, 0),
+ UMS9621_CMRST2_MISC = SPRD_PIN_INFO(445, MISC_PIN, 0, 0, 0),
+ UMS9621_CMRST3_MISC = SPRD_PIN_INFO(446, MISC_PIN, 0, 0, 0),
+ UMS9621_CMRST4_MISC = SPRD_PIN_INFO(447, MISC_PIN, 0, 0, 0),
+ UMS9621_CMRST5_MISC = SPRD_PIN_INFO(448, MISC_PIN, 0, 0, 0),
+ UMS9621_CMPD0_MISC = SPRD_PIN_INFO(449, MISC_PIN, 0, 0, 0),
+ UMS9621_CMPD1_MISC = SPRD_PIN_INFO(450, MISC_PIN, 0, 0, 0),
+ UMS9621_CMPD2_MISC = SPRD_PIN_INFO(451, MISC_PIN, 0, 0, 0),
+ UMS9621_CMPD3_MISC = SPRD_PIN_INFO(452, MISC_PIN, 0, 0, 0),
+ UMS9621_CMPD4_MISC = SPRD_PIN_INFO(453, MISC_PIN, 0, 0, 0),
+ UMS9621_CMPD5_MISC = SPRD_PIN_INFO(454, MISC_PIN, 0, 0, 0),
+ UMS9621_SCL0_MISC = SPRD_PIN_INFO(455, MISC_PIN, 0, 0, 0),
+ UMS9621_SDA0_MISC = SPRD_PIN_INFO(456, MISC_PIN, 0, 0, 0),
+ UMS9621_SCL1_MISC = SPRD_PIN_INFO(457, MISC_PIN, 0, 0, 0),
+ UMS9621_SDA1_MISC = SPRD_PIN_INFO(458, MISC_PIN, 0, 0, 0),
+ UMS9621_SCL8_MISC = SPRD_PIN_INFO(459, MISC_PIN, 0, 0, 0),
+ UMS9621_SDA8_MISC = SPRD_PIN_INFO(460, MISC_PIN, 0, 0, 0),
+ UMS9621_SCL9_MISC = SPRD_PIN_INFO(461, MISC_PIN, 0, 0, 0),
+ UMS9621_SDA9_MISC = SPRD_PIN_INFO(462, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI2_CSN_MISC = SPRD_PIN_INFO(463, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI2_DO_MISC = SPRD_PIN_INFO(464, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI2_DI_MISC = SPRD_PIN_INFO(465, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI2_CLK_MISC = SPRD_PIN_INFO(466, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI3_CSN_MISC = SPRD_PIN_INFO(467, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI3_CLK_MISC = SPRD_PIN_INFO(468, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI3_DI_MISC = SPRD_PIN_INFO(469, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI3_DO_MISC = SPRD_PIN_INFO(470, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI0_CSN_MISC = SPRD_PIN_INFO(471, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI0_DO_MISC = SPRD_PIN_INFO(472, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI0_DI_MISC = SPRD_PIN_INFO(473, MISC_PIN, 0, 0, 0),
+ UMS9621_SPI0_CLK_MISC = SPRD_PIN_INFO(474, MISC_PIN, 0, 0, 0),
+ UMS9621_SCL2_MISC = SPRD_PIN_INFO(475, MISC_PIN, 0, 0, 0),
+ UMS9621_SDA2_MISC = SPRD_PIN_INFO(476, MISC_PIN, 0, 0, 0),
+ UMS9621_KEYOUT1_MISC = SPRD_PIN_INFO(477, MISC_PIN, 0, 0, 0),
+ UMS9621_KEYOUT0_MISC = SPRD_PIN_INFO(478, MISC_PIN, 0, 0, 0),
+ UMS9621_KEYOUT2_MISC = SPRD_PIN_INFO(479, MISC_PIN, 0, 0, 0),
+ UMS9621_EXTINT9_MISC = SPRD_PIN_INFO(480, MISC_PIN, 0, 0, 0),
+ UMS9621_EXTINT10_MISC = SPRD_PIN_INFO(481, MISC_PIN, 0, 0, 0),
+ UMS9621_KEYIN0_MISC = SPRD_PIN_INFO(482, MISC_PIN, 0, 0, 0),
+ UMS9621_KEYIN1_MISC = SPRD_PIN_INFO(483, MISC_PIN, 0, 0, 0),
+ UMS9621_KEYIN2_MISC = SPRD_PIN_INFO(484, MISC_PIN, 0, 0, 0),
+ UMS9621_U5TXD_MISC = SPRD_PIN_INFO(485, MISC_PIN, 0, 0, 0),
+ UMS9621_U5RXD_MISC = SPRD_PIN_INFO(486, MISC_PIN, 0, 0, 0),
+ UMS9621_CLK_AUX0_MISC = SPRD_PIN_INFO(487, MISC_PIN, 0, 0, 0),
+ UMS9621_U0TXD_MISC = SPRD_PIN_INFO(488, MISC_PIN, 0, 0, 0),
+ UMS9621_U0RXD_MISC = SPRD_PIN_INFO(489, MISC_PIN, 0, 0, 0),
+ UMS9621_U0CTS_MISC = SPRD_PIN_INFO(490, MISC_PIN, 0, 0, 0),
+ UMS9621_U0RTS_MISC = SPRD_PIN_INFO(491, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS0DI_MISC = SPRD_PIN_INFO(492, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS0DO_MISC = SPRD_PIN_INFO(493, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS0CLK_MISC = SPRD_PIN_INFO(494, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS0LRCK_MISC = SPRD_PIN_INFO(495, MISC_PIN, 0, 0, 0),
+ UMS9621_PWMC_MISC = SPRD_PIN_INFO(496, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS4DO_MISC = SPRD_PIN_INFO(497, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS4DI_MISC = SPRD_PIN_INFO(498, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS4CLK_MISC = SPRD_PIN_INFO(499, MISC_PIN, 0, 0, 0),
+ UMS9621_IIS4LRCK_MISC = SPRD_PIN_INFO(500, MISC_PIN, 0, 0, 0),
+ UMS9621_U4TXD_MISC = SPRD_PIN_INFO(501, MISC_PIN, 0, 0, 0),
+ UMS9621_U4RXD_MISC = SPRD_PIN_INFO(502, MISC_PIN, 0, 0, 0),
+ UMS9621_U4CTS_MISC = SPRD_PIN_INFO(503, MISC_PIN, 0, 0, 0),
+ UMS9621_U4RTS_MISC = SPRD_PIN_INFO(504, MISC_PIN, 0, 0, 0),
+
+};
+
+static struct sprd_pins_info sprd_ums9621_pins_info[] = {
+
+ SPRD_PINCTRL_PIN(UMS9621_SIM_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_SIM_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF6_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF5_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF4_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF3_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF2_INF3_LOOP),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF2_INF4_LOOP),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF1_INF4_LOOP),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF1_INF3_LOOP),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF8_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_UART_INF7_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF4_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF3_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF1_INF2_LOOP),
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF0_INF2_LOOP),
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF0_INF1_LOOP),
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF6_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIS_INF5_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_SPI_INF3_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_SPI_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_SPI_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_SPI_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF7_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF6_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF5_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF4_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF3_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF9_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_IIC_INF8_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_HOT_PLUG_DET_INF2_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_HOT_PLUG_DET_INF1_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_HOT_PLUG_DET_INF0_SYS_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_PIN_CTRL_REG0_FUNC_CFG),
+
+ SPRD_PINCTRL_PIN(UMS9621_PIN_CTRL_REG1_FUNC_CFG),
+
+ SPRD_PINCTRL_PIN(UMS9621_UART_USB_PHY_SEL),
+
+ SPRD_PINCTRL_PIN(UMS9621_CH_EIC_DPAD3),
+ SPRD_PINCTRL_PIN(UMS9621_CH_EIC_DPAD2),
+ SPRD_PINCTRL_PIN(UMS9621_CH_EIC_DPAD1),
+ SPRD_PINCTRL_PIN(UMS9621_CH_EIC_DPAD0),
+
+ SPRD_PINCTRL_PIN(UMS9621_CH_EIC_DPAD7),
+ SPRD_PINCTRL_PIN(UMS9621_CH_EIC_DPAD6),
+ SPRD_PINCTRL_PIN(UMS9621_CH_EIC_DPAD5),
+ SPRD_PINCTRL_PIN(UMS9621_CH_EIC_DPAD4),
+
+ SPRD_PINCTRL_PIN(UMS9621_CORE_OUT_WDGRST_SOUR_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_VBC_IIS_INF_SYS_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_VAD_DIN_SEL),
+ SPRD_PINCTRL_PIN(UMS9621_TF_DET_SW),
+ SPRD_PINCTRL_PIN(UMS9621_CORE_IN_TF_DET_MUX),
+ SPRD_PINCTRL_PIN(UMS9621_SIM1_DET_SW),
+ SPRD_PINCTRL_PIN(UMS9621_CORE_IN_SIM1_DET_MUX),
+ SPRD_PINCTRL_PIN(UMS9621_SIM0_DET_SW),
+ SPRD_PINCTRL_PIN(UMS9621_CORE_IN_SIM0_DET_MUX),
+
+ SPRD_PINCTRL_PIN(UMS9621_SD1_CMD),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_D0),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_D1),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_CLK),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_D2),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_D3),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_RST),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_CMD),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D0),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D3),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D2),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D5),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_CLK),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_DS),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D1),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D4),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D6),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D7),
+ SPRD_PINCTRL_PIN(UMS9621_DNS_D0),
+ SPRD_PINCTRL_PIN(UMS9621_DNS_D1),
+ SPRD_PINCTRL_PIN(UMS9621_LCM0_RSTN),
+ SPRD_PINCTRL_PIN(UMS9621_DSI0_TE),
+ SPRD_PINCTRL_PIN(UMS9621_PWMA),
+ SPRD_PINCTRL_PIN(UMS9621_EXTINT0),
+ SPRD_PINCTRL_PIN(UMS9621_EXTINT1),
+ SPRD_PINCTRL_PIN(UMS9621_SDA3),
+ SPRD_PINCTRL_PIN(UMS9621_SCL3),
+ SPRD_PINCTRL_PIN(UMS9621_DCDC_ARM1_EN),
+ SPRD_PINCTRL_PIN(UMS9621_PTEST),
+ SPRD_PINCTRL_PIN(UMS9621_EXT_RST_B),
+ SPRD_PINCTRL_PIN(UMS9621_ADI_SCLK),
+ SPRD_PINCTRL_PIN(UMS9621_CLK_32K),
+ SPRD_PINCTRL_PIN(UMS9621_ANA_INT1),
+ SPRD_PINCTRL_PIN(UMS9621_ANA_INT0),
+ SPRD_PINCTRL_PIN(UMS9621_ANA_INT2),
+ SPRD_PINCTRL_PIN(UMS9621_ADI_D),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_SCLK),
+ SPRD_PINCTRL_PIN(UMS9621_DCDC_ARM0_EN),
+ SPRD_PINCTRL_PIN(UMS9621_DCDC_ARM2_EN),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_ADD0),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_ADD1),
+ SPRD_PINCTRL_PIN(UMS9621_XTL_EN0),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_ADSYNC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DAD0),
+ SPRD_PINCTRL_PIN(UMS9621_XTL_EN1),
+ SPRD_PINCTRL_PIN(UMS9621_XTL_EN2),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DASYNC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DAD1),
+ SPRD_PINCTRL_PIN(UMS9621_CHIP_SLEEP),
+ SPRD_PINCTRL_PIN(UMS9621_CHG_TYPE),
+ SPRD_PINCTRL_PIN(UMS9621_SIMCLK0),
+ SPRD_PINCTRL_PIN(UMS9621_SIMDA0),
+ SPRD_PINCTRL_PIN(UMS9621_SIMRST0),
+ SPRD_PINCTRL_PIN(UMS9621_SIMCLK1),
+ SPRD_PINCTRL_PIN(UMS9621_SIMDA1),
+ SPRD_PINCTRL_PIN(UMS9621_SIMRST1),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_CMD),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_D_0),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_D_1),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_CLK),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_D_2),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_D_3),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_CLK),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_D1),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_CMD),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_D0),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_D2),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_D3),
+ SPRD_PINCTRL_PIN(UMS9621_SIM_DET0),
+ SPRD_PINCTRL_PIN(UMS9621_SIM_DET1),
+ SPRD_PINCTRL_PIN(UMS9621_TF_DET),
+ SPRD_PINCTRL_PIN(UMS9621_BAT_DET),
+ SPRD_PINCTRL_PIN(UMS9621_SCL4),
+ SPRD_PINCTRL_PIN(UMS9621_SDA4),
+ SPRD_PINCTRL_PIN(UMS9621_CLK_AUX1),
+ SPRD_PINCTRL_PIN(UMS9621_IIS1DI),
+ SPRD_PINCTRL_PIN(UMS9621_IIS1DO),
+ SPRD_PINCTRL_PIN(UMS9621_IIS1CLK),
+ SPRD_PINCTRL_PIN(UMS9621_IIS1LRCK),
+ SPRD_PINCTRL_PIN(UMS9621_IIS3DI),
+ SPRD_PINCTRL_PIN(UMS9621_IIS3DO),
+ SPRD_PINCTRL_PIN(UMS9621_IIS3LRCK),
+ SPRD_PINCTRL_PIN(UMS9621_IIS3CLK),
+ SPRD_PINCTRL_PIN(UMS9621_CLK_AUX2),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_0),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_1),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_2),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_3),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_4),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_5),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_6),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_7),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_8),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_9),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_10),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_11),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_12),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_13),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_14),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_15),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE0_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE0_SDA),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE1_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE1_SDA),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE2_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE2_SDA),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE3_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE3_SDA),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE4_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE4_SDA),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE5_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE5_SDA),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE6_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE6_SDA),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE7_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE7_SDA),
+ SPRD_PINCTRL_PIN(UMS9621_LVDSRF_ADDAC0_ON),
+ SPRD_PINCTRL_PIN(UMS9621_LVDSRF_ADDAC1_ON),
+ SPRD_PINCTRL_PIN(UMS9621_LVDSRF_ADDAC2_ON),
+ SPRD_PINCTRL_PIN(UMS9621_LVDSRF_ADDAC3_ON),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SDA0),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SDA1),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SDA2),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SDA3),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SCK),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SEN),
+ SPRD_PINCTRL_PIN(UMS9621_SCL6),
+ SPRD_PINCTRL_PIN(UMS9621_SDA6),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_TDO),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_TDI),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_TMS),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_TCK),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_RTCK),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_CLK2),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_DATA2),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_CLK0),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_DATA0),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_CLK1),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_DATA1),
+ SPRD_PINCTRL_PIN(UMS9621_U2TXD),
+ SPRD_PINCTRL_PIN(UMS9621_U2RXD),
+ SPRD_PINCTRL_PIN(UMS9621_U1TXD),
+ SPRD_PINCTRL_PIN(UMS9621_U1RXD),
+ SPRD_PINCTRL_PIN(UMS9621_U7TXD),
+ SPRD_PINCTRL_PIN(UMS9621_U7RXD),
+ SPRD_PINCTRL_PIN(UMS9621_U6TXD),
+ SPRD_PINCTRL_PIN(UMS9621_U6RXD),
+ SPRD_PINCTRL_PIN(UMS9621_MTCK_ARM),
+ SPRD_PINCTRL_PIN(UMS9621_MTMS_ARM),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_TDO),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_RTCK),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_TDI),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_TCK),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_TMS),
+ SPRD_PINCTRL_PIN(UMS9621_CMMCLK0),
+ SPRD_PINCTRL_PIN(UMS9621_CMMCLK1),
+ SPRD_PINCTRL_PIN(UMS9621_CMMCLK2),
+ SPRD_PINCTRL_PIN(UMS9621_CMMCLK3),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST0),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST1),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST2),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST3),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST4),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST5),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD0),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD1),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD2),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD3),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD4),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD5),
+ SPRD_PINCTRL_PIN(UMS9621_SCL0),
+ SPRD_PINCTRL_PIN(UMS9621_SDA0),
+ SPRD_PINCTRL_PIN(UMS9621_SCL1),
+ SPRD_PINCTRL_PIN(UMS9621_SDA1),
+ SPRD_PINCTRL_PIN(UMS9621_SCL8),
+ SPRD_PINCTRL_PIN(UMS9621_SDA8),
+ SPRD_PINCTRL_PIN(UMS9621_SCL9),
+ SPRD_PINCTRL_PIN(UMS9621_SDA9),
+ SPRD_PINCTRL_PIN(UMS9621_SPI2_CSN),
+ SPRD_PINCTRL_PIN(UMS9621_SPI2_DO),
+ SPRD_PINCTRL_PIN(UMS9621_SPI2_DI),
+ SPRD_PINCTRL_PIN(UMS9621_SPI2_CLK),
+ SPRD_PINCTRL_PIN(UMS9621_SPI3_CSN),
+ SPRD_PINCTRL_PIN(UMS9621_SPI3_CLK),
+ SPRD_PINCTRL_PIN(UMS9621_SPI3_DI),
+ SPRD_PINCTRL_PIN(UMS9621_SPI3_DO),
+ SPRD_PINCTRL_PIN(UMS9621_SPI0_CSN),
+ SPRD_PINCTRL_PIN(UMS9621_SPI0_DO),
+ SPRD_PINCTRL_PIN(UMS9621_SPI0_DI),
+ SPRD_PINCTRL_PIN(UMS9621_SPI0_CLK),
+ SPRD_PINCTRL_PIN(UMS9621_SCL2),
+ SPRD_PINCTRL_PIN(UMS9621_SDA2),
+ SPRD_PINCTRL_PIN(UMS9621_KEYOUT1),
+ SPRD_PINCTRL_PIN(UMS9621_KEYOUT0),
+ SPRD_PINCTRL_PIN(UMS9621_KEYOUT2),
+ SPRD_PINCTRL_PIN(UMS9621_EXTINT9),
+ SPRD_PINCTRL_PIN(UMS9621_EXTINT10),
+ SPRD_PINCTRL_PIN(UMS9621_KEYIN0),
+ SPRD_PINCTRL_PIN(UMS9621_KEYIN1),
+ SPRD_PINCTRL_PIN(UMS9621_KEYIN2),
+ SPRD_PINCTRL_PIN(UMS9621_U5TXD),
+ SPRD_PINCTRL_PIN(UMS9621_U5RXD),
+ SPRD_PINCTRL_PIN(UMS9621_CLK_AUX0),
+ SPRD_PINCTRL_PIN(UMS9621_U0TXD),
+ SPRD_PINCTRL_PIN(UMS9621_U0RXD),
+ SPRD_PINCTRL_PIN(UMS9621_U0CTS),
+ SPRD_PINCTRL_PIN(UMS9621_U0RTS),
+ SPRD_PINCTRL_PIN(UMS9621_IIS0DI),
+ SPRD_PINCTRL_PIN(UMS9621_IIS0DO),
+ SPRD_PINCTRL_PIN(UMS9621_IIS0CLK),
+ SPRD_PINCTRL_PIN(UMS9621_IIS0LRCK),
+ SPRD_PINCTRL_PIN(UMS9621_PWMC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS4DO),
+ SPRD_PINCTRL_PIN(UMS9621_IIS4DI),
+ SPRD_PINCTRL_PIN(UMS9621_IIS4CLK),
+ SPRD_PINCTRL_PIN(UMS9621_IIS4LRCK),
+ SPRD_PINCTRL_PIN(UMS9621_U4TXD),
+ SPRD_PINCTRL_PIN(UMS9621_U4RXD),
+ SPRD_PINCTRL_PIN(UMS9621_U4CTS),
+ SPRD_PINCTRL_PIN(UMS9621_U4RTS),
+
+ SPRD_PINCTRL_PIN(UMS9621_SD1_CMD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_D2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD1_D3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_RST_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_CMD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D5_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_DS_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D4_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D6_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EMMC_D7_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DNS_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DNS_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_LCM0_RSTN_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DSI0_TE_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_PWMA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EXTINT0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EXTINT1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SDA3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SCL3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DCDC_ARM1_EN_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_PTEST_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EXT_RST_B_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_ADI_SCLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CLK_32K_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_ANA_INT1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_ANA_INT0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_ANA_INT2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_ADI_D_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_SCLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DCDC_ARM0_EN_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DCDC_ARM2_EN_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_ADD0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_ADD1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_XTL_EN0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_ADSYNC_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DAD0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_XTL_EN1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_XTL_EN2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DASYNC_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DAD1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CHIP_SLEEP_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CHG_TYPE_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SIMCLK0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SIMDA0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SIMRST0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SIMCLK1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SIMDA1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SIMRST1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_CMD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_D_0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_D_1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_D_2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD0_D_3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_D1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_CMD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_D0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_D2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SD2_D3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SIM_DET0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SIM_DET1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_TF_DET_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_BAT_DET_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SCL4_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SDA4_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CLK_AUX1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS1DI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS1DO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS1CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS1LRCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS3DI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS3DO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS3LRCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS3CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CLK_AUX2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_4_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_5_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_6_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_7_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_8_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_9_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_10_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_11_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_12_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_13_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_14_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFCTL_15_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE0_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE0_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE1_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE1_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE2_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE2_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE3_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE3_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE4_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE4_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE5_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE5_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE6_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE6_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE7_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFFE7_SDA_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_LVDSRF_ADDAC0_ON_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_LVDSRF_ADDAC1_ON_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_LVDSRF_ADDAC2_ON_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_LVDSRF_ADDAC3_ON_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SDA0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SDA1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SDA2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SDA3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_RFSPI_SEN_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SCL6_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SDA6_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_TDO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_TDI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_TMS_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_TCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_VDSP_RTCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_CLK2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_DATA2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_CLK0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_DATA0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_CLK1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_DMIC_DATA1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U2TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U2RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U1TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U1RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U7TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U7RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U6TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U6RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_MTCK_ARM_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_MTMS_ARM_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_TDO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_RTCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_TDI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_TCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_AUD_DSP_TMS_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMMCLK0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMMCLK1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMMCLK2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMMCLK3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST4_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMRST5_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD3_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD4_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CMPD5_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SCL0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SDA0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SCL1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SDA1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SCL8_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SDA8_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SCL9_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SDA9_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI2_CSN_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI2_DO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI2_DI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI2_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI3_CSN_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI3_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI3_DI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI3_DO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI0_CSN_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI0_DO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI0_DI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SPI0_CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SCL2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_SDA2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_KEYOUT1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_KEYOUT0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_KEYOUT2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EXTINT9_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_EXTINT10_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_KEYIN0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_KEYIN1_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_KEYIN2_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U5TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U5RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_CLK_AUX0_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U0TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U0RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U0CTS_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U0RTS_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS0DI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS0DO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS0CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS0LRCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_PWMC_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS4DO_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS4DI_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS4CLK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_IIS4LRCK_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U4TXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U4RXD_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U4CTS_MISC),
+ SPRD_PINCTRL_PIN(UMS9621_U4RTS_MISC),
+};
+
+static int sprd_pinctrl_probe(struct platform_device *pdev)
+{
+ return sprd_pinctrl_core_probe(pdev, sprd_ums9621_pins_info,
+ ARRAY_SIZE(sprd_ums9621_pins_info),
+ PINCTRL_REG_OFFSET,
+ PINCTRL_REG_MISC_OFFSET);
+}
+
+static const struct of_device_id sprd_pinctrl_of_match[] = {
+ { .compatible = "sprd,ums9621-pinctrl", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, sprd_pinctrl_of_match);
+
+static struct platform_driver sprd_pinctrl_driver = {
+ .driver = {
+ .name = "sprd-pinctrl",
+ .of_match_table = sprd_pinctrl_of_match,
+ },
+ .probe = sprd_pinctrl_probe,
+ .remove = sprd_pinctrl_remove,
+ .shutdown = sprd_pinctrl_shutdown,
+};
+module_platform_driver(sprd_pinctrl_driver);
+
+MODULE_DESCRIPTION("UNISOC Pin Controller Driver");
+MODULE_AUTHOR("zhirong qiu <zhirong.qiu@unisoc.com>");
+MODULE_LICENSE("GPL");
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH V2 4/6] pinctrl: sprd: Add pinctrl support for UMS512
2023-09-08 5:51 ` [PATCH V2 4/6] pinctrl: sprd: Add pinctrl support for UMS512 Linhua Xu
@ 2023-09-09 1:56 ` kernel test robot
2023-09-11 9:53 ` Andy Shevchenko
1 sibling, 0 replies; 22+ messages in thread
From: kernel test robot @ 2023-09-09 1:56 UTC (permalink / raw)
To: Linhua Xu, Linus Walleij
Cc: oe-kbuild-all, Orson Zhai, Baolin Wang, Chunyan Zhang,
linux-kernel, linux-gpio, Andy Shevchenko, lh xu, Linhua Xu,
Zhirong Qiu, Xiongpeng Wu
Hi Linhua,
kernel test robot noticed the following build errors:
[auto build test ERROR on linusw-pinctrl/devel]
[also build test ERROR on linusw-pinctrl/for-next linus/master v6.5 next-20230908]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Linhua-Xu/pinctrl-sprd-Modify-the-probe-function-parameters/20230908-135519
base: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
patch link: https://lore.kernel.org/r/20230908055146.18347-5-Linhua.xu%40unisoc.com
patch subject: [PATCH V2 4/6] pinctrl: sprd: Add pinctrl support for UMS512
config: alpha-randconfig-r011-20230909 (https://download.01.org/0day-ci/archive/20230909/202309090904.PsOH9TGp-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230909/202309090904.PsOH9TGp-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202309090904.PsOH9TGp-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/pinctrl/sprd/pinctrl-sprd.c: In function 'sprd_dt_node_to_map':
>> drivers/pinctrl/sprd/pinctrl-sprd.c:287:15: error: implicit declaration of function 'pinconf_generic_parse_dt_config'; did you mean 'pinconf_generic_dump_config'? [-Werror=implicit-function-declaration]
287 | ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| pinconf_generic_dump_config
cc1: some warnings being treated as errors
vim +287 drivers/pinctrl/sprd/pinctrl-sprd.c
41d32cfce1ae616 Baolin Wang 2017-08-17 246
41d32cfce1ae616 Baolin Wang 2017-08-17 247 static int sprd_dt_node_to_map(struct pinctrl_dev *pctldev,
41d32cfce1ae616 Baolin Wang 2017-08-17 248 struct device_node *np,
41d32cfce1ae616 Baolin Wang 2017-08-17 249 struct pinctrl_map **map,
41d32cfce1ae616 Baolin Wang 2017-08-17 250 unsigned int *num_maps)
41d32cfce1ae616 Baolin Wang 2017-08-17 251 {
41d32cfce1ae616 Baolin Wang 2017-08-17 252 struct sprd_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
41d32cfce1ae616 Baolin Wang 2017-08-17 253 const struct sprd_pin_group *grp;
41d32cfce1ae616 Baolin Wang 2017-08-17 254 unsigned long *configs = NULL;
41d32cfce1ae616 Baolin Wang 2017-08-17 255 unsigned int num_configs = 0;
41d32cfce1ae616 Baolin Wang 2017-08-17 256 unsigned int reserved_maps = 0;
41d32cfce1ae616 Baolin Wang 2017-08-17 257 unsigned int reserve = 0;
41d32cfce1ae616 Baolin Wang 2017-08-17 258 const char *function;
41d32cfce1ae616 Baolin Wang 2017-08-17 259 enum pinctrl_map_type type;
41d32cfce1ae616 Baolin Wang 2017-08-17 260 int ret;
41d32cfce1ae616 Baolin Wang 2017-08-17 261
41d32cfce1ae616 Baolin Wang 2017-08-17 262 grp = sprd_pinctrl_find_group_by_name(pctl, np->name);
41d32cfce1ae616 Baolin Wang 2017-08-17 263 if (!grp) {
41d32cfce1ae616 Baolin Wang 2017-08-17 264 dev_err(pctl->dev, "unable to find group for node %s\n",
41d32cfce1ae616 Baolin Wang 2017-08-17 265 of_node_full_name(np));
41d32cfce1ae616 Baolin Wang 2017-08-17 266 return -EINVAL;
41d32cfce1ae616 Baolin Wang 2017-08-17 267 }
41d32cfce1ae616 Baolin Wang 2017-08-17 268
41d32cfce1ae616 Baolin Wang 2017-08-17 269 ret = of_property_count_strings(np, "pins");
41d32cfce1ae616 Baolin Wang 2017-08-17 270 if (ret < 0)
41d32cfce1ae616 Baolin Wang 2017-08-17 271 return ret;
41d32cfce1ae616 Baolin Wang 2017-08-17 272
41d32cfce1ae616 Baolin Wang 2017-08-17 273 if (ret == 1)
41d32cfce1ae616 Baolin Wang 2017-08-17 274 type = PIN_MAP_TYPE_CONFIGS_PIN;
41d32cfce1ae616 Baolin Wang 2017-08-17 275 else
41d32cfce1ae616 Baolin Wang 2017-08-17 276 type = PIN_MAP_TYPE_CONFIGS_GROUP;
41d32cfce1ae616 Baolin Wang 2017-08-17 277
41d32cfce1ae616 Baolin Wang 2017-08-17 278 ret = of_property_read_string(np, "function", &function);
41d32cfce1ae616 Baolin Wang 2017-08-17 279 if (ret < 0) {
41d32cfce1ae616 Baolin Wang 2017-08-17 280 if (ret != -EINVAL)
41d32cfce1ae616 Baolin Wang 2017-08-17 281 dev_err(pctl->dev,
41d32cfce1ae616 Baolin Wang 2017-08-17 282 "%s: could not parse property function\n",
41d32cfce1ae616 Baolin Wang 2017-08-17 283 of_node_full_name(np));
41d32cfce1ae616 Baolin Wang 2017-08-17 284 function = NULL;
41d32cfce1ae616 Baolin Wang 2017-08-17 285 }
41d32cfce1ae616 Baolin Wang 2017-08-17 286
41d32cfce1ae616 Baolin Wang 2017-08-17 @287 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
41d32cfce1ae616 Baolin Wang 2017-08-17 288 &num_configs);
41d32cfce1ae616 Baolin Wang 2017-08-17 289 if (ret < 0) {
41d32cfce1ae616 Baolin Wang 2017-08-17 290 dev_err(pctl->dev, "%s: could not parse node property\n",
41d32cfce1ae616 Baolin Wang 2017-08-17 291 of_node_full_name(np));
41d32cfce1ae616 Baolin Wang 2017-08-17 292 return ret;
41d32cfce1ae616 Baolin Wang 2017-08-17 293 }
41d32cfce1ae616 Baolin Wang 2017-08-17 294
41d32cfce1ae616 Baolin Wang 2017-08-17 295 *map = NULL;
41d32cfce1ae616 Baolin Wang 2017-08-17 296 *num_maps = 0;
41d32cfce1ae616 Baolin Wang 2017-08-17 297
41d32cfce1ae616 Baolin Wang 2017-08-17 298 if (function != NULL)
41d32cfce1ae616 Baolin Wang 2017-08-17 299 reserve++;
41d32cfce1ae616 Baolin Wang 2017-08-17 300 if (num_configs)
41d32cfce1ae616 Baolin Wang 2017-08-17 301 reserve++;
41d32cfce1ae616 Baolin Wang 2017-08-17 302
41d32cfce1ae616 Baolin Wang 2017-08-17 303 ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps,
41d32cfce1ae616 Baolin Wang 2017-08-17 304 num_maps, reserve);
41d32cfce1ae616 Baolin Wang 2017-08-17 305 if (ret < 0)
41d32cfce1ae616 Baolin Wang 2017-08-17 306 goto out;
41d32cfce1ae616 Baolin Wang 2017-08-17 307
41d32cfce1ae616 Baolin Wang 2017-08-17 308 if (function) {
41d32cfce1ae616 Baolin Wang 2017-08-17 309 ret = pinctrl_utils_add_map_mux(pctldev, map,
41d32cfce1ae616 Baolin Wang 2017-08-17 310 &reserved_maps, num_maps,
41d32cfce1ae616 Baolin Wang 2017-08-17 311 grp->name, function);
41d32cfce1ae616 Baolin Wang 2017-08-17 312 if (ret < 0)
41d32cfce1ae616 Baolin Wang 2017-08-17 313 goto out;
41d32cfce1ae616 Baolin Wang 2017-08-17 314 }
41d32cfce1ae616 Baolin Wang 2017-08-17 315
41d32cfce1ae616 Baolin Wang 2017-08-17 316 if (num_configs) {
41d32cfce1ae616 Baolin Wang 2017-08-17 317 const char *group_or_pin;
41d32cfce1ae616 Baolin Wang 2017-08-17 318 unsigned int pin_id;
41d32cfce1ae616 Baolin Wang 2017-08-17 319
41d32cfce1ae616 Baolin Wang 2017-08-17 320 if (type == PIN_MAP_TYPE_CONFIGS_PIN) {
41d32cfce1ae616 Baolin Wang 2017-08-17 321 pin_id = grp->pins[0];
41d32cfce1ae616 Baolin Wang 2017-08-17 322 group_or_pin = pin_get_name(pctldev, pin_id);
41d32cfce1ae616 Baolin Wang 2017-08-17 323 } else {
41d32cfce1ae616 Baolin Wang 2017-08-17 324 group_or_pin = grp->name;
41d32cfce1ae616 Baolin Wang 2017-08-17 325 }
41d32cfce1ae616 Baolin Wang 2017-08-17 326
41d32cfce1ae616 Baolin Wang 2017-08-17 327 ret = pinctrl_utils_add_map_configs(pctldev, map,
41d32cfce1ae616 Baolin Wang 2017-08-17 328 &reserved_maps, num_maps,
41d32cfce1ae616 Baolin Wang 2017-08-17 329 group_or_pin, configs,
41d32cfce1ae616 Baolin Wang 2017-08-17 330 num_configs, type);
41d32cfce1ae616 Baolin Wang 2017-08-17 331 }
41d32cfce1ae616 Baolin Wang 2017-08-17 332
41d32cfce1ae616 Baolin Wang 2017-08-17 333 out:
41d32cfce1ae616 Baolin Wang 2017-08-17 334 kfree(configs);
41d32cfce1ae616 Baolin Wang 2017-08-17 335 return ret;
41d32cfce1ae616 Baolin Wang 2017-08-17 336 }
41d32cfce1ae616 Baolin Wang 2017-08-17 337
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 1/6] pinctrl: sprd: Modify the probe function parameters
2023-09-08 5:51 ` [PATCH V2 1/6] pinctrl: sprd: Modify the probe function parameters Linhua Xu
@ 2023-09-11 9:46 ` Andy Shevchenko
2023-09-12 8:13 ` Baolin Wang
1 sibling, 0 replies; 22+ messages in thread
From: Andy Shevchenko @ 2023-09-11 9:46 UTC (permalink / raw)
To: Linhua Xu
Cc: Linus Walleij, Orson Zhai, Baolin Wang, Chunyan Zhang,
linux-kernel, linux-gpio, lh xu, Zhirong Qiu, Xiongpeng Wu
On Fri, Sep 08, 2023 at 01:51:41PM +0800, Linhua Xu wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> For UNISOC pin controller, the offset values of the common register and
> misc register will be different. Thus put these in the probe function
> parameters.
...
> +#define PINCTRL_REG_OFFSET 0x20
0x0020 to make it look as related to the other one, as they are of the same
type: register offsets.
> +#define PINCTRL_REG_MISC_OFFSET 0x4020
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition
2023-09-08 5:51 ` [PATCH V2 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition Linhua Xu
@ 2023-09-11 9:50 ` Andy Shevchenko
2023-09-12 8:28 ` Baolin Wang
2023-11-13 13:50 ` Linus Walleij
2 siblings, 0 replies; 22+ messages in thread
From: Andy Shevchenko @ 2023-09-11 9:50 UTC (permalink / raw)
To: Linhua Xu
Cc: Linus Walleij, Orson Zhai, Baolin Wang, Chunyan Zhang,
linux-kernel, linux-gpio, lh xu, Zhirong Qiu, Xiongpeng Wu
On Fri, Sep 08, 2023 at 01:51:42PM +0800, Linhua Xu wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> Pull-up and pull-down are mutually exclusive. When setting one of them,
> the bit of the other needs to be clear. Now, there are cases where pull-up
> and pull-down are set at the same time in the code, thus fix them.
...
> #define SLEEP_PULL_DOWN BIT(2)
> -#define SLEEP_PULL_DOWN_MASK 0x1
> +#define SLEEP_PULL_DOWN_MASK GENMASK(1, 0)
> #define SLEEP_PULL_DOWN_SHIFT 2
>
> #define PULL_DOWN BIT(6)
> -#define PULL_DOWN_MASK 0x1
> +#define PULL_DOWN_MASK (GENMASK(1, 0) | BIT(6))
> #define PULL_DOWN_SHIFT 6
>
> #define SLEEP_PULL_UP BIT(3)
> -#define SLEEP_PULL_UP_MASK 0x1
> -#define SLEEP_PULL_UP_SHIFT 3
> +#define SLEEP_PULL_UP_MASK GENMASK(1, 0)
> +#define SLEEP_PULL_UP_SHIFT 2
>
> #define PULL_UP_4_7K (BIT(12) | BIT(7))
> #define PULL_UP_20K BIT(7)
> -#define PULL_UP_MASK 0x21
> -#define PULL_UP_SHIFT 7
> +#define PULL_UP_MASK (GENMASK(1, 0) | BIT(6))
> +#define PULL_UP_SHIFT 6
These look strange now.
So, SLEEP MASK doesn't cover bits 2 and 3.
I believe you should have
#define SLEEP_PULL_UP_DOWN_MASK GENMASK(3, 2)
The other even weirder with this BIT(6) there.
In the similar way:
#define PULL_UP_DOWN_MASK GENMASK(7, 6)
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 3/6] pinctrl: sprd: Modify pull-up parameters
2023-09-08 5:51 ` [PATCH V2 3/6] pinctrl: sprd: Modify pull-up parameters Linhua Xu
@ 2023-09-11 9:51 ` Andy Shevchenko
2023-09-12 8:22 ` Baolin Wang
1 sibling, 0 replies; 22+ messages in thread
From: Andy Shevchenko @ 2023-09-11 9:51 UTC (permalink / raw)
To: Linhua Xu
Cc: Linus Walleij, Orson Zhai, Baolin Wang, Chunyan Zhang,
linux-kernel, linux-gpio, lh xu, Zhirong Qiu, Xiongpeng Wu
On Fri, Sep 08, 2023 at 01:51:43PM +0800, Linhua Xu wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> For UNISOC pin controller, there are three different configurations of
> pull-up drive current. Modify the 20K pull-up resistor configuration and
> add the 1.8K pull-up resistor configuration.
...
> -#define PULL_UP_4_7K (BIT(12) | BIT(7))
> +#define PULL_UP_1_8K (BIT(12) | BIT(7))
> +#define PULL_UP_4_7K BIT(12)
This looks like a real fix, please add Fixes tag and move the patch to be the
first in the series.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 4/6] pinctrl: sprd: Add pinctrl support for UMS512
2023-09-08 5:51 ` [PATCH V2 4/6] pinctrl: sprd: Add pinctrl support for UMS512 Linhua Xu
2023-09-09 1:56 ` kernel test robot
@ 2023-09-11 9:53 ` Andy Shevchenko
1 sibling, 0 replies; 22+ messages in thread
From: Andy Shevchenko @ 2023-09-11 9:53 UTC (permalink / raw)
To: Linhua Xu
Cc: Linus Walleij, Orson Zhai, Baolin Wang, Chunyan Zhang,
linux-kernel, linux-gpio, lh xu, Zhirong Qiu, Xiongpeng Wu
On Fri, Sep 08, 2023 at 01:51:44PM +0800, Linhua Xu wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> Add the pin control driver for UNISOC UMS512 platform.
...
> +#define PINCTRL_REG_OFFSET 0x34
0x0034
> +#define PINCTRL_REG_MISC_OFFSET 0x434
...
> +static const struct of_device_id sprd_pinctrl_of_match[] = {
> + { .compatible = "sprd,ums512-pinctrl", },
Inner comma is not needed.
> + { }
> +};
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 5/6] pinctrl: sprd: Increase the range of register values
2023-09-08 5:51 ` [PATCH V2 5/6] pinctrl: sprd: Increase the range of register values Linhua Xu
@ 2023-09-11 9:55 ` Andy Shevchenko
2023-09-12 8:37 ` Baolin Wang
1 sibling, 0 replies; 22+ messages in thread
From: Andy Shevchenko @ 2023-09-11 9:55 UTC (permalink / raw)
To: Linhua Xu
Cc: Linus Walleij, Orson Zhai, Baolin Wang, Chunyan Zhang,
linux-kernel, linux-gpio, lh xu, Zhirong Qiu, Xiongpeng Wu
On Fri, Sep 08, 2023 at 01:51:45PM +0800, Linhua Xu wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> As the UNISOC pin controller version iterates, more registers are required
> to meet new functional requirements. Thus modify them.
LGTM,
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 6/6] pinctrl: sprd: Add pinctrl support for UMS9621
2023-09-08 5:51 ` [PATCH V2 6/6] pinctrl: sprd: Add pinctrl support for UMS9621 Linhua Xu
@ 2023-09-11 9:56 ` Andy Shevchenko
0 siblings, 0 replies; 22+ messages in thread
From: Andy Shevchenko @ 2023-09-11 9:56 UTC (permalink / raw)
To: Linhua Xu
Cc: Linus Walleij, Orson Zhai, Baolin Wang, Chunyan Zhang,
linux-kernel, linux-gpio, lh xu, Zhirong Qiu, Xiongpeng Wu
On Fri, Sep 08, 2023 at 01:51:46PM +0800, Linhua Xu wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> Add the pin control driver for UNISOC UMS9621 platform.
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/platform_device.h>
> +
...
> +#define PINCTRL_REG_OFFSET 0x44
0x0044
> +#define PINCTRL_REG_MISC_OFFSET 0x444
...
> +static const struct of_device_id sprd_pinctrl_of_match[] = {
> + { .compatible = "sprd,ums9621-pinctrl", },
Inner comma is not needed.
> + { }
> +};
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver
2023-09-08 5:51 [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linhua Xu
` (5 preceding siblings ...)
2023-09-08 5:51 ` [PATCH V2 6/6] pinctrl: sprd: Add pinctrl support for UMS9621 Linhua Xu
@ 2023-09-11 13:41 ` Linus Walleij
2023-09-12 8:40 ` Baolin Wang
6 siblings, 1 reply; 22+ messages in thread
From: Linus Walleij @ 2023-09-11 13:41 UTC (permalink / raw)
To: Linhua Xu, Baolin Wang
Cc: Orson Zhai, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Zhirong Qiu, Xiongpeng Wu
On Fri, Sep 8, 2023 at 7:52 AM Linhua Xu <Linhua.xu@unisoc.com> wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> Recently, some bugs have been discovered during use, and patch2 and patch3
> are bug fixes. Also, this patchset add new features: patch1 is for
> compatibility with more platforms, patch4 add pinctrl support for UMS512,
> patch5 Increase the range of register values, patch6 add pinctrl support
> for UMS9621.
>
> change in V2
V2 is starting to look good, please address Andy's comments, especially
move the fixes first in the series so they can be queued as fixes
if need be.
I would really appreciate if Baolin can review the patches as well as
he knows this hardware very well and wrote the initial version.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 1/6] pinctrl: sprd: Modify the probe function parameters
2023-09-08 5:51 ` [PATCH V2 1/6] pinctrl: sprd: Modify the probe function parameters Linhua Xu
2023-09-11 9:46 ` Andy Shevchenko
@ 2023-09-12 8:13 ` Baolin Wang
1 sibling, 0 replies; 22+ messages in thread
From: Baolin Wang @ 2023-09-12 8:13 UTC (permalink / raw)
To: Linhua Xu, Linus Walleij
Cc: Orson Zhai, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Zhirong Qiu, Xiongpeng Wu
On 9/8/2023 1:51 PM, Linhua Xu wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> For UNISOC pin controller, the offset values of the common register and
> misc register will be different. Thus put these in the probe function
> parameters.
>
> Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
> ---
> drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c | 7 +++++-
> drivers/pinctrl/sprd/pinctrl-sprd.c | 27 +++++++++++++---------
> drivers/pinctrl/sprd/pinctrl-sprd.h | 3 ++-
> 3 files changed, 24 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c
> index d14f382f2392..05158c71ad77 100644
> --- a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c
> +++ b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c
> @@ -10,6 +10,9 @@
>
> #include "pinctrl-sprd.h"
>
> +#define PINCTRL_REG_OFFSET 0x20
> +#define PINCTRL_REG_MISC_OFFSET 0x4020
> +
> enum sprd_sc9860_pins {
> /* pin global control register 0 */
> SC9860_VIO28_0_IRTE = SPRD_PIN_INFO(0, GLOBAL_CTRL_PIN, 11, 1, 0),
> @@ -926,7 +929,9 @@ static struct sprd_pins_info sprd_sc9860_pins_info[] = {
> static int sprd_pinctrl_probe(struct platform_device *pdev)
> {
> return sprd_pinctrl_core_probe(pdev, sprd_sc9860_pins_info,
> - ARRAY_SIZE(sprd_sc9860_pins_info));
> + ARRAY_SIZE(sprd_sc9860_pins_info),
> + PINCTRL_REG_OFFSET,
> + PINCTRL_REG_MISC_OFFSET);
> }
>
> static const struct of_device_id sprd_pinctrl_of_match[] = {
> diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c
> index ca9659f4e4b1..25fb9ce9ad78 100644
> --- a/drivers/pinctrl/sprd/pinctrl-sprd.c
> +++ b/drivers/pinctrl/sprd/pinctrl-sprd.c
> @@ -30,8 +30,6 @@
> #include "pinctrl-sprd.h"
>
> #define PINCTRL_BIT_MASK(width) (~(~0UL << (width)))
> -#define PINCTRL_REG_OFFSET 0x20
> -#define PINCTRL_REG_MISC_OFFSET 0x4020
> #define PINCTRL_REG_LEN 0x4
>
> #define PIN_FUNC_MASK (BIT(4) | BIT(5))
> @@ -148,12 +146,16 @@ struct sprd_pinctrl_soc_info {
> * @pctl: pointer to the pinctrl handle
> * @base: base address of the controller
> * @info: pointer to SoC's pins description information
> + * @common_pin_offset: offset value of common register
> + * @misc_pin_offset: offset value of misc register
> */
> struct sprd_pinctrl {
> struct device *dev;
> struct pinctrl_dev *pctl;
> void __iomem *base;
> struct sprd_pinctrl_soc_info *info;
> + u32 common_pin_offset;
> + u32 misc_pin_offset;
> };
>
> #define SPRD_PIN_CONFIG_CONTROL (PIN_CONFIG_END + 1)
> @@ -1023,12 +1025,12 @@ static int sprd_pinctrl_add_pins(struct sprd_pinctrl *sprd_pctl,
> ctrl_pin++;
> } else if (pin->type == COMMON_PIN) {
> pin->reg = (unsigned long)sprd_pctl->base +
> - PINCTRL_REG_OFFSET + PINCTRL_REG_LEN *
> + sprd_pctl->common_pin_offset + PINCTRL_REG_LEN *
> (i - ctrl_pin);
> com_pin++;
> } else if (pin->type == MISC_PIN) {
> pin->reg = (unsigned long)sprd_pctl->base +
> - PINCTRL_REG_MISC_OFFSET + PINCTRL_REG_LEN *
> + sprd_pctl->misc_pin_offset + PINCTRL_REG_LEN *
> (i - ctrl_pin - com_pin);
> }
> }
> @@ -1045,7 +1047,9 @@ static int sprd_pinctrl_add_pins(struct sprd_pinctrl *sprd_pctl,
>
> int sprd_pinctrl_core_probe(struct platform_device *pdev,
> struct sprd_pins_info *sprd_soc_pin_info,
> - int pins_cnt)
> + int pins_cnt,
> + u32 common_pin_offset,
> + u32 misc_pin_offset)
> {
> struct sprd_pinctrl *sprd_pctl;
> struct sprd_pinctrl_soc_info *pinctrl_info;
> @@ -1069,6 +1073,8 @@ int sprd_pinctrl_core_probe(struct platform_device *pdev,
>
> sprd_pctl->info = pinctrl_info;
> sprd_pctl->dev = &pdev->dev;
> + sprd_pctl->common_pin_offset = common_pin_offset;
> + sprd_pctl->misc_pin_offset = misc_pin_offset;
> platform_set_drvdata(pdev, sprd_pctl);
>
> ret = sprd_pinctrl_add_pins(sprd_pctl, sprd_soc_pin_info, pins_cnt);
> @@ -1077,12 +1083,6 @@ int sprd_pinctrl_core_probe(struct platform_device *pdev,
> return ret;
> }
>
> - ret = sprd_pinctrl_parse_dt(sprd_pctl);
> - if (ret) {
> - dev_err(&pdev->dev, "fail to parse dt properties\n");
> - return ret;
> - }
> -
> pin_desc = devm_kcalloc(&pdev->dev,
> pinctrl_info->npins,
> sizeof(struct pinctrl_pin_desc),
> @@ -1100,6 +1100,11 @@ int sprd_pinctrl_core_probe(struct platform_device *pdev,
> sprd_pinctrl_desc.name = dev_name(&pdev->dev);
> sprd_pinctrl_desc.npins = pinctrl_info->npins;
>
> + ret = sprd_pinctrl_parse_dt(sprd_pctl);
> + if (ret) {
> + dev_err(&pdev->dev, "fail to parse dt properties\n");
> + return ret;
> + }
Why change this? If this change fixed anything, please mention it in the
commit log.
> sprd_pctl->pctl = pinctrl_register(&sprd_pinctrl_desc,
> &pdev->dev, (void *)sprd_pctl);
> if (IS_ERR(sprd_pctl->pctl)) {
> diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.h b/drivers/pinctrl/sprd/pinctrl-sprd.h
> index 69544a3cd635..a696f81ce663 100644
> --- a/drivers/pinctrl/sprd/pinctrl-sprd.h
> +++ b/drivers/pinctrl/sprd/pinctrl-sprd.h
> @@ -52,7 +52,8 @@ struct sprd_pins_info {
>
> int sprd_pinctrl_core_probe(struct platform_device *pdev,
> struct sprd_pins_info *sprd_soc_pin_info,
> - int pins_cnt);
> + int pins_cnt, u32 common_pin_offset,
> + u32 misc_pin_offset);
IMO, I don't like this modification since it lacks scalability, and just
imagine that there might be more differences in SoC in the future. So
adding a SoC structure in sprd_pinctrl_of_match() and parsing it in the
sprd-pinctrl core seems the right way to go.
> int sprd_pinctrl_remove(struct platform_device *pdev);
> void sprd_pinctrl_shutdown(struct platform_device *pdev);
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 3/6] pinctrl: sprd: Modify pull-up parameters
2023-09-08 5:51 ` [PATCH V2 3/6] pinctrl: sprd: Modify pull-up parameters Linhua Xu
2023-09-11 9:51 ` Andy Shevchenko
@ 2023-09-12 8:22 ` Baolin Wang
1 sibling, 0 replies; 22+ messages in thread
From: Baolin Wang @ 2023-09-12 8:22 UTC (permalink / raw)
To: Linhua Xu, Linus Walleij
Cc: Orson Zhai, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Zhirong Qiu, Xiongpeng Wu
On 9/8/2023 1:51 PM, Linhua Xu wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> For UNISOC pin controller, there are three different configurations of
> pull-up drive current. Modify the 20K pull-up resistor configuration and
> add the 1.8K pull-up resistor configuration.
>
> Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
Please add a Fixes tag.
> ---
> drivers/pinctrl/sprd/pinctrl-sprd.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c
> index 5b9126b2cde2..6c75e6b8d2ca 100644
> --- a/drivers/pinctrl/sprd/pinctrl-sprd.c
> +++ b/drivers/pinctrl/sprd/pinctrl-sprd.c
> @@ -69,7 +69,8 @@
> #define SLEEP_PULL_UP_MASK GENMASK(1, 0)
> #define SLEEP_PULL_UP_SHIFT 2
>
> -#define PULL_UP_4_7K (BIT(12) | BIT(7))
> +#define PULL_UP_1_8K (BIT(12) | BIT(7))
> +#define PULL_UP_4_7K BIT(12)
> #define PULL_UP_20K BIT(7)
> #define PULL_UP_MASK (GENMASK(1, 0) | BIT(6))
> #define PULL_UP_SHIFT 6
> @@ -499,7 +500,7 @@ static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id,
> break;
> case PIN_CONFIG_BIAS_DISABLE:
> if ((reg & (SLEEP_PULL_DOWN | SLEEP_PULL_UP)) ||
> - (reg & (PULL_DOWN | PULL_UP_4_7K | PULL_UP_20K)))
> + (reg & (PULL_DOWN | PULL_UP_1_8K)))
The math logic is correct, but the code is not readable now. Since we
should mask all PULL UP configration, but the code only mask 'PULL_UP_1_8K'.
So changing to below will be more clear:
(reg & (PULL_DOWN | PULL_UP_4_7K | PULL_UP_20K | PULL_UP_1_8K)
> return -EINVAL;
>
> arg = 1;
> @@ -701,6 +702,8 @@ static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id,
> val |= PULL_UP_20K;
> else if (arg == 4700)
> val |= PULL_UP_4_7K;
> + else if (arg == 1800)
> + val |= PULL_UP_1_8K;
>
> mask = PULL_UP_MASK;
> shift = PULL_UP_SHIFT;
> @@ -712,8 +715,7 @@ static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id,
> mask = SLEEP_PULL_DOWN | SLEEP_PULL_UP;
> } else {
> val = shift = 0;
> - mask = PULL_DOWN | PULL_UP_20K |
> - PULL_UP_4_7K;
> + mask = PULL_DOWN | PULL_UP_1_8K;
ditto.
> }
> break;
> case PIN_CONFIG_SLEEP_HARDWARE_STATE:
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition
2023-09-08 5:51 ` [PATCH V2 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition Linhua Xu
2023-09-11 9:50 ` Andy Shevchenko
@ 2023-09-12 8:28 ` Baolin Wang
2023-11-13 13:50 ` Linus Walleij
2 siblings, 0 replies; 22+ messages in thread
From: Baolin Wang @ 2023-09-12 8:28 UTC (permalink / raw)
To: Linhua Xu, Linus Walleij
Cc: Orson Zhai, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Zhirong Qiu, Xiongpeng Wu
On 9/8/2023 1:51 PM, Linhua Xu wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> Pull-up and pull-down are mutually exclusive. When setting one of them,
> the bit of the other needs to be clear. Now, there are cases where pull-up
> and pull-down are set at the same time in the code, thus fix them.
>
> Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
> ---
> drivers/pinctrl/sprd/pinctrl-sprd.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c
> index 25fb9ce9ad78..5b9126b2cde2 100644
> --- a/drivers/pinctrl/sprd/pinctrl-sprd.c
> +++ b/drivers/pinctrl/sprd/pinctrl-sprd.c
> @@ -58,21 +58,21 @@
> #define DRIVE_STRENGTH_SHIFT 19
>
> #define SLEEP_PULL_DOWN BIT(2)
> -#define SLEEP_PULL_DOWN_MASK 0x1
> +#define SLEEP_PULL_DOWN_MASK GENMASK(1, 0)
> #define SLEEP_PULL_DOWN_SHIFT 2
>
> #define PULL_DOWN BIT(6)
> -#define PULL_DOWN_MASK 0x1
> +#define PULL_DOWN_MASK (GENMASK(1, 0) | BIT(6))
> #define PULL_DOWN_SHIFT 6
>
> #define SLEEP_PULL_UP BIT(3)
> -#define SLEEP_PULL_UP_MASK 0x1
> -#define SLEEP_PULL_UP_SHIFT 3
> +#define SLEEP_PULL_UP_MASK GENMASK(1, 0)
> +#define SLEEP_PULL_UP_SHIFT 2
>
> #define PULL_UP_4_7K (BIT(12) | BIT(7))
> #define PULL_UP_20K BIT(7)
> -#define PULL_UP_MASK 0x21
> -#define PULL_UP_SHIFT 7
> +#define PULL_UP_MASK (GENMASK(1, 0) | BIT(6))
> +#define PULL_UP_SHIFT 6
This change looks weird, BIT(6) is for PULL_DOWN. So I am curious these
changes are backward compatibility?
Now I can not access the SPRD Spec, Chunyan, can you help to confirm
these changes? Thanks.
>
> #define INPUT_SCHMITT BIT(11)
> #define INPUT_SCHMITT_MASK 0x1
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 5/6] pinctrl: sprd: Increase the range of register values
2023-09-08 5:51 ` [PATCH V2 5/6] pinctrl: sprd: Increase the range of register values Linhua Xu
2023-09-11 9:55 ` Andy Shevchenko
@ 2023-09-12 8:37 ` Baolin Wang
[not found] ` <CAPjKKSrs9X2msnDg=9rC8H57Dq8FPd7SWyBsr2MCwL0FMNkHPA@mail.gmail.com>
1 sibling, 1 reply; 22+ messages in thread
From: Baolin Wang @ 2023-09-12 8:37 UTC (permalink / raw)
To: Linhua Xu, Linus Walleij
Cc: Orson Zhai, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Zhirong Qiu, Xiongpeng Wu
On 9/8/2023 1:51 PM, Linhua Xu wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> As the UNISOC pin controller version iterates, more registers are required
> to meet new functional requirements. Thus modify them.
>
> Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
> ---
> drivers/pinctrl/sprd/pinctrl-sprd.h | 30 +++++++++++++++--------------
> 1 file changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.h b/drivers/pinctrl/sprd/pinctrl-sprd.h
> index a696f81ce663..5357874186fd 100644
> --- a/drivers/pinctrl/sprd/pinctrl-sprd.h
> +++ b/drivers/pinctrl/sprd/pinctrl-sprd.h
> @@ -7,30 +7,32 @@
> #ifndef __PINCTRL_SPRD_H__
> #define __PINCTRL_SPRD_H__
>
> +#include <linux/bits.h>
> +
> struct platform_device;
>
> -#define NUM_OFFSET (20)
> -#define TYPE_OFFSET (16)
> -#define BIT_OFFSET (8)
> -#define WIDTH_OFFSET (4)
> +#define NUM_OFFSET 22
> +#define TYPE_OFFSET 18
> +#define BIT_OFFSET 10
> +#define WIDTH_OFFSET 6
>
> #define SPRD_PIN_INFO(num, type, offset, width, reg) \
> - (((num) & 0xFFF) << NUM_OFFSET | \
> - ((type) & 0xF) << TYPE_OFFSET | \
> - ((offset) & 0xFF) << BIT_OFFSET | \
> - ((width) & 0xF) << WIDTH_OFFSET | \
> - ((reg) & 0xF))
> + (((num) & GENMASK(10, 0)) << NUM_OFFSET | \
> + ((type) & GENMASK(3, 0)) << TYPE_OFFSET | \
> + ((offset) & GENMASK(7, 0)) << BIT_OFFSET | \
> + ((width) & GENMASK(3, 0)) << WIDTH_OFFSET | \
> + ((reg) & GENMASK(5, 0)))
Can you define some readable macro for the mask bits?
>
> #define SPRD_PINCTRL_PIN(pin) SPRD_PINCTRL_PIN_DATA(pin, #pin)
>
> #define SPRD_PINCTRL_PIN_DATA(a, b) \
> { \
> .name = b, \
> - .num = (((a) >> NUM_OFFSET) & 0xfff), \
> - .type = (((a) >> TYPE_OFFSET) & 0xf), \
> - .bit_offset = (((a) >> BIT_OFFSET) & 0xff), \
> - .bit_width = ((a) >> WIDTH_OFFSET & 0xf), \
> - .reg = ((a) & 0xf) \
> + .num = (((a) & GENMASK(31, 22)) >> NUM_OFFSET), \
> + .type = (((a) & GENMASK(21, 18)) >> TYPE_OFFSET), \
> + .bit_offset = (((a) & GENMASK(17, 10)) >> BIT_OFFSET), \
> + .bit_width = (((a) & GENMASK(9, 6)) >> WIDTH_OFFSET), \
> + .reg = ((a) & GENMASK(5, 0)) \
Please keep the same logic operation as before, and you can reuse the
readable macros if you defined.
> }
>
> enum pin_type {
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver
2023-09-11 13:41 ` [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linus Walleij
@ 2023-09-12 8:40 ` Baolin Wang
0 siblings, 0 replies; 22+ messages in thread
From: Baolin Wang @ 2023-09-12 8:40 UTC (permalink / raw)
To: Linus Walleij, Linhua Xu
Cc: Orson Zhai, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Zhirong Qiu, Xiongpeng Wu
On 9/11/2023 9:41 PM, Linus Walleij wrote:
> On Fri, Sep 8, 2023 at 7:52 AM Linhua Xu <Linhua.xu@unisoc.com> wrote:
>
>> From: Linhua Xu <Linhua.Xu@unisoc.com>
>>
>> Recently, some bugs have been discovered during use, and patch2 and patch3
>> are bug fixes. Also, this patchset add new features: patch1 is for
>> compatibility with more platforms, patch4 add pinctrl support for UMS512,
>> patch5 Increase the range of register values, patch6 add pinctrl support
>> for UMS9621.
>>
>> change in V2
>
> V2 is starting to look good, please address Andy's comments, especially
> move the fixes first in the series so they can be queued as fixes
> if need be.
Yes, agree. Please send the fix patches separately with proper Fixes tag.
>
> I would really appreciate if Baolin can review the patches as well as
> he knows this hardware very well and wrote the initial version.
Sure.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 5/6] pinctrl: sprd: Increase the range of register values
[not found] ` <CAPjKKSrs9X2msnDg=9rC8H57Dq8FPd7SWyBsr2MCwL0FMNkHPA@mail.gmail.com>
@ 2023-10-26 2:57 ` Baolin Wang
0 siblings, 0 replies; 22+ messages in thread
From: Baolin Wang @ 2023-10-26 2:57 UTC (permalink / raw)
To: xu lh
Cc: Linhua Xu, Linus Walleij, Orson Zhai, Chunyan Zhang, linux-kernel,
linux-gpio, Andy Shevchenko, Zhirong Qiu, Xiongpeng Wu
On 10/25/2023 7:29 PM, xu lh wrote:
> On Tue, Sep 12, 2023 at 4:37 PM Baolin Wang <baolin.wang@linux.alibaba.com>
> wrote:
>
>>
>>
>> On 9/8/2023 1:51 PM, Linhua Xu wrote:
>>> From: Linhua Xu <Linhua.Xu@unisoc.com>
>>>
>>> As the UNISOC pin controller version iterates, more registers are
>> required
>>> to meet new functional requirements. Thus modify them.
>>>
>>> Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
>>> ---
>>> drivers/pinctrl/sprd/pinctrl-sprd.h | 30 +++++++++++++++--------------
>>> 1 file changed, 16 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.h
>> b/drivers/pinctrl/sprd/pinctrl-sprd.h
>>> index a696f81ce663..5357874186fd 100644
>>> --- a/drivers/pinctrl/sprd/pinctrl-sprd.h
>>> +++ b/drivers/pinctrl/sprd/pinctrl-sprd.h
>>> @@ -7,30 +7,32 @@
>>> #ifndef __PINCTRL_SPRD_H__
>>> #define __PINCTRL_SPRD_H__
>>>
>>> +#include <linux/bits.h>
>>> +
>>> struct platform_device;
>>>
>>> -#define NUM_OFFSET (20)
>>> -#define TYPE_OFFSET (16)
>>> -#define BIT_OFFSET (8)
>>> -#define WIDTH_OFFSET (4)
>>> +#define NUM_OFFSET 22
>>> +#define TYPE_OFFSET 18
>>> +#define BIT_OFFSET 10
>>> +#define WIDTH_OFFSET 6
>>>
>>> #define SPRD_PIN_INFO(num, type, offset, width, reg) \
>>> - (((num) & 0xFFF) << NUM_OFFSET | \
>>> - ((type) & 0xF) << TYPE_OFFSET | \
>>> - ((offset) & 0xFF) << BIT_OFFSET | \
>>> - ((width) & 0xF) << WIDTH_OFFSET | \
>>> - ((reg) & 0xF))
>>> + (((num) & GENMASK(10, 0)) << NUM_OFFSET | \
>>> + ((type) & GENMASK(3, 0)) << TYPE_OFFSET | \
>>> + ((offset) & GENMASK(7, 0)) << BIT_OFFSET | \
>>> + ((width) & GENMASK(3, 0)) << WIDTH_OFFSET | \
>>> + ((reg) & GENMASK(5, 0)))
>>
>> Can you define some readable macro for the mask bits?
>
>
>>> okay. Do you think the following modification is okay?
> +#define PIN_ID GENMASK(10, 0)
> +#define PIN_TYPE GENMASK(3, 0)
> +#define FIELD_OFFSET GENMASK(7, 0)
> +#define FIELD_WIDTH GENMASK(3, 0)
> +#define PIN_REG GENMASK(5, 0)
Looks better. To keep consistent, I perfer to something as below:
#define NUM_MASK xxx
#define TYPE_MASK xxx
#define BIT_MASK xxx
#define WIDTH_MASK xxx
#define REG_MASK xxx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH V2 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition
2023-09-08 5:51 ` [PATCH V2 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition Linhua Xu
2023-09-11 9:50 ` Andy Shevchenko
2023-09-12 8:28 ` Baolin Wang
@ 2023-11-13 13:50 ` Linus Walleij
2 siblings, 0 replies; 22+ messages in thread
From: Linus Walleij @ 2023-11-13 13:50 UTC (permalink / raw)
To: Linhua Xu
Cc: Orson Zhai, Baolin Wang, Chunyan Zhang, linux-kernel, linux-gpio,
Andy Shevchenko, lh xu, Zhirong Qiu, Xiongpeng Wu
On Fri, Sep 8, 2023 at 7:52 AM Linhua Xu <Linhua.xu@unisoc.com> wrote:
> From: Linhua Xu <Linhua.Xu@unisoc.com>
>
> Pull-up and pull-down are mutually exclusive. When setting one of them,
> the bit of the other needs to be clear. Now, there are cases where pull-up
> and pull-down are set at the same time in the code, thus fix them.
>
> Signed-off-by: Linhua Xu <Linhua.Xu@unisoc.com>
I'm uncertain what to do with this patch because it fixes something
while there are unaddressed review comments, I think we need
some more discussion here?
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2023-11-13 13:50 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-09-08 5:51 [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linhua Xu
2023-09-08 5:51 ` [PATCH V2 1/6] pinctrl: sprd: Modify the probe function parameters Linhua Xu
2023-09-11 9:46 ` Andy Shevchenko
2023-09-12 8:13 ` Baolin Wang
2023-09-08 5:51 ` [PATCH V2 2/6] pinctrl: sprd: Fix the incorrect mask and shift definition Linhua Xu
2023-09-11 9:50 ` Andy Shevchenko
2023-09-12 8:28 ` Baolin Wang
2023-11-13 13:50 ` Linus Walleij
2023-09-08 5:51 ` [PATCH V2 3/6] pinctrl: sprd: Modify pull-up parameters Linhua Xu
2023-09-11 9:51 ` Andy Shevchenko
2023-09-12 8:22 ` Baolin Wang
2023-09-08 5:51 ` [PATCH V2 4/6] pinctrl: sprd: Add pinctrl support for UMS512 Linhua Xu
2023-09-09 1:56 ` kernel test robot
2023-09-11 9:53 ` Andy Shevchenko
2023-09-08 5:51 ` [PATCH V2 5/6] pinctrl: sprd: Increase the range of register values Linhua Xu
2023-09-11 9:55 ` Andy Shevchenko
2023-09-12 8:37 ` Baolin Wang
[not found] ` <CAPjKKSrs9X2msnDg=9rC8H57Dq8FPd7SWyBsr2MCwL0FMNkHPA@mail.gmail.com>
2023-10-26 2:57 ` Baolin Wang
2023-09-08 5:51 ` [PATCH V2 6/6] pinctrl: sprd: Add pinctrl support for UMS9621 Linhua Xu
2023-09-11 9:56 ` Andy Shevchenko
2023-09-11 13:41 ` [PATCH V2 0/6] pinctrl: sprd: Modification of UNIOC Platform pinctrl Driver Linus Walleij
2023-09-12 8:40 ` Baolin Wang
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