From: William McVicker <willmcvicker@google.com>
To: Peter Griffin <peter.griffin@linaro.org>
Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org,
tomasz.figa@gmail.com, s.nawrocki@samsung.com,
linus.walleij@linaro.org, wim@linux-watchdog.org,
linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org,
arnd@arndb.de, olof@lixom.net, gregkh@linuxfoundation.org,
cw00.choi@samsung.com, tudor.ambarus@linaro.org,
andre.draszik@linaro.org, semen.protsenko@linaro.org,
saravanak@google.com, soc@kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org,
kernel-team@android.com, linux-serial@vger.kernel.org
Subject: Re: [PATCH v3 14/20] pinctrl: samsung: Add gs101 SoC pinctrl configuration
Date: Wed, 11 Oct 2023 14:53:02 -0700 [thread overview]
Message-ID: <ZScZPstpJInZxwlD@google.com> (raw)
In-Reply-To: <20231011184823.443959-15-peter.griffin@linaro.org>
On 10/11/2023, Peter Griffin wrote:
> Add support for the pin-controller found on the gs101 SoC used in
> Pixel 6 phones.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Thanks,
Will
> ---
> .../pinctrl/samsung/pinctrl-exynos-arm64.c | 163 ++++++++++++++++++
> drivers/pinctrl/samsung/pinctrl-exynos.c | 2 +
> drivers/pinctrl/samsung/pinctrl-exynos.h | 34 ++++
> drivers/pinctrl/samsung/pinctrl-samsung.c | 2 +
> drivers/pinctrl/samsung/pinctrl-samsung.h | 1 +
> 5 files changed, 202 insertions(+)
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> index cb965cf93705..db47001d1b35 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> @@ -796,3 +796,166 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
> .ctrl = fsd_pin_ctrl,
> .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl),
> };
> +
> +/*
> + * bank type for non-alive type
> + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> + * (CONPDN bit field: 2, PUDPDN bit field: 4)
> + */
> +static struct samsung_pin_bank_type gs101_bank_type_off = {
> + .fld_width = { 4, 1, 4, 4, 2, 4, },
> + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
> +};
> +
> +/*
> + * bank type for alive type
> + * (CON bit field: 4, DAT bit field: 1, PUD bit field: 4, DRV bit field: 4)
> + */
> +static const struct samsung_pin_bank_type gs101_bank_type_alive = {
> + .fld_width = { 4, 1, 4, 4, },
> + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
> +};
> +
> +/* pin banks of gs101 pin-controller (ALIVE) */
> +static const struct samsung_pin_bank_data gs101_pin_alive[] = {
> + EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x0, "gpa0", 0x00, 0x00, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 7, 0x20, "gpa1", 0x04, 0x08, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 5, 0x40, "gpa2", 0x08, 0x10, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x60, "gpa3", 0x0c, 0x18, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x80, "gpa4", 0x10, 0x1c, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 7, 0xa0, "gpa5", 0x14, 0x20, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0xc0, "gpa9", 0x18, 0x28, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 2, 0xe0, "gpa10", 0x1c, 0x30, FLT_SELECTABLE),
> +};
> +
> +/* pin banks of gs101 pin-controller (FAR_ALIVE) */
> +static const struct samsung_pin_bank_data gs101_pin_far_alive[] = {
> + EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x0, "gpa6", 0x00, 0x00, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 4, 0x20, "gpa7", 0x04, 0x08, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 8, 0x40, "gpa8", 0x08, 0x0c, FLT_SELECTABLE),
> + EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 2, 0x60, "gpa11", 0x0c, 0x14, FLT_SELECTABLE),
> +};
> +
> +/* pin banks of gs101 pin-controller (GSACORE) */
> +static const struct samsung_pin_bank_data gs101_pin_gsacore[] = {
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x0, "gps0", 0x00, 0x00, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x20, "gps1", 0x04, 0x04, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 3, 0x40, "gps2", 0x08, 0x0c, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (GSACTRL) */
> +static const struct samsung_pin_bank_data gs101_pin_gsactrl[] = {
> + EXYNOS9_PIN_BANK_EINTW(gs101_bank_type_alive, 6, 0x0, "gps3", 0x00, 0x00, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (PERIC0) */
> +static const struct samsung_pin_bank_data gs101_pin_peric0[] = {
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 5, 0x0, "gpp0", 0x00, 0x00, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x20, "gpp1", 0x04, 0x08, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x40, "gpp2", 0x08, 0x0c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x60, "gpp3", 0x0c, 0x10, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x80, "gpp4", 0x10, 0x14, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0xa0, "gpp5", 0x14, 0x18, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xc0, "gpp6", 0x18, 0x1c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0xe0, "gpp7", 0x1c, 0x20, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x100, "gpp8", 0x20, 0x24, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x120, "gpp9", 0x24, 0x28, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x140, "gpp10", 0x28, 0x2c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x160, "gpp11", 0x2c, 0x30, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x180, "gpp12", 0x30, 0x34, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x1a0, "gpp13", 0x34, 0x38, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x1c0, "gpp14", 0x38, 0x3c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x1e0, "gpp15", 0x3c, 0x40, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x200, "gpp16", 0x40, 0x44, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x220, "gpp17", 0x44, 0x48, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x240, "gpp18", 0x48, 0x4c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x260, "gpp19", 0x4c, 0x50, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (PERIC1) */
> +static const struct samsung_pin_bank_data gs101_pin_peric1[] = {
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x0, "gpp20", 0x00, 0x00, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x20, "gpp21", 0x04, 0x08, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x40, "gpp22", 0x08, 0x0c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 8, 0x60, "gpp23", 0x0c, 0x10, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0x80, "gpp24", 0x10, 0x18, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xa0, "gpp25", 0x14, 0x1c, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 5, 0xc0, "gpp26", 0x18, 0x20, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 4, 0xe0, "gpp27", 0x1c, 0x28, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (HSI1) */
> +static const struct samsung_pin_bank_data gs101_pin_hsi1[] = {
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x0, "gph0", 0x00, 0x00, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 7, 0x20, "gph1", 0x04, 0x08, FLT_DEFAULT),
> +};
> +
> +/* pin banks of gs101 pin-controller (HSI2) */
> +static const struct samsung_pin_bank_data gs101_pin_hsi2[] = {
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x0, "gph2", 0x00, 0x00, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 2, 0x20, "gph3", 0x04, 0x08, FLT_DEFAULT),
> + EXYNOS9_PIN_BANK_EINTG(gs101_bank_type_off, 6, 0x40, "gph4", 0x08, 0x0c, FLT_DEFAULT),
> +};
> +
> +static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst = {
> + {
> + /* pin banks of gs101 pin-controller (ALIVE) */
> + .pin_banks = gs101_pin_alive,
> + .nr_banks = ARRAY_SIZE(gs101_pin_alive),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .eint_wkup_init = exynos_eint_wkup_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin banks of gs101 pin-controller (FAR_ALIVE) */
> + .pin_banks = gs101_pin_far_alive,
> + .nr_banks = ARRAY_SIZE(gs101_pin_far_alive),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .eint_wkup_init = exynos_eint_wkup_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin banks of gs101 pin-controller (GSACORE) */
> + .pin_banks = gs101_pin_gsacore,
> + .nr_banks = ARRAY_SIZE(gs101_pin_gsacore),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + }, {
> + /* pin banks of gs101 pin-controller (GSACTRL) */
> + .pin_banks = gs101_pin_gsactrl,
> + .nr_banks = ARRAY_SIZE(gs101_pin_gsactrl),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + }, {
> + /* pin banks of gs101 pin-controller (PERIC0) */
> + .pin_banks = gs101_pin_peric0,
> + .nr_banks = ARRAY_SIZE(gs101_pin_peric0),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin banks of gs101 pin-controller (PERIC1) */
> + .pin_banks = gs101_pin_peric1,
> + .nr_banks = ARRAY_SIZE(gs101_pin_peric1),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin banks of gs101 pin-controller (HSI1) */
> + .pin_banks = gs101_pin_hsi1,
> + .nr_banks = ARRAY_SIZE(gs101_pin_hsi1),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + }, {
> + /* pin banks of gs101 pin-controller (HSI2) */
> + .pin_banks = gs101_pin_hsi2,
> + .nr_banks = ARRAY_SIZE(gs101_pin_hsi2),
> + .eint_gpio_init = exynos_eint_gpio_init,
> + .suspend = exynos_pinctrl_suspend,
> + .resume = exynos_pinctrl_resume,
> + },
> +};
> +
> +const struct samsung_pinctrl_of_match_data gs101_of_data __initconst = {
> + .ctrl = gs101_pin_ctrl,
> + .num_ctrl = ARRAY_SIZE(gs101_pin_ctrl),
> +};
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
> index 800831aa8357..014f0c37f97f 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.c
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
> @@ -533,6 +533,8 @@ static const struct of_device_id exynos_wkup_irq_ids[] = {
> .data = &exynos7_wkup_irq_chip },
> { .compatible = "samsung,exynosautov9-wakeup-eint",
> .data = &exynos7_wkup_irq_chip },
> + { .compatible = "google,gs101-wakeup-eint",
> + .data = &exynos7_wkup_irq_chip },
> { }
> };
>
> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
> index 63b2426ad5d6..0dd013654bd2 100644
> --- a/drivers/pinctrl/samsung/pinctrl-exynos.h
> +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
> @@ -147,6 +147,40 @@
> .name = id \
> }
>
> +#define EXYNOS9_PIN_BANK_EINTN(types, pins, reg, id) \
> + { \
> + .type = &types, \
> + .pctl_offset = reg, \
> + .nr_pins = pins, \
> + .eint_type = EINT_TYPE_NONE, \
> + .fltcon_type = FLT_DEFAULT \
> + .name = id \
> + }
> +
> +#define EXYNOS9_PIN_BANK_EINTG(types, pins, reg, id, offs, fltcon_offs, fltcontype) \
> + { \
> + .type = &types, \
> + .pctl_offset = reg, \
> + .nr_pins = pins, \
> + .eint_type = EINT_TYPE_GPIO, \
> + .eint_offset = offs, \
> + .fltcon_type = fltcontype, \
> + .fltcon_offset = fltcon_offs, \
> + .name = id \
> + }
> +
> +#define EXYNOS9_PIN_BANK_EINTW(types, pins, reg, id, offs, fltcon_offs, fltcontype) \
> + { \
> + .type = &types, \
> + .pctl_offset = reg, \
> + .nr_pins = pins, \
> + .eint_type = EINT_TYPE_WKUP, \
> + .eint_offset = offs, \
> + .fltcon_type = fltcontype, \
> + .fltcon_offset = fltcon_offs, \
> + .name = id \
> + }
> +
> /**
> * struct exynos_weint_data: irq specific data for all the wakeup interrupts
> * generated by the external wakeup interrupt controller.
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
> index 449f8109d8b5..12176f98440d 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.c
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
> @@ -1321,6 +1321,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
> .data = &exynosautov9_of_data },
> { .compatible = "tesla,fsd-pinctrl",
> .data = &fsd_of_data },
> + { .compatible = "google,gs101-pinctrl",
> + .data = &gs101_of_data },
> #endif
> #ifdef CONFIG_PINCTRL_S3C64XX
> { .compatible = "samsung,s3c64xx-pinctrl",
> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
> index de2ca8e8b378..e62e909fb10d 100644
> --- a/drivers/pinctrl/samsung/pinctrl-samsung.h
> +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
> @@ -374,6 +374,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
> extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
> extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
> extern const struct samsung_pinctrl_of_match_data fsd_of_data;
> +extern const struct samsung_pinctrl_of_match_data gs101_of_data;
> extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
> extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
> extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
> --
> 2.42.0.655.g421f12c284-goog
>
next prev parent reply other threads:[~2023-10-11 21:53 UTC|newest]
Thread overview: 100+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-11 18:48 [PATCH v3 00/20] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board Peter Griffin
2023-10-11 18:48 ` [PATCH v3 01/20] dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible Peter Griffin
2023-10-11 18:54 ` Sam Protsenko
2023-10-11 18:48 ` [PATCH v3 02/20] dt-bindings: clock: Add Google gs101 clock management unit bindings Peter Griffin
2023-10-11 21:48 ` William McVicker
2023-10-12 6:07 ` Krzysztof Kozlowski
2023-10-12 8:56 ` Peter Griffin
2023-10-12 9:36 ` Krzysztof Kozlowski
2023-10-12 10:45 ` Peter Griffin
2023-10-12 11:33 ` Krzysztof Kozlowski
2023-10-12 16:41 ` William McVicker
2023-10-11 22:55 ` Sam Protsenko
2023-10-12 6:11 ` Krzysztof Kozlowski
2023-10-12 10:15 ` Peter Griffin
2023-10-12 10:20 ` Krzysztof Kozlowski
2023-10-12 10:39 ` Peter Griffin
2023-10-11 18:48 ` [PATCH v3 03/20] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101 Peter Griffin
2023-10-11 22:56 ` Sam Protsenko
2023-10-16 13:36 ` Rob Herring
2023-10-19 13:10 ` Peter Griffin
2023-10-11 18:48 ` [PATCH v3 04/20] dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings Peter Griffin
2023-10-11 22:57 ` Sam Protsenko
2023-10-12 10:56 ` Peter Griffin
2023-10-11 18:48 ` [PATCH v3 05/20] dt-bindings: arm: google: Add bindings for Google ARM platforms Peter Griffin
2023-10-11 23:06 ` Sam Protsenko
2023-10-12 11:19 ` Peter Griffin
2023-10-11 18:48 ` [PATCH v3 06/20] dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible Peter Griffin
2023-10-11 23:10 ` Sam Protsenko
2023-10-16 13:41 ` Rob Herring
2023-11-07 12:18 ` Peter Griffin
2023-10-11 18:48 ` [PATCH v3 07/20] dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible Peter Griffin
2023-10-12 6:13 ` Krzysztof Kozlowski
2023-10-11 18:48 ` [PATCH v3 08/20] dt-bindings: serial: samsung: Add google-gs101-uart compatible Peter Griffin
2023-10-11 23:13 ` Sam Protsenko
2023-10-11 18:48 ` [PATCH v3 09/20] clk: samsung: clk-pll: Add support for pll_{0516,0517,518} Peter Griffin
2023-10-11 21:49 ` William McVicker
2023-10-11 23:19 ` Sam Protsenko
2023-10-12 11:50 ` Peter Griffin
[not found] ` <ef25ed87-f065-4a75-9e57-1f1073d9c805@kernel.org>
2023-10-17 20:39 ` Peter Griffin
2023-10-11 18:48 ` [PATCH v3 10/20] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates Peter Griffin
2023-10-11 21:50 ` William McVicker
2023-10-12 0:06 ` Sam Protsenko
2023-10-12 12:06 ` Peter Griffin
2023-10-12 12:24 ` Krzysztof Kozlowski
2023-10-12 13:52 ` Peter Griffin
[not found] ` <aae4e6cd-dcfc-442d-9ed7-d5a73c419ba8@kernel.org>
2023-11-07 13:57 ` Peter Griffin
2023-11-08 17:33 ` Sam Protsenko
2023-12-01 13:59 ` Peter Griffin
2023-10-11 18:48 ` [PATCH v3 11/20] clk: samsung: clk-gs101: add CMU_APM support Peter Griffin
2023-10-11 21:50 ` William McVicker
2023-10-12 0:10 ` Sam Protsenko
2023-10-11 18:48 ` [PATCH v3 12/20] clk: samsung: clk-gs101: Add support for CMU_MISC clock unit Peter Griffin
2023-10-11 21:51 ` William McVicker
2023-10-12 0:12 ` Sam Protsenko
2023-10-12 16:02 ` Peter Griffin
2023-10-11 18:48 ` [PATCH v3 13/20] pinctrl: samsung: Add filter selection support for alive banks Peter Griffin
2023-10-11 21:51 ` William McVicker
2023-10-11 22:47 ` Sam Protsenko
2023-10-20 13:54 ` Peter Griffin
2023-10-11 18:48 ` [PATCH v3 14/20] pinctrl: samsung: Add gs101 SoC pinctrl configuration Peter Griffin
2023-10-11 21:52 ` William McVicker
2023-10-11 21:53 ` William McVicker [this message]
2023-10-12 5:59 ` Sam Protsenko
2023-11-08 13:43 ` Peter Griffin
2023-10-11 18:48 ` [PATCH v3 15/20] watchdog: s3c2410_wdt: Add support for Google tensor SoCs Peter Griffin
2023-10-11 21:20 ` Guenter Roeck
2023-10-17 21:26 ` Peter Griffin
2023-10-12 2:32 ` Sam Protsenko
2023-10-17 21:39 ` Peter Griffin
2023-10-12 6:22 ` Krzysztof Kozlowski
2023-10-11 18:48 ` [PATCH v3 16/20] tty: serial: samsung: Add gs101 compatible and SoC data Peter Griffin
2023-10-11 21:54 ` William McVicker
2023-10-12 5:38 ` Sam Protsenko
2023-10-12 6:07 ` Arnd Bergmann
2023-10-20 21:47 ` Peter Griffin
2023-10-12 6:26 ` Krzysztof Kozlowski
2023-10-12 14:03 ` Peter Griffin
2023-10-12 14:10 ` Krzysztof Kozlowski
2023-10-11 18:48 ` [PATCH v3 17/20] arm64: dts: google: Add initial Google gs101 SoC support Peter Griffin
2023-10-11 21:55 ` William McVicker
2023-10-12 6:40 ` Krzysztof Kozlowski
2023-11-24 23:22 ` Peter Griffin
2023-11-28 8:58 ` Krzysztof Kozlowski
2023-10-12 6:44 ` Krzysztof Kozlowski
2023-11-24 23:53 ` Peter Griffin
2023-10-12 7:23 ` Sam Protsenko
2023-10-12 7:39 ` Krzysztof Kozlowski
2023-11-28 22:43 ` Peter Griffin
2023-10-11 18:48 ` [PATCH v3 18/20] arm64: dts: google: Add initial Oriole/pixel 6 board support Peter Griffin
2023-10-11 21:55 ` William McVicker
2023-10-12 6:44 ` Krzysztof Kozlowski
2023-10-12 7:40 ` Sam Protsenko
2023-10-11 18:48 ` [PATCH v3 19/20] arm64: defconfig: Enable Google Tensor SoC Peter Griffin
2023-10-11 21:56 ` William McVicker
2023-10-12 6:15 ` Sam Protsenko
2023-10-11 18:48 ` [PATCH v3 20/20] MAINTAINERS: add entry for " Peter Griffin
2023-10-12 6:02 ` Sam Protsenko
2023-10-11 21:58 ` [PATCH v3 00/20] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board William McVicker
2023-10-11 22:51 ` Sam Protsenko
2023-10-12 6:28 ` Krzysztof Kozlowski
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