From: Benjamin Larsson <benjamin.larsson@genexis.eu>
To: "Uwe Kleine-König" <u.kleine-koenig@baylibre.com>
Cc: Lorenzo Bianconi <lorenzo@kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Sean Wang <sean.wang@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Lee Jones <lee@kernel.org>,
linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
upstream@airoha.com, ansuelsmth@gmail.com,
linux-pwm@vger.kernel.org
Subject: Re: [PATCH v3 5/5] pwm: airoha: Add support for EN7581 SoC
Date: Thu, 5 Sep 2024 14:18:41 +0200 [thread overview]
Message-ID: <a0a14b57-cc4e-43ef-984f-fb405949b41d@genexis.eu> (raw)
In-Reply-To: <xmlta4za6malgthd6cmt5fcipxgyzwmqwxqdg5e4qahcuqzcrt@eidsf6mexrkz>
On 2024-09-05 11:30, Uwe Kleine-König wrote:
> 1 second long pulses with a period size of 1 second, so a constant high
> signal?
Hi, I think I was unclear. The SoC documentation is not that detailed.
But I think I understand how it works now.
One register contains the minimum duration (d_min). And then there is
one 8 bit register for the signal low period (lp) and then another 8bit
register for the high period (hp). Per my understanding a change of
polarity is then just a swap of lp and hp.
The period is d_min * (lp + hp) and duty_cycle (on time) is then
d_min*hp (per my understanding of the linux api). This means that there
can be different settings that result in the same pwm signal (if you
double d_min and halving lp and hp the signal should be the same).
This means that when requesting a period and duty cycle you need to
search through the configuration space to find the optimal value.
>
> Another thing that would be interesting is, if it can happen that you
> get a mixed signal. That is, if you update from
>
> .period = A
> .duty_cycle = B
>
> to
>
> .period = C
> .duty_cycle = D
>
> that you get one period with length C and duty_cycle B when the period
> completes after configuring period but before duty_cycle.
>
> Best regards
> UWe
I will perform this test also.
MvH
Benjamin Larsson
next prev parent reply other threads:[~2024-09-05 12:18 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-31 14:27 [PATCH v3 0/5] Add mfd, pinctrl and pwm support to EN7581 SoC Lorenzo Bianconi
2024-08-31 14:27 ` [PATCH v3 1/5] dt-bindings: arm: airoha: Add the chip-scu node for " Lorenzo Bianconi
2024-09-03 15:05 ` Rob Herring (Arm)
2024-08-31 14:27 ` [PATCH v3 2/5] dt-bindings: mfd: Add support for Airoha EN7581 GPIO System Controller Lorenzo Bianconi
2024-09-03 15:09 ` Rob Herring
2024-09-03 15:33 ` Lee Jones
2024-09-03 14:00 ` Christian Marangi
2024-09-03 16:42 ` Lee Jones
2024-09-04 11:06 ` Christian Marangi
2024-08-31 14:27 ` [PATCH v3 3/5] mfd: airoha: Add support for Airoha EN7581 MFD Lorenzo Bianconi
2024-08-31 14:27 ` [PATCH v3 4/5] pinctrl: airoha: Add support for EN7581 SoC Lorenzo Bianconi
2024-08-31 17:35 ` kernel test robot
2024-09-01 12:46 ` kernel test robot
2024-09-01 13:28 ` kernel test robot
2024-08-31 14:27 ` [PATCH v3 5/5] pwm: " Lorenzo Bianconi
2024-09-03 10:46 ` Uwe Kleine-König
2024-09-03 11:58 ` Benjamin Larsson
2024-09-03 15:47 ` Uwe Kleine-König
2024-09-04 23:09 ` Benjamin Larsson
2024-09-05 9:30 ` Uwe Kleine-König
2024-09-05 12:18 ` Benjamin Larsson [this message]
2024-09-05 15:39 ` Uwe Kleine-König
2024-09-05 18:35 ` Benjamin Larsson
2024-09-06 8:01 ` Uwe Kleine-König
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