* [PATCH v4 0/2] Introduce ExynosAutov920 SoC and SADK board [not found] <CGME20231211114215epcas2p226d66c6dd01a4414559272c648c3d464@epcas2p2.samsung.com> @ 2023-12-11 11:41 ` Jaewon Kim [not found] ` <CGME20231211114215epcas2p21c9a1c2157cd1650f5ec12487eddb576@epcas2p2.samsung.com> ` (2 more replies) 0 siblings, 3 replies; 7+ messages in thread From: Jaewon Kim @ 2023-12-11 11:41 UTC (permalink / raw) To: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley, Tomasz Figa, Sylwester Nawrocki, Linus Walleij, Thierry Reding, Uwe Kleine-K?nig, Greg Kroah-Hartman, Jiri Slaby Cc: linux-arm-kernel, linux-samsung-soc, devicetree, linux-kernel, linux-gpio, linux-pwm, linux-serial, Jaewon Kim ExynosAutov920[1] is ARMv8-based automotive-oriented SoC. This SoC is the next generation of exynosautov9 and AE(Automotive Enhanced) IPs are used for safety. This patchset is the minimal set for ExynosAutov920 SoC and SADK board. Currently, ramdisk console is available and Clock, UFS, and USI will be added after this patchset. [1] : https://semiconductor.samsung.com/processor/automotive-processor/exynos-auto-v920 --- Changes in v4: - Modify the comment for clear understanding - svc-related changes moved to exynosautov920 support patch - device-tree file merged in v3 Changes in v3: - Split pinctrl driver change patch and v920 support patch - Remove 'combine' variable and use offset variable - Fix coding style warning in checkpatch with --strict option - Fix CHECK_DTBS=y waring with W=1 option - dt-binding document merged in v2 Changes in v2: - Rebase to git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git branch : for-v6.8/samsung-bindings-compatibles - Specific exynosautov920 compatible - Add dt-binding patch for pmu, chipid Jaewon Kim (2): pinctrl: samsung: support ExynosAuto GPIO structure pinctrl: samsung: add exynosautov920 pinctrl .../pinctrl/samsung/pinctrl-exynos-arm64.c | 140 ++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.c | 95 ++++++++++-- drivers/pinctrl/samsung/pinctrl-exynos.h | 25 ++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 5 + drivers/pinctrl/samsung/pinctrl-samsung.h | 13 ++ 5 files changed, 269 insertions(+), 9 deletions(-) -- 2.43.0 ^ permalink raw reply [flat|nested] 7+ messages in thread
[parent not found: <CGME20231211114215epcas2p21c9a1c2157cd1650f5ec12487eddb576@epcas2p2.samsung.com>]
* [PATCH v4 1/2] pinctrl: samsung: support ExynosAuto GPIO structure [not found] ` <CGME20231211114215epcas2p21c9a1c2157cd1650f5ec12487eddb576@epcas2p2.samsung.com> @ 2023-12-11 11:41 ` Jaewon Kim 0 siblings, 0 replies; 7+ messages in thread From: Jaewon Kim @ 2023-12-11 11:41 UTC (permalink / raw) To: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley, Tomasz Figa, Sylwester Nawrocki, Linus Walleij, Thierry Reding, Uwe Kleine-K?nig, Greg Kroah-Hartman, Jiri Slaby Cc: linux-arm-kernel, linux-samsung-soc, devicetree, linux-kernel, linux-gpio, linux-pwm, linux-serial, Jaewon Kim New ExynosAuto series GPIO have a different register structure. In the existing Exynos series, EINT control register is enumerated after a specific offset (e.g EXYNOS_GPIO_ECON_OFFSET, EXYNOS_GPIO_EMASK_OFFSET). However, from ExynosAutov920 SoC, the register that controls EINT belongs to each GPIO bank, and each GPIO bank has 0x1000 align. This is a structure to protect the GPIO bank using S2MPU in VM environment, and will only be applied in ExynosAuto series SoCs. -------------------------------------------------------------- | Original Exynos | ExynosAuto | |------------------------------------------------------------| | 0x0 GPIO_CON | 0x0 GPIO_CON | | 0x4 GPIO_DAT | 0x4 GPIO_DAT | | 0x8 GPIO_PUD | 0x8 GPIO_PUD | | 0xc GPIO_DRV | 0xc GPIO_DRV | | 0x10 GPIO_CONPDN | 0x10 GPIO_CONPDN | | 0x14 GPIO_PUDPDN | 0x14 GPIO_PUDPDN | |----------------------------| 0x18 EINT_CON (per_bank) | | ... | 0x1c EINT_FLTCON0 (per_bank) | | ... | 0x20 EINT_FLTCON1 (per_bank) | | ... | 0x24 EINT_MASK (per_bank) | | ... | 0x28 EINT_PEND (per_bank) | |----------------------------|-------------------------------| | 0x700 EINT_CON (global) | ... | | 0x800 EINT_FLTCON (global) | ... | | 0x900 EINT_MASK (global) | ... | | 0xa00 EINT_FEND (global) | ... | -------------------------------------------------------------- Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> --- drivers/pinctrl/samsung/pinctrl-exynos.c | 72 ++++++++++++++++++++--- drivers/pinctrl/samsung/pinctrl-samsung.c | 3 + drivers/pinctrl/samsung/pinctrl-samsung.h | 12 ++++ 3 files changed, 79 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 6b58ec84e34b..77f747e629f7 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -52,10 +52,15 @@ static void exynos_irq_mask(struct irq_data *irqd) struct irq_chip *chip = irq_data_get_irq_chip(irqd); struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); - unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; + unsigned long reg_mask; unsigned int mask; unsigned long flags; + if (bank->eint_mask_offset) + reg_mask = bank->pctl_offset + bank->eint_mask_offset; + else + reg_mask = our_chip->eint_mask + bank->eint_offset; + raw_spin_lock_irqsave(&bank->slock, flags); mask = readl(bank->eint_base + reg_mask); @@ -70,7 +75,12 @@ static void exynos_irq_ack(struct irq_data *irqd) struct irq_chip *chip = irq_data_get_irq_chip(irqd); struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); - unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; + unsigned long reg_pend; + + if (bank->eint_pend_offset) + reg_pend = bank->pctl_offset + bank->eint_pend_offset; + else + reg_pend = our_chip->eint_pend + bank->eint_offset; writel(1 << irqd->hwirq, bank->eint_base + reg_pend); } @@ -80,7 +90,7 @@ static void exynos_irq_unmask(struct irq_data *irqd) struct irq_chip *chip = irq_data_get_irq_chip(irqd); struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); - unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; + unsigned long reg_mask; unsigned int mask; unsigned long flags; @@ -95,6 +105,11 @@ static void exynos_irq_unmask(struct irq_data *irqd) if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) exynos_irq_ack(irqd); + if (bank->eint_mask_offset) + reg_mask = bank->pctl_offset + bank->eint_mask_offset; + else + reg_mask = our_chip->eint_mask + bank->eint_offset; + raw_spin_lock_irqsave(&bank->slock, flags); mask = readl(bank->eint_base + reg_mask); @@ -111,7 +126,7 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; unsigned int con, trig_type; - unsigned long reg_con = our_chip->eint_con + bank->eint_offset; + unsigned long reg_con; switch (type) { case IRQ_TYPE_EDGE_RISING: @@ -139,6 +154,11 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) else irq_set_handler_locked(irqd, handle_level_irq); + if (bank->eint_con_offset) + reg_con = bank->pctl_offset + bank->eint_con_offset; + else + reg_con = our_chip->eint_con + bank->eint_offset; + con = readl(bank->eint_base + reg_con); con &= ~(EXYNOS_EINT_CON_MASK << shift); con |= trig_type << shift; @@ -655,6 +675,19 @@ static void exynos_pinctrl_suspend_bank( pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); } +static void exynosauto_pinctrl_suspend_bank(struct samsung_pinctrl_drv_data *drvdata, + struct samsung_pin_bank *bank) +{ + struct exynos_eint_gpio_save *save = bank->soc_priv; + void __iomem *regs = bank->eint_base; + + save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset); + save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset); + + pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); + pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); +} + void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) { struct samsung_pin_bank *bank = drvdata->pin_banks; @@ -662,8 +695,12 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) int i; for (i = 0; i < drvdata->nr_banks; ++i, ++bank) { - if (bank->eint_type == EINT_TYPE_GPIO) - exynos_pinctrl_suspend_bank(drvdata, bank); + if (bank->eint_type == EINT_TYPE_GPIO) { + if (bank->eint_con_offset) + exynosauto_pinctrl_suspend_bank(drvdata, bank); + else + exynos_pinctrl_suspend_bank(drvdata, bank); + } else if (bank->eint_type == EINT_TYPE_WKUP) { if (!irq_chip) { irq_chip = bank->irq_chip; @@ -704,14 +741,33 @@ static void exynos_pinctrl_resume_bank( + bank->eint_offset); } +static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data *drvdata, + struct samsung_pin_bank *bank) +{ + struct exynos_eint_gpio_save *save = bank->soc_priv; + void __iomem *regs = bank->eint_base; + + pr_debug("%s: con %#010x => %#010x\n", bank->name, + readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con); + pr_debug("%s: mask %#010x => %#010x\n", bank->name, + readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_mask); + + writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset); + writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset); +} + void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) { struct samsung_pin_bank *bank = drvdata->pin_banks; int i; for (i = 0; i < drvdata->nr_banks; ++i, ++bank) - if (bank->eint_type == EINT_TYPE_GPIO) - exynos_pinctrl_resume_bank(drvdata, bank); + if (bank->eint_type == EINT_TYPE_GPIO) { + if (bank->eint_con_offset) + exynosauto_pinctrl_resume_bank(drvdata, bank); + else + exynos_pinctrl_resume_bank(drvdata, bank); + } } static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 79babbb39ced..362e99566919 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1106,6 +1106,9 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d, bank->eint_type = bdata->eint_type; bank->eint_mask = bdata->eint_mask; bank->eint_offset = bdata->eint_offset; + bank->eint_con_offset = bdata->eint_con_offset; + bank->eint_mask_offset = bdata->eint_mask_offset; + bank->eint_pend_offset = bdata->eint_pend_offset; bank->name = bdata->name; raw_spin_lock_init(&bank->slock); diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 9b3db50adef3..789358bcd9c5 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -122,6 +122,9 @@ struct samsung_pin_bank_type { * @eint_type: type of the external interrupt supported by the bank. * @eint_mask: bit mask of pins which support EINT function. * @eint_offset: SoC-specific EINT register or interrupt offset of bank. + * @eint_con_offset: ExynosAuto SoC-specific EINT control register offset of bank. + * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank. + * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank. * @name: name to be prefixed for each pin in this pin bank. */ struct samsung_pin_bank_data { @@ -133,6 +136,9 @@ struct samsung_pin_bank_data { enum eint_type eint_type; u32 eint_mask; u32 eint_offset; + u32 eint_con_offset; + u32 eint_mask_offset; + u32 eint_pend_offset; const char *name; }; @@ -147,6 +153,9 @@ struct samsung_pin_bank_data { * @eint_type: type of the external interrupt supported by the bank. * @eint_mask: bit mask of pins which support EINT function. * @eint_offset: SoC-specific EINT register or interrupt offset of bank. + * @eint_con_offset: ExynosAuto SoC-specific EINT register or interrupt offset of bank. + * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of bank. + * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of bank. * @name: name to be prefixed for each pin in this pin bank. * @id: id of the bank, propagated to the pin range. * @pin_base: starting pin number of the bank. @@ -170,6 +179,9 @@ struct samsung_pin_bank { enum eint_type eint_type; u32 eint_mask; u32 eint_offset; + u32 eint_con_offset; + u32 eint_mask_offset; + u32 eint_pend_offset; const char *name; u32 id; -- 2.43.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
[parent not found: <CGME20231211114216epcas2p300bbf4c592d495991c6cc2d96e0b1f85@epcas2p3.samsung.com>]
* [PATCH v4 2/2] pinctrl: samsung: add exynosautov920 pinctrl [not found] ` <CGME20231211114216epcas2p300bbf4c592d495991c6cc2d96e0b1f85@epcas2p3.samsung.com> @ 2023-12-11 11:41 ` Jaewon Kim 2023-12-13 7:52 ` Krzysztof Kozlowski 0 siblings, 1 reply; 7+ messages in thread From: Jaewon Kim @ 2023-12-11 11:41 UTC (permalink / raw) To: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley, Tomasz Figa, Sylwester Nawrocki, Linus Walleij, Thierry Reding, Uwe Kleine-K?nig, Greg Kroah-Hartman, Jiri Slaby Cc: linux-arm-kernel, linux-samsung-soc, devicetree, linux-kernel, linux-gpio, linux-pwm, linux-serial, Jaewon Kim Add pinctrl data for ExynosAutov920 SoC. It has a newly applied pinctrl register layer for ExynosAuto series. Pinctrl data for ExynosAutoV920 SoC. - GPA0,GPA1 (10): External wake up interrupt - GPQ0 (2): SPMI (PMIC I/F) - GPB0,GPB1,GPB2,GPB3,GPB4,GPB5,GPB6 (47): I2S Audio - GPH0,GPH1,GPH2,GPH3,GPH4,GPH5,GPH6,GPH8 (49): PCIE, UFS, Ethernet - GPG0,GPG1,GPG2,GPG3,GPG4,GPG5 (29): General purpose - GPP0,GPP1,GPP2,GPP3,GPP4,GPP5,GPP6,GPP7,GPP8,GPP9,GPP10 (77): USI Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 140 ++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.c | 23 ++- drivers/pinctrl/samsung/pinctrl-exynos.h | 25 ++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 5 files changed, 190 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c index cb965cf93705..a998c296dd05 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -796,3 +796,143 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { .ctrl = fsd_pin_ctrl, .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), }; + +/* pin banks of exynosautov920 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynosautov920_pin_banks0[] = { + EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24), + EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"), +}; + +/* pin banks of exynosautov920 pin-controller 1 (AUD) */ +static const struct samsung_pin_bank_data exynosautov920_pin_banks1[] = { + EXYNOSV920_PIN_BANK_EINTG(7, 0x0000, "gpb0", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(6, 0x1000, "gpb1", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpb2", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpb3", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpb4", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(5, 0x5000, "gpb5", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(5, 0x6000, "gpb6", 0x18, 0x24, 0x28), +}; + +/* pin banks of exynosautov920 pin-controller 2 (HSI0) */ +static const struct samsung_pin_bank_data exynosautov920_pin_banks2[] = { + EXYNOSV920_PIN_BANK_EINTG(6, 0x0000, "gph0", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(2, 0x1000, "gph1", 0x18, 0x20, 0x24), +}; + +/* pin banks of exynosautov920 pin-controller 3 (HSI1) */ +static const struct samsung_pin_bank_data exynosautov920_pin_banks3[] = { + EXYNOSV920_PIN_BANK_EINTG(7, 0x000, "gph8", 0x18, 0x24, 0x28), +}; + +/* pin banks of exynosautov920 pin-controller 4 (HSI2) */ +static const struct samsung_pin_bank_data exynosautov920_pin_banks4[] = { + EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gph3", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(7, 0x1000, "gph4", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gph5", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(7, 0x3000, "gph6", 0x18, 0x24, 0x28), +}; + +/* pin banks of exynosautov920 pin-controller 5 (HSI2UFS) */ +static const struct samsung_pin_bank_data exynosautov920_pin_banks5[] = { + EXYNOSV920_PIN_BANK_EINTG(4, 0x000, "gph2", 0x18, 0x20, 0x24), +}; + +/* pin banks of exynosautov920 pin-controller 6 (PERIC0) */ +static const struct samsung_pin_bank_data exynosautov920_pin_banks6[] = { + EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp0", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(8, 0x1000, "gpp1", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(8, 0x2000, "gpp2", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(5, 0x3000, "gpg0", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(8, 0x4000, "gpp3", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp4", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpg2", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpg5", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(3, 0x8000, "gpg3", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(5, 0x9000, "gpg4", 0x18, 0x24, 0x28), +}; + +/* pin banks of exynosautov920 pin-controller 7 (PERIC1) */ +static const struct samsung_pin_bank_data exynosautov920_pin_banks7[] = { + EXYNOSV920_PIN_BANK_EINTG(8, 0x0000, "gpp5", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(5, 0x1000, "gpp6", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(4, 0x2000, "gpp10", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(8, 0x3000, "gpp7", 0x18, 0x24, 0x28), + EXYNOSV920_PIN_BANK_EINTG(4, 0x4000, "gpp8", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(4, 0x5000, "gpp11", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(4, 0x6000, "gpp9", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(4, 0x7000, "gpp12", 0x18, 0x20, 0x24), + EXYNOSV920_PIN_BANK_EINTG(8, 0x8000, "gpg1", 0x18, 0x24, 0x28), +}; + +static const struct samsung_retention_data exynosautov920_retention_data __initconst = { + .regs = NULL, + .nr_regs = 0, + .value = 0, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + +static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynosautov920_pin_banks0, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynosautov920_retention_data, + }, { + /* pin-controller instance 1 AUD data */ + .pin_banks = exynosautov920_pin_banks1, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks1), + }, { + /* pin-controller instance 2 HSI0 data */ + .pin_banks = exynosautov920_pin_banks2, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 HSI1 data */ + .pin_banks = exynosautov920_pin_banks3, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 4 HSI2 data */ + .pin_banks = exynosautov920_pin_banks4, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 5 HSI2UFS data */ + .pin_banks = exynosautov920_pin_banks5, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 6 PERIC0 data */ + .pin_banks = exynosautov920_pin_banks6, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 7 PERIC1 data */ + .pin_banks = exynosautov920_pin_banks7, + .nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +const struct samsung_pinctrl_of_match_data exynosautov920_of_data __initconst = { + .ctrl = exynosautov920_pin_ctrl, + .num_ctrl = ARRAY_SIZE(exynosautov920_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 77f747e629f7..934426d61a6f 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -267,7 +267,10 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) unsigned int svc, group, pin; int ret; - svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); + if (bank->eint_con_offset) + svc = readl(bank->eint_base + EXYNOSAUTO_SVC_OFFSET); + else + svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); group = EXYNOS_SVC_GROUP(svc); pin = svc & EXYNOS_SVC_NUM_MASK; @@ -476,6 +479,22 @@ static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = { .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask, }; +static const struct exynos_irq_chip exynosautov920_wkup_irq_chip __initconst = { + .chip = { + .name = "exynosautov920_wkup_irq_chip", + .irq_unmask = exynos_irq_unmask, + .irq_mask = exynos_irq_mask, + .irq_ack = exynos_irq_ack, + .irq_set_type = exynos_irq_set_type, + .irq_set_wake = exynos_wkup_irq_set_wake, + .irq_request_resources = exynos_irq_request_resources, + .irq_release_resources = exynos_irq_release_resources, + }, + .eint_wake_mask_value = &eint_wake_mask_value, + .eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK, + .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask, +}; + /* list of external wakeup controllers supported */ static const struct of_device_id exynos_wkup_irq_ids[] = { { .compatible = "samsung,s5pv210-wakeup-eint", @@ -488,6 +507,8 @@ static const struct of_device_id exynos_wkup_irq_ids[] = { .data = &exynos7_wkup_irq_chip }, { .compatible = "samsung,exynosautov9-wakeup-eint", .data = &exynos7_wkup_irq_chip }, + { .compatible = "samsung,exynosautov920-wakeup-eint", + .data = &exynosautov920_wkup_irq_chip }, { } }; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index 3ac52c2cf998..305cb1d31de4 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -31,6 +31,7 @@ #define EXYNOS7_WKUP_EMASK_OFFSET 0x900 #define EXYNOS7_WKUP_EPEND_OFFSET 0xA00 #define EXYNOS_SVC_OFFSET 0xB08 +#define EXYNOSAUTO_SVC_OFFSET 0xF008 /* helpers to access interrupt service register */ #define EXYNOS_SVC_GROUP_SHIFT 3 @@ -140,6 +141,30 @@ .name = id \ } +#define EXYNOSV920_PIN_BANK_EINTG(pins, reg, id, con_offs, mask_offs, pend_offs) \ + { \ + .type = &exynos850_bank_type_off, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_GPIO, \ + .eint_con_offset = con_offs, \ + .eint_mask_offset = mask_offs, \ + .eint_pend_offset = pend_offs, \ + .name = id \ + } + +#define EXYNOSV920_PIN_BANK_EINTW(pins, reg, id, con_offs, mask_offs, pend_offs) \ + { \ + .type = &exynos850_bank_type_alive, \ + .pctl_offset = reg, \ + .nr_pins = pins, \ + .eint_type = EINT_TYPE_WKUP, \ + .eint_con_offset = con_offs, \ + .eint_mask_offset = mask_offs, \ + .eint_pend_offset = pend_offs, \ + .name = id \ + } + /** * struct exynos_weint_data: irq specific data for all the wakeup interrupts * generated by the external wakeup interrupt controller. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index 362e99566919..47fb72fad8eb 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1322,6 +1322,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { .data = &exynos850_of_data }, { .compatible = "samsung,exynosautov9-pinctrl", .data = &exynosautov9_of_data }, + { .compatible = "samsung,exynosautov920-pinctrl", + .data = &exynosautov920_of_data }, { .compatible = "tesla,fsd-pinctrl", .data = &fsd_of_data }, #endif diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h index 789358bcd9c5..987086fa0d1d 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -362,6 +362,7 @@ extern const struct samsung_pinctrl_of_match_data exynos7_of_data; extern const struct samsung_pinctrl_of_match_data exynos7885_of_data; extern const struct samsung_pinctrl_of_match_data exynos850_of_data; extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data; +extern const struct samsung_pinctrl_of_match_data exynosautov920_of_data; extern const struct samsung_pinctrl_of_match_data fsd_of_data; extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data; extern const struct samsung_pinctrl_of_match_data s3c2412_of_data; -- 2.43.0 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v4 2/2] pinctrl: samsung: add exynosautov920 pinctrl 2023-12-11 11:41 ` [PATCH v4 2/2] pinctrl: samsung: add exynosautov920 pinctrl Jaewon Kim @ 2023-12-13 7:52 ` Krzysztof Kozlowski 2023-12-13 8:10 ` Jaewon Kim 0 siblings, 1 reply; 7+ messages in thread From: Krzysztof Kozlowski @ 2023-12-13 7:52 UTC (permalink / raw) To: Jaewon Kim, Alim Akhtar, Rob Herring, Conor Dooley, Tomasz Figa, Sylwester Nawrocki, Linus Walleij, Thierry Reding, Uwe Kleine-K?nig, Greg Kroah-Hartman, Jiri Slaby Cc: linux-arm-kernel, linux-samsung-soc, devicetree, linux-kernel, linux-gpio, linux-pwm, linux-serial On 11/12/2023 12:41, Jaewon Kim wrote: > Add pinctrl data for ExynosAutov920 SoC. > It has a newly applied pinctrl register layer for ExynosAuto series. > > Pinctrl data for ExynosAutoV920 SoC. > - GPA0,GPA1 (10): External wake up interrupt > - GPQ0 (2): SPMI (PMIC I/F) > - GPB0,GPB1,GPB2,GPB3,GPB4,GPB5,GPB6 (47): I2S Audio > - GPH0,GPH1,GPH2,GPH3,GPH4,GPH5,GPH6,GPH8 (49): PCIE, UFS, Ethernet > - GPG0,GPG1,GPG2,GPG3,GPG4,GPG5 (29): General purpose > - GPP0,GPP1,GPP2,GPP3,GPP4,GPP5,GPP6,GPP7,GPP8,GPP9,GPP10 (77): USI > > Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> > --- > .../pinctrl/samsung/pinctrl-exynos-arm64.c | 140 ++++++++++++++++++ > drivers/pinctrl/samsung/pinctrl-exynos.c | 23 ++- > drivers/pinctrl/samsung/pinctrl-exynos.h | 25 ++++ > drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + > drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + > 5 files changed, 190 insertions(+), 1 deletion(-) > > diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > index cb965cf93705..a998c296dd05 100644 > --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c > @@ -796,3 +796,143 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { > .ctrl = fsd_pin_ctrl, > .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), > }; > + > +/* pin banks of exynosautov920 pin-controller 0 (ALIVE) */ > +static const struct samsung_pin_bank_data exynosautov920_pin_banks0[] = { > + EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28), > + EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24), > + EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"), > +}; Applied with re-ordering it, to keep it after ExynosAutov9. For the future: don't add entries to the end of lists because it causes exactly this issue we have here: unnecessary conflicts. Please keep this rule for entire development, not only pinctrl. If both you and Peter were observing this basic rule, I would not have work of reshuffling and fixing conflicts. Please check the result if I reshuffled/solved conflicts correctly. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 2/2] pinctrl: samsung: add exynosautov920 pinctrl 2023-12-13 7:52 ` Krzysztof Kozlowski @ 2023-12-13 8:10 ` Jaewon Kim 2023-12-13 8:14 ` Krzysztof Kozlowski 0 siblings, 1 reply; 7+ messages in thread From: Jaewon Kim @ 2023-12-13 8:10 UTC (permalink / raw) To: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley, Tomasz Figa, Sylwester Nawrocki, Linus Walleij, Thierry Reding, Uwe Kleine-K?nig, Greg Kroah-Hartman, Jiri Slaby Cc: linux-arm-kernel, linux-samsung-soc, devicetree, linux-kernel, linux-gpio, linux-pwm, linux-serial On 23. 12. 13. 16:52, Krzysztof Kozlowski wrote: > On 11/12/2023 12:41, Jaewon Kim wrote: >> Add pinctrl data for ExynosAutov920 SoC. >> It has a newly applied pinctrl register layer for ExynosAuto series. >> >> Pinctrl data for ExynosAutoV920 SoC. >> - GPA0,GPA1 (10): External wake up interrupt >> - GPQ0 (2): SPMI (PMIC I/F) >> - GPB0,GPB1,GPB2,GPB3,GPB4,GPB5,GPB6 (47): I2S Audio >> - GPH0,GPH1,GPH2,GPH3,GPH4,GPH5,GPH6,GPH8 (49): PCIE, UFS, Ethernet >> - GPG0,GPG1,GPG2,GPG3,GPG4,GPG5 (29): General purpose >> - GPP0,GPP1,GPP2,GPP3,GPP4,GPP5,GPP6,GPP7,GPP8,GPP9,GPP10 (77): USI >> >> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> >> --- >> .../pinctrl/samsung/pinctrl-exynos-arm64.c | 140 ++++++++++++++++++ >> drivers/pinctrl/samsung/pinctrl-exynos.c | 23 ++- >> drivers/pinctrl/samsung/pinctrl-exynos.h | 25 ++++ >> drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + >> drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + >> 5 files changed, 190 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c >> index cb965cf93705..a998c296dd05 100644 >> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c >> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c >> @@ -796,3 +796,143 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { >> .ctrl = fsd_pin_ctrl, >> .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), >> }; >> + >> +/* pin banks of exynosautov920 pin-controller 0 (ALIVE) */ >> +static const struct samsung_pin_bank_data exynosautov920_pin_banks0[] = { >> + EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28), >> + EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24), >> + EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"), >> +};e > Applied with re-ordering it, to keep it after ExynosAutov9. For the > future: don't add entries to the end of lists because it causes exactly > this issue we have here: unnecessary conflicts. Please keep this rule > for entire development, not only pinctrl. > > If both you and Peter were observing this basic rule, I would not have > work of reshuffling and fixing conflicts. > > Please check the result if I reshuffled/solved conflicts correctly. > I thought the new SoC should go to the end, but I was wrong. I will follow your comments in alphabetical order. Thanks you sincerely. Thanks Jaewon Kim ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 2/2] pinctrl: samsung: add exynosautov920 pinctrl 2023-12-13 8:10 ` Jaewon Kim @ 2023-12-13 8:14 ` Krzysztof Kozlowski 0 siblings, 0 replies; 7+ messages in thread From: Krzysztof Kozlowski @ 2023-12-13 8:14 UTC (permalink / raw) To: Jaewon Kim, Alim Akhtar, Rob Herring, Conor Dooley, Tomasz Figa, Sylwester Nawrocki, Linus Walleij, Thierry Reding, Uwe Kleine-K?nig, Greg Kroah-Hartman, Jiri Slaby Cc: linux-arm-kernel, linux-samsung-soc, devicetree, linux-kernel, linux-gpio, linux-pwm, linux-serial On 13/12/2023 09:10, Jaewon Kim wrote: > > On 23. 12. 13. 16:52, Krzysztof Kozlowski wrote: >> On 11/12/2023 12:41, Jaewon Kim wrote: >>> Add pinctrl data for ExynosAutov920 SoC. >>> It has a newly applied pinctrl register layer for ExynosAuto series. >>> >>> Pinctrl data for ExynosAutoV920 SoC. >>> - GPA0,GPA1 (10): External wake up interrupt >>> - GPQ0 (2): SPMI (PMIC I/F) >>> - GPB0,GPB1,GPB2,GPB3,GPB4,GPB5,GPB6 (47): I2S Audio >>> - GPH0,GPH1,GPH2,GPH3,GPH4,GPH5,GPH6,GPH8 (49): PCIE, UFS, Ethernet >>> - GPG0,GPG1,GPG2,GPG3,GPG4,GPG5 (29): General purpose >>> - GPP0,GPP1,GPP2,GPP3,GPP4,GPP5,GPP6,GPP7,GPP8,GPP9,GPP10 (77): USI >>> >>> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> >>> --- >>> .../pinctrl/samsung/pinctrl-exynos-arm64.c | 140 ++++++++++++++++++ >>> drivers/pinctrl/samsung/pinctrl-exynos.c | 23 ++- >>> drivers/pinctrl/samsung/pinctrl-exynos.h | 25 ++++ >>> drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + >>> drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + >>> 5 files changed, 190 insertions(+), 1 deletion(-) >>> >>> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c >>> index cb965cf93705..a998c296dd05 100644 >>> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c >>> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c >>> @@ -796,3 +796,143 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = { >>> .ctrl = fsd_pin_ctrl, >>> .num_ctrl = ARRAY_SIZE(fsd_pin_ctrl), >>> }; >>> + >>> +/* pin banks of exynosautov920 pin-controller 0 (ALIVE) */ >>> +static const struct samsung_pin_bank_data exynosautov920_pin_banks0[] = { >>> + EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28), >>> + EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24), >>> + EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"), >>> +};e >> Applied with re-ordering it, to keep it after ExynosAutov9. For the >> future: don't add entries to the end of lists because it causes exactly >> this issue we have here: unnecessary conflicts. Please keep this rule >> for entire development, not only pinctrl. >> >> If both you and Peter were observing this basic rule, I would not have >> work of reshuffling and fixing conflicts. >> >> Please check the result if I reshuffled/solved conflicts correctly. >> > > I thought the new SoC should go to the end, but I was wrong. > Peter's Google's structures went to the end, which was actually alphabetical. You also added to the end thus git could not apply the patch. Even cherry-pick had troubles, so I need to manually copy code from downloaded patch. That's the main reason of not putting stuff to the end, but to some logical place, usually alphabetical. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 0/2] Introduce ExynosAutov920 SoC and SADK board 2023-12-11 11:41 ` [PATCH v4 0/2] Introduce ExynosAutov920 SoC and SADK board Jaewon Kim [not found] ` <CGME20231211114215epcas2p21c9a1c2157cd1650f5ec12487eddb576@epcas2p2.samsung.com> [not found] ` <CGME20231211114216epcas2p300bbf4c592d495991c6cc2d96e0b1f85@epcas2p3.samsung.com> @ 2023-12-13 7:50 ` Krzysztof Kozlowski 2 siblings, 0 replies; 7+ messages in thread From: Krzysztof Kozlowski @ 2023-12-13 7:50 UTC (permalink / raw) To: Alim Akhtar, Rob Herring, Conor Dooley, Tomasz Figa, Sylwester Nawrocki, Linus Walleij, Thierry Reding, Uwe Kleine-K?nig, Greg Kroah-Hartman, Jiri Slaby, Jaewon Kim Cc: linux-arm-kernel, linux-samsung-soc, devicetree, linux-kernel, linux-gpio, linux-pwm, linux-serial On Mon, 11 Dec 2023 20:41:43 +0900, Jaewon Kim wrote: > ExynosAutov920[1] is ARMv8-based automotive-oriented SoC. > This SoC is the next generation of exynosautov9 and AE(Automotive Enhanced) > IPs are used for safety. > > This patchset is the minimal set for ExynosAutov920 SoC and SADK board. > Currently, ramdisk console is available and Clock, UFS, and USI will be > added after this patchset. > > [...] Applied, thanks! [1/2] pinctrl: samsung: support ExynosAuto GPIO structure https://git.kernel.org/pinctrl/samsung/c/884fdaa53b38921165cd9afdb230502b4e1690b0 [2/2] pinctrl: samsung: add exynosautov920 pinctrl https://git.kernel.org/pinctrl/samsung/c/6cf96df77338c6a7e753229fe6d330ab60e28cda Best regards, -- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> ^ permalink raw reply [flat|nested] 7+ messages in thread
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