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[94.175.9.129]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-432bd5ee5e3sm22332156f8f.35.2026.01.09.04.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jan 2026 04:51:44 -0800 (PST) Date: Fri, 9 Jan 2026 12:51:43 +0000 From: Stafford Horne To: Linus Walleij Cc: Geert Uytterhoeven , LKML , Linux OpenRISC , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 1/5] dt-bindings: Add compatible string opencores,gpio to gpio-mmio Message-ID: References: <20251217080843.70621-1-shorne@gmail.com> <20251217080843.70621-2-shorne@gmail.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Fri, Jan 09, 2026 at 11:07:17AM +0100, Linus Walleij wrote: > On Thu, Jan 8, 2026 at 9:41 AM Geert Uytterhoeven wrote: > > > > > What is the rationale behind using brcm,bcm6345-gpio? > > > > Given brcm,bcm6345-gpio has 32-bit registers, while opencores,gpio > > > > has 8-bit registers, I doubt the latter is compatible with the former... > > Yeah this needs to be fixed/reverted pronto :/ > > > > I switch the size from 32-bit to 8-bit using the reg = <* 0x1>, <* 0x1> setting. > > > Also the reg addresses of "dat" and "dirout" are different for the real > > > brcm,bcm6345-gpio. > > > > > > brcm,bcm6345-gpio. Example: > > > > > > /* GPIOs 192 .. 223 */ > > > gpio6: gpio@518 { > > > compatible = "brcm,bcm6345-gpio"; > > > reg = <0x518 0x04>, <0x538 0x04>; > > > reg-names = "dirout", "dat"; > > > gpio-controller; > > > #gpio-cells = <2>; > > > }; > > > > > > vs opencores,gpio Example: > > > > > > gpio0: gpio@91000000 { > > > compatible = "opencores,gpio", "brcm,bcm6345-gpio"; > > > reg = <0x91000000 0x1>, <0x91000001 0x1>; > > > reg-names = "dat", "dirout"; > > > gpio-controller; > > > #gpio-cells = <2>; > > > }; > > > > Exactly, the register space and register widths are different > > ...as proved here. > > Stafford can you send a fixup or revert patch? > (Only need to revert if you can't make a fix quick enough, which I > think you can.) Sure, I'll send a fixup to the devicetree binding and a update to the driver to just support opencores,gpio. Hopefully, that can be picked up in time by Bartosz who has this one staged in gpio/for-next. I'll send the 2 patches as part of my series for OpenRISC multicore fixups as the devicetree's I have added have a soft dependency the patches. After/if the patches are pulled to the gpio branch I can drop them from my queue and I'll just have to make sure Linux merged the GPIO changes binding updates before the OpenRISC updates during the merge window. Let me know if there are any issues. > > > The opencores,gpio setup does work. > > > > > > Now that I think about it, would it have been better to just add opencores,gpio > > > to gpio-mmio.c compatible list? > > > > I think that would be better. > > Yes this is better. > > I should have seen this, I guess I was sloppy :( I should have also thought more, but I don't do this often enough to remember all of the rules. Sorry for the head ache. -Stafford