[PATCH 0/3] SDM670 LPASS LPI pin controller support

[PATCH 0/3] SDM670 LPASS LPI pin controller support

[Richard Acayan]

This adds support for the LPASS LPI pin controller on SDM670, which
controls some audio pins (e.g. TDM or PDM busses). The ADSP patches are
not sent yet.

Richard Acayan (3):
  dt-bindings: pinctrl: qcom: Add SDM670 LPI pinctrl
  pinctrl: qcom: add sdm670 lpi tlmm
  arm64: dts: qcom: sdm670: add lpi pinctrl

 .../qcom,sdm670-lpass-lpi-pinctrl.yaml        |  81 ++++++++
 arch/arm64/boot/dts/qcom/sdm670.dtsi          |  74 ++++++++
 drivers/pinctrl/qcom/Kconfig                  |  10 +
 drivers/pinctrl/qcom/Makefile                 |   1 +
 .../pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c   | 174 ++++++++++++++++++
 5 files changed, 340 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml
 create mode 100644 drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c

-- 
2.53.0

[PATCH 1/3] dt-bindings: pinctrl: qcom: Add SDM670 LPI pinctrl

[Richard Acayan]

Add the pin controller for the audio Low-Power Island (LPI) on SDM670.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
 .../qcom,sdm670-lpass-lpi-pinctrl.yaml        | 81 +++++++++++++++++++
 1 file changed, 81 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml
new file mode 100644
index 000000000000..125f365d11fa
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SDM670 SoC LPASS LPI TLMM
+
+maintainers:
+  - Richard Acayan <mailingradian@gmail.com>
+
+description:
+  Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
+  (LPASS) Low Power Island (LPI) of Qualcomm SDM670 SoC.
+
+properties:
+  compatible:
+    const: qcom,sdm670-lpass-lpi-pinctrl
+
+  reg:
+    items:
+      - description: LPASS LPI TLMM Control and Status registers
+
+patternProperties:
+  "-state$":
+    oneOf:
+      - $ref: "#/$defs/qcom-sdm670-lpass-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-sdm670-lpass-state"
+        additionalProperties: false
+
+$defs:
+  qcom-sdm670-lpass-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+    $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
+    unevaluatedProperties: false
+
+    properties:
+      pins:
+        description:
+          List of gpio pins affected by the properties specified in this
+          subnode.
+        items:
+          pattern: "^gpio([0-9]|1[0-9]|2[0-9]|3[0-1])$"
+
+      function:
+        enum: [ gpio, comp_rx, dmic1_clk, dmic1_data, dmic2_clk, dmic2_data,
+                lpi_cdc_rst, mclk0, pdm_tx, pdm_clk, pdm_rx, pdm_sync, sec_tdm,
+                sec_tdm_din, sec_tdm_dout ]
+        description:
+          Specify the alternative function to be configured for the specified
+          pins.
+
+allOf:
+  - $ref: qcom,lpass-lpi-common.yaml#
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    lpi_tlmm: pinctrl@62b40000 {
+        compatible = "qcom,sdm670-lpass-lpi-pinctrl";
+        reg = <0x62b40000 0x20000>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        gpio-ranges = <&lpi_tlmm 0 0 32>;
+
+        cdc_comp_default: cdc-comp-default-state {
+            pins = "gpio22", "gpio24";
+            function = "comp_rx";
+            drive-strength = <4>;
+        };
+    };
-- 
2.53.0

Re: [PATCH 1/3] dt-bindings: pinctrl: qcom: Add SDM670 LPI pinctrl

[Krzysztof Kozlowski]

On 10/02/2026 03:11, Richard Acayan wrote:
> Add the pin controller for the audio Low-Power Island (LPI) on SDM670.

Subject: Missing "LPASS" before LPI. I really thought you just add TLMM...

> 
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
>  .../qcom,sdm670-lpass-lpi-pinctrl.yaml        | 81 +++++++++++++++++++
>  1 file changed, 81 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml
> new file mode 100644
> index 000000000000..125f365d11fa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml
> @@ -0,0 +1,81 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SDM670 SoC LPASS LPI TLMM
> +
> +maintainers:
> +  - Richard Acayan <mailingradian@gmail.com>
> +
> +description:
> +  Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
> +  (LPASS) Low Power Island (LPI) of Qualcomm SDM670 SoC.
> +
> +properties:
> +  compatible:
> +    const: qcom,sdm670-lpass-lpi-pinctrl
> +
> +  reg:
> +    items:
> +      - description: LPASS LPI TLMM Control and Status registers
> +

Hm, no clocks? In most designs there has to be HW macro or HW codec
vote. I see SDM660 does not have it either, but I think this might be
exactly the same mistake.


> +patternProperties:
> +  "-state$":
> +    oneOf:
> +      - $ref: "#/$defs/qcom-sdm670-lpass-state"
> +      - patternProperties:
> +          "-pins$":
> +            $ref: "#/$defs/qcom-sdm670-lpass-state"
> +        additionalProperties: false
> +



Best regards,
Krzysztof

Re: [PATCH 1/3] dt-bindings: pinctrl: qcom: Add SDM670 LPI pinctrl

[Richard Acayan]

On Tue, Feb 10, 2026 at 08:41:32AM +0100, Krzysztof Kozlowski wrote:
> On 10/02/2026 03:11, Richard Acayan wrote:
> > Add the pin controller for the audio Low-Power Island (LPI) on SDM670.
> 
> Subject: Missing "LPASS" before LPI. I really thought you just add TLMM...

Added, but does this extend to the other patches as well?

> > 
> > Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> > ---
> >  .../qcom,sdm670-lpass-lpi-pinctrl.yaml        | 81 +++++++++++++++++++
> >  1 file changed, 81 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml
> > new file mode 100644
> > index 000000000000..125f365d11fa
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml
> > @@ -0,0 +1,81 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm SDM670 SoC LPASS LPI TLMM
> > +
> > +maintainers:
> > +  - Richard Acayan <mailingradian@gmail.com>
> > +
> > +description:
> > +  Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
> > +  (LPASS) Low Power Island (LPI) of Qualcomm SDM670 SoC.
> > +
> > +properties:
> > +  compatible:
> > +    const: qcom,sdm670-lpass-lpi-pinctrl
> > +
> > +  reg:
> > +    items:
> > +      - description: LPASS LPI TLMM Control and Status registers
> > +
> 
> Hm, no clocks? In most designs there has to be HW macro or HW codec
> vote. I see SDM660 does not have it either, but I think this might be
> exactly the same mistake.

No clocks for the pin controller, unless the ADSP enables them on its own.

I see other clocks required for full sound support (including some
board-specific codecs), which are unrelated:
- INT_MCLK_0
- PRI_TDM_IBIT
- SEC_TDM_IBIT
- INT0_MI2S_IBIT
- INT3_MI2S_IBIT

Re: [PATCH 1/3] dt-bindings: pinctrl: qcom: Add SDM670 LPI pinctrl

[Krzysztof Kozlowski]

On 10/02/2026 03:11, Richard Acayan wrote:
> Add the pin controller for the audio Low-Power Island (LPI) on SDM670.
> 
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH 2/3] pinctrl: qcom: add sdm670 lpi tlmm

[Richard Acayan]

The Snapdragon 670 has an Low-Power Island (LPI) TLMM for configuring
pins related to audio. Add the driver for this.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
 drivers/pinctrl/qcom/Kconfig                  |  10 +
 drivers/pinctrl/qcom/Makefile                 |   1 +
 .../pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c   | 174 ++++++++++++++++++
 3 files changed, 185 insertions(+)
 create mode 100644 drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c

diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index c480e8b78503..a88f1db96841 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -88,6 +88,16 @@ config PINCTRL_SM4250_LPASS_LPI
 	  Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
 	  (Low Power Island) found on the Qualcomm Technologies Inc SM4250 platform.
 
+config PINCTRL_SDM670_LPASS_LPI
+	tristate "Qualcomm Technologies Inc SDM670 LPASS LPI pin controller driver"
+	depends on GPIOLIB
+	depends on ARM64 || COMPILE_TEST
+	depends on PINCTRL_LPASS_LPI
+	help
+	  This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+	  Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI
+	  (Low Power Island) found on the Qualcomm Technologies Inc SDM670 platform.
+
 config PINCTRL_SM6115_LPASS_LPI
 	tristate "Qualcomm Technologies Inc SM6115 LPASS LPI pin controller driver"
 	depends on ARM64 || COMPILE_TEST
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 748b17a77b2c..a0520e1f8aa0 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_PINCTRL_SC8280XP)	+= pinctrl-sc8280xp.o
 obj-$(CONFIG_PINCTRL_SDM660)   += pinctrl-sdm660.o
 obj-$(CONFIG_PINCTRL_SDM660_LPASS_LPI) += pinctrl-sdm660-lpass-lpi.o
 obj-$(CONFIG_PINCTRL_SDM670) += pinctrl-sdm670.o
+obj-$(CONFIG_PINCTRL_SDM670_LPASS_LPI) += pinctrl-sdm670-lpass-lpi.o
 obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
 obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o
 obj-$(CONFIG_PINCTRL_SDX65) += pinctrl-sdx65.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c
new file mode 100644
index 000000000000..604a445d4ec5
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sdm670-lpass-lpi.c
@@ -0,0 +1,174 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2023-2026, Richard Acayan. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-lpass-lpi.h"
+
+enum lpass_lpi_functions {
+	LPI_MUX_sec_tdm,
+	LPI_MUX_sec_tdm_din,
+	LPI_MUX_sec_tdm_dout,
+
+	LPI_MUX_comp_rx,
+	LPI_MUX_dmic1_clk,
+	LPI_MUX_dmic1_data,
+	LPI_MUX_dmic2_clk,
+	LPI_MUX_dmic2_data,
+	LPI_MUX_lpi_cdc_rst,
+	LPI_MUX_mclk0,
+	LPI_MUX_pdm_clk,
+	LPI_MUX_pdm_rx,
+	LPI_MUX_pdm_sync,
+	LPI_MUX_pdm_tx,
+
+	LPI_MUX_gpio,
+	LPI_MUX__,
+};
+
+static const struct pinctrl_pin_desc sdm670_lpi_pinctrl_pins[] = {
+	PINCTRL_PIN(0, "gpio0"),
+	PINCTRL_PIN(1, "gpio1"),
+	PINCTRL_PIN(2, "gpio2"),
+	PINCTRL_PIN(3, "gpio3"),
+	PINCTRL_PIN(4, "gpio4"),
+	PINCTRL_PIN(5, "gpio5"),
+	PINCTRL_PIN(6, "gpio6"),
+	PINCTRL_PIN(7, "gpio7"),
+	PINCTRL_PIN(8, "gpio8"),
+	PINCTRL_PIN(9, "gpio9"),
+	PINCTRL_PIN(10, "gpio10"),
+	PINCTRL_PIN(11, "gpio11"),
+	PINCTRL_PIN(12, "gpio12"),
+	PINCTRL_PIN(13, "gpio13"),
+	PINCTRL_PIN(14, "gpio14"),
+	PINCTRL_PIN(15, "gpio15"),
+	PINCTRL_PIN(16, "gpio16"),
+	PINCTRL_PIN(17, "gpio17"),
+	PINCTRL_PIN(18, "gpio18"),
+	PINCTRL_PIN(19, "gpio19"),
+	PINCTRL_PIN(20, "gpio20"),
+	PINCTRL_PIN(21, "gpio21"),
+	PINCTRL_PIN(22, "gpio22"),
+	PINCTRL_PIN(23, "gpio23"),
+	PINCTRL_PIN(24, "gpio24"),
+	PINCTRL_PIN(25, "gpio25"),
+	PINCTRL_PIN(26, "gpio26"),
+	PINCTRL_PIN(27, "gpio27"),
+	PINCTRL_PIN(28, "gpio28"),
+	PINCTRL_PIN(29, "gpio29"),
+	PINCTRL_PIN(30, "gpio30"),
+	PINCTRL_PIN(31, "gpio31"),
+};
+
+static const char * const sec_tdm_groups[] = { "gpio8", "gpio9" };
+static const char * const sec_tdm_din_groups[] = { "gpio10" };
+static const char * const sec_tdm_dout_groups[] = { "gpio11" };
+
+static const char * const comp_rx_groups[] = { "gpio22", "gpio24" };
+static const char * const dmic1_clk_groups[] = { "gpio26" };
+static const char * const dmic1_data_groups[] = { "gpio27" };
+static const char * const dmic2_clk_groups[] = { "gpio28" };
+static const char * const dmic2_data_groups[] = { "gpio29" };
+static const char * const lpi_cdc_rst_groups[] = { "gpio29" };
+static const char * const mclk0_groups[] = { "gpio19" };
+static const char * const pdm_clk_groups[] = { "gpio18" };
+static const char * const pdm_rx_groups[] = { "gpio21", "gpio23", "gpio25" };
+static const char * const pdm_sync_groups[] = { "gpio19" };
+static const char * const pdm_tx_groups[] = { "gpio20" };
+
+const struct lpi_pingroup sdm670_lpi_pinctrl_groups[] = {
+	LPI_PINGROUP(0, LPI_NO_SLEW, _, _, _, _),
+	LPI_PINGROUP(1, LPI_NO_SLEW, _, _, _, _),
+	LPI_PINGROUP(2, LPI_NO_SLEW, _, _, _, _),
+	LPI_PINGROUP(3, LPI_NO_SLEW, _, _, _, _),
+	LPI_PINGROUP(4, LPI_NO_SLEW, _, _, _, _),
+	LPI_PINGROUP(5, LPI_NO_SLEW, _, _, _, _),
+	LPI_PINGROUP(6, LPI_NO_SLEW, _, _, _, _),
+	LPI_PINGROUP(7, LPI_NO_SLEW, _, _, _, _),
+
+	LPI_PINGROUP(8, LPI_NO_SLEW, _, _, sec_tdm, _),
+	LPI_PINGROUP(9, LPI_NO_SLEW, _, _, sec_tdm, _),
+	LPI_PINGROUP(10, LPI_NO_SLEW, _, _, _, sec_tdm_din),
+	LPI_PINGROUP(11, LPI_NO_SLEW, _, sec_tdm_dout, _, _),
+
+	LPI_PINGROUP(12, LPI_NO_SLEW, _, _, _, _),
+	LPI_PINGROUP(13, LPI_NO_SLEW, _, _, _, _),
+	LPI_PINGROUP(14, LPI_NO_SLEW, _, _, _, _),
+	LPI_PINGROUP(15, LPI_NO_SLEW, _, _, _, _),
+	LPI_PINGROUP(16, LPI_NO_SLEW, _, _, _, _),
+	LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _),
+
+	LPI_PINGROUP(18, LPI_NO_SLEW, _, pdm_clk, _, _),
+	LPI_PINGROUP(19, LPI_NO_SLEW, mclk0, _, pdm_sync, _),
+	LPI_PINGROUP(20, LPI_NO_SLEW, _, pdm_tx, _, _),
+	LPI_PINGROUP(21, LPI_NO_SLEW, _, pdm_rx, _, _),
+	LPI_PINGROUP(22, LPI_NO_SLEW, _, comp_rx, _, _),
+	LPI_PINGROUP(23, LPI_NO_SLEW, pdm_rx, _, _, _),
+	LPI_PINGROUP(24, LPI_NO_SLEW, comp_rx, _, _, _),
+	LPI_PINGROUP(25, LPI_NO_SLEW, pdm_rx, _, _, _),
+	LPI_PINGROUP(26, LPI_NO_SLEW, dmic1_clk, _, _, _),
+	LPI_PINGROUP(27, LPI_NO_SLEW, dmic1_data, _, _, _),
+	LPI_PINGROUP(28, LPI_NO_SLEW, dmic2_clk, _, _, _),
+	LPI_PINGROUP(29, LPI_NO_SLEW, dmic2_data, lpi_cdc_rst, _, _),
+
+	LPI_PINGROUP(30, LPI_NO_SLEW, _, _, _, _),
+	LPI_PINGROUP(31, LPI_NO_SLEW, _, _, _, _),
+};
+
+const struct lpi_function sdm670_lpi_pinctrl_functions[] = {
+	LPI_FUNCTION(sec_tdm),
+	LPI_FUNCTION(sec_tdm_din),
+	LPI_FUNCTION(sec_tdm_dout),
+
+	LPI_FUNCTION(comp_rx),
+	LPI_FUNCTION(dmic1_clk),
+	LPI_FUNCTION(dmic1_data),
+	LPI_FUNCTION(dmic2_clk),
+	LPI_FUNCTION(dmic2_data),
+	LPI_FUNCTION(lpi_cdc_rst),
+	LPI_FUNCTION(mclk0),
+	LPI_FUNCTION(pdm_tx),
+	LPI_FUNCTION(pdm_clk),
+	LPI_FUNCTION(pdm_rx),
+	LPI_FUNCTION(pdm_sync),
+};
+
+static const struct lpi_pinctrl_variant_data sdm670_lpi_pinctrl_data = {
+	.pins = sdm670_lpi_pinctrl_pins,
+	.npins = ARRAY_SIZE(sdm670_lpi_pinctrl_pins),
+	.groups = sdm670_lpi_pinctrl_groups,
+	.ngroups = ARRAY_SIZE(sdm670_lpi_pinctrl_groups),
+	.functions = sdm670_lpi_pinctrl_functions,
+	.nfunctions = ARRAY_SIZE(sdm670_lpi_pinctrl_functions),
+	.flags = LPI_FLAG_SLEW_RATE_SAME_REG,
+};
+
+static const struct of_device_id sdm670_lpi_pinctrl_of_match[] = {
+	{
+		.compatible = "qcom,sdm670-lpass-lpi-pinctrl",
+		.data = &sdm670_lpi_pinctrl_data,
+	},
+	{ }
+};
+MODULE_DEVICE_TABLE(of, sdm670_lpi_pinctrl_of_match);
+
+static struct platform_driver sdm670_lpi_pinctrl_driver = {
+	.driver = {
+		.name = "qcom-sdm670-lpass-lpi-pinctrl",
+		.of_match_table = sdm670_lpi_pinctrl_of_match,
+	},
+	.probe = lpi_pinctrl_probe,
+	.remove = lpi_pinctrl_remove,
+};
+module_platform_driver(sdm670_lpi_pinctrl_driver);
+
+MODULE_AUTHOR("Richard Acayan <mailingradian@gmail.com>");
+MODULE_DESCRIPTION("QTI SDM670 LPI GPIO pin control driver");
+MODULE_LICENSE("GPL");
-- 
2.53.0

Re: [PATCH 2/3] pinctrl: qcom: add sdm670 lpi tlmm

[Konrad Dybcio]

On 2/10/26 3:11 AM, Richard Acayan wrote:
> The Snapdragon 670 has an Low-Power Island (LPI) TLMM for configuring
> pins related to audio. Add the driver for this.
> 
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---

[...]

> +const struct lpi_pingroup sdm670_lpi_pinctrl_groups[] = {
> +	LPI_PINGROUP(0, LPI_NO_SLEW, _, _, _, _),
> +	LPI_PINGROUP(1, LPI_NO_SLEW, _, _, _, _),
> +	LPI_PINGROUP(2, LPI_NO_SLEW, _, _, _, _),
> +	LPI_PINGROUP(3, LPI_NO_SLEW, _, _, _, _),
> +	LPI_PINGROUP(4, LPI_NO_SLEW, _, _, _, _),
> +	LPI_PINGROUP(5, LPI_NO_SLEW, _, _, _, _),
> +	LPI_PINGROUP(6, LPI_NO_SLEW, _, _, _, _),
> +	LPI_PINGROUP(7, LPI_NO_SLEW, _, _, _, _),
> +
> +	LPI_PINGROUP(8, LPI_NO_SLEW, _, _, sec_tdm, _),

"i2s1_clk"

> +	LPI_PINGROUP(9, LPI_NO_SLEW, _, _, sec_tdm, _),

"i2s1_ws"

> +	LPI_PINGROUP(10, LPI_NO_SLEW, _, _, _, sec_tdm_din),

"i2s1_data"

> +	LPI_PINGROUP(11, LPI_NO_SLEW, _, sec_tdm_dout, _, _),

"i2s1_data"

> +
> +	LPI_PINGROUP(12, LPI_NO_SLEW, _, _, _, _),
> +	LPI_PINGROUP(13, LPI_NO_SLEW, _, _, _, _),
> +	LPI_PINGROUP(14, LPI_NO_SLEW, _, _, _, _),
> +	LPI_PINGROUP(15, LPI_NO_SLEW, _, _, _, _),
> +	LPI_PINGROUP(16, LPI_NO_SLEW, _, _, _, _),
> +	LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _),
> +
> +	LPI_PINGROUP(18, LPI_NO_SLEW, _, pdm_clk, _, _),

"slimbus_clk"

Konrad

Re: [PATCH 2/3] pinctrl: qcom: add sdm670 lpi tlmm

[Richard Acayan]

On Tue, Feb 10, 2026 at 10:08:19AM +0100, Konrad Dybcio wrote:
> On 2/10/26 3:11 AM, Richard Acayan wrote:
> > The Snapdragon 670 has an Low-Power Island (LPI) TLMM for configuring
> > pins related to audio. Add the driver for this.
> > 
> > Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> > ---
> 
> [...]
> 
> > +const struct lpi_pingroup sdm670_lpi_pinctrl_groups[] = {
> > +	LPI_PINGROUP(0, LPI_NO_SLEW, _, _, _, _),
> > +	LPI_PINGROUP(1, LPI_NO_SLEW, _, _, _, _),
> > +	LPI_PINGROUP(2, LPI_NO_SLEW, _, _, _, _),
> > +	LPI_PINGROUP(3, LPI_NO_SLEW, _, _, _, _),
> > +	LPI_PINGROUP(4, LPI_NO_SLEW, _, _, _, _),
> > +	LPI_PINGROUP(5, LPI_NO_SLEW, _, _, _, _),
> > +	LPI_PINGROUP(6, LPI_NO_SLEW, _, _, _, _),
> > +	LPI_PINGROUP(7, LPI_NO_SLEW, _, _, _, _),
> > +
> > +	LPI_PINGROUP(8, LPI_NO_SLEW, _, _, sec_tdm, _),
> 
> "i2s1_clk"
> 
> > +	LPI_PINGROUP(9, LPI_NO_SLEW, _, _, sec_tdm, _),
> 
> "i2s1_ws"
> 
> > +	LPI_PINGROUP(10, LPI_NO_SLEW, _, _, _, sec_tdm_din),
> 
> "i2s1_data"
> 
> > +	LPI_PINGROUP(11, LPI_NO_SLEW, _, sec_tdm_dout, _, _),
> 
> "i2s1_data"

What are the pinfunc numbers for these? Or are the pinfuncs the same
between I2S and TDM?

> > +
> > +	LPI_PINGROUP(12, LPI_NO_SLEW, _, _, _, _),
> > +	LPI_PINGROUP(13, LPI_NO_SLEW, _, _, _, _),
> > +	LPI_PINGROUP(14, LPI_NO_SLEW, _, _, _, _),
> > +	LPI_PINGROUP(15, LPI_NO_SLEW, _, _, _, _),
> > +	LPI_PINGROUP(16, LPI_NO_SLEW, _, _, _, _),
> > +	LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _),
> > +
> > +	LPI_PINGROUP(18, LPI_NO_SLEW, _, pdm_clk, _, _),
> 
> "slimbus_clk"

Again, what pinfunc? Is PDM, the protocol between analog and digital
codec, using the SLIM clock?

Re: [PATCH 2/3] pinctrl: qcom: add sdm670 lpi tlmm

[Konrad Dybcio]

On 2/11/26 1:35 AM, Richard Acayan wrote:
> On Tue, Feb 10, 2026 at 10:08:19AM +0100, Konrad Dybcio wrote:
>> On 2/10/26 3:11 AM, Richard Acayan wrote:
>>> The Snapdragon 670 has an Low-Power Island (LPI) TLMM for configuring
>>> pins related to audio. Add the driver for this.
>>>
>>> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
>>> ---

[...]

>>> +	LPI_PINGROUP(12, LPI_NO_SLEW, _, _, _, _),
>>> +	LPI_PINGROUP(13, LPI_NO_SLEW, _, _, _, _),
>>> +	LPI_PINGROUP(14, LPI_NO_SLEW, _, _, _, _),
>>> +	LPI_PINGROUP(15, LPI_NO_SLEW, _, _, _, _),
>>> +	LPI_PINGROUP(16, LPI_NO_SLEW, _, _, _, _),
>>> +	LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _),
>>> +
>>> +	LPI_PINGROUP(18, LPI_NO_SLEW, _, pdm_clk, _, _),
>>
>> "slimbus_clk"
> 
> Again, what pinfunc? Is PDM, the protocol between analog and digital
> codec, using the SLIM clock?

Where I suggested other names, they're at the same index as the existing
entries, just that they align better with the documentation I have

Konrad

[PATCH 3/3] arm64: dts: qcom: sdm670: add lpi pinctrl

[Richard Acayan]

The Snapdragon 670 has a separate TLMM for audio pins. Add the device
node for it.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
---
 arch/arm64/boot/dts/qcom/sdm670.dtsi | 74 ++++++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index b8a8dcbdfbe3..0da3e22ce402 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -2273,5 +2273,79 @@ cpufreq_hw: cpufreq@17d43000 {
 
 			#freq-domain-cells = <1>;
 		};
+
+		lpi_tlmm: pinctrl@62b40000 {
+			compatible = "qcom,sdm670-lpass-lpi-pinctrl";
+			reg = <0 0x62b40000 0 0x20000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&lpi_tlmm 0 0 32>;
+			status = "disabled";
+
+			cdc_pdm_default: cdc-pdm-default-state {
+				clk-pins {
+					pins = "gpio18";
+					function = "pdm_clk";
+					drive-strength = <4>;
+					output-low;
+				};
+
+				sync-pins {
+					pins = "gpio19";
+					function = "pdm_sync";
+					drive-strength = <4>;
+					output-low;
+				};
+
+				tx-pins {
+					pins = "gpio20";
+					function = "pdm_tx";
+					drive-strength = <8>;
+				};
+
+				rx-pins {
+					pins = "gpio21", "gpio23", "gpio25";
+					function = "pdm_rx";
+					drive-strength = <4>;
+					output-low;
+				};
+			};
+
+			cdc_comp_default: cdc-comp-default-state {
+				pins = "gpio22", "gpio24";
+				function = "comp_rx";
+				drive-strength = <4>;
+			};
+
+			cdc_dmic_default: cdc-dmic-default-state {
+				clk1-pins {
+					pins = "gpio26";
+					function = "dmic1_clk";
+					drive-strength = <8>;
+					output-high;
+				};
+
+				clk2-pins {
+					pins = "gpio28";
+					function = "dmic2_clk";
+					drive-strength = <8>;
+					output-high;
+				};
+
+				data1-pins {
+					pins = "gpio27";
+					function = "dmic1_data";
+					drive-strength = <8>;
+					input-enable;
+				};
+
+				data2-pins {
+					pins = "gpio29";
+					function = "dmic2_data";
+					drive-strength = <8>;
+					input-enable;
+				};
+			};
+		};
 	};
 };
-- 
2.53.0

Re: [PATCH 3/3] arm64: dts: qcom: sdm670: add lpi pinctrl

[Krzysztof Kozlowski]

On 10/02/2026 03:11, Richard Acayan wrote:
> The Snapdragon 670 has a separate TLMM for audio pins. Add the device
> node for it.
> 
> Signed-off-by: Richard Acayan <mailingradian@gmail.com>
> ---
>  arch/arm64/boot/dts/qcom/sdm670.dtsi | 74 ++++++++++++++++++++++++++++
>  1 file changed, 74 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
> index b8a8dcbdfbe3..0da3e22ce402 100644
> --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
> @@ -2273,5 +2273,79 @@ cpufreq_hw: cpufreq@17d43000 {
>  
>  			#freq-domain-cells = <1>;
>  		};
> +
> +		lpi_tlmm: pinctrl@62b40000 {
> +			compatible = "qcom,sdm670-lpass-lpi-pinctrl";
> +			reg = <0 0x62b40000 0 0x20000>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&lpi_tlmm 0 0 32>;
> +			status = "disabled";

Why is this disabled? We disable blocks needing external resources or
being busses/connectors. This is not the case.

Best regards,
Krzysztof

Re: [PATCH 3/3] arm64: dts: qcom: sdm670: add lpi pinctrl

[Richard Acayan]

On Tue, Feb 10, 2026 at 08:42:59AM +0100, Krzysztof Kozlowski wrote:
> On 10/02/2026 03:11, Richard Acayan wrote:
> > +		lpi_tlmm: pinctrl@62b40000 {
> > +			compatible = "qcom,sdm670-lpass-lpi-pinctrl";
> > +			reg = <0 0x62b40000 0 0x20000>;
> > +			gpio-controller;
> > +			#gpio-cells = <2>;
> > +			gpio-ranges = <&lpi_tlmm 0 0 32>;
> > +			status = "disabled";
> 
> Why is this disabled? We disable blocks needing external resources or
> being busses/connectors. This is not the case.

There are reserved GPIOs on the Pixel 3a. Since commit 4f0d22ec60ce
("pinctrl: lpass-lpi: implement .get_direction() for the GPIO driver"),
this can't be probed when the reserved GPIOs are unspecified.

Re: [PATCH 3/3] arm64: dts: qcom: sdm670: add lpi pinctrl

[Konrad Dybcio]

On 2/11/26 1:23 AM, Richard Acayan wrote:
> On Tue, Feb 10, 2026 at 08:42:59AM +0100, Krzysztof Kozlowski wrote:
>> On 10/02/2026 03:11, Richard Acayan wrote:
>>> +		lpi_tlmm: pinctrl@62b40000 {
>>> +			compatible = "qcom,sdm670-lpass-lpi-pinctrl";
>>> +			reg = <0 0x62b40000 0 0x20000>;
>>> +			gpio-controller;
>>> +			#gpio-cells = <2>;
>>> +			gpio-ranges = <&lpi_tlmm 0 0 32>;
>>> +			status = "disabled";
>>
>> Why is this disabled? We disable blocks needing external resources or
>> being busses/connectors. This is not the case.
> 
> There are reserved GPIOs on the Pixel 3a. Since commit 4f0d22ec60ce
> ("pinctrl: lpass-lpi: implement .get_direction() for the GPIO driver"),
> this can't be probed when the reserved GPIOs are unspecified.

Are all of them reserved?

Does gpio-reserved-ranges help?

Konrad

Re: [PATCH 3/3] arm64: dts: qcom: sdm670: add lpi pinctrl

[Richard Acayan]

On Thu, Feb 12, 2026 at 10:08:39AM +0100, Konrad Dybcio wrote:
> On 2/11/26 1:23 AM, Richard Acayan wrote:
> > On Tue, Feb 10, 2026 at 08:42:59AM +0100, Krzysztof Kozlowski wrote:
> >> On 10/02/2026 03:11, Richard Acayan wrote:
> >>> +		lpi_tlmm: pinctrl@62b40000 {
> >>> +			compatible = "qcom,sdm670-lpass-lpi-pinctrl";
> >>> +			reg = <0 0x62b40000 0 0x20000>;
> >>> +			gpio-controller;
> >>> +			#gpio-cells = <2>;
> >>> +			gpio-ranges = <&lpi_tlmm 0 0 32>;
> >>> +			status = "disabled";
> >>
> >> Why is this disabled? We disable blocks needing external resources or
> >> being busses/connectors. This is not the case.
> > 
> > There are reserved GPIOs on the Pixel 3a. Since commit 4f0d22ec60ce
> > ("pinctrl: lpass-lpi: implement .get_direction() for the GPIO driver"),
> > this can't be probed when the reserved GPIOs are unspecified.
> 
> Are all of them reserved?
> 
> Does gpio-reserved-ranges help?

Yes. It would need changes in dt-bindings and in sdm670-google-common.dtsi
(introducing a dependency on Pixel 3a XL support).

Re: [PATCH 0/3] SDM670 LPASS LPI pin controller support

[Linus Walleij]

On Tue, Feb 10, 2026 at 3:10 AM Richard Acayan <mailingradian@gmail.com> wrote:

> This adds support for the LPASS LPI pin controller on SDM670, which
> controls some audio pins (e.g. TDM or PDM busses). The ADSP patches are
> not sent yet.
>
> Richard Acayan (3):
>   dt-bindings: pinctrl: qcom: Add SDM670 LPI pinctrl
>   pinctrl: qcom: add sdm670 lpi tlmm
>   arm64: dts: qcom: sdm670: add lpi pinctrl

The way I read it there are some review comments on 2/3, so resend this
as soon as you manage to revise it.

Yours,
Linus Walleij