From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F28C01FDA61; Thu, 12 Mar 2026 10:41:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773312101; cv=none; b=g+yLaY2gKiXC/MBydUmK9tV/znm0H1B333J1RwgWUbnVXRpaq0ssrs8OWezD2Dzu3/IdKAkAO/Wehy+E/BBmro64ntcJGznJVA67PbsZepvcNtgX8IH07GN08btsjNJjbw4sOFLTjRm+hNXgIa1FYtjheXo7RKS/Tm2z1JHVqTg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773312101; c=relaxed/simple; bh=q2lTzhr65RcW7dhfxWFZWxgUukU/MnITP1xNzzmxAQk=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=j6RFdEleKk9yXA6nT62/htQQ2uoACVjOl9AiV4rjbhgIOPpy6KhB5An0JYSAXoFDotybGVXODi2WDrYOmCGg0/3OYarlNnC6jcj0/efOkPHqx5ntz90qKFb92aQCbXaOJDtG6+l1OKjsTpgvZQ0w2nVN36HC46wSHjkU1VZpmbo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GFI2XYKu; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GFI2XYKu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773312098; x=1804848098; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=q2lTzhr65RcW7dhfxWFZWxgUukU/MnITP1xNzzmxAQk=; b=GFI2XYKuOjGnoDd9a0+m6ZbrU1KGBfUEPoeYSEjOXYDcIwbqM+eMCLfB oRt5MFs/TiEfyWSvaq1g9VhZnRiimuWJdrhbenoFm14qXM7sFq0q70NMo fdeebM/ehp8BHyKf0sh4xOUzEgXPIMswxDL/yCmNlJfsCGpz8zovRKa4z w1QfK4W1UfXH94P4bIvhRXxNkoZx7S+T7SZB6wOfGT2gMoY9+OiQbo44n 2ksFPcGh/2IsQg6syxoEyoyV4FPvEamLAXTFbi/iZjI7hV2wPTHPZq7zw tPG0FICE+MMjFFsu8O1VVBLEZRERYGa3GiiQIHMou63g1ePlw/OZCp1EZ Q==; X-CSE-ConnectionGUID: 2Yd7BMXcRTWbbVAl252M9Q== X-CSE-MsgGUID: dkUQGSSRRtCg/c4igd0Jog== X-IronPort-AV: E=McAfee;i="6800,10657,11726"; a="85485480" X-IronPort-AV: E=Sophos;i="6.23,116,1770624000"; d="scan'208";a="85485480" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2026 03:41:37 -0700 X-CSE-ConnectionGUID: rK+Vt53VTVilt6f+idwrdw== X-CSE-MsgGUID: i8lqrHI4RNKxO8ai5lxSGA== X-ExtLoop1: 1 Received: from pgcooper-mobl3.ger.corp.intel.com (HELO localhost) ([10.245.245.112]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Mar 2026 03:41:35 -0700 Date: Thu, 12 Mar 2026 12:41:32 +0200 From: Andy Shevchenko To: Linus Walleij Cc: Dan Carpenter , AKASHI Takahiro , Bartosz Golaszewski , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Bartosz Golaszewski , arm-scmi@vger.kernel.org Subject: Re: [PATCH v3 7/7] gpio: add pinctrl based generic gpio driver Message-ID: References: <93920f541564bc4e6aaf0f2b6df2f5aca721d452.1773150895.git.dan.carpenter@linaro.org> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Wed, Mar 11, 2026 at 11:00:02PM +0100, Linus Walleij wrote: > On Wed, Mar 11, 2026 at 9:34 PM Andy Shevchenko > wrote: > > On Wed, Mar 11, 2026 at 10:39:24PM +0300, Dan Carpenter wrote: > > > > > The ARM SCMI pinctrl protocol allows GPIO access. Instead of creating > > > a new SCMI gpio driver, this driver is a generic GPIO driver that uses > > > standard pinctrl interfaces. > > > > Similar wondering here... Can't this code be integrated with one of > > the existing generic things, like gpio-aggregator? > > The aggregator is very different, it takes existing GPIOs and > creates a new GPIOchip from them. > > What this does is essentially take the gpio-ranges, find the > backing pins on the pin controller, and creates a GPIOchip > from them. Thanks for elaboration! But why is it done this way? It doesn't sound like a usual (generic) problem to solve. > I don't see anything that can be shared by the other generic > business sadly, but I think maybe another back-end using just > pin control can re-use this. In this case it is SCMI but any other > firmware API just exposing pin control and no explicit GPIO > could use this. (Not that I can think of any.) -- With Best Regards, Andy Shevchenko