From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B99B332610; Mon, 16 Mar 2026 16:14:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773677647; cv=none; b=ej2cMRBrHMfz79wGjPDweZK/XRZxkIw2ZZNHm3gQUuUR7H4E71RwzDD7nx+x+oh9NH724ajG/Ng1k/oJUYneYtx9wfOYyaiMmwSbLbwrYoy6a2AQrnCVqsoNlZp6iXe0Tb7iAF9W2XR+kp1P7iMhTSrxL1YYGouaR9m7Ww3q2Bc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773677647; c=relaxed/simple; bh=L2hOlbVbeBnX2zvVvlt7wm3QiGVXO5V89NnZSJckvUU=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=AfL8LVZ+0zaRHRj475s+zgxeL4xyLVxUeyZfDHgDrCM64FekV/cLxaFu66ykVkLb6JzjTDZuiceNRqTLmeMU+q94AXbb+Pj/3Coh/SY3C8BnAGtyOPBhI8kBHNtqBJgprxxWEMEkapbY3m1qyNlhq8XNE0aTy0rVxUi7SY1OSPk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YXBToig9; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YXBToig9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773677645; x=1805213645; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=L2hOlbVbeBnX2zvVvlt7wm3QiGVXO5V89NnZSJckvUU=; b=YXBToig9MIoe8vQ6gzxQ9SV0KDg6jIXfnHtT3NcbqbINKeVe/0rirzmn hkeQ85G/IHYbfeA4zE+sjzTlQmEFoSnIljex4H91i/LO1hrnV6/IfSO6V o/m2L/TMPDsAs6TnjXUc7lhh62kr4s7uYck1kLo0hslj6Fj2oGsAgKr7n mFTAoLzH1cQZwDJ/iWghH2gGjE5gDq3c5Tlx00GIf03Znc+70t5ToSkgn 5VnBozFe/vauBxLHv6xS0qqJPToGl1hDz1eIWgb7la0XLehCu91EZQnry L152J77M/1xGoYJqZnDRoyLzlyhOCfLQ2UhizgyG4yMjgzhFhNiMCCyjC g==; X-CSE-ConnectionGUID: aF4DRiS0S8yxvO+Ilwlh4w== X-CSE-MsgGUID: xEI9vGG0TRemxVf1hJtRiQ== X-IronPort-AV: E=McAfee;i="6800,10657,11731"; a="73718889" X-IronPort-AV: E=Sophos;i="6.23,124,1770624000"; d="scan'208";a="73718889" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2026 09:14:04 -0700 X-CSE-ConnectionGUID: hAHqELnXQxS2nIftdBLOYg== X-CSE-MsgGUID: iD1kbxRDTIqwbgm4gzrFNQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,124,1770624000"; d="scan'208";a="216462797" Received: from vpanait-mobl.ger.corp.intel.com (HELO localhost) ([10.245.244.237]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2026 09:13:59 -0700 Date: Mon, 16 Mar 2026 18:13:57 +0200 From: Andy Shevchenko To: "Sabau, Radu bogdan" Cc: David Lechner , Lars-Peter Clausen , "Hennerich, Michael" , Jonathan Cameron , "Sa, Nuno" , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski , Philipp Zabel , "linux-iio@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pwm@vger.kernel.org" , "linux-gpio@vger.kernel.org" Subject: Re: [PATCH v3 2/4] iio: adc: ad4691: add initial driver for AD4691 family Message-ID: References: <20260313-ad4692-multichannel-sar-adc-driver-v3-0-b4d14d81a181@analog.com> <20260313-ad4692-multichannel-sar-adc-driver-v3-2-b4d14d81a181@analog.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Mon, Mar 16, 2026 at 03:57:53PM +0000, Sabau, Radu bogdan wrote: > > From: David Lechner > > Sent: Monday, March 16, 2026 5:51 PM > > On 3/16/26 10:29 AM, Sabau, Radu bogdan wrote: > > >> From: Andy Shevchenko > > >> Sent: Friday, March 13, 2026 12:58 PM > > >> To: Sabau, Radu bogdan ... > > >>> + u32 acc_mask[2] = { mask & 0xFF, mask >> 8 }; > > >> > > >> This looks quite wrong. Is it for sure like two 32-bit stances per each mask > > >> byte? If not, this should be __le16 acc_mask = cpu_to_le16(~BIT(...)); > > >> > > > > > > Hi Andy, > > > > > > Each acc_mask has its own register, therefore the u32 acc_mask[2] is > > > intentional - since the regmap is configured with val_bits=32 - the 4-byte > > > stride matches what regmap reads. However, I understand how this > > > can be confusing for anyone reading the code, therefore I propose > > > two ways for this : > > > > > > 1. Keep regmap_bulk_write and add a comment above acc_mask explaining > > > why u32 is used, although these register values are 8 bits. > > > 2. Switch to regmap_multi_reg_write, which takes explicit (reg, value) pairs > > > and sidesteps the ambiguity entirely. > > > > > > Do you have a preference? > > > > Since we already have a custom read/write functions to handle different > > register sizes and the chip can read more than one consecutive register > > at once, can we just call this a single register and add a special case > > to ad4691_reg_read/write() to handle it? Then we can just do a regular > > regmap_read/write() functions to access it as a single 16-bit value. > > This sounds even better! I will have this in the next version! I also second David's suggestion, please go for it. -- With Best Regards, Andy Shevchenko