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Fri, 03 Jul 2026 01:46:49 -0700 (PDT) X-Received: by 2002:a17:902:c40d:b0:2c0:d94f:50c7 with SMTP id d9443c01a7336-2cacabc2ae9mr36764955ad.7.1783068409489; Fri, 03 Jul 2026 01:46:49 -0700 (PDT) Received: from [10.217.198.242] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13b3c870effsm21512940c88.12.2026.07.03.01.46.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 03 Jul 2026 01:46:49 -0700 (PDT) Message-ID: Date: Fri, 3 Jul 2026 14:16:43 +0530 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/8] irqchip/qcom-pdc: Move all statics to struct pdc_desc To: Thomas Gleixner , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, Sneh Mankad References: <20260616-hamoa_pdc_v3-v3-0-4d8e1504ea75@oss.qualcomm.com> <20260616-hamoa_pdc_v3-v3-2-4d8e1504ea75@oss.qualcomm.com> <87jyrgqe5m.ffs@fw13> Content-Language: en-US From: "Maulik Shah (mkshah)" In-Reply-To: <87jyrgqe5m.ffs@fw13> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: Sh8CaqpC87G3bZ3GGuaUBosHOEjT46CP X-Proofpoint-ORIG-GUID: Sh8CaqpC87G3bZ3GGuaUBosHOEjT46CP X-Proofpoint-Spam-Info: AW1haW4tMjYwNzAzMDA4MiBTYWx0ZWRfX/undHlPi3HmL e0VIteyYGnbi9QcyPaq8ePJ4k9nNLdLrlNSQ33r9YwTQkA3BipT3PYDK6Nuhm1MZCcogGdJF4Z2 nbYcjK1BmCF1fQRWkmUB9Y1RvSlZEHY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzAzMDA4MiBTYWx0ZWRfX+t+tsH2FIxyM yrhl1hdo5ja7J1YgBp23o4BPqU3f8ZqiZKy99Z7DEljoymZk1/3AKEVZwviZ2yvDux90/P2R+XN eBcrtk5mdh4lkvnfo4AC3X+8CjSF6khQzcKJ7qe88qjCZK4nERy+sw6Ayhx10usdz89thaELjPq 1CDzpYTYvhsaLbbOB+JP5bfFEU2vPIco0ARretBjYmoexwdIDp4kGDlbsOZwYTlM/YDNL/sZTYC ndqx+fQfOydn9r1cjlrAJS+/MagnQ5y2pcx/NqUxyGARi+vAoNUGXM6RyJMXRh/7pm2/ZHvOr7U Mi+0hku1rjcS64IM1b5fiXQkFgoeoHsnbiR3gyJwu37sDkDfOTovQWYo7Ith0fIG3N3I3gB+TNT AJ+flnK/FZ1Wflc/lmkxrSVJvF8jgPSm9MVQc8t1FpnuQ8r5KOsc6tQbR7kynOp2DQFLqyPVGNm LQn8Ov4UJUE5kLStlEA== X-Authority-Analysis: v=2.4 cv=OaKoyBTY c=1 sm=1 tr=0 ts=6a4776fa cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=xKoXzObbE768e6KogzsA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-07-03_02,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 spamscore=0 phishscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607030082 On 6/30/2026 8:16 PM, Thomas Gleixner wrote: > On Tue, Jun 16 2026 at 14:55, Maulik Shah wrote: >> - for (i = 0; i < pdc_region[n].cnt; i++) >> - __pdc_enable_intr(i + pdc_region[n].pin_base, 0); >> + for (int i = 0; i < pdc->region[n].cnt; i++) >> + pdc->enable_intr(i + pdc->region[n].pin_base, 0); > > This needs a guard(raw_spinlock_irqsave)() when invoking > pdc->enable_intr(). The probe function is only invoked > with interrupts disabled during early boot. If it's called later, then > this still works, but lockdep will be rightfully upset. > Patch 3 of the series moved guard(raw_spinlock)() within the pdc->enable_intr(). I will merge patch 2 and patch 3 in v4 series so that lock movement and newly adding it at probe time is captured in single change. Lock is required only for old PDC HW versions (v2.7 and v3.0) where enable bank is used instead of separate enable register for each IRQ. Adding lock like below will apply the lock unnecessary on HW v3.2 specific pdc->enable_intr() as well which is initialized to pdc_enable_intr_cfg(). guard(raw_spinlock_irqsave)(&pdc->lock); pdc->enable_intr(i + pdc->region[n].pin_base, false); To address this, lock is still kept within pdc->enable_intr() which is pointing to pdc_enable_intr_bank() for PDC HW v2.7 and v3.0. Since probe gets invoked later during probe, i will keep guard(raw_spinlock_irqsave)() within pdc->enable_intr(), even if chip callbacks like .irq_enable invoking pdc->enable_intr() may not need _irqsave() variant as it seems no better way as keeping lock before calling pdc->enable_intr() will apply for PDC HW v3.2 as well. Thanks, Maulik