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[82.37.195.13]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48fc8cd49fesm78578015e9.0.2026.05.13.05.49.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 May 2026 05:49:49 -0700 (PDT) Date: Wed, 13 May 2026 13:49:46 +0100 From: Daniel Thompson To: Konrad Dybcio Cc: Alex Elder , andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, maxime.chevallier@bootlin.com, rmk+kernel@armlinux.org.uk, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linusw@kernel.org, brgl@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, mohd.anwar@oss.qualcomm.com, a0987203069@gmail.com, alexandre.torgue@foss.st.com, ast@kernel.org, boon.khai.ng@altera.com, chenchuangyu@xiaomi.com, chenhuacai@kernel.org, daniel@iogearbox.net, hawk@kernel.org, hkallweit1@gmail.com, inochiama@gmail.com, john.fastabend@gmail.com, julianbraha@gmail.com, livelycarpet87@gmail.com, matthew.gerlach@altera.com, mcoquelin.stm32@gmail.com, me@ziyao.cc, prabhakar.mahadev-lad.rj@bp.renesas.com, richardcochran@gmail.com, rohan.g.thomas@altera.com, sdf@fomichev.me, siyanteng@cqsoftware.com.cn, weishangjuan@eswincomputing.com, wens@kernel.org, netdev@vger.kernel.org, bpf@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next 12/12] arm64: dts: qcom: qcs6490-rb3gen2: enable TC9564 with a single QCS8081 phy Message-ID: References: <20260501155421.3329862-1-elder@riscstar.com> <20260501155421.3329862-13-elder@riscstar.com> <01d6ea18-e022-41c7-a642-ac0321957923@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <01d6ea18-e022-41c7-a642-ac0321957923@oss.qualcomm.com> On Fri, May 08, 2026 at 04:03:36PM +0200, Konrad Dybcio wrote: > On 5/1/26 5:54 PM, Alex Elder wrote: > > From: Daniel Thompson > > > > The QCS6490 RB3Gen2 includes a Toshiba TC9564 (a.k.a. Qualcomm QPS615). > > TC9564 is an twin Ethernet-AVB/TSN bridge with an integrated PCIe switch. > > > > There are multiple builds of RB3Gen2 with components included/excluded. > > That means whether or not there is a phy attached to eMAC0 depends on > > the exact board. However all versions include a TC9564 combined with a > > single QCS8081 attached to eMAC1. > > > > Add properties to the existing PCI nodes to describe how the TC9564 and > > QCS8081 are connected to each other (and to the host SoC). > > > > (Note: "pci1179,0220" is documented in the "net/toshiba,tc956x-dwmac.yaml" > > binding, but checkpatch.pl doesn't recognize that.) > > This should probably go under the --- line I'll leave that with Alex... > > + qep_1p8: regulator-qep-1p8 { > > + compatible = "regulator-fixed"; > > + regulator-name = "qep_1p8"; > > + gpio = <&pm7325_gpios 8 GPIO_ACTIVE_HIGH>; > > + regulator-min-microvolt = <1800000>; > > + regulator-max-microvolt = <1800000>; > > + enable-active-high; > > + regulator-always-on; > > + }; > > If I'm reading the schematics right, this is only required for the PHY > - is it collapsible, or does it really need to be a-on? It could be turned off if the socket isn't in use but it would prevent hotplug detection from working. In practice that means it can only collapse during suspend/resume. However the real reason we jammed this on is because I couldn't find a way to get the phy/mdio code to turn one on. However it is possible to add regulator support to MDIO devices by extending their existing logic to manage resets so it can also manage a regulator. It comes out fairly clean so we can add that to the patch set and remove the regulator-always-on. > > + qep_irq_pin: qep-irq-state { > > + pins = "gpio101"; > > + function = "gpio"; > > + drive-strength = <2>; > > + bias-disable; > > There's no pull-up onboard, should we use the on-chip one? It is configured the same as lt9611_irq_pin (which I couldn't see a pull-up for). I switched the interrupt trigger to active-low based on other feedback on the patchset and the counts in /proc/interrupts remain unchanged (with a single figure value). It certainly doesn't look like the irq line floats when the PHY interrupt is deasserted. Daniel.