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Thu, 22 Oct 2026 10:25:39 -0700 (PDT) Date: Thu, 22 Oct 2026 19:25:38 +0200 From: Lorenzo Bianconi To: Bjorn Helgaas Cc: Bjorn Andersson , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chaitanya Chundru , Linus Walleij , Bartosz Golaszewski , Konrad Dybcio , Michael Walle , Alex Elder , Daniel Thompson , Sushrut Shree Trivedi , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio , Bartosz Golaszewski , Abel Vesa Subject: Re: [PATCH v5 5/5] arm64: dts: qcom: qcs6490-rb3gen2: Enable TC9563 embedded GPIO controller Message-ID: References: <20261015172620.GA1780580@bhelgaas> <20261019220111.GA2271378@bhelgaas> X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; 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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable > On Thu, Oct 15, 2026 at 12:26:21PM -0500, Bjorn Helgaas wrote: > > On Wed, Sep 09, 2026 at 04:55:57PM +0200, Lorenzo Bianconi wrote: > > > The Toshiba TC9563 PCIe switch embeds a GPIO controller providing 37 = GPIO > > > lines. The controller is registered as an auxiliary device by the TC9= 563 > > > power controller driver and accessed through the same i2c device. > > >=20 > > > Describe the switch node itself as the embedded GPIO controller and us > > > it to drive the PERST# reset lines of the two external downstream port > > > (pcie@1,0 and pcie@2,0), as expected by the TC9563 power controller a= fter > > > switching to the GPIO descriptor API for per-port resets. > > >=20 > > > Reviewed-by: Konrad Dybcio > > > Reviewed-by: Bartosz Golaszewski > > > Reviewed-by: Abel Vesa > > > Reviewed-by: Alex Elder > > > Signed-off-by: Lorenzo Bianconi > >=20 > > Bjorn A, I first applied this arch/arm64 DTS patch to the PCI tree > > along with the rest of this series, but that was a mistake because=20 > > those changes should go through your tree instead. > >=20 > > I dropped it from pci/pwrctrl. Do you want to pick it up? >=20 > Just following up to make sure this DTS patch gets merged somewhere... Hi Bjorn A, is this patch supposed to be applied to your tree? Regards, Lorenzo >=20 > > > --- > > > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 7 ++++++- > > > 1 file changed, 6 insertions(+), 1 deletion(-) > > >=20 > > > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm6= 4/boot/dts/qcom/qcs6490-rb3gen2.dts > > > index a13315bf0fb0..4da7342ca90d 100644 > > > --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > > > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts > > > @@ -867,7 +867,7 @@ &pcie1_phy { > > > &pcie1_port0 { > > > reset-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; > > > =20 > > > - pcie@0,0 { > > > + tc9563: pcie@0,0 { > > > compatible =3D "pci1179,0623"; > > > reg =3D <0x10000 0x0 0x0 0x0 0x0>; > > > #address-cells =3D <3>; > > > @@ -891,6 +891,9 @@ pcie@0,0 { > > > pinctrl-0 =3D <&tc9563_resx_n>; > > > pinctrl-names =3D "default"; > > > =20 > > > + gpio-controller; > > > + #gpio-cells =3D <2>; > > > + > > > pcie1_switch0_dsp1: pcie@1,0 { > > > reg =3D <0x20800 0x0 0x0 0x0 0x0>; > > > #address-cells =3D <3>; > > > @@ -899,6 +902,7 @@ pcie1_switch0_dsp1: pcie@1,0 { > > > device_type =3D "pci"; > > > ranges; > > > bus-range =3D <0x3 0xff>; > > > + reset-gpios =3D <&tc9563 2 GPIO_ACTIVE_LOW>; > > > }; > > > =20 > > > pcie@2,0 { > > > @@ -909,6 +913,7 @@ pcie@2,0 { > > > device_type =3D "pci"; > > > ranges; > > > bus-range =3D <0x4 0xff>; > > > + reset-gpios =3D <&tc9563 3 GPIO_ACTIVE_LOW>; > > > =20 > > > /* Renesas =CE=BCPD720201 PCIe USB3.0 Host Controller */ > > > usb-controller@0,0 { > > >=20 > > > --=20 > > > 2.55.0 > > >=20 --THddspKwcrT7mb3a Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTquNwa3Txd3rGGn7Y6cBh0uS2trAUCatpHEgAKCRA6cBh0uS2t rIAcAQD9XMFk9P0Wcr2AnQ1Vo7zfOmzMMBX19nW9jYUu4UxD3wD/b0ihb2VzRcme Iwdwa1q9ZZQu+2CgZgGygpLAkLGRqQc= =CJkx -----END PGP SIGNATURE----- --THddspKwcrT7mb3a--