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a=rsa-sha256; c=relaxed/relaxed; d= sang-engineering.com; h=date:from:to:cc:subject:message-id :references:mime-version:content-type:in-reply-to; s=k1; bh=WEci nyzXvpzdrQbdmzGRVBkMmzuM3NlP9qlzk0r7u+M=; b=BtuJ+9TGthEvfHggV1K7 8HCM7lmDmDVKnstgAkSutQeepbxM9f+LBjaFk5F7H0FOumehplkJKLqoJ4+ceSBh YK2ss/QChr71ijKyvjcVkjJLIy4l+mwVhX+S0+XWv8HGGxsgbS3TL9RxhUbSVG/E axv8+Pk12kFE5H2dIY84wmQcx62TwwtQW8iTi8kMfH2anW9M1GuJzYn0um/iNzoS MqQKrx44llXCiyQQ7aiR0H9+sB8qB7UaGm2wtCRRck41rxjhBhdU4H/PyL28+gfh 1iQa6igkkswZenPR28OwGiM6B5IRigeuzt7kfw2me4EMvNskJM0zliJLQI9IogCF wA== Received: (qmail 853660 invoked from network); 1 Nov 2026 21:34:07 +0100 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 1 Nov 2026 21:34:07 +0100 X-UD-Smtp-Session: l3s3148p1@YnRo8zxfVKTB0HFD Date: Sun, 1 Nov 2026 22:34:06 +0200 From: Wolfram Sang To: Diogo Ivo Cc: Tommaso Merciai , Alexandre Belloni , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Stephen Boyd , Brian Masney , Jerome Brunet , Linus Walleij , linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org Subject: Re: [PATCH v2 7/7] arm64: dts: renesas: r9a08g046: Add I3C support Message-ID: References: <20261026-divo-ssgrlpcsrc-2966-i3c-v2-0-2e76b87209bb@renesas.com> <20261026-divo-ssgrlpcsrc-2966-i3c-v2-7-2e76b87209bb@renesas.com> X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261026-divo-ssgrlpcsrc-2966-i3c-v2-7-2e76b87209bb@renesas.com> On Mon, Oct 26, 2026 at 11:35:50AM +0000, Diogo Ivo wrote: > Add the I3C Bus Interface node to the RZ/G3L (R9A08G046) SoC DTSI and > enable it on the RZ/G3L SMARC EVK, together with the required pin > control. > > The driver only consumes resources that are common to the RZ/G3L and > the RZ/G3S (R9A08G045), so the node uses the SoC-specific > renesas,r9a08g046-i3c compatible with a fallback to the > renesas,r9a08g045-i3c compatible of the RZ/G3S, following the bindings. > > The I3C pins are shared with RIIC3, so the controller is only enabled > when the SW_I3C_EN switch is on. > > The I3C I/O voltage can be set to 1.2V or 1.8V on the board through > the SYS.3 (I3C_IOVS) switch, so configure the pin controller for the > selected voltage through the power-source property. > > Signed-off-by: Diogo Ivo Didn't double check the pinmux values, but rest looks good to me: Reviewed-by: Wolfram Sang