[PATCH 1/5] pinctrl: sunxi: refactor pinctrl choice selecting for ARM64

[PATCH 1/5] pinctrl: sunxi: refactor pinctrl choice selecting for ARM64

[Icenowy Zheng]

ARM64 Allwinner SoCs used to have every pinctrl driver selected in
ARCH_SUNXI. Change this to make their default value to (ARM64 &&
ARCH_SUNXI).

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
 drivers/pinctrl/sunxi/Kconfig | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 816015cf7053..92325736d953 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -48,8 +48,9 @@ config PINCTRL_SUN8I_H3
 	select PINCTRL_SUNXI
 
 config PINCTRL_SUN8I_H3_R
-	def_bool MACH_SUN8I
-	select PINCTRL_SUNXI_COMMON
+	def_bool MACH_SUN8I || (ARM64 && ARCH_SUNXI)
+	depends on RESET_CONTROLLER
+	select PINCTRL_SUNXI
 
 config PINCTRL_SUN8I_V3S
 	def_bool MACH_SUN8I
@@ -65,11 +66,11 @@ config PINCTRL_SUN9I_A80_R
 	select PINCTRL_SUNXI
 
 config PINCTRL_SUN50I_A64
-	bool
+	def_bool ARM64 && ARCH_SUNXI
 	select PINCTRL_SUNXI
 
 config PINCTRL_SUN50I_H5
-	bool
+	def_bool ARM64 && ARCH_SUNXI
 	select PINCTRL_SUNXI
 
 endif
-- 
2.11.1

[PATCH 2/5] arm64: only select PINCTRL_SUNXI for Allwinner platforms

[Icenowy Zheng]

As the pinctrl driver selecting is refactored in Kconfig file of
pinctrl-sunxi, now we can select only PINCTRL_SUNXI for Allwinner
platform, and the default value of several pinctrl drivers useful on
ARM64 Allwinner SoCs will become Y.

Drop the select of per-SoC pinctrl choices, but select PINCTRL_SUNXI.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
 arch/arm64/Kconfig.platforms | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 129cc5ae4091..f6db2a938b1e 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -4,7 +4,7 @@ config ARCH_SUNXI
 	bool "Allwinner sunxi 64-bit SoC Family"
 	select GENERIC_IRQ_CHIP
 	select PINCTRL
-	select PINCTRL_SUN50I_A64
+	select PINCTRL_SUNXI
 	help
 	  This enables support for Allwinner sunxi based SoCs like the A64.
 
-- 
2.11.1

Re: [PATCH 2/5] arm64: only select PINCTRL_SUNXI for Allwinner platforms

[Andre Przywara]

Hi,

On 28/02/17 17:24, Icenowy Zheng wrote:
> As the pinctrl driver selecting is refactored in Kconfig file of
> pinctrl-sunxi, now we can select only PINCTRL_SUNXI for Allwinner
> platform, and the default value of several pinctrl drivers useful on
> ARM64 Allwinner SoCs will become Y.
> 
> Drop the select of per-SoC pinctrl choices, but select PINCTRL_SUNXI.
> 
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> ---
>  arch/arm64/Kconfig.platforms | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 129cc5ae4091..f6db2a938b1e 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -4,7 +4,7 @@ config ARCH_SUNXI
>  	bool "Allwinner sunxi 64-bit SoC Family"
>  	select GENERIC_IRQ_CHIP
>  	select PINCTRL
> -	select PINCTRL_SUN50I_A64
> +	select PINCTRL_SUNXI

Why do we need to add this generic PINCTRL_SUNXI here? This is selected
already by the SoC specific PINCTRL symbols (see your previous patch).

Cheers,
Andre.

>  	help
>  	  This enables support for Allwinner sunxi based SoCs like the A64.
>  
> 

Re: [PATCH 2/5] arm64: only select PINCTRL_SUNXI for Allwinner platforms

[Icenowy Zheng]

01.03.2017, 02:17, "Andre Przywara" <andre.przywara-5wv7dgnIgG8@public.gmane.org>:
> Hi,
>
> On 28/02/17 17:24, Icenowy Zheng wrote:
>>  As the pinctrl driver selecting is refactored in Kconfig file of
>>  pinctrl-sunxi, now we can select only PINCTRL_SUNXI for Allwinner
>>  platform, and the default value of several pinctrl drivers useful on
>>  ARM64 Allwinner SoCs will become Y.
>>
>>  Drop the select of per-SoC pinctrl choices, but select PINCTRL_SUNXI.
>>
>>  Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
>>  ---
>>   arch/arm64/Kconfig.platforms | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>>  diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>>  index 129cc5ae4091..f6db2a938b1e 100644
>>  --- a/arch/arm64/Kconfig.platforms
>>  +++ b/arch/arm64/Kconfig.platforms
>>  @@ -4,7 +4,7 @@ config ARCH_SUNXI
>>           bool "Allwinner sunxi 64-bit SoC Family"
>>           select GENERIC_IRQ_CHIP
>>           select PINCTRL
>>  - select PINCTRL_SUN50I_A64
>>  + select PINCTRL_SUNXI
>
> Why do we need to add this generic PINCTRL_SUNXI here? This is selected
> already by the SoC specific PINCTRL symbols (see your previous patch).
>
> Cheers,
> Andre.

Oh yes... You're right...

>
>>           help
>>             This enables support for Allwinner sunxi based SoCs like the A64.

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[PATCH 3/5] dt-bindings: fix for Allwinner H5 pinctrl's compatible

[Icenowy Zheng]

The compatible for Allwinner H5 pin controller is wrong written as
allwinner,sun50i-h5-r-pinctrl, however, it's really a generic pinctrl
rather than a "r" one.

Fix this compatible string.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
 Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 2fd688c8dbdb..8177bb4d5f53 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -23,7 +23,7 @@ Required properties:
   "allwinner,sun8i-h3-pinctrl"
   "allwinner,sun8i-h3-r-pinctrl"
   "allwinner,sun50i-a64-pinctrl"
-  "allwinner,sun50i-h5-r-pinctrl"
+  "allwinner,sun50i-h5-pinctrl"
   "nextthing,gr8-pinctrl"
 
 - reg: Should contain the register physical address and length for the
-- 
2.11.1

[PATCH 4/5] dt: bindings: add binding for Allwinner A64 R_PIO pinctrl

[Icenowy Zheng]

Allwinner A64 SoC has also a dedicated pin controller for Port L GPIOs,
which is called "Port Controller (CPUs-PORT)" in SoC User Manual.

Add a binding for this pin controller, like the ones in A23/33 and H3.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
 Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 8177bb4d5f53..b53224473672 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -23,6 +23,7 @@ Required properties:
   "allwinner,sun8i-h3-pinctrl"
   "allwinner,sun8i-h3-r-pinctrl"
   "allwinner,sun50i-a64-pinctrl"
+  "allwinner,sun50i-a64-r-pinctrl"
   "allwinner,sun50i-h5-pinctrl"
   "nextthing,gr8-pinctrl"
 
-- 
2.11.1

[PATCH 5/5] pinctrl: sunxi: Add A64 R_PIO controller support

[Icenowy Zheng]

The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
Add support for the pins controlled by the R_PIO controller.

Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
 drivers/pinctrl/sunxi/Kconfig                |   5 +
 drivers/pinctrl/sunxi/Makefile               |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 143 +++++++++++++++++++++++++++
 3 files changed, 149 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 92325736d953..0738b0df5a0b 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -69,6 +69,11 @@ config PINCTRL_SUN50I_A64
 	def_bool ARM64 && ARCH_SUNXI
 	select PINCTRL_SUNXI
 
+config PINCTRL_SUN50I_A64_R
+	def_bool ARM64 && ARCH_SUNXI
+	depends on RESET_CONTROLLER
+	select PINCTRL_SUNXI
+
 config PINCTRL_SUN50I_H5
 	def_bool ARM64 && ARCH_SUNXI
 	select PINCTRL_SUNXI
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 04ccb88ebd5f..df4ccd6cd44c 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)		+= pinctrl-sun8i-a23.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23_R)	+= pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)		+= pinctrl-sun8i-a33.o
 obj-$(CONFIG_PINCTRL_SUN50I_A64)	+= pinctrl-sun50i-a64.o
+obj-$(CONFIG_PINCTRL_SUN50I_A64_R)	+= pinctrl-sun50i-a64-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A83T)	+= pinctrl-sun8i-a83t.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3)		+= pinctrl-sun8i-h3.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3_R)	+= pinctrl-sun8i-h3-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
new file mode 100644
index 000000000000..90996a63689b
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
@@ -0,0 +1,143 @@
+/*
+ * Allwinner A64 SoCs special pins pinctrl driver.
+ *
+ * Based on pinctrl-sun8i-a23-r.c
+ *
+ * Copyright (C) 2016 Icenowy Zheng
+ * Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
+ *
+ * Copyright (C) 2014 Chen-Yu Tsai
+ * Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
+ *
+ * Copyright (C) 2014 Boris Brezillon
+ * Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * Copyright (C) 2014 Maxime Ripard
+ * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun50i_a64_r_pins[] = {
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_rsb"),		/* SCK */
+		  SUNXI_FUNCTION(0x3, "s_i2c"),		/* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),	/* PL_EINT0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_rsb"),		/* SDA */
+		  SUNXI_FUNCTION(0x3, "s_i2c"),		/* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),	/* PL_EINT1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_uart"),	/* TX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),	/* PL_EINT2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_uart"),	/* RX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),	/* PL_EINT3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* MS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),	/* PL_EINT4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* CK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),	/* PL_EINT5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* DO */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),	/* PL_EINT6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* DI */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),	/* PL_EINT7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_i2c"),		/* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),	/* PL_EINT8 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_i2c"),		/* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),	/* PL_EINT9 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_pwm"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),	/* PL_EINT10 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_cir_rx"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),	/* PL_EINT11 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),	/* PL_EINT12 */
+};
+
+static const struct sunxi_pinctrl_desc sun50i_a64_r_pinctrl_data = {
+	.pins = sun50i_a64_r_pins,
+	.npins = ARRAY_SIZE(sun50i_a64_r_pins),
+	.pin_base = PL_BASE,
+	.irq_banks = 1,
+};
+
+static int sun50i_a64_r_pinctrl_probe(struct platform_device *pdev)
+{
+	struct reset_control *rstc;
+	int ret;
+
+	rstc = devm_reset_control_get(&pdev->dev, NULL);
+	if (IS_ERR(rstc)) {
+		dev_err(&pdev->dev, "Reset controller missing\n");
+		return PTR_ERR(rstc);
+	}
+
+	ret = reset_control_deassert(rstc);
+	if (ret)
+		return ret;
+
+	ret = sunxi_pinctrl_init(pdev,
+				 &sun50i_a64_r_pinctrl_data);
+
+	if (ret)
+		reset_control_assert(rstc);
+
+	return ret;
+}
+
+static const struct of_device_id sun50i_a64_r_pinctrl_match[] = {
+	{ .compatible = "allwinner,sun50i-a64-r-pinctrl", },
+	{}
+};
+
+static struct platform_driver sun50i_a64_r_pinctrl_driver = {
+	.probe	= sun50i_a64_r_pinctrl_probe,
+	.driver	= {
+		.name		= "sun50i-a64-r-pinctrl",
+		.of_match_table	= sun50i_a64_r_pinctrl_match,
+	},
+};
+builtin_platform_driver(sun50i_a64_r_pinctrl_driver);
-- 
2.11.1

Re: [PATCH 5/5] pinctrl: sunxi: Add A64 R_PIO controller support

[Andre Przywara]

Hi,

On 28/02/17 17:24, Icenowy Zheng wrote:
> The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
> Add support for the pins controlled by the R_PIO controller.
> 
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> ---
>  drivers/pinctrl/sunxi/Kconfig                |   5 +
>  drivers/pinctrl/sunxi/Makefile               |   1 +
>  drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 143 +++++++++++++++++++++++++++
>  3 files changed, 149 insertions(+)
>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
> 
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index 92325736d953..0738b0df5a0b 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -69,6 +69,11 @@ config PINCTRL_SUN50I_A64
>  	def_bool ARM64 && ARCH_SUNXI
>  	select PINCTRL_SUNXI
>  
> +config PINCTRL_SUN50I_A64_R
> +	def_bool ARM64 && ARCH_SUNXI
> +	depends on RESET_CONTROLLER

Same comment as on patch 1/5 (select instead of "depends on").
I take it this for drivers/reset/reset-sunxi.c?
Shouldn't this be the sunxi specific CONFIG_RESET_SUNXI then?
Also from from having a quick look at the driver this is broken for
arm64 (BITS_PER_LONG usage).
>From having a closer look this driver is actually not Allwinner specific
at all, since it just describes a number of bits in consecutive
32-bit(!) registers as reset cells.
As I today stumbled upon another SoC which has the same reset register
layout I was wondering if it's worth to generalise this? Possibly
renaming the driver, and allowing additional compatibles?
I can take a stab at this.

Cheers,
Andre.

> +	select PINCTRL_SUNXI
> +
>  config PINCTRL_SUN50I_H5
>  	def_bool ARM64 && ARCH_SUNXI
>  	select PINCTRL_SUNXI
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index 04ccb88ebd5f..df4ccd6cd44c 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)		+= pinctrl-sun8i-a23.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A23_R)	+= pinctrl-sun8i-a23-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A33)		+= pinctrl-sun8i-a33.o
>  obj-$(CONFIG_PINCTRL_SUN50I_A64)	+= pinctrl-sun50i-a64.o
> +obj-$(CONFIG_PINCTRL_SUN50I_A64_R)	+= pinctrl-sun50i-a64-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A83T)	+= pinctrl-sun8i-a83t.o
>  obj-$(CONFIG_PINCTRL_SUN8I_H3)		+= pinctrl-sun8i-h3.o
>  obj-$(CONFIG_PINCTRL_SUN8I_H3_R)	+= pinctrl-sun8i-h3-r.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
> new file mode 100644
> index 000000000000..90996a63689b
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
> @@ -0,0 +1,143 @@
> +/*
> + * Allwinner A64 SoCs special pins pinctrl driver.
> + *
> + * Based on pinctrl-sun8i-a23-r.c
> + *
> + * Copyright (C) 2016 Icenowy Zheng
> + * Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> + *
> + * Copyright (C) 2014 Chen-Yu Tsai
> + * Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> + *
> + * Copyright (C) 2014 Boris Brezillon
> + * Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> + *
> + * Copyright (C) 2014 Maxime Ripard
> + * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const struct sunxi_desc_pin sun50i_a64_r_pins[] = {
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "s_rsb"),		/* SCK */
> +		  SUNXI_FUNCTION(0x3, "s_i2c"),		/* SCK */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),	/* PL_EINT0 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "s_rsb"),		/* SDA */
> +		  SUNXI_FUNCTION(0x3, "s_i2c"),		/* SDA */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),	/* PL_EINT1 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "s_uart"),	/* TX */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),	/* PL_EINT2 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "s_uart"),	/* RX */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),	/* PL_EINT3 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* MS */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),	/* PL_EINT4 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* CK */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),	/* PL_EINT5 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* DO */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),	/* PL_EINT6 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x3, "s_jtag"),	/* DI */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),	/* PL_EINT7 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "s_i2c"),		/* SCK */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),	/* PL_EINT8 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "s_i2c"),		/* SDA */
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),	/* PL_EINT9 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "s_pwm"),
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),	/* PL_EINT10 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION(0x2, "s_cir_rx"),
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),	/* PL_EINT11 */
> +	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
> +		  SUNXI_FUNCTION(0x0, "gpio_in"),
> +		  SUNXI_FUNCTION(0x1, "gpio_out"),
> +		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),	/* PL_EINT12 */
> +};
> +
> +static const struct sunxi_pinctrl_desc sun50i_a64_r_pinctrl_data = {
> +	.pins = sun50i_a64_r_pins,
> +	.npins = ARRAY_SIZE(sun50i_a64_r_pins),
> +	.pin_base = PL_BASE,
> +	.irq_banks = 1,
> +};
> +
> +static int sun50i_a64_r_pinctrl_probe(struct platform_device *pdev)
> +{
> +	struct reset_control *rstc;
> +	int ret;
> +
> +	rstc = devm_reset_control_get(&pdev->dev, NULL);
> +	if (IS_ERR(rstc)) {
> +		dev_err(&pdev->dev, "Reset controller missing\n");
> +		return PTR_ERR(rstc);
> +	}
> +
> +	ret = reset_control_deassert(rstc);
> +	if (ret)
> +		return ret;
> +
> +	ret = sunxi_pinctrl_init(pdev,
> +				 &sun50i_a64_r_pinctrl_data);
> +
> +	if (ret)
> +		reset_control_assert(rstc);
> +
> +	return ret;
> +}
> +
> +static const struct of_device_id sun50i_a64_r_pinctrl_match[] = {
> +	{ .compatible = "allwinner,sun50i-a64-r-pinctrl", },
> +	{}
> +};
> +
> +static struct platform_driver sun50i_a64_r_pinctrl_driver = {
> +	.probe	= sun50i_a64_r_pinctrl_probe,
> +	.driver	= {
> +		.name		= "sun50i-a64-r-pinctrl",
> +		.of_match_table	= sun50i_a64_r_pinctrl_match,
> +	},
> +};
> +builtin_platform_driver(sun50i_a64_r_pinctrl_driver);
> 

Re: [PATCH 5/5] pinctrl: sunxi: Add A64 R_PIO controller support

[Icenowy Zheng]

01.03.2017, 02:27, "Andre Przywara" <andre.przywara-5wv7dgnIgG8@public.gmane.org>:
> Hi,
>
> On 28/02/17 17:24, Icenowy Zheng wrote:
>>  The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
>>  Add support for the pins controlled by the R_PIO controller.
>>
>>  Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
>>  ---
>>   drivers/pinctrl/sunxi/Kconfig | 5 +
>>   drivers/pinctrl/sunxi/Makefile | 1 +
>>   drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 143 +++++++++++++++++++++++++++
>>   3 files changed, 149 insertions(+)
>>   create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
>>
>>  diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
>>  index 92325736d953..0738b0df5a0b 100644
>>  --- a/drivers/pinctrl/sunxi/Kconfig
>>  +++ b/drivers/pinctrl/sunxi/Kconfig
>>  @@ -69,6 +69,11 @@ config PINCTRL_SUN50I_A64
>>           def_bool ARM64 && ARCH_SUNXI
>>           select PINCTRL_SUNXI
>>
>>  +config PINCTRL_SUN50I_A64_R
>>  + def_bool ARM64 && ARCH_SUNXI
>>  + depends on RESET_CONTROLLER
>
> Same comment as on patch 1/5 (select instead of "depends on").
> I take it this for drivers/reset/reset-sunxi.c?
> Shouldn't this be the sunxi specific CONFIG_RESET_SUNXI then?
> Also from from having a quick look at the driver this is broken for
> arm64 (BITS_PER_LONG usage).
> From having a closer look this driver is actually not Allwinner specific
> at all, since it just describes a number of bits in consecutive
> 32-bit(!) registers as reset cells.
> As I today stumbled upon another SoC which has the same reset register
> layout I was wondering if it's worth to generalise this? Possibly
> renaming the driver, and allowing additional compatibles?
> I can take a stab at this.

As I said, the driver now doesn't play under ARM64.
But, sunxi-ng ccu driver is now a reset controller.

>
> Cheers,
> Andre.
>
>>  + select PINCTRL_SUNXI
>>  +
>>   config PINCTRL_SUN50I_H5
>>           def_bool ARM64 && ARCH_SUNXI
>>           select PINCTRL_SUNXI
>>  diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
>>  index 04ccb88ebd5f..df4ccd6cd44c 100644
>>  --- a/drivers/pinctrl/sunxi/Makefile
>>  +++ b/drivers/pinctrl/sunxi/Makefile
>>  @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o
>>   obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o
>>   obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o
>>   obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o
>>  +obj-$(CONFIG_PINCTRL_SUN50I_A64_R) += pinctrl-sun50i-a64-r.o
>>   obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o
>>   obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
>>   obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
>>  diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
>>  new file mode 100644
>>  index 000000000000..90996a63689b
>>  --- /dev/null
>>  +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
>>  @@ -0,0 +1,143 @@
>>  +/*
>>  + * Allwinner A64 SoCs special pins pinctrl driver.
>>  + *
>>  + * Based on pinctrl-sun8i-a23-r.c
>>  + *
>>  + * Copyright (C) 2016 Icenowy Zheng
>>  + * Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
>>  + *
>>  + * Copyright (C) 2014 Chen-Yu Tsai
>>  + * Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
>>  + *
>>  + * Copyright (C) 2014 Boris Brezillon
>>  + * Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>  + *
>>  + * Copyright (C) 2014 Maxime Ripard
>>  + * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>  + *
>>  + * This file is licensed under the terms of the GNU General Public
>>  + * License version 2. This program is licensed "as is" without any
>>  + * warranty of any kind, whether express or implied.
>>  + */
>>  +
>>  +#include <linux/of.h>
>>  +#include <linux/of_device.h>
>>  +#include <linux/pinctrl/pinctrl.h>
>>  +#include <linux/platform_device.h>
>>  +#include <linux/reset.h>
>>  +
>>  +#include "pinctrl-sunxi.h"
>>  +
>>  +static const struct sunxi_desc_pin sun50i_a64_r_pins[] = {
>>  + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
>>  + SUNXI_FUNCTION(0x0, "gpio_in"),
>>  + SUNXI_FUNCTION(0x1, "gpio_out"),
>>  + SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
>>  + SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */
>>  + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */
>>  + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
>>  + SUNXI_FUNCTION(0x0, "gpio_in"),
>>  + SUNXI_FUNCTION(0x1, "gpio_out"),
>>  + SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
>>  + SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */
>>  + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */
>>  + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
>>  + SUNXI_FUNCTION(0x0, "gpio_in"),
>>  + SUNXI_FUNCTION(0x1, "gpio_out"),
>>  + SUNXI_FUNCTION(0x2, "s_uart"), /* TX */
>>  + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */
>>  + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
>>  + SUNXI_FUNCTION(0x0, "gpio_in"),
>>  + SUNXI_FUNCTION(0x1, "gpio_out"),
>>  + SUNXI_FUNCTION(0x2, "s_uart"), /* RX */
>>  + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */
>>  + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
>>  + SUNXI_FUNCTION(0x0, "gpio_in"),
>>  + SUNXI_FUNCTION(0x1, "gpio_out"),
>>  + SUNXI_FUNCTION(0x3, "s_jtag"), /* MS */
>>  + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */
>>  + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
>>  + SUNXI_FUNCTION(0x0, "gpio_in"),
>>  + SUNXI_FUNCTION(0x1, "gpio_out"),
>>  + SUNXI_FUNCTION(0x3, "s_jtag"), /* CK */
>>  + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */
>>  + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
>>  + SUNXI_FUNCTION(0x0, "gpio_in"),
>>  + SUNXI_FUNCTION(0x1, "gpio_out"),
>>  + SUNXI_FUNCTION(0x3, "s_jtag"), /* DO */
>>  + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */
>>  + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
>>  + SUNXI_FUNCTION(0x0, "gpio_in"),
>>  + SUNXI_FUNCTION(0x1, "gpio_out"),
>>  + SUNXI_FUNCTION(0x3, "s_jtag"), /* DI */
>>  + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */
>>  + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
>>  + SUNXI_FUNCTION(0x0, "gpio_in"),
>>  + SUNXI_FUNCTION(0x1, "gpio_out"),
>>  + SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */
>>  + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */
>>  + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
>>  + SUNXI_FUNCTION(0x0, "gpio_in"),
>>  + SUNXI_FUNCTION(0x1, "gpio_out"),
>>  + SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */
>>  + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */
>>  + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
>>  + SUNXI_FUNCTION(0x0, "gpio_in"),
>>  + SUNXI_FUNCTION(0x1, "gpio_out"),
>>  + SUNXI_FUNCTION(0x2, "s_pwm"),
>>  + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
>>  + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
>>  + SUNXI_FUNCTION(0x0, "gpio_in"),
>>  + SUNXI_FUNCTION(0x1, "gpio_out"),
>>  + SUNXI_FUNCTION(0x2, "s_cir_rx"),
>>  + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
>>  + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
>>  + SUNXI_FUNCTION(0x0, "gpio_in"),
>>  + SUNXI_FUNCTION(0x1, "gpio_out"),
>>  + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PL_EINT12 */
>>  +};
>>  +
>>  +static const struct sunxi_pinctrl_desc sun50i_a64_r_pinctrl_data = {
>>  + .pins = sun50i_a64_r_pins,
>>  + .npins = ARRAY_SIZE(sun50i_a64_r_pins),
>>  + .pin_base = PL_BASE,
>>  + .irq_banks = 1,
>>  +};
>>  +
>>  +static int sun50i_a64_r_pinctrl_probe(struct platform_device *pdev)
>>  +{
>>  + struct reset_control *rstc;
>>  + int ret;
>>  +
>>  + rstc = devm_reset_control_get(&pdev->dev, NULL);
>>  + if (IS_ERR(rstc)) {
>>  + dev_err(&pdev->dev, "Reset controller missing\n");
>>  + return PTR_ERR(rstc);
>>  + }
>>  +
>>  + ret = reset_control_deassert(rstc);
>>  + if (ret)
>>  + return ret;
>>  +
>>  + ret = sunxi_pinctrl_init(pdev,
>>  + &sun50i_a64_r_pinctrl_data);
>>  +
>>  + if (ret)
>>  + reset_control_assert(rstc);
>>  +
>>  + return ret;
>>  +}
>>  +
>>  +static const struct of_device_id sun50i_a64_r_pinctrl_match[] = {
>>  + { .compatible = "allwinner,sun50i-a64-r-pinctrl", },
>>  + {}
>>  +};
>>  +
>>  +static struct platform_driver sun50i_a64_r_pinctrl_driver = {
>>  + .probe = sun50i_a64_r_pinctrl_probe,
>>  + .driver = {
>>  + .name = "sun50i-a64-r-pinctrl",
>>  + .of_match_table = sun50i_a64_r_pinctrl_match,
>>  + },
>>  +};
>>  +builtin_platform_driver(sun50i_a64_r_pinctrl_driver);
>
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Re: [PATCH 5/5] pinctrl: sunxi: Add A64 R_PIO controller support

[Chen-Yu Tsai]

On Wed, Mar 1, 2017 at 2:29 AM, Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org> wrote:
> Hi,
>
> On 28/02/17 17:24, Icenowy Zheng wrote:
>> The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC.
>> Add support for the pins controlled by the R_PIO controller.
>>
>> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
>> ---
>>  drivers/pinctrl/sunxi/Kconfig                |   5 +
>>  drivers/pinctrl/sunxi/Makefile               |   1 +
>>  drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 143 +++++++++++++++++++++++++++
>>  3 files changed, 149 insertions(+)
>>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
>>
>> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
>> index 92325736d953..0738b0df5a0b 100644
>> --- a/drivers/pinctrl/sunxi/Kconfig
>> +++ b/drivers/pinctrl/sunxi/Kconfig
>> @@ -69,6 +69,11 @@ config PINCTRL_SUN50I_A64
>>       def_bool ARM64 && ARCH_SUNXI
>>       select PINCTRL_SUNXI
>>
>> +config PINCTRL_SUN50I_A64_R
>> +     def_bool ARM64 && ARCH_SUNXI
>> +     depends on RESET_CONTROLLER
>
> Same comment as on patch 1/5 (select instead of "depends on").
> I take it this for drivers/reset/reset-sunxi.c?
> Shouldn't this be the sunxi specific CONFIG_RESET_SUNXI then?
> Also from from having a quick look at the driver this is broken for
> arm64 (BITS_PER_LONG usage).
> From having a closer look this driver is actually not Allwinner specific
> at all, since it just describes a number of bits in consecutive
> 32-bit(!) registers as reset cells.
> As I today stumbled upon another SoC which has the same reset register
> layout I was wondering if it's worth to generalise this? Possibly
> renaming the driver, and allowing additional compatibles?
> I can take a stab at this.

CONFIG_RESET_SUNXI enables the old (pre-sunxi-ng) reset controller driver.
This driver was never used for ARM64 sunxi. As for it being generic,
I guess it's pretty standard, as it's just a bunch of registers with each
bit assigned to some peripheral.

CONFIG_RESET enables the reset control subsystem, which we need. This
is enabled by default if the platform selects ARCH_HAS_RESET_CONTROLLER,
which we do.

Regards
ChenYu

> Cheers,
> Andre.
>
>> +     select PINCTRL_SUNXI
>> +
>>  config PINCTRL_SUN50I_H5
>>       def_bool ARM64 && ARCH_SUNXI
>>       select PINCTRL_SUNXI
>> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
>> index 04ccb88ebd5f..df4ccd6cd44c 100644
>> --- a/drivers/pinctrl/sunxi/Makefile
>> +++ b/drivers/pinctrl/sunxi/Makefile
>> @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)             += pinctrl-sun8i-a23.o
>>  obj-$(CONFIG_PINCTRL_SUN8I_A23_R)    += pinctrl-sun8i-a23-r.o
>>  obj-$(CONFIG_PINCTRL_SUN8I_A33)              += pinctrl-sun8i-a33.o
>>  obj-$(CONFIG_PINCTRL_SUN50I_A64)     += pinctrl-sun50i-a64.o
>> +obj-$(CONFIG_PINCTRL_SUN50I_A64_R)   += pinctrl-sun50i-a64-r.o
>>  obj-$(CONFIG_PINCTRL_SUN8I_A83T)     += pinctrl-sun8i-a83t.o
>>  obj-$(CONFIG_PINCTRL_SUN8I_H3)               += pinctrl-sun8i-h3.o
>>  obj-$(CONFIG_PINCTRL_SUN8I_H3_R)     += pinctrl-sun8i-h3-r.o
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
>> new file mode 100644
>> index 000000000000..90996a63689b
>> --- /dev/null
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
>> @@ -0,0 +1,143 @@
>> +/*
>> + * Allwinner A64 SoCs special pins pinctrl driver.
>> + *
>> + * Based on pinctrl-sun8i-a23-r.c
>> + *
>> + * Copyright (C) 2016 Icenowy Zheng
>> + * Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
>> + *
>> + * Copyright (C) 2014 Chen-Yu Tsai
>> + * Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
>> + *
>> + * Copyright (C) 2014 Boris Brezillon
>> + * Boris Brezillon <boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>> + *
>> + * Copyright (C) 2014 Maxime Ripard
>> + * Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2.  This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/pinctrl/pinctrl.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/reset.h>
>> +
>> +#include "pinctrl-sunxi.h"
>> +
>> +static const struct sunxi_desc_pin sun50i_a64_r_pins[] = {
>> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
>> +               SUNXI_FUNCTION(0x0, "gpio_in"),
>> +               SUNXI_FUNCTION(0x1, "gpio_out"),
>> +               SUNXI_FUNCTION(0x2, "s_rsb"),         /* SCK */
>> +               SUNXI_FUNCTION(0x3, "s_i2c"),         /* SCK */
>> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */
>> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
>> +               SUNXI_FUNCTION(0x0, "gpio_in"),
>> +               SUNXI_FUNCTION(0x1, "gpio_out"),
>> +               SUNXI_FUNCTION(0x2, "s_rsb"),         /* SDA */
>> +               SUNXI_FUNCTION(0x3, "s_i2c"),         /* SDA */
>> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */
>> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
>> +               SUNXI_FUNCTION(0x0, "gpio_in"),
>> +               SUNXI_FUNCTION(0x1, "gpio_out"),
>> +               SUNXI_FUNCTION(0x2, "s_uart"),        /* TX */
>> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PL_EINT2 */
>> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
>> +               SUNXI_FUNCTION(0x0, "gpio_in"),
>> +               SUNXI_FUNCTION(0x1, "gpio_out"),
>> +               SUNXI_FUNCTION(0x2, "s_uart"),        /* RX */
>> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PL_EINT3 */
>> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
>> +               SUNXI_FUNCTION(0x0, "gpio_in"),
>> +               SUNXI_FUNCTION(0x1, "gpio_out"),
>> +               SUNXI_FUNCTION(0x3, "s_jtag"),        /* MS */
>> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PL_EINT4 */
>> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
>> +               SUNXI_FUNCTION(0x0, "gpio_in"),
>> +               SUNXI_FUNCTION(0x1, "gpio_out"),
>> +               SUNXI_FUNCTION(0x3, "s_jtag"),        /* CK */
>> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PL_EINT5 */
>> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
>> +               SUNXI_FUNCTION(0x0, "gpio_in"),
>> +               SUNXI_FUNCTION(0x1, "gpio_out"),
>> +               SUNXI_FUNCTION(0x3, "s_jtag"),        /* DO */
>> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PL_EINT6 */
>> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
>> +               SUNXI_FUNCTION(0x0, "gpio_in"),
>> +               SUNXI_FUNCTION(0x1, "gpio_out"),
>> +               SUNXI_FUNCTION(0x3, "s_jtag"),        /* DI */
>> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PL_EINT7 */
>> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
>> +               SUNXI_FUNCTION(0x0, "gpio_in"),
>> +               SUNXI_FUNCTION(0x1, "gpio_out"),
>> +               SUNXI_FUNCTION(0x2, "s_i2c"),         /* SCK */
>> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PL_EINT8 */
>> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
>> +               SUNXI_FUNCTION(0x0, "gpio_in"),
>> +               SUNXI_FUNCTION(0x1, "gpio_out"),
>> +               SUNXI_FUNCTION(0x2, "s_i2c"),         /* SDA */
>> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PL_EINT9 */
>> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
>> +               SUNXI_FUNCTION(0x0, "gpio_in"),
>> +               SUNXI_FUNCTION(0x1, "gpio_out"),
>> +               SUNXI_FUNCTION(0x2, "s_pwm"),
>> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
>> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
>> +               SUNXI_FUNCTION(0x0, "gpio_in"),
>> +               SUNXI_FUNCTION(0x1, "gpio_out"),
>> +               SUNXI_FUNCTION(0x2, "s_cir_rx"),
>> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */
>> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12),
>> +               SUNXI_FUNCTION(0x0, "gpio_in"),
>> +               SUNXI_FUNCTION(0x1, "gpio_out"),
>> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PL_EINT12 */
>> +};
>> +
>> +static const struct sunxi_pinctrl_desc sun50i_a64_r_pinctrl_data = {
>> +     .pins = sun50i_a64_r_pins,
>> +     .npins = ARRAY_SIZE(sun50i_a64_r_pins),
>> +     .pin_base = PL_BASE,
>> +     .irq_banks = 1,
>> +};
>> +
>> +static int sun50i_a64_r_pinctrl_probe(struct platform_device *pdev)
>> +{
>> +     struct reset_control *rstc;
>> +     int ret;
>> +
>> +     rstc = devm_reset_control_get(&pdev->dev, NULL);
>> +     if (IS_ERR(rstc)) {
>> +             dev_err(&pdev->dev, "Reset controller missing\n");
>> +             return PTR_ERR(rstc);
>> +     }
>> +
>> +     ret = reset_control_deassert(rstc);
>> +     if (ret)
>> +             return ret;
>> +
>> +     ret = sunxi_pinctrl_init(pdev,
>> +                              &sun50i_a64_r_pinctrl_data);
>> +
>> +     if (ret)
>> +             reset_control_assert(rstc);
>> +
>> +     return ret;
>> +}
>> +
>> +static const struct of_device_id sun50i_a64_r_pinctrl_match[] = {
>> +     { .compatible = "allwinner,sun50i-a64-r-pinctrl", },
>> +     {}
>> +};
>> +
>> +static struct platform_driver sun50i_a64_r_pinctrl_driver = {
>> +     .probe  = sun50i_a64_r_pinctrl_probe,
>> +     .driver = {
>> +             .name           = "sun50i-a64-r-pinctrl",
>> +             .of_match_table = sun50i_a64_r_pinctrl_match,
>> +     },
>> +};
>> +builtin_platform_driver(sun50i_a64_r_pinctrl_driver);
>>

Re: [PATCH 1/5] pinctrl: sunxi: refactor pinctrl choice selecting for ARM64

[Andre Przywara]

Hi Icenowy,

(first thing: could you create your series with --cover-letter and fill
this in? There you could explain what this series is about and also
state things like dependencies from other patches and the commit that
you based that on.)

On 28/02/17 17:24, Icenowy Zheng wrote:
> ARM64 Allwinner SoCs used to have every pinctrl driver selected in
> ARCH_SUNXI. Change this to make their default value to (ARM64 &&
> ARCH_SUNXI).
> 
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>

Overall this is a nice solution. Thanks for posting this.

> ---
>  drivers/pinctrl/sunxi/Kconfig | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index 816015cf7053..92325736d953 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -48,8 +48,9 @@ config PINCTRL_SUN8I_H3
>  	select PINCTRL_SUNXI
>  
>  config PINCTRL_SUN8I_H3_R
> -	def_bool MACH_SUN8I
> -	select PINCTRL_SUNXI_COMMON
> +	def_bool MACH_SUN8I || (ARM64 && ARCH_SUNXI)
> +	depends on RESET_CONTROLLER

So this looks a bit odd. I take it this is for the extra reset register
in the PRCM block.
1) I don't think this belongs into this patch. If this has been
forgotten in the past, please make an extra patch for this. It's cheap
to do so ;-)
2) Is this really a "depends on"? Shouldn't this be a select? With
sunxi_ng clocks we don't need the reset controller for the normal
peripherals anymore, so this option might not be selected by default in
the future. And having this "depends on" leads to the PINCTRL_ option
being hidden if RESET_CONTROLLER isn't selected.
I think this bites us already in arm64, where ARCH_HAS_RESET_CONTROLLER
is not enabled for ARCH_SUNXI.


But as the rest of the patch is fine, if you remove this line:
Reviewed-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>

Cheers,
Andre.

> +	select PINCTRL_SUNXI
>  
>  config PINCTRL_SUN8I_V3S
>  	def_bool MACH_SUN8I
> @@ -65,11 +66,11 @@ config PINCTRL_SUN9I_A80_R
>  	select PINCTRL_SUNXI
>  
>  config PINCTRL_SUN50I_A64
> -	bool
> +	def_bool ARM64 && ARCH_SUNXI
>  	select PINCTRL_SUNXI
>  
>  config PINCTRL_SUN50I_H5
> -	bool
> +	def_bool ARM64 && ARCH_SUNXI
>  	select PINCTRL_SUNXI
>  
>  endif
> 

Re: [PATCH 1/5] pinctrl: sunxi: refactor pinctrl choice selecting for ARM64

[Icenowy Zheng]

01.03.2017, 02:15, "Andre Przywara" <andre.przywara-5wv7dgnIgG8@public.gmane.org>:
> Hi Icenowy,
>
> (first thing: could you create your series with --cover-letter and fill
> this in? There you could explain what this series is about and also
> state things like dependencies from other patches and the commit that
> you based that on.)
>
> On 28/02/17 17:24, Icenowy Zheng wrote:
>>  ARM64 Allwinner SoCs used to have every pinctrl driver selected in
>>  ARCH_SUNXI. Change this to make their default value to (ARM64 &&
>>  ARCH_SUNXI).
>>
>>  Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
>
> Overall this is a nice solution. Thanks for posting this.
>
>>  ---
>>   drivers/pinctrl/sunxi/Kconfig | 9 +++++----
>>   1 file changed, 5 insertions(+), 4 deletions(-)
>>
>>  diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
>>  index 816015cf7053..92325736d953 100644
>>  --- a/drivers/pinctrl/sunxi/Kconfig
>>  +++ b/drivers/pinctrl/sunxi/Kconfig
>>  @@ -48,8 +48,9 @@ config PINCTRL_SUN8I_H3
>>           select PINCTRL_SUNXI
>>
>>   config PINCTRL_SUN8I_H3_R
>>  - def_bool MACH_SUN8I
>>  - select PINCTRL_SUNXI_COMMON
>>  + def_bool MACH_SUN8I || (ARM64 && ARCH_SUNXI)
>>  + depends on RESET_CONTROLLER
>
> So this looks a bit odd. I take it this is for the extra reset register
> in the PRCM block.
> 1) I don't think this belongs into this patch. If this has been
> forgotten in the past, please make an extra patch for this. It's cheap
> to do so ;-)
> 2) Is this really a "depends on"? Shouldn't this be a select? With
> sunxi_ng clocks we don't need the reset controller for the normal
> peripherals anymore, so this option might not be selected by default in
> the future. And having this "depends on" leads to the PINCTRL_ option
> being hidden if RESET_CONTROLLER isn't selected.
> I think this bites us already in arm64, where ARCH_HAS_RESET_CONTROLLER
> is not enabled for ARCH_SUNXI.

PINCTRL_ options are always hidden now, Maxime, do you
want to change that?

We should enable ARCH_HAS_RESET_CONTROLLER for
ARCH_SUNXI, as sunxi-ng ccu is a reset controller.

Without RESET_CONTROLLER enabled, errors will occur
when linking:
```
drivers/built-in.o: In function `sunxi_ccu_probe':
of_reserved_mem.c:(.text+0x16058): undefined reference to `reset_controller_register'
```

If you don't care, I will make it an additional patch.

And there's really a reset line for the R_PIO pinctrls.

But you're right, this line shouldn't occur in this patch.
I will make a more patch for it.

>
> But as the rest of the patch is fine, if you remove this line:
> Reviewed-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
>
> Cheers,
> Andre.
>
>>  + select PINCTRL_SUNXI
>>
>>   config PINCTRL_SUN8I_V3S
>>           def_bool MACH_SUN8I
>>  @@ -65,11 +66,11 @@ config PINCTRL_SUN9I_A80_R
>>           select PINCTRL_SUNXI
>>
>>   config PINCTRL_SUN50I_A64
>>  - bool
>>  + def_bool ARM64 && ARCH_SUNXI
>>           select PINCTRL_SUNXI
>>
>>   config PINCTRL_SUN50I_H5
>>  - bool
>>  + def_bool ARM64 && ARCH_SUNXI
>>           select PINCTRL_SUNXI
>>
>>   endif

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Re: [PATCH 1/5] pinctrl: sunxi: refactor pinctrl choice selecting for ARM64

[Chen-Yu Tsai]

On Wed, Mar 1, 2017 at 2:55 AM, Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> wrote:
>
>
> 01.03.2017, 02:15, "Andre Przywara" <andre.przywara-5wv7dgnIgG8@public.gmane.org>:
>> Hi Icenowy,
>>
>> (first thing: could you create your series with --cover-letter and fill
>> this in? There you could explain what this series is about and also
>> state things like dependencies from other patches and the commit that
>> you based that on.)
>>
>> On 28/02/17 17:24, Icenowy Zheng wrote:
>>>  ARM64 Allwinner SoCs used to have every pinctrl driver selected in
>>>  ARCH_SUNXI. Change this to make their default value to (ARM64 &&
>>>  ARCH_SUNXI).
>>>
>>>  Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
>>
>> Overall this is a nice solution. Thanks for posting this.
>>
>>>  ---
>>>   drivers/pinctrl/sunxi/Kconfig | 9 +++++----
>>>   1 file changed, 5 insertions(+), 4 deletions(-)
>>>
>>>  diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
>>>  index 816015cf7053..92325736d953 100644
>>>  --- a/drivers/pinctrl/sunxi/Kconfig
>>>  +++ b/drivers/pinctrl/sunxi/Kconfig
>>>  @@ -48,8 +48,9 @@ config PINCTRL_SUN8I_H3
>>>           select PINCTRL_SUNXI
>>>
>>>   config PINCTRL_SUN8I_H3_R
>>>  - def_bool MACH_SUN8I
>>>  - select PINCTRL_SUNXI_COMMON
>>>  + def_bool MACH_SUN8I || (ARM64 && ARCH_SUNXI)
>>>  + depends on RESET_CONTROLLER
>>
>> So this looks a bit odd. I take it this is for the extra reset register
>> in the PRCM block.
>> 1) I don't think this belongs into this patch. If this has been
>> forgotten in the past, please make an extra patch for this. It's cheap
>> to do so ;-)
>> 2) Is this really a "depends on"? Shouldn't this be a select? With
>> sunxi_ng clocks we don't need the reset controller for the normal
>> peripherals anymore, so this option might not be selected by default in
>> the future. And having this "depends on" leads to the PINCTRL_ option
>> being hidden if RESET_CONTROLLER isn't selected.
>> I think this bites us already in arm64, where ARCH_HAS_RESET_CONTROLLER
>> is not enabled for ARCH_SUNXI.
>
> PINCTRL_ options are always hidden now, Maxime, do you
> want to change that?
>
> We should enable ARCH_HAS_RESET_CONTROLLER for
> ARCH_SUNXI, as sunxi-ng ccu is a reset controller.

Agreed.

> Without RESET_CONTROLLER enabled, errors will occur
> when linking:
> ```
> drivers/built-in.o: In function `sunxi_ccu_probe':
> of_reserved_mem.c:(.text+0x16058): undefined reference to `reset_controller_register'
> ```
>
> If you don't care, I will make it an additional patch.
>
> And there's really a reset line for the R_PIO pinctrls.

Depends on is the right thing here, since this driver depends
on the reset controller subsystem to be present for any
devm_reset_control_get calls. Now if this pinctrl has a reset
line, but is missing that call, it needs to be fixed.

It seems only A23 and A31 R_PIO drivers have them.

Regards
ChenYu

>
> But you're right, this line shouldn't occur in this patch.
> I will make a more patch for it.
>
>>
>> But as the rest of the patch is fine, if you remove this line:
>> Reviewed-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
>>
>> Cheers,
>> Andre.
>>
>>>  + select PINCTRL_SUNXI
>>>
>>>   config PINCTRL_SUN8I_V3S
>>>           def_bool MACH_SUN8I
>>>  @@ -65,11 +66,11 @@ config PINCTRL_SUN9I_A80_R
>>>           select PINCTRL_SUNXI
>>>
>>>   config PINCTRL_SUN50I_A64
>>>  - bool
>>>  + def_bool ARM64 && ARCH_SUNXI
>>>           select PINCTRL_SUNXI
>>>
>>>   config PINCTRL_SUN50I_H5
>>>  - bool
>>>  + def_bool ARM64 && ARCH_SUNXI
>>>           select PINCTRL_SUNXI
>>>
>>>   endif

Re: [PATCH 5/5] pinctrl: sunxi: Add A64 R_PIO controller support

[Icenowy Zheng]

2017年3月1日 10:34于 Chen-Yu Tsai <wens@csie.org>写道：
>
> On Wed, Mar 1, 2017 at 2:29 AM, Andre Przywara <andre.przywara@arm.com> wrote: 
> > Hi, 
> > 
> > On 28/02/17 17:24, Icenowy Zheng wrote: 
> >> The A64 has a R_PIO pin controller, similar to the one found on the H3 SoC. 
> >> Add support for the pins controlled by the R_PIO controller. 
> >> 
> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> 
> >> --- 
> >>  drivers/pinctrl/sunxi/Kconfig                |   5 + 
> >>  drivers/pinctrl/sunxi/Makefile               |   1 + 
> >>  drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c | 143 +++++++++++++++++++++++++++ 
> >>  3 files changed, 149 insertions(+) 
> >>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c 
> >> 
> >> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig 
> >> index 92325736d953..0738b0df5a0b 100644 
> >> --- a/drivers/pinctrl/sunxi/Kconfig 
> >> +++ b/drivers/pinctrl/sunxi/Kconfig 
> >> @@ -69,6 +69,11 @@ config PINCTRL_SUN50I_A64 
> >>       def_bool ARM64 && ARCH_SUNXI 
> >>       select PINCTRL_SUNXI 
> >> 
> >> +config PINCTRL_SUN50I_A64_R 
> >> +     def_bool ARM64 && ARCH_SUNXI 
> >> +     depends on RESET_CONTROLLER 
> > 
> > Same comment as on patch 1/5 (select instead of "depends on"). 
> > I take it this for drivers/reset/reset-sunxi.c? 
> > Shouldn't this be the sunxi specific CONFIG_RESET_SUNXI then? 
> > Also from from having a quick look at the driver this is broken for 
> > arm64 (BITS_PER_LONG usage). 
> > From having a closer look this driver is actually not Allwinner specific 
> > at all, since it just describes a number of bits in consecutive 
> > 32-bit(!) registers as reset cells. 
> > As I today stumbled upon another SoC which has the same reset register 
> > layout I was wondering if it's worth to generalise this? Possibly 
> > renaming the driver, and allowing additional compatibles? 
> > I can take a stab at this. 
>
> CONFIG_RESET_SUNXI enables the old (pre-sunxi-ng) reset controller driver. 
> This driver was never used for ARM64 sunxi. As for it being generic, 
> I guess it's pretty standard, as it's just a bunch of registers with each 
> bit assigned to some peripheral. 
>
> CONFIG_RESET enables the reset control subsystem, which we need. This 
> is enabled by default if the platform selects ARCH_HAS_RESET_CONTROLLER, 
> which we do. 
>

On ARM64 ARCH_SUNXI  ARCH_HAS_RESET_CONTROLLER
is forgot to be selected.

I will soon send out a patch for it.

P.S. I think thus sunxi-ng should select RESET_CONTROLLER again, as it may be built with COMPILE_TEST.

> Regards 
> ChenYu 
>
> > Cheers, 
> > Andre. 
> > 
> >> +     select PINCTRL_SUNXI 
> >> + 
> >>  config PINCTRL_SUN50I_H5 
> >>       def_bool ARM64 && ARCH_SUNXI 
> >>       select PINCTRL_SUNXI 
> >> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile 
> >> index 04ccb88ebd5f..df4ccd6cd44c 100644 
> >> --- a/drivers/pinctrl/sunxi/Makefile 
> >> +++ b/drivers/pinctrl/sunxi/Makefile 
> >> @@ -11,6 +11,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)             += pinctrl-sun8i-a23.o 
> >>  obj-$(CONFIG_PINCTRL_SUN8I_A23_R)    += pinctrl-sun8i-a23-r.o 
> >>  obj-$(CONFIG_PINCTRL_SUN8I_A33)              += pinctrl-sun8i-a33.o 
> >>  obj-$(CONFIG_PINCTRL_SUN50I_A64)     += pinctrl-sun50i-a64.o 
> >> +obj-$(CONFIG_PINCTRL_SUN50I_A64_R)   += pinctrl-sun50i-a64-r.o 
> >>  obj-$(CONFIG_PINCTRL_SUN8I_A83T)     += pinctrl-sun8i-a83t.o 
> >>  obj-$(CONFIG_PINCTRL_SUN8I_H3)               += pinctrl-sun8i-h3.o 
> >>  obj-$(CONFIG_PINCTRL_SUN8I_H3_R)     += pinctrl-sun8i-h3-r.o 
> >> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c 
> >> new file mode 100644 
> >> index 000000000000..90996a63689b 
> >> --- /dev/null 
> >> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c 
> >> @@ -0,0 +1,143 @@ 
> >> +/* 
> >> + * Allwinner A64 SoCs special pins pinctrl driver. 
> >> + * 
> >> + * Based on pinctrl-sun8i-a23-r.c 
> >> + * 
> >> + * Copyright (C) 2016 Icenowy Zheng 
> >> + * Icenowy Zheng <icenowy@aosc.xyz> 
> >> + * 
> >> + * Copyright (C) 2014 Chen-Yu Tsai 
> >> + * Chen-Yu Tsai <wens@csie.org> 
> >> + * 
> >> + * Copyright (C) 2014 Boris Brezillon 
> >> + * Boris Brezillon <boris.brezillon@free-electrons.com> 
> >> + * 
> >> + * Copyright (C) 2014 Maxime Ripard 
> >> + * Maxime Ripard <maxime.ripard@free-electrons.com> 
> >> + * 
> >> + * This file is licensed under the terms of the GNU General Public 
> >> + * License version 2.  This program is licensed "as is" without any 
> >> + * warranty of any kind, whether express or implied. 
> >> + */ 
> >> + 
> >> +#include <linux/of.h> 
> >> +#include <linux/of_device.h> 
> >> +#include <linux/pinctrl/pinctrl.h> 
> >> +#include <linux/platform_device.h> 
> >> +#include <linux/reset.h> 
> >> + 
> >> +#include "pinctrl-sunxi.h" 
> >> + 
> >> +static const struct sunxi_desc_pin sun50i_a64_r_pins[] = { 
> >> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), 
> >> +               SUNXI_FUNCTION(0x0, "gpio_in"), 
> >> +               SUNXI_FUNCTION(0x1, "gpio_out"), 
> >> +               SUNXI_FUNCTION(0x2, "s_rsb"),         /* SCK */ 
> >> +               SUNXI_FUNCTION(0x3, "s_i2c"),         /* SCK */ 
> >> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */ 
> >> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), 
> >> +               SUNXI_FUNCTION(0x0, "gpio_in"), 
> >> +               SUNXI_FUNCTION(0x1, "gpio_out"), 
> >> +               SUNXI_FUNCTION(0x2, "s_rsb"),         /* SDA */ 
> >> +               SUNXI_FUNCTION(0x3, "s_i2c"),         /* SDA */ 
> >> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */ 
> >> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), 
> >> +               SUNXI_FUNCTION(0x0, "gpio_in"), 
> >> +               SUNXI_FUNCTION(0x1, "gpio_out"), 
> >> +               SUNXI_FUNCTION(0x2, "s_uart"),        /* TX */ 
> >> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PL_EINT2 */ 
> >> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3), 
> >> +               SUNXI_FUNCTION(0x0, "gpio_in"), 
> >> +               SUNXI_FUNCTION(0x1, "gpio_out"), 
> >> +               SUNXI_FUNCTION(0x2, "s_uart"),        /* RX */ 
> >> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PL_EINT3 */ 
> >> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4), 
> >> +               SUNXI_FUNCTION(0x0, "gpio_in"), 
> >> +               SUNXI_FUNCTION(0x1, "gpio_out"), 
> >> +               SUNXI_FUNCTION(0x3, "s_jtag"),        /* MS */ 
> >> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PL_EINT4 */ 
> >> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), 
> >> +               SUNXI_FUNCTION(0x0, "gpio_in"), 
> >> +               SUNXI_FUNCTION(0x1, "gpio_out"), 
> >> +               SUNXI_FUNCTION(0x3, "s_jtag"),        /* CK */ 
> >> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PL_EINT5 */ 
> >> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), 
> >> +               SUNXI_FUNCTION(0x0, "gpio_in"), 
> >> +               SUNXI_FUNCTION(0x1, "gpio_out"), 
> >> +               SUNXI_FUNCTION(0x3, "s_jtag"),        /* DO */ 
> >> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PL_EINT6 */ 
> >> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), 
> >> +               SUNXI_FUNCTION(0x0, "gpio_in"), 
> >> +               SUNXI_FUNCTION(0x1, "gpio_out"), 
> >> +               SUNXI_FUNCTION(0x3, "s_jtag"),        /* DI */ 
> >> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PL_EINT7 */ 
> >> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), 
> >> +               SUNXI_FUNCTION(0x0, "gpio_in"), 
> >> +               SUNXI_FUNCTION(0x1, "gpio_out"), 
> >> +               SUNXI_FUNCTION(0x2, "s_i2c"),         /* SCK */ 
> >> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PL_EINT8 */ 
> >> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9), 
> >> +               SUNXI_FUNCTION(0x0, "gpio_in"), 
> >> +               SUNXI_FUNCTION(0x1, "gpio_out"), 
> >> +               SUNXI_FUNCTION(0x2, "s_i2c"),         /* SDA */ 
> >> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PL_EINT9 */ 
> >> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10), 
> >> +               SUNXI_FUNCTION(0x0, "gpio_in"), 
> >> +               SUNXI_FUNCTION(0x1, "gpio_out"), 
> >> +               SUNXI_FUNCTION(0x2, "s_pwm"), 
> >> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */ 
> >> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11), 
> >> +               SUNXI_FUNCTION(0x0, "gpio_in"), 
> >> +               SUNXI_FUNCTION(0x1, "gpio_out"), 
> >> +               SUNXI_FUNCTION(0x2, "s_cir_rx"), 
> >> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */ 
> >> +     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12), 
> >> +               SUNXI_FUNCTION(0x0, "gpio_in"), 
> >> +               SUNXI_FUNCTION(0x1, "gpio_out"), 
> >> +               SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PL_EINT12 */ 
> >> +}; 
> >> + 
> >> +static const struct sunxi_pinctrl_desc sun50i_a64_r_pinctrl_data = { 
> >> +     .pins = sun50i_a64_r_pins, 
> >> +     .npins = ARRAY_SIZE(sun50i_a64_r_pins), 
> >> +     .pin_base = PL_BASE, 
> >> +     .irq_banks = 1, 
> >> +}; 
> >> + 
> >> +static int sun50i_a64_r_pinctrl_probe(struct platform_device *pdev) 
> >> +{ 
> >> +     struct reset_control *rstc; 
> >> +     int ret; 
> >> + 
> >> +     rstc = devm_reset_control_get(&pdev->dev, NULL); 
> >> +     if (IS_ERR(rstc)) { 
> >> +             dev_err(&pdev->dev, "Reset controller missing\n"); 
> >> +             return PTR_ERR(rstc); 
> >> +     } 
> >> + 
> >> +     ret = reset_control_deassert(rstc); 
> >> +     if (ret) 
> >> +             return ret; 
> >> + 
> >> +     ret = sunxi_pinctrl_init(pdev, 
> >> +                              &sun50i_a64_r_pinctrl_data); 
> >> + 
> >> +     if (ret) 
> >> +             reset_control_assert(rstc); 
> >> + 
> >> +     return ret; 
> >> +} 
> >> + 
> >> +static const struct of_device_id sun50i_a64_r_pinctrl_match[] = { 
> >> +     { .compatible = "allwinner,sun50i-a64-r-pinctrl", }, 
> >> +     {} 
> >> +}; 
> >> + 
> >> +static struct platform_driver sun50i_a64_r_pinctrl_driver = { 
> >> +     .probe  = sun50i_a64_r_pinctrl_probe, 
> >> +     .driver = { 
> >> +             .name           = "sun50i-a64-r-pinctrl", 
> >> +             .of_match_table = sun50i_a64_r_pinctrl_match, 
> >> +     }, 
> >> +}; 
> >> +builtin_platform_driver(sun50i_a64_r_pinctrl_driver); 
> >> 
>
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