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charset=UTF-8 Content-Transfer-Encoding: 7bit On 08.02.2024 15:56, Claudiu wrote: > From: Claudiu Beznea > > pinctrl-rzg2l driver is used on RZ/G3S which support deep sleep states > where power to most of the SoC components is turned off. > > For this add suspend/resume support. This involves saving and restoring > configured registers along with disabling clock in case there is no pin > configured as wakeup sources. > > To save/restore registers 2 caches were allocated: one for GPIO pins and > one for dedicated pins. > > On suspend path the pin controller registers are saved and if none of the > pins are configured as wakeup sources the pinctrl clock is disabled. > Otherwise it remains on. > > On resume path the configuration is done as follows: > 1/ setup PFCs by writing to registers on pin based accesses > 2/ setup GPIOs by writing to registers on port based accesses and > following configuration steps specified in hardware manual > 3/ setup dedicated pins by writing to registers on port based accesses > 4/ setup interrupts. > > Because interrupt signals are routed to IA55 interrupt controller and > IA55 interrupt controller resumes before pin controller, patch restores > also the configured interrupts just after pin settings are restored to > avoid invalid interrupts while resuming. > > Signed-off-by: Claudiu Beznea > --- [ ... ] > > +/** > + * struct rzg2l_pinctrl_reg_cache - register cache structure (to be used in suspend/resume) > + * @p: P registers cache > + * @pm: PM registers cache > + * @pmc: PMC registers cache > + * @pfc: PFC registers cache > + * @iolh: IOLH registers cache > + * @ien: IEN registers cache > + * @sd_ch: SD_CH registers cache > + * @eth_poc: ET_POC registers cache > + * @eth_mode: ETH_MODE register cache > + * @qspi: QSPI registers cache > + */ > +struct rzg2l_pinctrl_reg_cache { > + u8 *p; > + u16 *pm; > + u8 *pmc; > + u32 *pfc; > + u32 *iolh[2]; > + u32 *ien[2]; > + u32 sd_ch[2]; > + u32 eth_poc[2]; > + u32 eth_mode; > + u32 qspi; I missed it, u8 should be enough for these. [ ... ]