From: Florian Fainelli <f.fainelli@gmail.com>
To: Chris Packham <chris.packham@alliedtelesis.co.nz>,
linus.walleij@linaro.org, rjui@broadcom.com,
sbranden@broadcom.com, bcm-kernel-feedback-list@broadcom.com
Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/2] pinctrl: bcm: nsp: use gpiolib infrastructure for interrupts
Date: Fri, 1 Nov 2019 19:55:11 -0700 [thread overview]
Message-ID: <b681ed9d-a31a-e5cc-04ba-6f38a5cc745b@gmail.com> (raw)
In-Reply-To: <20191101015621.12451-2-chris.packham@alliedtelesis.co.nz>
On 10/31/2019 6:56 PM, Chris Packham wrote:
> Use more of the gpiolib infrastructure for handling interrupts. The
> root interrupt still needs to be handled manually as it is shared with
> other peripherals on the SoC.
>
> This will allow multiple instances of this driver to be supported and
> will clean up gracefully on failure thanks to the device managed APIs.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
Just a couple of comments below:
[snip]
> + irqc->name = dev_name(dev);
The irq_chip used to be named "gpio-a" now it most likely will contain
the address.unit-name notation from Device Tree, since this is visible
in /proc/interrupts one might consider this to be an ABI breakage.
> + irqc->irq_ack = nsp_gpio_irq_ack;
> + irqc->irq_mask = nsp_gpio_irq_mask;
> + irqc->irq_unmask = nsp_gpio_irq_unmask;
> + irqc->irq_set_type = nsp_gpio_irq_set_type;
>
> - irq_set_chip_and_handler(irq, &nsp_gpio_irq_chip,
> - handle_simple_irq);
> - irq_set_chip_data(irq, chip);
> - }
> + val = readl(chip->base + NSP_CHIP_A_INT_MASK);
> + val = val | NSP_CHIP_A_GPIO_INT_BIT;
> + writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
>
> /* Install ISR for this GPIO controller. */
> - ret = devm_request_irq(&pdev->dev, irq, nsp_gpio_irq_handler,
> - IRQF_SHARED, "gpio-a", chip);
> + ret = devm_request_irq(dev, irq, nsp_gpio_irq_handler,
> + IRQF_SHARED, "gpio-a", &chip->gc);
> if (ret) {
> dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
> irq, ret);
> - goto err_rm_gpiochip;
> + return ret;
> }
>
> - val = readl(chip->base + NSP_CHIP_A_INT_MASK);
> - val = val | NSP_CHIP_A_GPIO_INT_BIT;
> - writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
> + girq = &chip->gc.irq;
> + girq->chip = irqc;
> + /* This will let us handle the parent IRQ in the driver */
> + girq->parent_handler = NULL;
> + girq->num_parents = 0;
> + girq->parents = NULL;
> + girq->default_type = IRQ_TYPE_NONE;
> + girq->handler = handle_simple_irq;
It might be worth creating a helper that can be called to initialize all
relevant members to the values that indicate: let me manage the
interrupt. This would make us more future proof with respect to
assumptions being made in gpiolib as well as if new fields are added in
the future. This would be a separate patch obviously.
Other than that:
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
--
Florian
next prev parent reply other threads:[~2019-11-02 2:55 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-01 1:56 [PATCH 0/2] pinctrl: bcm: nsp: gpio improvements Chris Packham
2019-11-01 1:56 ` [PATCH 1/2] pinctrl: bcm: nsp: use gpiolib infrastructure for interrupts Chris Packham
2019-11-02 2:55 ` Florian Fainelli [this message]
2019-11-03 21:17 ` Chris Packham
2019-11-03 22:23 ` Linus Walleij
2019-11-01 1:56 ` [PATCH 2/2] pinctrl: bcm: nsp: implement get_direction Chris Packham
2019-11-02 2:55 ` Florian Fainelli
-- strict thread matches above, loose matches on Subject: below --
2019-10-25 4:00 [PATCH 0/2] ARM: bcm: nsp: gpio improvements (hopefully) Chris Packham
2019-10-25 4:00 ` [PATCH 1/2] pinctrl: bcm: nsp: use gpiolib infrastructure for interrupts Chris Packham
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