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AJvYcCWcuHKI++iaoW+fi36BZlDeafWepZ0kl0KkL65d6iNv4s0XuTFubtQ9hme6i8tpCsBQWXSeeuli3Jx862bi17VjGevckVJzteIM5w== X-Gm-Message-State: AOJu0YzcUBrnR5jPpSes0xcyLRZ+MwsjdH0FCF5e6WPUnWMeMw7rg70h nMppSD6djbhOolJrJHQN8GBo+ZJP1PnQF4+WytvKenPofgK7EmKjx07sCV2x/r4= X-Google-Smtp-Source: AGHT+IEfucJcctzZC8UBvZQeq6f9QZjWkgL5lvSz0lZ62cuXHSgW+76tyPLaKHZwCKmq33V0C3VBOA== X-Received: by 2002:a05:600c:5250:b0:413:f3f0:c591 with SMTP id fc16-20020a05600c525000b00413f3f0c591mr1901771wmb.41.1711612882008; Thu, 28 Mar 2024 01:01:22 -0700 (PDT) Received: from [192.168.50.4] ([82.78.167.144]) by smtp.gmail.com with ESMTPSA id jg5-20020a05600ca00500b00414850d567fsm4609630wmb.1.2024.03.28.01.01.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Mar 2024 01:01:21 -0700 (PDT) Message-ID: Date: Thu, 28 Mar 2024 10:01:19 +0200 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 07/13] pinctrl: renesas: pinctrl-rzg2l: Validate power registers for SD and ETH Content-Language: en-US To: Prabhakar , Geert Uytterhoeven , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Fabrizio Castro , Lad Prabhakar References: <20240326222844.1422948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240326222844.1422948-8-prabhakar.mahadev-lad.rj@bp.renesas.com> From: claudiu beznea In-Reply-To: <20240326222844.1422948-8-prabhakar.mahadev-lad.rj@bp.renesas.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, Prabhakar, On 27.03.2024 00:28, Prabhakar wrote: > From: Lad Prabhakar > > On RZ/V2H(P) SoC, the power registers for SD and ETH do not exist, > resulting in invalid register offsets. Ensure that the register offsets > are valid before any read/write operations are performed. If the power > registers are not available, both SD and ETH will be set to -EINVAL. > > Signed-off-by: Lad Prabhakar > --- > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 16 ++++++++++------ > 1 file changed, 10 insertions(+), 6 deletions(-) > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > index 348fdccaff72..705372faaeff 100644 > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -184,8 +184,8 @@ > */ > struct rzg2l_register_offsets { > u16 pwpr; > - u16 sd_ch; > - u16 eth_poc; > + int sd_ch; > + int eth_poc; > }; > > /** > @@ -2567,8 +2567,10 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev) > rzg2l_pinctrl_pm_setup_dedicated_regs(pctrl, true); > > for (u8 i = 0; i < 2; i++) { > - cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); > - cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); > + if (regs->sd_ch != -EINVAL) As of my knowledge, the current users of this driver uses SD and ETH offsets different from zero. To avoid populating these values for all the SoCs and avoid increasing the size of these fields I think you can add checks like these: if (regs->sd_ch) // set sd_ch Same for the rest. > + cache->sd_ch[i] = readb(pctrl->base + SD_CH(regs->sd_ch, i)); > + if (regs->eth_poc != -EINVAL) > + cache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i)); > } > > cache->qspi = readb(pctrl->base + QSPI); > @@ -2599,8 +2601,10 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev) > writeb(cache->qspi, pctrl->base + QSPI); > writeb(cache->eth_mode, pctrl->base + ETH_MODE); > for (u8 i = 0; i < 2; i++) { > - writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); > - writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); > + if (regs->sd_ch != -EINVAL) > + writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); > + if (regs->eth_poc != -EINVAL) > + writeb(cache->eth_poc[i], pctrl->base + ETH_POC(regs->eth_poc, i)); > } > > rzg2l_pinctrl_pm_setup_pfc(pctrl);