From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF6B9146D4B; Fri, 3 May 2024 09:13:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714727595; cv=none; b=ZPcGbs5qqrSDumqzPc0HatnGC2f3xUxotCm/oulyIxN2iZxnpR/rJR5f2L8uwq3NI1lZvHr/4YphirWr80wlSe1n22tD0qzy3d3Tcz4MCpN2poXRq+urm6UBFd5q400KqXAz8qOan3JuMw6whjbNH9JwpRc4ESIM7FRqR0n8jN4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714727595; c=relaxed/simple; bh=3LaUaAv7CyMgsmPwhMzjeWmmLQOKPPAU1rg5+fLg16Y=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=Akz5aPQWVFLeH3C0yX62tyAlATK181UBEji1DFiEQZzk/G2xXonEZPKNg2C1ONVq+HNZjflc3HCE+/D7Zm2rEMC7msuKuF3ZcYLMGjCC0KiSIdyFaYHsdz7qlBHrw1KMtHx5EBpy+oxhMuuUBVdEbmmMheRGWIVRGXO/im43hZU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=X14Yt8iO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="X14Yt8iO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3C6B6C116B1; Fri, 3 May 2024 09:13:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1714727594; bh=3LaUaAv7CyMgsmPwhMzjeWmmLQOKPPAU1rg5+fLg16Y=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=X14Yt8iOniJkilrmKoZkCD67RtnmMu1YNUsyONG1snPV1Xl2iOjt5G/S9DDBkqhDE +oLAX5nuJ2lbJuEGOQrMsxSVlWclgAXvyouhYBOqERsC8trTUQrVNf2Hp1pyRA5NbP 15cwS8bOq57cZfaShsVHT9DoPy8EWK1REvCTtkV41JybZBF1PYKJJ9TT0OgM8G5fr2 octBJP4J3rV0uBoP6x6WaIolQcXWFYOXiR5g8gIwfGeBPg96F5L+vOLKWa2nBQN8/4 C0gM8lCFunDpmlEbheXfKT1e30qNKHZ1F68YMQeI1J4qwo0pFUtSREJ7PzjUer6gEJ xRS1eqReFgfZA== Message-ID: Date: Fri, 3 May 2024 11:13:06 +0200 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/2] pinctrl: samsung: support a bus clock To: =?UTF-8?Q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Sylwester Nawrocki , Alim Akhtar , Linus Walleij , Rob Herring , Conor Dooley , Tomasz Figa , Peter Griffin Cc: Will McVicker , Sam Protsenko , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20240426-samsung-pinctrl-busclock-v3-0-adb8664b8a7e@linaro.org> <20240426-samsung-pinctrl-busclock-v3-2-adb8664b8a7e@linaro.org> <9a960401-f41f-4902-bcbd-8f30f318ba98@kernel.org> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 02/05/2024 12:41, André Draszik wrote: > On Thu, 2024-05-02 at 09:46 +0200, Krzysztof Kozlowski wrote: >> On 02/05/2024 09:41, Tudor Ambarus wrote: >>>>   >>>> @@ -223,6 +268,13 @@ static void exynos_irq_release_resources(struct irq_data *irqd) >>>>   shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; >>>>   mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; >>>>   >>>> + if (clk_enable(bank->drvdata->pclk)) { >>>> + dev_err(bank->gpio_chip.parent, >>>> + "unable to enable clock for deconfiguring pin %s-%lu\n", >>>> + bank->name, irqd->hwirq); >>>> + return; >>> >>> but here we just print an error. I guess that for consistency reasons it >>> would be good to follow up with a patch and change the return types of >>> these methods and return the error too when the clock enable fails. >> >> That's a release, so usually void callback. The true issue is that we >> expect release to always succeed, I think. >> >> This points to issue with this patchset: looks like some patchwork all >> around the places having register accesses. But how do you even expect >> interrupts and pins to work if entire pinctrl block is clock gated? > > I was initially thinking the same, but the clock seems to be required for > register access only, interrupts are still being received and triggered > with pclk turned off as per my testing. Probably we could simplify this all and keep the clock enabled always, when device is not suspended. Toggling clock on/off for every pin change is also an overhead. Anyway, I merged the patches for now, because it addresses real problem and seems like one of reasonable solutions. Best regards, Krzysztof