From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB4FFC74A5B for ; Wed, 29 Mar 2023 13:21:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230197AbjC2NVr (ORCPT ); Wed, 29 Mar 2023 09:21:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230178AbjC2NVq (ORCPT ); Wed, 29 Mar 2023 09:21:46 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 31C8455AF; Wed, 29 Mar 2023 06:21:14 -0700 (PDT) Received: from [192.168.1.100] (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id DFC3A6603170; Wed, 29 Mar 2023 14:21:11 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1680096072; bh=yO91BroR7iHw7kVLw8m4fi1PudYWDnQ6vk8SsbYSshU=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=YoCN+EPxnJ2LoZ3B/sAG8QF+Lakg247Xt3coYx/2+BIt47HWOXApA2Z0N0pOA9q3G ablLIG5ZlD87/gqGYVmmMc/FDgqgmnwV6cSpZ+vJjNiZx83ZoVr+aL6i767zhhKt43 oRSy2x09fVLjPjpvE6JbUewtTivlvUeCKv1G7R3fJT0FV2yqAbFcaNaVdCt26bfVnQ glZGjmUbq7wO+nYWV2+Tztgf7DwrvZNissg8r3RlhOOyp4JwpmSDHSJ/WVQ5NqEL4V SzP6nMHusdf33ymqniBrHNBME6oRCfVY39NKZrEG7oEmOiUPi4GPmhIV/ClPaS80PK rdfRxYhcfXurg== Message-ID: Date: Wed, 29 Mar 2023 15:21:09 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH v3 08/17] arm64: dts: mediatek: add mmc support for mt8365 SoC Content-Language: en-US To: Alexandre Mergnat , Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Chaotian Jing , Ulf Hansson , Wenbin Mei , Linus Walleij , Zhiyong Tao , =?UTF-8?Q?Bernhard_Rosenkr=c3=a4nzer?= Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, Alexandre Bailon , Fabien Parent , Amjad Ouled-Ameur References: <20230203-evk-board-support-v3-0-0003e80e0095@baylibre.com> <20230203-evk-board-support-v3-8-0003e80e0095@baylibre.com> From: AngeloGioacchino Del Regno In-Reply-To: <20230203-evk-board-support-v3-8-0003e80e0095@baylibre.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Il 29/03/23 10:54, Alexandre Mergnat ha scritto: > There are three ports of MSDC (MMC and SD Controller), which are: > - MSDC0: EMMC5.1 > - MSDC1: SD3.0/SDIO3.0 > - MSDC2: SDIO3.0+ > > Signed-off-by: Alexandre Mergnat > --- > arch/arm64/boot/dts/mediatek/mt8365.dtsi | 39 ++++++++++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi > index 687011353f69..a67eeca28da5 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi > @@ -399,6 +399,45 @@ usb_host: usb@11200000 { > }; > }; > > + mmc0: mmc@11230000 { > + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; > + reg = <0 0x11230000 0 0x1000>, > + <0 0x11cd0000 0 0x1000>; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, > + <&infracfg CLK_IFR_MSDC0_HCLK>, > + <&infracfg CLK_IFR_MSDC0_SRC>; > + clock-names = "source", "hclk", "source_cg"; > + status = "disabled"; > + }; > + > + mmc1: mmc@11240000 { > + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; > + reg = <0 0x11240000 0 0x1000>, > + <0 0x11c90000 0 0x1000>; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, > + <&infracfg CLK_IFR_MSDC1_HCLK>, > + <&infracfg CLK_IFR_MSDC1_SRC>; > + clock-names = "source", "hclk", "source_cg"; > + status = "disabled"; > + }; > + > + mmc2: mmc@11250000 { > + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; > + reg = <0 0x11250000 0 0x1000>, > + <0 0x11c60000 0 0x1000>; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>, > + <&infracfg CLK_IFR_MSDC2_HCLK>, > + <&infracfg CLK_IFR_MSDC2_SRC>, > + <&infracfg CLK_IFR_MSDC2_BK>, > + <&infracfg CLK_IFR_AP_MSDC0>; > + clock-names = "source", "hclk", "source_cg", > + "bus_clk", "sys_cg"; clock-names for this do fit in one 90 columns line. After compressing it, Reviewed-by: AngeloGioacchino Del Regno