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([2600:100b:b034:8212:4cd5:c80f:ba72:80cb]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4a25722e3d8sm1005183fac.15.2026.10.06.17.57.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 06 Oct 2026 17:57:04 -0700 (PDT) Message-ID: Date: Tue, 6 Oct 2026 19:57:01 -0500 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] pinctrl: mediatek: common-v1: Use a raw spinlock for the pinctrl regmap To: Chen-Yu Tsai , Sebastian Andrzej Siewior Cc: Mark Brown , Lee Jones , Arnd Bergmann , Sean Wang , Linus Walleij , Matthias Brugger , AngeloGioacchino Del Regno , Bartosz Golaszewski , Clark Williams , Steven Rostedt , Yingjoe Chen , Chaotian Jing , Hongzhou Yang , linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rt-devel@lists.linux.dev, mfd@lists.linux.dev References: <20260929-rbrue-suez-upstreaming-mtk-pinctrl-raw-regmap-v1-1-db92943f42cb@gmail.com> <20260930080609.dnK1-Uta@linutronix.de> Content-Language: en-US From: Ryan Brue In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Chen-Yu and Sebastian, Thanks for looking at this. On 9/30/26 3:17 AM, Chen-Yu Tsai wrote: > The syscon node is the provider of the regmap. You need to fix it there, > not duplicate it in the consumer. Unless I'm misunderstanding, no driver binds to that node, so its regmap comes from the generic syscon code, and changing it there would affect every syscon. Lee, Arnd, Mark, would that be acceptable? These are the options I see. Please let me know if there's a better one: - Do what Sebastian suggested and make syscon use a raw spinlock, except when the node has a clock, since regmap-mmio calls clk_enable() under the lock. Off PREEMPT_RT, nothing changes. On RT the lock would no longer be preemptible for most syscons, including across bulk writes. Most syscon users that do bulk writes only write a few registers, but enabling the Amlogic G12A PCIe PLL writes a sequence with 40 us of udelay() under the lock. - Have the pinctrl ioremap() the node a second time alongside syscon's mapping and read the input register (DIN) with readl(). That read is the only access the EINT code makes in raw context. This would go around the syscon, and it requires that DIN never be written in a multi-step sequence, which is currently the case. I'd like to know the best approach before sending out a v2. Best regards, Ryan Brue