From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D354C433EF for ; Tue, 26 Jul 2022 07:42:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238426AbiGZHmM (ORCPT ); Tue, 26 Jul 2022 03:42:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238460AbiGZHl7 (ORCPT ); Tue, 26 Jul 2022 03:41:59 -0400 Received: from polaris.svanheule.net (polaris.svanheule.net [84.16.241.116]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9758F2AE26 for ; Tue, 26 Jul 2022 00:41:32 -0700 (PDT) Received: from vanadium.ugent.be (vanadium.ugent.be [157.193.99.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sander@svanheule.net) by polaris.svanheule.net (Postfix) with ESMTPSA id 6256A30119E; Tue, 26 Jul 2022 09:41:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=svanheule.net; s=mail1707; t=1658821290; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=x6mhpRVjeY02y9PKjADFibHQ+QplFQdFMkH4yzixOv8=; b=svLpUGvmOVh7MtkHNWW2Yl0XLrnw1OfUWUmrCq8RRZ5L0BASxUo3AEjuchoc8o/84gbT8X NdtDB7cYaKrNpETyPE/RnAt7tp2j9akhjM5RzfaRWDzw1ammbvJS0Ag8fHp1d5fwPG2SsG fKdhvfkGsC3/morICGPIYkDzZs7+vtYNEuj3GAX8oYOqTbfhWFlDJErexm1apOe23XAbDG XwkqSyt9qStSEf6NDL0H5baQLV8MG+anH+P4K+OWQfYu/18h9h+Rjo9XeS4afFFPBi1AVk +xlh0TsN0tte8XYyO0c7uJPCDRLUHhd5SpTTpMPkQQEnQv4UigwaeMgL9zsbmw== Message-ID: Subject: Re: [PATCH v2] gpio: realtek-otto: switch to 32-bit I/O From: Sander Vanheule To: linux-gpio@vger.kernel.org, Bartosz Golaszewski , Linus Walleij Cc: linux-kernel@vger.kernel.org, Andy Shevchenko , Luiz Angelo Daros de Luca , Birger Koblitz , Jan Hoffmann , Paul Cercueil Date: Tue, 26 Jul 2022 09:41:28 +0200 In-Reply-To: <20220724113141.51646-1-sander@svanheule.net> References: <20220724113141.51646-1-sander@svanheule.net> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.3 (3.44.3-1.fc36) MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Sun, 2022-07-24 at 13:31 +0200, Sander Vanheule wrote: > By using 16-bit I/O on the GPIO peripheral, which is apparently not safe > on MIPS, the IMR can end up containing garbage. This then results in > interrupt triggers for lines that don't have an interrupt source > associated. The irq_desc lookup fails, and the ISR will not be cleared, > keeping the CPU busy until reboot, or until another IMR operation > restores the correct value. This situation appears to happen very > rarely, for < 0.5% of IMR writes. >=20 > Instead of using 8-bit or 16-bit I/O operations on the 32-bit memory > mapped peripheral registers, switch to using 32-bit I/O only, operating > on the entire bank for all single bit line settings. For 2-bit line > settings, with 16-bit port values, stick to manual (un)packing. >=20 > This issue has been seen on RTL8382M (HPE 1920-16G), RTL8391M (Netgear > GS728TP v2), and RTL8393M (D-Link DGS-1210-52 F3, Zyxel GS1900-48). >=20 > Reported-by: Luiz Angelo Daros de Luca # DGS-1210-52 > Reported-by: Birger Koblitz # GS728TP > Reported-by: Jan Hoffmann # 1920-16G > Cc: Paul Cercueil > Signed-off-by: Sander Vanheule > --- ... > @@ -307,16 +308,17 @@ static int realtek_gpio_irq_set_affinity(struct irq= _data > *data, > =C2=A0static int realtek_gpio_irq_init(struct gpio_chip *gc) > =C2=A0{ > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0struct realtek_gpio_ctrl = *ctrl =3D gpiochip_get_data(gc); > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0unsigned int port; > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0u32 mask_all =3D GENMASK(gc->n= gpio, 0); This should be GENMASK(gc->ngpio - 1, 0). I'll wait a bit more for other comments before sending a v3. Best, Sander