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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-672c47fe8a0sm3291152a12.5.2026.04.22.06.08.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Apr 2026 06:08:42 -0700 (PDT) Message-ID: Date: Wed, 22 Apr 2026 15:08:38 +0200 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] arm64: dts: qcom: sm6350: add LPASS LPI pin controller To: Luca Weiss , Dmitry Baryshkov Cc: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla References: <20260128-sm6350-lpi-tlmm-v1-0-36583f2a2a2a@fairphone.com> <20260128-sm6350-lpi-tlmm-v1-4-36583f2a2a2a@fairphone.com> <91812db8-9774-468e-8a8b-10699a63310c@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIyMDEyNiBTYWx0ZWRfXwBb/B5n22dwk nEoQfwEgqKHTV9VWs1MA/se0Dan0CAeIdFTYbBK9XTfJsGKhmVWUx8YzA660b1NyeYopMWM7ER/ /jLOSg5BaJqheOo5LgQX96kEd39wabEUxl/Uh0cST6Z1WG+cgJSOTd/V3ogzpcApyxtOSNLu3K0 QLhWga3dkwisYUI2zAazjp9JX8bWW2dIwhF7lS8vBkTt8uFQYO+8Zh1+PiNJ5YGexyAVi3dE1Ix +i5XY6sMFCRtgseY2IE8vmDMODY7aUMXeNuNFDeg/Z187H+eU5WBRExhTkqUgEUOV4ydHoUcxQL 1b1Al38cPvpr3ZWYlG4NSuwdjcHWvyMGDAuUplVdZryC7uVrQUkFOo45rjWGTNflapiyScai57h UYi6zkWPPZ0CIWdw19C0awh9VO93wtkiV8RJhfpiFlkJw0ETN1AVKKgCaH714e5sVe6BtGf+kfV Kuh6S8KEdpoQa9G6ECA== X-Authority-Analysis: v=2.4 cv=VMrtWdPX c=1 sm=1 tr=0 ts=69e8c860 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=W6naqKN7AAAA:8 a=6H0WHjuAAAAA:8 a=EUspDBNiAAAA:8 a=WRoefMb1mtoobpndLnoA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=Xp8b5NkTPdl8jt_qJiRs:22 a=Soq9LBFxuPC4vsCAQt-j:22 X-Proofpoint-GUID: eD7ziyRF4wmjYc6GF8HyyHiKj2_gfMLb X-Proofpoint-ORIG-GUID: eD7ziyRF4wmjYc6GF8HyyHiKj2_gfMLb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-22_01,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 impostorscore=0 bulkscore=0 malwarescore=0 spamscore=0 phishscore=0 priorityscore=1501 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604220126 On 4/13/26 10:55 AM, Luca Weiss wrote: > Hi Konrad, > > On Thu Jan 29, 2026 at 12:19 PM CET, Konrad Dybcio wrote: >> On 1/29/26 9:32 AM, Luca Weiss wrote: >>> On Wed Jan 28, 2026 at 11:16 PM CET, Dmitry Baryshkov wrote: >>>> On Wed, Jan 28, 2026 at 01:26:52PM +0100, Luca Weiss wrote: >>>>> Add LPASS LPI pinctrl node required for audio functionality on SM6350. >>>>> >>>>> Signed-off-by: Luca Weiss >>>>> --- >>>>> arch/arm64/boot/dts/qcom/sm6350.dtsi | 66 ++++++++++++++++++++++++++++++++++++ >>>>> 1 file changed, 66 insertions(+) >>>>> >>>>> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi >>>>> index 9f9b9f9af0da..b1fb6c812da7 100644 >>>>> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi >>>>> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi >>>>> @@ -1448,6 +1448,72 @@ compute-cb@5 { >>>>> }; >>>>> }; >>>>> >>>>> + lpass_tlmm: pinctrl@33c0000 { >>>>> + compatible = "qcom,sm6350-lpass-lpi-pinctrl"; >>>>> + reg = <0x0 0x033c0000 0x0 0x20000>, >>>>> + <0x0 0x03550000 0x0 0x10000>; >>>>> + gpio-controller; >>>>> + #gpio-cells = <2>; >>>>> + gpio-ranges = <&lpass_tlmm 0 0 15>; >>>>> + >>>>> + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, >>>>> + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; >>>>> + clock-names = "core", >>>>> + "audio"; >>>>> + >>>>> + i2s1_active: i2s1-active-state { >>>>> + clk-pins { >>>>> + pins = "gpio6"; >>>>> + function = "i2s1_clk"; >>>>> + drive-strength = <8>; >>>>> + bias-disable; >>>>> + output-high; >>>> >>>> This looks suspicious for the clock pin. >>>> >>>>> + }; >>>>> + >>>>> + ws-pins { >>>>> + pins = "gpio7"; >>>>> + function = "i2s1_ws"; >>>>> + drive-strength = <8>; >>>>> + bias-disable; >>>>> + output-high; >>>> >>>> The same >>>> >>>>> + }; >>>>> + >>>>> + data-pins { >>>>> + pins = "gpio8", "gpio9"; >>>>> + function = "i2s1_data"; >>>>> + drive-strength = <8>; >>>>> + bias-disable; >>>>> + output-high; >>>> >>>> And here. >>> >>> I've taken this pinctrl from downstream lagoon-lpi.dtsi. There the >>> active config for these pins have "output-high;" set. >>> >>> And fwiw this pinctrl works fine at runtime for driving the speaker. >> >> I tried to find an answer. >> >> A doc for this SoC says that i2s clock pins should be at output-low >> (2 mA) when muxed to the i2s_xxx function, with no information about >> bias settings (perhaps bias-disable), and in sleep they should be the >> same (minus the drive strength note, but 2mA is the lowest setting) >> >> I am further confused because the output-enable bit in the cfg >> register specifically says "when in GPIO mode" > > Thanks for checking. > > What should we do here now? Follow what you found in the docs, or follow > what downstream is doing (8ma output-high)? > > https://gerrit-public.fairphone.software/plugins/gitiles/kernel/msm-extra/devicetree/+/refs/heads/int/15/fp4/qcom/lagoon-lpi.dtsi#219 > > I think apart from this question, this patchset should be ready to land. I think I'm OK with following downstream. If we make any discoveries wrt docs, we'll likely need a mass fixup anyway, so Reviewed-by: Konrad Dybcio adding +Srini for awareness Konrad