From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B91A639B4A9; Thu, 5 Mar 2026 12:44:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772714668; cv=none; b=rYCIaF0iWB2jJLB34MX8Leaij/+QFhcG4wk59dhb35BycVKNcIwCS+FKIHtYnq1heJswqdLza3FgR5Nlrd51e++Ew+ryR/7BYdtO2K/Tu5dw2oYqkZc8NdmwBseGocdxbjwTruii3YilqhYiQm4p2/UegYquLTXjfh4bcUgCgSc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772714668; c=relaxed/simple; bh=1w1RB447ldnhlv8Hxu9zjeDMNtNYv/NPl51WMASJdHA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=tGcSQVLaLf6PoU9KSijosV1RXLeVCHeDXSmeD8EPGnyu2VCi2urciYYPhYHp5PSDKWDwzr1VJi/Vb+OH6ZGtsjfbM49TS2TVW8wag2Nib2yJ3qns3e1XDyLgJqLkBtYzV5o5iQ1OHSS2zz5V0NNevmviXCrLrIjpEOjtrCKf+VU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LDxIZTHJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LDxIZTHJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3DB4FC116C6; Thu, 5 Mar 2026 12:44:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772714668; bh=1w1RB447ldnhlv8Hxu9zjeDMNtNYv/NPl51WMASJdHA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=LDxIZTHJ2mYAqUYUpM4rqzZqtOy9udLdU1nPT/u3StPVOAxHfd1HkkpzQVNBSMNCH tHAAbXHXvchUiXKghhZ/gTWDIczkMPjXTj5SXEg2l6KA5uZ9T7SNE2pTHnkOPGiC/N R+jvYfQZkT5R0zYOrUApdyIuMpJE2gaQKcjZiWS0aIapVW/Gl7pvBkItwBaJNBWaqY DspG8lnPxmxXQfJlwIaAI4BIe1+2wKsNdNXPNfblQVleHP6DcEQPVv0LznMOrZKC6L i1iJ3VLPsiU1NRIuHz9lNYrs/PLJjveniEzGFvjojTShf9jVCLI39Fudl1ICZ2sB7K 1RYQ3uYn/pX2A== Message-ID: Date: Thu, 5 Mar 2026 13:44:22 +0100 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] dt-bindings: iio: adc: add bindings for AD4691 family To: radu.sabau@analog.com, Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , David Lechner , =?UTF-8?Q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org References: <20260305-ad4692-multichannel-sar-adc-driver-v1-0-336229a8dcc7@analog.com> <20260305-ad4692-multichannel-sar-adc-driver-v1-1-336229a8dcc7@analog.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 05/03/2026 13:23, Radu Sabau via B4 Relay wrote: > From: Radu Sabau > > Add YAML bindings and dt-bindings header for the Analog Devices AD4691 There are no such thing as YAML bindings. DT bindings. > family of multichannel SAR ADCs (AD4691, AD4692, AD4693, AD4694). > > The binding describes five operating modes selectable via the No, describe the hardware, not binding. A nit, subject: drop second/last, redundant "bindings". The "dt-bindings" prefix is already stating that these are bindings. See also: https://elixir.bootlin.com/linux/v6.17-rc3/source/Documentation/devicetree/bindings/submitting-patches.rst#L18 > adi,spi-mode property, optional PWM/clock for CNV Clock and CNV Burst > modes, GPIO pins, voltage supplies and the trigger-source interface for > SPI Engine offload operation. > > Signed-off-by: Radu Sabau > --- > .../devicetree/bindings/iio/adc/adi,ad4691.yaml | 278 +++++++++++++++++++++ > MAINTAINERS | 8 + > include/dt-bindings/iio/adc/adi,ad4691.h | 13 + > 3 files changed, 299 insertions(+) > > diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml > new file mode 100644 > index 000000000000..b0d8036184b0 > --- /dev/null > +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml > @@ -0,0 +1,278 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/iio/adc/adi,ad4691.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Analog Devices AD4691 Family Multichannel SAR ADCs > + > +maintainers: > + - Radu Sabau > + > +description: | > + The AD4691 family are high-speed, low-power, multichannel successive > + approximation register (SAR) analog-to-digital converters (ADCs) with > + an SPI-compatible serial interface. The family supports multiple operating > + modes including CNV Clock Mode, CNV Burst Mode, Autonomous Mode, SPI Burst > + Mode, and Manual Mode. > + > + The driver supports both standard SPI and SPI Engine (offload) operation. Driver is irrelevant. If you change mode, you change bindings? > + > + Datasheets: > + * https://www.analog.com/en/products/ad4692.html > + * https://www.analog.com/en/products/ad4691.html > + * https://www.analog.com/en/products/ad4694.html > + * https://www.analog.com/en/products/ad4693.html > + > +$ref: /schemas/spi/spi-peripheral-props.yaml# > + > +properties: > + compatible: > + enum: > + - adi,ad4691 > + - adi,ad4692 > + - adi,ad4693 > + - adi,ad4694 > + > + reg: > + maxItems: 1 > + > + spi-max-frequency: > + maximum: 40000000 > + > + spi-cpol: true > + spi-cpha: true > + > + adi,spi-mode: > + $ref: /schemas/types.yaml#/definitions/uint32 Nope. You already have such property, so you cannot redefine it. Look at other sources. ... > + clocks: > + description: Reference clock for PWM timing in CNV Clock and CNV Burst modes. > + maxItems: 1 > + > + clock-names: Drop clock-names. Not useful if you call it just ref. > + items: > + - const: ref_clk > + > + pwms: > + description: > + PWM connected to the CNV pin. Required for CNV Clock Mode and CNV Burst > + Mode to control conversion timing. > + maxItems: 1 > + > + pwm-names: > + items: > + - const: cnv > + > + interrupts: > + description: > + Interrupt from the GP0 pin configured as DATA_READY or BUSY. Required > + for non-offload operation in all modes except Manual Mode (mode 4), > + where CNV is tied to CS and no DATA_READY signal is generated. > + maxItems: 1 > + > + interrupt-names: > + items: > + - const: DRDY Lowercase. Or actually drop names... > + > + '#trigger-source-cells': > + description: | > + For SPI Engine offload operation, this node acts as a trigger source. > + Two cells are required: > + - First cell: Trigger event type (0 = BUSY, 1 = DATA_READY) > + - Second cell: GPIO pin number (only 0 = GP0 is supported) > + > + Macros are available in dt-bindings/iio/adc/adi,ad4691.h: > + AD4691_TRIGGER_EVENT_BUSY, AD4691_TRIGGER_EVENT_DATA_READY > + AD4691_TRIGGER_PIN_GP0 > + const: 2 > + > +required: > + - compatible > + - reg > + - adi,spi-mode > + - vio-supply > + - reset-gpios > + > +allOf: > + # vref-supply and vrefin-supply are mutually exclusive, one is required > + - oneOf: > + - required: > + - vref-supply > + - required: > + - vrefin-supply > + > + # AD4694 (20-bit) does not support Manual Mode > + - if: > + properties: > + compatible: > + const: adi,ad4694 > + then: > + properties: > + adi,spi-mode: > + enum: [0, 1, 2, 3] > + > + # CNV Clock Mode and CNV Burst Mode require PWM and clock > + - if: > + properties: > + adi,spi-mode: > + enum: [0, 1] > + then: > + required: > + - clocks > + - clock-names > + - pwms > + - pwm-names > + > + # Non-Manual modes (0-3) without SPI offload require a DRDY interrupt. > + # Offload configurations expose '#trigger-source-cells' instead. > + - if: > + properties: > + adi,spi-mode: > + enum: [0, 1, 2, 3] > + not: > + required: > + - '#trigger-source-cells' > + then: > + required: > + - interrupts > + - interrupt-names > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + > + /* Example: AD4692 in CNV Clock Mode with standard SPI */ > + spi { > + #address-cells = <1>; > + #size-cells = <0>; > + > + adc@0 { > + compatible = "adi,ad4692"; > + reg = <0>; > + spi-cpol; > + spi-cpha; > + spi-max-frequency = <40000000>; > + > + adi,spi-mode = <0>; /* CNV Clock Mode */ > + > + vio-supply = <&vio_supply>; > + vref-supply = <&vref_5v>; > + > + reset-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; > + gp0-gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; > + > + clocks = <&ref_clk>; > + clock-names = "ref_clk"; > + > + pwms = <&pwm_gen 0 0>; > + pwm-names = "cnv"; > + > + interrupts = <12 4>; > + interrupt-names = "DRDY"; > + }; > + }; > + > + - | > + #include > + #include > + > + /* Example: AD4692 in Manual Mode with SPI Engine offload */ > + spi { > + #address-cells = <1>; > + #size-cells = <0>; > + > + adc@0 { > + compatible = "adi,ad4692"; > + reg = <0>; > + spi-cpol; > + spi-cpha; > + spi-max-frequency = <31250000>; > + > + adi,spi-mode = <4>; /* Manual Mode */ > + > + vio-supply = <&vio_supply>; > + vrefin-supply = <&vrefin_supply>; > + > + reset-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; > + }; > + }; > + > + - | > + #include > + #include Where do you use the header? Anyway, drop example, two are enough. Best regards, Krzysztof