[PATCH 00/22] arm64: qcom: Introduce SA8255p Ride platform

[PATCH 00/22] arm64: qcom: Introduce SA8255p Ride platform

[Nikunj Kela]

This series enables the support for SA8255p Qualcomm SoC and Ride
platform. This platform uses SCMI power, reset, performance, sensor
protocols for resources(e.g. clocks, regulator, interconnect, phy etc.)
management. SA8255p is a virtual platforms that uses Qualcomm smc/hvc
transport driver.

Multiple virtual SCMI instances are being used to achieve the parallelism.
SCMI platform stack runs in SMP enabled VM hence allows platform to service
multiple resource requests in parallel. Each device is assigned its own
dedicated SCMI channel and Tx/Rx doorbells.

Resource operations are grouped together to achieve better abstraction
and to reduce the number of requests being sent to SCMI platform(server)
thus improving boot time KPIs. This design approach was presented during
LinaroConnect 2024 conference[1].

Architecture:
------------
                                                          +--------------------+
                                                          |   Shared Memory    |
                                                          |                    |
                                                          | +----------------+ |                +----------------------------------+
     +----------------------------+                     +-+->  ufs-shmem     <-+---+            |            Linux VM              |
     |        Firmware VM         |                     | | +----------------+ |   |            |   +----------+   +----------+    |
     |                            |                     | |                    |   |            |   |   UFS    |   |   PCIe   |    |
     | +---------+ f +----------+ |                     | |                    |   |            |   |  Driver  |   |  Driver  |    |
     | |Drivers  <---+  SCMI    | |        e            | |         |          |   |            |   +--+----^--+   +----------+    |
     | | (clks,  | g | Server   +-+---------------------+ |                    |   |            |      |    |                      |
     | |  vreg,  +--->          | |        h              |         |          |  b|k           |     a|   l|                      |
     | |  gpio,  |   +--^-----+-+ |                       |                    |   |            |      |    |                      |
     | |  phy,   |      |     |   |                       |         |          |   |            |  +---v----+----+  +----------+   |
     | |  etc.)  |      |     |   |                       |                    |   +------------+--+  UFS SCMI   |  | PCIe SCMI|   |
     | +---------+      |     |   |                       |                    |                |  |  INSTANCE   |  | INSTANCE |   |
     |                  |     |   |                       |  +---------------+ |                |  +-^-----+-----+  +----------+   |
     |                  |     |   |                       |  |  pcie-shmem   | |                |    |     |                       |
     +------------------+-----+---+                       |  +---------------+ |                +----+-----+-----------------------+
                        |     |                           |                    |                     |     |
                        |     |                           +--------------------+                     |     |
                       d|IRQ i|HVC                                                                  j|IRQ c|HVC
                        |     |                                                                      |     |
                        |     |                                                                      |     |
+-----------------------+-----v----------------------------------------------------------------------+-----v------------------------------+
|                                                                                                                                         |
|                                                                                                                                         |
|                                                                                                                                         |
|                                                               HYPERVISOR                                                                |
|                                                                                                                                         |
|                                                                                                                                         |
+-----------------------------------------------------------------------------------------------------------------------------------------+

        +--------+   +--------+                                                                         +----------+  +-----------+
        | CLOCK  |   |  PHY   |                                                                         |   UFS    |  |   PCIe    |
        +--------+   +--------+                                                                         +----------+  +-----------+


This series is based on next-20240828.

[1]: https://resources.linaro.org/en/resource/wfnfEwBhRjLV1PEAJoDDte

Nikunj Kela (22):
  dt-bindings: arm: qcom: add the SoC ID for SA8255P
  soc: qcom: socinfo: add support for SA8255P
  dt-bindings: arm: qcom: add SA8255p Ride board
  dt-bindings: firmware: qcom,scm: document support for SA8255p
  dt-bindings: mailbox: qcom-ipcc: document the support for SA8255p
  dt-bindings: watchdog: qcom-wdt: document support on SA8255p
  dt-bindings: crypto: qcom,prng: document support for SA8255p
  dt-bindings: interrupt-controller: qcom-pdc: document support for
    SA8255p
  dt-bindings: soc: qcom: aoss-qmp: document support for SA8255p
  dt-bindings: pinctrl: document support for SA8255p
  pinctrl: qcom: sa8775p: Add support for SA8255p SoC
  dt-bindings: cpufreq: qcom-hw: document support for SA8255p
  dt-bindings: thermal: tsens: document support on SA8255p
  dt-bindings: arm-smmu: document the support on SA8255p
  dt-bindings: mfd: qcom,tcsr: document support for SA8255p
  dt-bindings: qcom: geni-se: document support for SA8255P
  dt-bindings: serial: document support for SA8255p
  dt-bindings: spi: document support for SA8255p
  dt-bindings: i2c: document support for SA8255p
  dt-bindings: firmware: arm,scmi: allow multiple virtual instances
  ARM: dt: GIC: add extended SPI specifier
  arm64: dts: qcom: Add reduced functional DT for SA8255p Ride platform

 .../devicetree/bindings/arm/qcom.yaml         |    6 +
 .../bindings/cpufreq/cpufreq-qcom-hw.yaml     |    1 +
 .../devicetree/bindings/crypto/qcom,prng.yaml |    1 +
 .../bindings/firmware/arm,scmi.yaml           |    2 +-
 .../bindings/firmware/qcom,scm.yaml           |    2 +
 .../bindings/i2c/qcom,i2c-geni-qcom.yaml      |   56 +-
 .../interrupt-controller/qcom,pdc.yaml        |    1 +
 .../devicetree/bindings/iommu/arm,smmu.yaml   |    3 +
 .../bindings/mailbox/qcom-ipcc.yaml           |    1 +
 .../devicetree/bindings/mfd/qcom,tcsr.yaml    |    1 +
 .../bindings/pinctrl/qcom,sa8775p-tlmm.yaml   |    4 +-
 .../serial/qcom,serial-geni-qcom.yaml         |   58 +-
 .../bindings/soc/qcom/qcom,aoss-qmp.yaml      |    1 +
 .../bindings/soc/qcom/qcom,geni-se.yaml       |   47 +-
 .../bindings/spi/qcom,spi-geni-qcom.yaml      |   64 +-
 .../bindings/thermal/qcom-tsens.yaml          |    1 +
 .../bindings/watchdog/qcom-wdt.yaml           |    1 +
 arch/arm64/boot/dts/qcom/Makefile             |    1 +
 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi   |   80 +
 arch/arm64/boot/dts/qcom/sa8255p-ride.dts     |  149 +
 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi    | 2312 ++++++++++++++++
 arch/arm64/boot/dts/qcom/sa8255p.dtsi         | 2405 +++++++++++++++++
 drivers/pinctrl/qcom/pinctrl-sa8775p.c        |    1 +
 drivers/soc/qcom/socinfo.c                    |    1 +
 include/dt-bindings/arm/qcom,ids.h            |    1 +
 .../interrupt-controller/arm-gic.h            |    1 +
 26 files changed, 5157 insertions(+), 44 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi


base-commit: 195a402a75791e6e0d96d9da27ca77671bc656a8
-- 
2.34.1

[PATCH 01/22] dt-bindings: arm: qcom: add the SoC ID for SA8255P

[Nikunj Kela]

Add the SoC ID entry for SA8255P.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 include/dt-bindings/arm/qcom,ids.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
index 8332f8d82f96..16f00ecdcc09 100644
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -257,6 +257,7 @@
 #define QCOM_ID_QRB2210			524
 #define QCOM_ID_SM8475			530
 #define QCOM_ID_SM8475P			531
+#define QCOM_ID_SA8255P			532
 #define QCOM_ID_SA8775P			534
 #define QCOM_ID_QRU1000			539
 #define QCOM_ID_SM8475_2		540
-- 
2.34.1

Re: [PATCH 01/22] dt-bindings: arm: qcom: add the SoC ID for SA8255P

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:00PM -0700, Nikunj Kela wrote:
> Add the SoC ID entry for SA8255P.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  include/dt-bindings/arm/qcom,ids.h | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 02/22] soc: qcom: socinfo: add support for SA8255P

[Nikunj Kela]

Add SocInfo support for SA8255P.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 drivers/soc/qcom/socinfo.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
index 24c3971f2ef1..5c3bd59eaa69 100644
--- a/drivers/soc/qcom/socinfo.c
+++ b/drivers/soc/qcom/socinfo.c
@@ -424,6 +424,7 @@ static const struct soc_id soc_id[] = {
 	{ qcom_board_id(QRB2210) },
 	{ qcom_board_id(SM8475) },
 	{ qcom_board_id(SM8475P) },
+	{ qcom_board_id(SA8255P) },
 	{ qcom_board_id(SA8775P) },
 	{ qcom_board_id(QRU1000) },
 	{ qcom_board_id(SM8475_2) },
-- 
2.34.1

Re: [PATCH 02/22] soc: qcom: socinfo: add support for SA8255P

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:01PM -0700, Nikunj Kela wrote:
> Add SocInfo support for SA8255P.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  drivers/soc/qcom/socinfo.c | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 03/22] dt-bindings: arm: qcom: add SA8255p Ride board

[Nikunj Kela]

Document the SA8255p SoC and its reference board: sa8255p-ride.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index c0529486810f..d8d12ad073ba 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -50,6 +50,7 @@ description: |
         qrb4210
         qru1000
         sa8155p
+        sa8255p
         sa8540p
         sa8775p
         sc7180
@@ -900,6 +901,11 @@ properties:
               - qcom,sa8155p-adp
           - const: qcom,sa8155p
 
+      - items:
+          - enum:
+              - qcom,sa8255p-ride
+          - const: qcom,sa8255p
+
       - items:
           - enum:
               - qcom,sa8295p-adp
-- 
2.34.1

Re: [PATCH 03/22] dt-bindings: arm: qcom: add SA8255p Ride board

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:02PM -0700, Nikunj Kela wrote:
> Document the SA8255p SoC and its reference board: sa8255p-ride.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 04/22] dt-bindings: firmware: qcom,scm: document support for SA8255p

[Nikunj Kela]

Add a compatible for the SA8255p platform's Secure Channel Manager
firmware interface.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
index 2cc83771d8e7..65057f5c8972 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
@@ -43,6 +43,7 @@ properties:
           - qcom,scm-msm8998
           - qcom,scm-qcm2290
           - qcom,scm-qdu1000
+          - qcom,scm-sa8255p
           - qcom,scm-sa8775p
           - qcom,scm-sc7180
           - qcom,scm-sc7280
@@ -204,6 +205,7 @@ allOf:
           compatible:
             contains:
               enum:
+                - qcom,scm-sa8255p
                 - qcom,scm-sa8775p
     then:
       properties:
-- 
2.34.1

Re: [PATCH 04/22] dt-bindings: firmware: qcom,scm: document support for SA8255p

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:03PM -0700, Nikunj Kela wrote:
> Add a compatible for the SA8255p platform's Secure Channel Manager
> firmware interface.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 2 ++
>  1 file changed, 2 insertions(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 05/22] dt-bindings: mailbox: qcom-ipcc: document the support for SA8255p

[Nikunj Kela]

Add a compatible for the ipcc on SA8255p platforms.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
index 05e4e1d51713..bc108b8db9f4 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
@@ -25,6 +25,7 @@ properties:
     items:
       - enum:
           - qcom,qdu1000-ipcc
+          - qcom,sa8255p-ipcc
           - qcom,sa8775p-ipcc
           - qcom,sc7280-ipcc
           - qcom,sc8280xp-ipcc
-- 
2.34.1

Re: [PATCH 05/22] dt-bindings: mailbox: qcom-ipcc: document the support for SA8255p

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:04PM -0700, Nikunj Kela wrote:
> Add a compatible for the ipcc on SA8255p platforms.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 06/22] dt-bindings: watchdog: qcom-wdt: document support on SA8255p

[Nikunj Kela]

Add a compatible for the SA8255p platform's KPSS watchdog.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
index 47587971fb0b..932393f8c649 100644
--- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
@@ -26,6 +26,7 @@ properties:
               - qcom,apss-wdt-msm8994
               - qcom,apss-wdt-qcm2290
               - qcom,apss-wdt-qcs404
+              - qcom,apss-wdt-sa8255p
               - qcom,apss-wdt-sa8775p
               - qcom,apss-wdt-sc7180
               - qcom,apss-wdt-sc7280
-- 
2.34.1

Re: [PATCH 06/22] dt-bindings: watchdog: qcom-wdt: document support on SA8255p

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:05PM -0700, Nikunj Kela wrote:
> Add a compatible for the SA8255p platform's KPSS watchdog.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 07/22] dt-bindings: crypto: qcom,prng: document support for SA8255p

[Nikunj Kela]

Document SA8255p compatible for the True Random Number Generator.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
index 89c88004b41b..048b769a73c0 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
@@ -17,6 +17,7 @@ properties:
           - qcom,prng-ee  # 8996 and later using EE
       - items:
           - enum:
+              - qcom,sa8255p-trng
               - qcom,sa8775p-trng
               - qcom,sc7280-trng
               - qcom,sm8450-trng
-- 
2.34.1

Re: [PATCH 07/22] dt-bindings: crypto: qcom,prng: document support for SA8255p

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:06PM -0700, Nikunj Kela wrote:
> Document SA8255p compatible for the True Random Number Generator.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 08/22] dt-bindings: interrupt-controller: qcom-pdc: document support for SA8255p

[Nikunj Kela]

Add compatible for pdc interrupt controller representing support on
SA8255p.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
index 985fa10abb99..b1ea08a41bb0 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
@@ -27,6 +27,7 @@ properties:
     items:
       - enum:
           - qcom,qdu1000-pdc
+          - qcom,sa8255p-pdc
           - qcom,sa8775p-pdc
           - qcom,sc7180-pdc
           - qcom,sc7280-pdc
-- 
2.34.1

Re: [PATCH 08/22] dt-bindings: interrupt-controller: qcom-pdc: document support for SA8255p

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:07PM -0700, Nikunj Kela wrote:
> Add compatible for pdc interrupt controller representing support on
> SA8255p.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml       | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 09/22] dt-bindings: soc: qcom: aoss-qmp: document support for SA8255p

[Nikunj Kela]

Add compatible for AOSS QMP representing support on SA8255p.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
index 7afdb60edb22..bd873e7e4ae5 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
@@ -26,6 +26,7 @@ properties:
     items:
       - enum:
           - qcom,qdu1000-aoss-qmp
+          - qcom,sa8255p-aoss-qmp
           - qcom,sa8775p-aoss-qmp
           - qcom,sc7180-aoss-qmp
           - qcom,sc7280-aoss-qmp
-- 
2.34.1

Re: [PATCH 09/22] dt-bindings: soc: qcom: aoss-qmp: document support for SA8255p

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:08PM -0700, Nikunj Kela wrote:
> Add compatible for AOSS QMP representing support on SA8255p.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 10/22] dt-bindings: pinctrl: document support for SA8255p

[Nikunj Kela]

Add compatible for pincontrol representing support on SA8255p.

SA8255p uses the same TLMM block as SA8775p however the ownership
of pins are split between Firmware VM and Linux VM on SA8255p. For
example, pins used by UART are owned and configured by Firmware VM
while pins used by ethernet are owned and configured by Linux VM.
Therefore, adding a sa8255p specific compatible to mark the difference.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 .../devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml        | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml
index e9abbf2c0689..0d712153f9d7 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml
@@ -17,7 +17,9 @@ allOf:
 
 properties:
   compatible:
-    const: qcom,sa8775p-tlmm
+    enum:
+      - qcom,sa8255p-tlmm
+      - qcom,sa8775p-tlmm
 
   reg:
     maxItems: 1
-- 
2.34.1

Re: [PATCH 10/22] dt-bindings: pinctrl: document support for SA8255p

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:09PM -0700, Nikunj Kela wrote:
> Add compatible for pincontrol representing support on SA8255p.
> 
> SA8255p uses the same TLMM block as SA8775p however the ownership
> of pins are split between Firmware VM and Linux VM on SA8255p. For
> example, pins used by UART are owned and configured by Firmware VM
> while pins used by ethernet are owned and configured by Linux VM.
> Therefore, adding a sa8255p specific compatible to mark the difference.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---

Explanation does not match driver (discussion in the driver).

Best regards,
Krzysztof

[PATCH 11/22] pinctrl: qcom: sa8775p: Add support for SA8255p SoC

[Nikunj Kela]

SA8255p platform uses the same TLMM block as used in SA8775p,
though the pins are split between Firmware VM and Linux VM.
let's add SA8255p specific compatible.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 drivers/pinctrl/qcom/pinctrl-sa8775p.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c
index 5459c0c681a2..9a48abdf9b71 100644
--- a/drivers/pinctrl/qcom/pinctrl-sa8775p.c
+++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c
@@ -1519,6 +1519,7 @@ static int sa8775p_pinctrl_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id sa8775p_pinctrl_of_match[] = {
+	{ .compatible = "qcom,sa8255p-tlmm", },
 	{ .compatible = "qcom,sa8775p-tlmm", },
 	{ },
 };
-- 
2.34.1

Re: [PATCH 11/22] pinctrl: qcom: sa8775p: Add support for SA8255p SoC

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:10PM -0700, Nikunj Kela wrote:
> SA8255p platform uses the same TLMM block as used in SA8775p,
> though the pins are split between Firmware VM and Linux VM.
> let's add SA8255p specific compatible.

The change suggests devices are fully compatible, but above description
does not.

This looks conflicting.

Best regards,
Krzysztof

Re: [PATCH 11/22] pinctrl: qcom: sa8775p: Add support for SA8255p SoC

[Nikunj Kela]

On 8/29/2024 12:29 AM, Krzysztof Kozlowski wrote:
> On Wed, Aug 28, 2024 at 01:37:10PM -0700, Nikunj Kela wrote:
>> SA8255p platform uses the same TLMM block as used in SA8775p,
>> though the pins are split between Firmware VM and Linux VM.
>> let's add SA8255p specific compatible.
> The change suggests devices are fully compatible, but above description
> does not.
>
> This looks conflicting.
>
> Best regards,
> Krzysztof

Hi Krzysztof,

Thanks for reviewing patches. TLMM HW block is exactly same as used in
SA8775p however ownership of pins can be split between firmware VM and
Linux VM. It is upto devices to decide what pins they want to use in
what VM. I will extend the subject with same description as used in DT
binding.

Regards,

-Nikunj

Re: [PATCH 11/22] pinctrl: qcom: sa8775p: Add support for SA8255p SoC

[Krzysztof Kozlowski]

On 29/08/2024 16:17, Nikunj Kela wrote:
> 
> On 8/29/2024 12:29 AM, Krzysztof Kozlowski wrote:
>> On Wed, Aug 28, 2024 at 01:37:10PM -0700, Nikunj Kela wrote:
>>> SA8255p platform uses the same TLMM block as used in SA8775p,
>>> though the pins are split between Firmware VM and Linux VM.
>>> let's add SA8255p specific compatible.
>> The change suggests devices are fully compatible, but above description
>> does not.
>>
>> This looks conflicting.
>>
>> Best regards,
>> Krzysztof
> 
> Hi Krzysztof,
> 
> Thanks for reviewing patches. TLMM HW block is exactly same as used in
> SA8775p however ownership of pins can be split between firmware VM and
> Linux VM. It is upto devices to decide what pins they want to use in
> what VM. I will extend the subject with same description as used in DT
> binding.

So there is no difference? Then devices should be made compatible with
fallback.

Best regards,
Krzysztof

Re: [PATCH 11/22] pinctrl: qcom: sa8775p: Add support for SA8255p SoC

[Nikunj Kela]

On 8/30/2024 2:52 AM, Krzysztof Kozlowski wrote:
> On 29/08/2024 16:17, Nikunj Kela wrote:
>> On 8/29/2024 12:29 AM, Krzysztof Kozlowski wrote:
>>> On Wed, Aug 28, 2024 at 01:37:10PM -0700, Nikunj Kela wrote:
>>>> SA8255p platform uses the same TLMM block as used in SA8775p,
>>>> though the pins are split between Firmware VM and Linux VM.
>>>> let's add SA8255p specific compatible.
>>> The change suggests devices are fully compatible, but above description
>>> does not.
>>>
>>> This looks conflicting.
>>>
>>> Best regards,
>>> Krzysztof
>> Hi Krzysztof,
>>
>> Thanks for reviewing patches. TLMM HW block is exactly same as used in
>> SA8775p however ownership of pins can be split between firmware VM and
>> Linux VM. It is upto devices to decide what pins they want to use in
>> what VM. I will extend the subject with same description as used in DT
>> binding.
> So there is no difference? Then devices should be made compatible with
> fallback.
>
> Best regards,
> Krzysztof

Yes, I get your point now. I will discuss internally. I am leaning
towards using sa8775p-tlmm compatible in SA8255p TLMM node so there is
no need for adding new compatible. Will drop the two pincontrol related
patches from the series in next version if agreed internally.

Thanks,

-Nikunj

Re: [PATCH 11/22] pinctrl: qcom: sa8775p: Add support for SA8255p SoC

[Krzysztof Kozlowski]

On 03/09/2024 17:24, Nikunj Kela wrote:
> 
> On 8/30/2024 2:52 AM, Krzysztof Kozlowski wrote:
>> On 29/08/2024 16:17, Nikunj Kela wrote:
>>> On 8/29/2024 12:29 AM, Krzysztof Kozlowski wrote:
>>>> On Wed, Aug 28, 2024 at 01:37:10PM -0700, Nikunj Kela wrote:
>>>>> SA8255p platform uses the same TLMM block as used in SA8775p,
>>>>> though the pins are split between Firmware VM and Linux VM.
>>>>> let's add SA8255p specific compatible.
>>>> The change suggests devices are fully compatible, but above description
>>>> does not.
>>>>
>>>> This looks conflicting.
>>>>
>>>> Best regards,
>>>> Krzysztof
>>> Hi Krzysztof,
>>>
>>> Thanks for reviewing patches. TLMM HW block is exactly same as used in
>>> SA8775p however ownership of pins can be split between firmware VM and
>>> Linux VM. It is upto devices to decide what pins they want to use in
>>> what VM. I will extend the subject with same description as used in DT
>>> binding.
>> So there is no difference? Then devices should be made compatible with
>> fallback.
>>
>> Best regards,
>> Krzysztof
> 
> Yes, I get your point now. I will discuss internally. I am leaning
> towards using sa8775p-tlmm compatible in SA8255p TLMM node so there is
> no need for adding new compatible. Will drop the two pincontrol related
> patches from the series in next version if agreed internally.
> 

You need compatible followed by fallback (and therefore drop driver
change). That's how compatibility is expressed.


Best regards,
Krzysztof

[PATCH 12/22] dt-bindings: cpufreq: qcom-hw: document support for SA8255p

[Nikunj Kela]

Add compatible for the cpufreq engine representing support on SA8255p.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
index 1e9797f96410..71f6168f6d48 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
@@ -34,6 +34,7 @@ properties:
         items:
           - enum:
               - qcom,qdu1000-cpufreq-epss
+              - qcom,sa8255p-cpufreq-epss
               - qcom,sa8775p-cpufreq-epss
               - qcom,sc7280-cpufreq-epss
               - qcom,sc8280xp-cpufreq-epss
-- 
2.34.1

Re: [PATCH 12/22] dt-bindings: cpufreq: qcom-hw: document support for SA8255p

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:11PM -0700, Nikunj Kela wrote:
> Add compatible for the cpufreq engine representing support on SA8255p.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 1 +
>  1 file changed, 1 insertion(+)
>

You need to update allOf:if:then section.

Best regards,
Krzysztof

[PATCH 13/22] dt-bindings: thermal: tsens: document support on SA8255p

[Nikunj Kela]

Add compatible for sensors representing support on SA8255p.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
index 72048c5a0412..d45690d6a465 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
@@ -51,6 +51,7 @@ properties:
               - qcom,msm8996-tsens
               - qcom,msm8998-tsens
               - qcom,qcm2290-tsens
+              - qcom,sa8255p-tsens
               - qcom,sa8775p-tsens
               - qcom,sc7180-tsens
               - qcom,sc7280-tsens
-- 
2.34.1

Re: [PATCH 13/22] dt-bindings: thermal: tsens: document support on SA8255p

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:12PM -0700, Nikunj Kela wrote:
> Add compatible for sensors representing support on SA8255p.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 13/22] dt-bindings: thermal: tsens: document support on SA8255p

[Daniel Lezcano]

On 28/08/2024 22:37, Nikunj Kela wrote:
> Add compatible for sensors representing support on SA8255p.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---

Applied, thanks

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[PATCH 14/22] dt-bindings: arm-smmu: document the support on SA8255p

[Nikunj Kela]

Add compatible for smmu representing support on SA8255p.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index 280b4e49f219..3353c2d37841 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -37,6 +37,7 @@ properties:
           - enum:
               - qcom,qcm2290-smmu-500
               - qcom,qdu1000-smmu-500
+              - qcom,sa8255p-smmu-500
               - qcom,sa8775p-smmu-500
               - qcom,sc7180-smmu-500
               - qcom,sc7280-smmu-500
@@ -84,6 +85,7 @@ properties:
         items:
           - enum:
               - qcom,qcm2290-smmu-500
+              - qcom,sa8255p-smmu-500
               - qcom,sa8775p-smmu-500
               - qcom,sc7280-smmu-500
               - qcom,sc8180x-smmu-500
@@ -553,6 +555,7 @@ allOf:
               - marvell,ap806-smmu-500
               - nvidia,smmu-500
               - qcom,qdu1000-smmu-500
+              - qcom,sa8255p-smmu-500
               - qcom,sc7180-smmu-500
               - qcom,sdm670-smmu-500
               - qcom,sdm845-smmu-500
-- 
2.34.1

Re: [PATCH 14/22] dt-bindings: arm-smmu: document the support on SA8255p

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:13PM -0700, Nikunj Kela wrote:
> Add compatible for smmu representing support on SA8255p.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
>  1 file changed, 3 insertions(+)
> 

Your subjects contain quite redundant/excessive information. In the same
time they lack information about device. 

1. s/document the support on/add/
2. s/SA8255p/SA8255p SMMU-or-whatever-device-it-is/

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 14/22] dt-bindings: arm-smmu: document the support on SA8255p

[Nikunj Kela]

On 8/29/2024 12:36 AM, Krzysztof Kozlowski wrote:
> On Wed, Aug 28, 2024 at 01:37:13PM -0700, Nikunj Kela wrote:
>> Add compatible for smmu representing support on SA8255p.
>>
>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>> ---
>>  Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
>>  1 file changed, 3 insertions(+)
>>
> Your subjects contain quite redundant/excessive information. In the same
> time they lack information about device. 
>
> 1. s/document the support on/add/
> 2. s/SA8255p/SA8255p SMMU-or-whatever-device-it-is/
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> Best regards,
> Krzysztof

Okay. I thought arm-smmu tag already indicate which device this patch is
for but would put SMMU explicitly in the subject.

Thanks,

-Nikunj

Re: [PATCH 14/22] dt-bindings: arm-smmu: document the support on SA8255p

[Krzysztof Kozlowski]

On 29/08/2024 17:39, Nikunj Kela wrote:
> 
> On 8/29/2024 12:36 AM, Krzysztof Kozlowski wrote:
>> On Wed, Aug 28, 2024 at 01:37:13PM -0700, Nikunj Kela wrote:
>>> Add compatible for smmu representing support on SA8255p.
>>>
>>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>>> ---
>>>  Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
>>>  1 file changed, 3 insertions(+)
>>>
>> Your subjects contain quite redundant/excessive information. In the same
>> time they lack information about device. 
>>
>> 1. s/document the support on/add/
>> 2. s/SA8255p/SA8255p SMMU-or-whatever-device-it-is/
>>
>> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>>
>> Best regards,
>> Krzysztof
> 
> Okay. I thought arm-smmu tag already indicate which device this patch is
> for but would put SMMU explicitly in the subject.

arm,smmu indicates the binding file which might be or might not exactly
be the same as actual device. Sometimes they have difference names. I am
not saying that it would be beneficial here, but some other patches
could benefit probably.

Best regards,
Krzysztof

[PATCH 15/22] dt-bindings: mfd: qcom,tcsr: document support for SA8255p

[Nikunj Kela]

Add compatible for tcsr representing support on SA8255p SoC.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
index c6bd14ec5aa0..88f804bd7581 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
@@ -21,6 +21,7 @@ properties:
           - qcom,msm8998-tcsr
           - qcom,qcm2290-tcsr
           - qcom,qcs404-tcsr
+          - qcom,sa8255p-tcsr
           - qcom,sc7180-tcsr
           - qcom,sc7280-tcsr
           - qcom,sc8280xp-tcsr
-- 
2.34.1

Re: [PATCH 15/22] dt-bindings: mfd: qcom,tcsr: document support for SA8255p

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:14PM -0700, Nikunj Kela wrote:
> Add compatible for tcsr representing support on SA8255p SoC.
> 
> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 +

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH 16/22] dt-bindings: qcom: geni-se: document support for SA8255P

[Nikunj Kela]

Add "qcom,sa8255p-geni-se-qup" compatible for representing QUP on
SA8255p.

Clocks are being managed by the firmware VM and not required on
SA8255p Linux VM hence removing it from required list.

CC: Praveen Talari <quic_ptalari@quicinc.com>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 .../bindings/soc/qcom/qcom,geni-se.yaml       | 47 +++++++++++++++++--
 1 file changed, 43 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
index 7b031ef09669..40e3a3e045da 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
@@ -22,17 +22,16 @@ properties:
     enum:
       - qcom,geni-se-qup
       - qcom,geni-se-i2c-master-hub
+      - qcom,sa8255p-geni-se-qup
 
   reg:
     description: QUP wrapper common register address and length.
     maxItems: 1
 
   clock-names:
-    minItems: 1
     maxItems: 2
 
   clocks:
-    minItems: 1
     maxItems: 2
 
   "#address-cells":
@@ -57,8 +56,6 @@ properties:
 required:
   - compatible
   - reg
-  - clock-names
-  - clocks
   - "#address-cells"
   - "#size-cells"
   - ranges
@@ -83,6 +80,17 @@ patternProperties:
     $ref: /schemas/serial/qcom,serial-geni-qcom.yaml#
 
 allOf:
+  - if:
+      not:
+        properties:
+          compatible:
+            contains:
+              const: qcom,sa8255p-geni-se-qup
+    then:
+      required:
+        - clocks
+        - clock-names
+
   - if:
       properties:
         compatible:
@@ -162,4 +170,35 @@ examples:
         };
     };
 
+  - |
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        geniqup@9c0000 {
+            compatible = "qcom,sa8255p-geni-se-qup";
+            reg = <0 0x9c0000 0 0x6000>;
+            #address-cells = <2>;
+            #size-cells = <2>;
+            ranges;
+
+            i2c1: i2c@984000 {
+                compatible = "qcom,sa8255p-geni-i2c";
+                reg = <0 0x984000 0 0x4000>;
+                interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                power-domains = <&scmi9_pd 1>;
+            };
+
+            uart4: serial@990000 {
+                compatible = "qcom,sa8255p-geni-uart";
+                reg = <0 0x990000 0 0x4000>;
+                interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
+                power-domains = <&scmi11_pd 4>, <&scmi11_dvfs 4>;
+                power-domain-names = "power", "perf";
+            };
+        };
+    };
 ...
-- 
2.34.1

Re: [PATCH 16/22] dt-bindings: qcom: geni-se: document support for SA8255P

[Rob Herring (Arm)]

On Wed, 28 Aug 2024 13:37:15 -0700, Nikunj Kela wrote:
> Add "qcom,sa8255p-geni-se-qup" compatible for representing QUP on
> SA8255p.
> 
> Clocks are being managed by the firmware VM and not required on
> SA8255p Linux VM hence removing it from required list.
> 
> CC: Praveen Talari <quic_ptalari@quicinc.com>
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  .../bindings/soc/qcom/qcom,geni-se.yaml       | 47 +++++++++++++++++--
>  1 file changed, 43 insertions(+), 4 deletions(-)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: i2c@984000:compatible:0: 'qcom,sa8255p-geni-i2c' is not one of ['qcom,geni-i2c', 'qcom,geni-i2c-master-hub']
	from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: i2c@984000: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: i2c@984000: 'clock-names' is a required property
	from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: i2c@984000: Unevaluated properties are not allowed ('compatible' was unexpected)
	from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: serial@990000:compatible:0: 'qcom,sa8255p-geni-uart' is not one of ['qcom,geni-uart', 'qcom,geni-debug-uart']
	from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: serial@990000:power-domains: [[4294967295, 4], [4294967295, 4]] is too long
	from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: serial@990000: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: serial@990000: 'clock-names' is a required property
	from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: serial@990000: Unevaluated properties are not allowed ('compatible', 'power-domain-names', 'power-domains' were unexpected)
	from schema $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: /example-1/soc/geniqup@9c0000/i2c@984000: failed to match any schema with compatible: ['qcom,sa8255p-geni-i2c']
Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: /example-1/soc/geniqup@9c0000/serial@990000: failed to match any schema with compatible: ['qcom,sa8255p-geni-uart']

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240828203721.2751904-17-quic_nkela@quicinc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH 16/22] dt-bindings: qcom: geni-se: document support for SA8255P

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:15PM -0700, Nikunj Kela wrote:
> Add "qcom,sa8255p-geni-se-qup" compatible for representing QUP on
> SA8255p.
> 
> Clocks are being managed by the firmware VM and not required on
> SA8255p Linux VM hence removing it from required list.
> 
> CC: Praveen Talari <quic_ptalari@quicinc.com>
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  .../bindings/soc/qcom/qcom,geni-se.yaml       | 47 +++++++++++++++++--
>  1 file changed, 43 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
> index 7b031ef09669..40e3a3e045da 100644
> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
> @@ -22,17 +22,16 @@ properties:
>      enum:
>        - qcom,geni-se-qup
>        - qcom,geni-se-i2c-master-hub
> +      - qcom,sa8255p-geni-se-qup

Same problems. If you decide to use generic compatibles, it means it
covers all devices. Otherwise it does not make any sense.

>  
>    reg:
>      description: QUP wrapper common register address and length.
>      maxItems: 1
>  
>    clock-names:
> -    minItems: 1

Huh?

Best regards,
Krzysztof

Re: [PATCH 16/22] dt-bindings: qcom: geni-se: document support for SA8255P

[Nikunj Kela]

On 8/29/2024 12:42 AM, Krzysztof Kozlowski wrote:
> On Wed, Aug 28, 2024 at 01:37:15PM -0700, Nikunj Kela wrote:
>> Add "qcom,sa8255p-geni-se-qup" compatible for representing QUP on
>> SA8255p.
>>
>> Clocks are being managed by the firmware VM and not required on
>> SA8255p Linux VM hence removing it from required list.
>>
>> CC: Praveen Talari <quic_ptalari@quicinc.com>
>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>> ---
>>  .../bindings/soc/qcom/qcom,geni-se.yaml       | 47 +++++++++++++++++--
>>  1 file changed, 43 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
>> index 7b031ef09669..40e3a3e045da 100644
>> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
>> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
>> @@ -22,17 +22,16 @@ properties:
>>      enum:
>>        - qcom,geni-se-qup
>>        - qcom,geni-se-i2c-master-hub
>> +      - qcom,sa8255p-geni-se-qup
> Same problems. If you decide to use generic compatibles, it means it
> covers all devices. Otherwise it does not make any sense.

Hi Krzysztof,

SA8255p platform is not compatible with generic ones. At the time
generic compatibles were added, no one thought of such platform will
appear in future. Please advise what should we do in this case?

Thanks,

-Nikunj

>>  
>>    reg:
>>      description: QUP wrapper common register address and length.
>>      maxItems: 1
>>  
>>    clock-names:
>> -    minItems: 1
> Huh?
>
> Best regards,
> Krzysztof
>

Re: [PATCH 16/22] dt-bindings: qcom: geni-se: document support for SA8255P

[Krzysztof Kozlowski]

On 29/08/2024 16:23, Nikunj Kela wrote:
> 
> On 8/29/2024 12:42 AM, Krzysztof Kozlowski wrote:
>> On Wed, Aug 28, 2024 at 01:37:15PM -0700, Nikunj Kela wrote:
>>> Add "qcom,sa8255p-geni-se-qup" compatible for representing QUP on
>>> SA8255p.
>>>
>>> Clocks are being managed by the firmware VM and not required on
>>> SA8255p Linux VM hence removing it from required list.
>>>
>>> CC: Praveen Talari <quic_ptalari@quicinc.com>
>>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>>> ---
>>>  .../bindings/soc/qcom/qcom,geni-se.yaml       | 47 +++++++++++++++++--
>>>  1 file changed, 43 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
>>> index 7b031ef09669..40e3a3e045da 100644
>>> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
>>> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
>>> @@ -22,17 +22,16 @@ properties:
>>>      enum:
>>>        - qcom,geni-se-qup
>>>        - qcom,geni-se-i2c-master-hub
>>> +      - qcom,sa8255p-geni-se-qup
>> Same problems. If you decide to use generic compatibles, it means it
>> covers all devices. Otherwise it does not make any sense.
> 
> Hi Krzysztof,
> 
> SA8255p platform is not compatible with generic ones. At the time
> generic compatibles were added, no one thought of such platform will

That's kind of obvious and expected yet these were added...

> appear in future. Please advise what should we do in this case?

I don't know. We keep telling - do not use generic compatibles, because
you will have something like this, but people use generic compatibles -
so what can I say? I told you so?

Can we get agreement that using generic compatibles is a wrong idea? Or
sort of promise - we won't use them? Or policy? I don't know, we can
move on assuming this was a mistake 8 years ago, approaches evolve,
reviews change, but I am just afraid I will be repeating the same to
several future contributions and every time come with long arguments
exhausting my energy - don't add generic compatibles.

If devices are not compatible, I suggest different bindings.

Best regards,
Krzysztof

Re: [PATCH 16/22] dt-bindings: qcom: geni-se: document support for SA8255P

[Nikunj Kela]

On 8/30/2024 2:58 AM, Krzysztof Kozlowski wrote:
> On 29/08/2024 16:23, Nikunj Kela wrote:
>> On 8/29/2024 12:42 AM, Krzysztof Kozlowski wrote:
>>> On Wed, Aug 28, 2024 at 01:37:15PM -0700, Nikunj Kela wrote:
>>>> Add "qcom,sa8255p-geni-se-qup" compatible for representing QUP on
>>>> SA8255p.
>>>>
>>>> Clocks are being managed by the firmware VM and not required on
>>>> SA8255p Linux VM hence removing it from required list.
>>>>
>>>> CC: Praveen Talari <quic_ptalari@quicinc.com>
>>>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>>>> ---
>>>>  .../bindings/soc/qcom/qcom,geni-se.yaml       | 47 +++++++++++++++++--
>>>>  1 file changed, 43 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
>>>> index 7b031ef09669..40e3a3e045da 100644
>>>> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
>>>> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
>>>> @@ -22,17 +22,16 @@ properties:
>>>>      enum:
>>>>        - qcom,geni-se-qup
>>>>        - qcom,geni-se-i2c-master-hub
>>>> +      - qcom,sa8255p-geni-se-qup
>>> Same problems. If you decide to use generic compatibles, it means it
>>> covers all devices. Otherwise it does not make any sense.
>> Hi Krzysztof,
>>
>> SA8255p platform is not compatible with generic ones. At the time
>> generic compatibles were added, no one thought of such platform will
> That's kind of obvious and expected yet these were added...
>
>> appear in future. Please advise what should we do in this case?
> I don't know. We keep telling - do not use generic compatibles, because
> you will have something like this, but people use generic compatibles -
> so what can I say? I told you so?
>
> Can we get agreement that using generic compatibles is a wrong idea? Or
> sort of promise - we won't use them? Or policy? I don't know, we can
> move on assuming this was a mistake 8 years ago, approaches evolve,
> reviews change, but I am just afraid I will be repeating the same to
> several future contributions and every time come with long arguments
> exhausting my energy - don't add generic compatibles.
>
> If devices are not compatible, I suggest different bindings.
>
> Best regards,
> Krzysztof

Hi Krzysztof,

I will bring your concerns (raised above) to Qualcomm leads' attention.
Thank you for your feedback and support.

Thanks,

-Nikunj

>

[PATCH 17/22] dt-bindings: serial: document support for SA8255p

[Nikunj Kela]

Add compatibles representing UART support on SA8255p.

Clocks and interconnects are being configured in the firmware VM
on SA8255p platform, therefore making them optional.

CC: Praveen Talari <quic_ptalari@quicinc.com>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 .../serial/qcom,serial-geni-qcom.yaml         | 58 ++++++++++++++++---
 1 file changed, 51 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
index dd33794b3534..dcd43e1353ec 100644
--- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
+++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
@@ -13,11 +13,42 @@ maintainers:
 allOf:
   - $ref: /schemas/serial/serial.yaml#
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sa8255p-geni-uart
+              - qcom,sa8255p-geni-debug-uart
+    then:
+      required:
+        - power-domains
+        - power-domain-names
+      properties:
+        power-domains:
+          minItems: 2
+          maxItems: 2
+    else:
+      required:
+        - clocks
+        - clock-names
+      properties:
+        power-domains:
+          maxItems: 1
+        interconnects:
+          maxItems: 2
+        interconnect-names:
+          items:
+            - const: qup-core
+            - const: qup-config
+
 properties:
   compatible:
     enum:
       - qcom,geni-uart
       - qcom,geni-debug-uart
+      - qcom,sa8255p-geni-uart
+      - qcom,sa8255p-geni-debug-uart
 
   clocks:
     maxItems: 1
@@ -26,12 +57,10 @@ properties:
     const: se
 
   interconnects:
-    maxItems: 2
+    description: phandles of interconnect bw provider
 
   interconnect-names:
-    items:
-      - const: qup-core
-      - const: qup-config
+    description: names of interconnects
 
   interrupts:
     minItems: 1
@@ -51,15 +80,19 @@ properties:
       - const: sleep
 
   power-domains:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
+
+  power-domain-names:
+    items:
+      - const: power
+      - const: perf
 
   reg:
     maxItems: 1
 
 required:
   - compatible
-  - clocks
-  - clock-names
   - interrupts
   - reg
 
@@ -83,4 +116,15 @@ examples:
                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
         interconnect-names = "qup-core", "qup-config";
     };
+
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    serial@990000 {
+        compatible = "qcom,sa8255p-geni-uart";
+        reg = <0x990000 0x4000>;
+        interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
+        power-domains = <&scmi11_pd 4>, <&scmi11_dvfs 4>;
+        power-domain-names = "power", "perf";
+    };
 ...
-- 
2.34.1

Re: [PATCH 17/22] dt-bindings: serial: document support for SA8255p

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:16PM -0700, Nikunj Kela wrote:
> Add compatibles representing UART support on SA8255p.
> 
> Clocks and interconnects are being configured in the firmware VM
> on SA8255p platform, therefore making them optional.
> 
> CC: Praveen Talari <quic_ptalari@quicinc.com>
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  .../serial/qcom,serial-geni-qcom.yaml         | 58 ++++++++++++++++---
>  1 file changed, 51 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
> index dd33794b3534..dcd43e1353ec 100644
> --- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
> +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
> @@ -13,11 +13,42 @@ maintainers:
>  allOf:
>    - $ref: /schemas/serial/serial.yaml#

Please move entire allOf: to the place after "required:" block.

>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,sa8255p-geni-uart
> +              - qcom,sa8255p-geni-debug-uart
> +    then:
> +      required:
> +        - power-domains
> +        - power-domain-names
> +      properties:
> +        power-domains:
> +          minItems: 2
> +          maxItems: 2
> +    else:
> +      required:
> +        - clocks
> +        - clock-names
> +      properties:
> +        power-domains:
> +          maxItems: 1
> +        interconnects:
> +          maxItems: 2
> +        interconnect-names:
> +          items:
> +            - const: qup-core
> +            - const: qup-config
> +
>  properties:
>    compatible:
>      enum:
>        - qcom,geni-uart
>        - qcom,geni-debug-uart
> +      - qcom,sa8255p-geni-uart
> +      - qcom,sa8255p-geni-debug-uart

Not compatible with the old ones? Well, it is impossible. Generic
compatible like "qcom,geni-uart" means ALL DEVICES forever will be
compatible, because otherwise it just does not make any sense.  Of
course "all devices forever will be compatible" is impossible as well,
thus DT maintainers are suggesting SoC-specific compatibles all the
time, but if developers decide that they know the future, you should
keep it, right?

>  
>    clocks:
>      maxItems: 1
> @@ -26,12 +57,10 @@ properties:
>      const: se
>  
>    interconnects:
> -    maxItems: 2
> +    description: phandles of interconnect bw provider

Constraints must stay in top-level.

Best regards,
Krzysztof

Re: [PATCH 17/22] dt-bindings: serial: document support for SA8255p

[Nikunj Kela]

On 8/29/2024 12:41 AM, Krzysztof Kozlowski wrote:
> On Wed, Aug 28, 2024 at 01:37:16PM -0700, Nikunj Kela wrote:
>> Add compatibles representing UART support on SA8255p.
>>
>> Clocks and interconnects are being configured in the firmware VM
>> on SA8255p platform, therefore making them optional.
>>
>> CC: Praveen Talari <quic_ptalari@quicinc.com>
>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>> ---
>>  .../serial/qcom,serial-geni-qcom.yaml         | 58 ++++++++++++++++---
>>  1 file changed, 51 insertions(+), 7 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>> index dd33794b3534..dcd43e1353ec 100644
>> --- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>> +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>> @@ -13,11 +13,42 @@ maintainers:
>>  allOf:
>>    - $ref: /schemas/serial/serial.yaml#
> Please move entire allOf: to the place after "required:" block.
>
>>  
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            enum:
>> +              - qcom,sa8255p-geni-uart
>> +              - qcom,sa8255p-geni-debug-uart
>> +    then:
>> +      required:
>> +        - power-domains
>> +        - power-domain-names
>> +      properties:
>> +        power-domains:
>> +          minItems: 2
>> +          maxItems: 2
>> +    else:
>> +      required:
>> +        - clocks
>> +        - clock-names
>> +      properties:
>> +        power-domains:
>> +          maxItems: 1
>> +        interconnects:
>> +          maxItems: 2
>> +        interconnect-names:
>> +          items:
>> +            - const: qup-core
>> +            - const: qup-config
>> +
>>  properties:
>>    compatible:
>>      enum:
>>        - qcom,geni-uart
>>        - qcom,geni-debug-uart
>> +      - qcom,sa8255p-geni-uart
>> +      - qcom,sa8255p-geni-debug-uart
> Not compatible with the old ones? Well, it is impossible. Generic
> compatible like "qcom,geni-uart" means ALL DEVICES forever will be
> compatible, because otherwise it just does not make any sense.  Of
> course "all devices forever will be compatible" is impossible as well,
> thus DT maintainers are suggesting SoC-specific compatibles all the
> time, but if developers decide that they know the future, you should
> keep it, right?

Hi Krzysztof,

SA8255p uart is not compatible with generic ones. While I get your
point, could you please advise how to proceed on this? Of course, no one
could predict the future at the time generic compatibles were added but
here we are now with the usecase!

Thanks,

-Nikunj

>>  
>>    clocks:
>>      maxItems: 1
>> @@ -26,12 +57,10 @@ properties:
>>      const: se
>>  
>>    interconnects:
>> -    maxItems: 2
>> +    description: phandles of interconnect bw provider
> Constraints must stay in top-level.
>
> Best regards,
> Krzysztof
>

[PATCH 18/22] dt-bindings: spi: document support for SA8255p

[Nikunj Kela]

Add compatible representing spi support on SA8255p.

Clocks and interconnects are being configured in firmware VM
on SA8255p platform, therefore making them optional.

CC: Praveen Talari <quic_ptalari@quicinc.com>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 .../bindings/spi/qcom,spi-geni-qcom.yaml      | 64 +++++++++++++++----
 1 file changed, 53 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
index 2e20ca313ec1..74ea7c4f2451 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
@@ -25,10 +25,41 @@ description:
 
 allOf:
   - $ref: /schemas/spi/spi-controller.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: qcom,sa8255p-geni-spi
+    then:
+      required:
+        - power-domains
+        - power-domain-names
+      properties:
+        power-domains:
+          minItems: 2
+          maxItems: 2
+    else:
+      required:
+        - clocks
+        - clock-names
+      properties:
+        power-domains:
+          maxItems: 1
+        interconnects:
+          minItems: 2
+          maxItems: 3
+        interconnect-names:
+          minItems: 2
+          items:
+            - const: qup-core
+            - const: qup-config
+            - const: qup-memory
 
 properties:
   compatible:
-    const: qcom,geni-spi
+    enum:
+      - qcom,geni-spi
+      - qcom,sa8255p-geni-spi
 
   clocks:
     maxItems: 1
@@ -45,15 +76,10 @@ properties:
       - const: rx
 
   interconnects:
-    minItems: 2
-    maxItems: 3
+    description: phandles of interconnect bw provider
 
   interconnect-names:
-    minItems: 2
-    items:
-      - const: qup-core
-      - const: qup-config
-      - const: qup-memory
+    description: names of interconnects
 
   interrupts:
     maxItems: 1
@@ -61,15 +87,18 @@ properties:
   operating-points-v2: true
 
   power-domains:
-    maxItems: 1
+    $ref: "/schemas/power/power-domain.yaml#/properties/power-domains"
+
+  power-domain-names:
+    items:
+      - const: power
+      - const: perf
 
   reg:
     maxItems: 1
 
 required:
   - compatible
-  - clocks
-  - clock-names
   - interrupts
   - reg
 
@@ -116,3 +145,16 @@ examples:
         #address-cells = <1>;
         #size-cells = <0>;
     };
+
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    spi@888000 {
+        compatible = "qcom,sa8255p-geni-spi";
+        reg = <0x888000 0x4000>;
+        interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        power-domains = <&scmi10_pd 16>, <&scmi10_dvfs 16>;
+        power-domain-names = "power", "perf";
+    };
-- 
2.34.1

Re: [PATCH 18/22] dt-bindings: spi: document support for SA8255p

[Rob Herring (Arm)]

On Wed, 28 Aug 2024 13:37:17 -0700, Nikunj Kela wrote:
> Add compatible representing spi support on SA8255p.
> 
> Clocks and interconnects are being configured in firmware VM
> on SA8255p platform, therefore making them optional.
> 
> CC: Praveen Talari <quic_ptalari@quicinc.com>
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  .../bindings/spi/qcom,spi-geni-qcom.yaml      | 64 +++++++++++++++----
>  1 file changed, 53 insertions(+), 11 deletions(-)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:
./Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml:90:11: [error] string value is redundantly quoted with any quotes (quoted-strings)

dtschema/dtc warnings/errors:

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240828203721.2751904-19-quic_nkela@quicinc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH 18/22] dt-bindings: spi: document support for SA8255p

[Rob Herring]

On Wed, Aug 28, 2024 at 01:37:17PM -0700, Nikunj Kela wrote:
> Add compatible representing spi support on SA8255p.
> 
> Clocks and interconnects are being configured in firmware VM
> on SA8255p platform, therefore making them optional.
> 
> CC: Praveen Talari <quic_ptalari@quicinc.com>
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  .../bindings/spi/qcom,spi-geni-qcom.yaml      | 64 +++++++++++++++----
>  1 file changed, 53 insertions(+), 11 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
> index 2e20ca313ec1..74ea7c4f2451 100644
> --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
> @@ -25,10 +25,41 @@ description:
>  
>  allOf:
>    - $ref: /schemas/spi/spi-controller.yaml#
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: qcom,sa8255p-geni-spi
> +    then:
> +      required:
> +        - power-domains
> +        - power-domain-names

blank line

> +      properties:
> +        power-domains:
> +          minItems: 2
> +          maxItems: 2

Drop maxItems as 2 is already the max (with my change below).

Add blank line here.

> +    else:
> +      required:
> +        - clocks
> +        - clock-names

blank line

> +      properties:
> +        power-domains:
> +          maxItems: 1

blank line

> +        interconnects:
> +          minItems: 2
> +          maxItems: 3

blank line

> +        interconnect-names:
> +          minItems: 2
> +          items:
> +            - const: qup-core
> +            - const: qup-config
> +            - const: qup-memory
>  
>  properties:
>    compatible:
> -    const: qcom,geni-spi
> +    enum:
> +      - qcom,geni-spi
> +      - qcom,sa8255p-geni-spi
>  
>    clocks:
>      maxItems: 1
> @@ -45,15 +76,10 @@ properties:
>        - const: rx
>  
>    interconnects:
> -    minItems: 2
> -    maxItems: 3
> +    description: phandles of interconnect bw provider
>  
>    interconnect-names:
> -    minItems: 2
> -    items:
> -      - const: qup-core
> -      - const: qup-config
> -      - const: qup-memory
> +    description: names of interconnects

No, keep all properties defined at the top-level and then add 
constraints in if/then schemas.

>  
>    interrupts:
>      maxItems: 1
> @@ -61,15 +87,18 @@ properties:
>    operating-points-v2: true
>  
>    power-domains:
> -    maxItems: 1
> +    $ref: "/schemas/power/power-domain.yaml#/properties/power-domains"

Do you see an example of this anywhere else? No. You need:

minItems: 1
maxItems: 2

> +
> +  power-domain-names:
> +    items:
> +      - const: power
> +      - const: perf
>  
>    reg:
>      maxItems: 1
>  
>  required:
>    - compatible
> -  - clocks
> -  - clock-names
>    - interrupts
>    - reg
>  
> @@ -116,3 +145,16 @@ examples:
>          #address-cells = <1>;
>          #size-cells = <0>;
>      };
> +
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    spi@888000 {
> +        compatible = "qcom,sa8255p-geni-spi";
> +        reg = <0x888000 0x4000>;
> +        interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +        power-domains = <&scmi10_pd 16>, <&scmi10_dvfs 16>;
> +        power-domain-names = "power", "perf";
> +    };
> -- 
> 2.34.1
> 

Re: [PATCH 18/22] dt-bindings: spi: document support for SA8255p

[Nikunj Kela]

On 8/28/2024 8:06 PM, Rob Herring wrote:
> On Wed, Aug 28, 2024 at 01:37:17PM -0700, Nikunj Kela wrote:
>> Add compatible representing spi support on SA8255p.
>>
>> Clocks and interconnects are being configured in firmware VM
>> on SA8255p platform, therefore making them optional.
>>
>> CC: Praveen Talari <quic_ptalari@quicinc.com>
>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>> ---
>>  .../bindings/spi/qcom,spi-geni-qcom.yaml      | 64 +++++++++++++++----
>>  1 file changed, 53 insertions(+), 11 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
>> index 2e20ca313ec1..74ea7c4f2451 100644
>> --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
>> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
>> @@ -25,10 +25,41 @@ description:
>>  
>>  allOf:
>>    - $ref: /schemas/spi/spi-controller.yaml#
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            const: qcom,sa8255p-geni-spi
>> +    then:
>> +      required:
>> +        - power-domains
>> +        - power-domain-names
> blank line
>
>> +      properties:
>> +        power-domains:
>> +          minItems: 2
>> +          maxItems: 2
> Drop maxItems as 2 is already the max (with my change below).
>
> Add blank line here.
>
>> +    else:
>> +      required:
>> +        - clocks
>> +        - clock-names
> blank line
>
>> +      properties:
>> +        power-domains:
>> +          maxItems: 1
> blank line
>
>> +        interconnects:
>> +          minItems: 2
>> +          maxItems: 3
> blank line
>
>> +        interconnect-names:
>> +          minItems: 2
>> +          items:
>> +            - const: qup-core
>> +            - const: qup-config
>> +            - const: qup-memory
>>  
>>  properties:
>>    compatible:
>> -    const: qcom,geni-spi
>> +    enum:
>> +      - qcom,geni-spi
>> +      - qcom,sa8255p-geni-spi
>>  
>>    clocks:
>>      maxItems: 1
>> @@ -45,15 +76,10 @@ properties:
>>        - const: rx
>>  
>>    interconnects:
>> -    minItems: 2
>> -    maxItems: 3
>> +    description: phandles of interconnect bw provider
>>  
>>    interconnect-names:
>> -    minItems: 2
>> -    items:
>> -      - const: qup-core
>> -      - const: qup-config
>> -      - const: qup-memory
>> +    description: names of interconnects
> No, keep all properties defined at the top-level and then add 
> constraints in if/then schemas.
>
>>  
>>    interrupts:
>>      maxItems: 1
>> @@ -61,15 +87,18 @@ properties:
>>    operating-points-v2: true
>>  
>>    power-domains:
>> -    maxItems: 1
>> +    $ref: "/schemas/power/power-domain.yaml#/properties/power-domains"
> Do you see an example of this anywhere else? No. You need:
>
> minItems: 1
> maxItems: 2

Thanks Rob for reviewing the patch. Will take care of your comments in
next version.


>> +
>> +  power-domain-names:
>> +    items:
>> +      - const: power
>> +      - const: perf
>>  
>>    reg:
>>      maxItems: 1
>>  
>>  required:
>>    - compatible
>> -  - clocks
>> -  - clock-names
>>    - interrupts
>>    - reg
>>  
>> @@ -116,3 +145,16 @@ examples:
>>          #address-cells = <1>;
>>          #size-cells = <0>;
>>      };
>> +
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +    spi@888000 {
>> +        compatible = "qcom,sa8255p-geni-spi";
>> +        reg = <0x888000 0x4000>;
>> +        interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
>> +        #address-cells = <1>;
>> +        #size-cells = <0>;
>> +        power-domains = <&scmi10_pd 16>, <&scmi10_dvfs 16>;
>> +        power-domain-names = "power", "perf";
>> +    };
>> -- 
>> 2.34.1
>>

[PATCH 19/22] dt-bindings: i2c: document support for SA8255p

[Nikunj Kela]

Add compatible representing i2c support on SA8255p.

Clocks and interconnects are being configured in Firmware VM
on SA8255p, therefore making them optional.

CC: Praveen Talari <quic_ptalari@quicinc.com>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 .../bindings/i2c/qcom,i2c-geni-qcom.yaml      | 56 ++++++++++++-------
 1 file changed, 36 insertions(+), 20 deletions(-)

diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
index 9f66a3bb1f80..88f513fc5b08 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
@@ -15,14 +15,13 @@ properties:
     enum:
       - qcom,geni-i2c
       - qcom,geni-i2c-master-hub
+      - qcom,sa8255p-geni-i2c
 
   clocks:
-    minItems: 1
-    maxItems: 2
+    description: phandles for the clock providers
 
   clock-names:
-    minItems: 1
-    maxItems: 2
+    description: names for the clocks
 
   clock-frequency:
     default: 100000
@@ -36,12 +35,13 @@ properties:
       - const: rx
 
   interconnects:
-    minItems: 2
-    maxItems: 3
+    description: phandles of interconnect bw provider
 
   interconnect-names:
-    minItems: 2
-    maxItems: 3
+    items:
+      - const: qup-core
+      - const: qup-config
+      - const: qup-memory
 
   interrupts:
     maxItems: 1
@@ -69,8 +69,6 @@ properties:
 required:
   - compatible
   - interrupts
-  - clocks
-  - clock-names
   - reg
 
 allOf:
@@ -100,22 +98,28 @@ allOf:
           items:
             - const: qup-core
             - const: qup-config
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: qcom,sa8255p-geni-i2c
+    then:
+      required:
+        - power-domains
     else:
       properties:
         clocks:
-          maxItems: 1
-
+          minItems: 1
+          maxItems: 2
         clock-names:
-          const: se
-
+          minItems: 1
+          maxItems: 2
         interconnects:
-          minItems: 3
-
+          minItems: 2
+          maxItems: 3
         interconnect-names:
-          items:
-            - const: qup-core
-            - const: qup-config
-            - const: qup-memory
+          minItems: 2
+          maxItems: 3
 
 unevaluatedProperties: false
 
@@ -143,4 +147,16 @@ examples:
         power-domains = <&rpmhpd SC7180_CX>;
         required-opps = <&rpmhpd_opp_low_svs>;
     };
+
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    i2c@a90000 {
+        compatible = "qcom,sa8255p-geni-i2c";
+        reg = <0xa90000 0x4000>;
+        interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        power-domains = <&scmi9_pd 11>;
+    };
 ...
-- 
2.34.1

Re: [PATCH 19/22] dt-bindings: i2c: document support for SA8255p

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:18PM -0700, Nikunj Kela wrote:
> Add compatible representing i2c support on SA8255p.
> 
> Clocks and interconnects are being configured in Firmware VM
> on SA8255p, therefore making them optional.
> 
> CC: Praveen Talari <quic_ptalari@quicinc.com>
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  .../bindings/i2c/qcom,i2c-geni-qcom.yaml      | 56 ++++++++++++-------
>  1 file changed, 36 insertions(+), 20 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
> index 9f66a3bb1f80..88f513fc5b08 100644
> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
> @@ -15,14 +15,13 @@ properties:
>      enum:
>        - qcom,geni-i2c
>        - qcom,geni-i2c-master-hub
> +      - qcom,sa8255p-geni-i2c

Same as in other patches, this does not make sense. What is the point of
generic compatibles?


>  
>    clocks:
> -    minItems: 1
> -    maxItems: 2

Nope.

> +    description: phandles for the clock providers

Useless description. This cannot be anything else than phandles for the
clock providers.

Best regards,
Krzysztof

[PATCH 20/22] dt-bindings: firmware: arm,scmi: allow multiple virtual instances

[Nikunj Kela]

This change extends scmi node name so as to allow multiple virtual
SCMI instances.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/firmware/arm,scmi.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
index 211f5254adf2..a168be6dd30c 100644
--- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
+++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
@@ -24,7 +24,7 @@ description: |
 
 properties:
   $nodename:
-    const: scmi
+    pattern: '^scmi\.*'
 
   compatible:
     oneOf:
-- 
2.34.1

Re: [PATCH 20/22] dt-bindings: firmware: arm,scmi: allow multiple virtual instances

[Krzysztof Kozlowski]

On Wed, Aug 28, 2024 at 01:37:19PM -0700, Nikunj Kela wrote:
> This change extends scmi node name so as to allow multiple virtual
> SCMI instances.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  Documentation/devicetree/bindings/firmware/arm,scmi.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
> index 211f5254adf2..a168be6dd30c 100644
> --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
> +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
> @@ -24,7 +24,7 @@ description: |
>  
>  properties:
>    $nodename:
> -    const: scmi
> +    pattern: '^scmi\.*'


^scmi(-[0-9]+)?$

Best regards,
Krzysztof

[PATCH 21/22] ARM: dt: GIC: add extended SPI specifier

[Nikunj Kela]

Add interrupt specifier for extended SPI interrupts.

Qualcomm SA8255p platform uses extended SPI for SCMI 'a2p' doorbells.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 include/dt-bindings/interrupt-controller/arm-gic.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h
index 35b6f69b7db6..9c06248446b7 100644
--- a/include/dt-bindings/interrupt-controller/arm-gic.h
+++ b/include/dt-bindings/interrupt-controller/arm-gic.h
@@ -12,6 +12,7 @@
 
 #define GIC_SPI 0
 #define GIC_PPI 1
+#define GIC_ESPI 2
 
 /*
  * Interrupt specifier cell 2.
-- 
2.34.1

Re: [PATCH 21/22] ARM: dt: GIC: add extended SPI specifier

[Krzysztof Kozlowski]

On 28/08/2024 22:37, Nikunj Kela wrote:
> Add interrupt specifier for extended SPI interrupts.
> 
> Qualcomm SA8255p platform uses extended SPI for SCMI 'a2p' doorbells.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---

This is still bindings patch. Use proper subject prefix.

Best regards,
Krzysztof

Re: [PATCH 21/22] ARM: dt: GIC: add extended SPI specifier

[Rob Herring]

On Wed, Aug 28, 2024 at 01:37:20PM -0700, Nikunj Kela wrote:
> Add interrupt specifier for extended SPI interrupts.

What's an "extended SPI"? Is this a GIC spec thing? If so, what version?

> 
> Qualcomm SA8255p platform uses extended SPI for SCMI 'a2p' doorbells.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  include/dt-bindings/interrupt-controller/arm-gic.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h
> index 35b6f69b7db6..9c06248446b7 100644
> --- a/include/dt-bindings/interrupt-controller/arm-gic.h
> +++ b/include/dt-bindings/interrupt-controller/arm-gic.h
> @@ -12,6 +12,7 @@
>  
>  #define GIC_SPI 0
>  #define GIC_PPI 1
> +#define GIC_ESPI 2
>  
>  /*
>   * Interrupt specifier cell 2.
> -- 
> 2.34.1
> 

Re: [PATCH 21/22] ARM: dt: GIC: add extended SPI specifier

[Nikunj Kela]

On 8/29/2024 11:52 AM, Rob Herring wrote:
> On Wed, Aug 28, 2024 at 01:37:20PM -0700, Nikunj Kela wrote:
>> Add interrupt specifier for extended SPI interrupts.
> What's an "extended SPI"? Is this a GIC spec thing? If so, what version?

Extended SPI is an extended range of SPI interrupts supported by GIC.

Excerpt below from
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

"The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
interrupts, 2 for interrupts in the Extended SPI range, 3 for the
Extended PPI range. Other values are reserved for future use."

"The 2nd cell contains the interrupt number for the interrupt type. SPI
interrupts are in the range [0-987]. PPI interrupts are in the range
[0-15]. Extented SPI interrupts are in the range [0-1023]. Extended PPI
interrupts are in the range [0-127]."

>> Qualcomm SA8255p platform uses extended SPI for SCMI 'a2p' doorbells.
>>
>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>> ---
>>  include/dt-bindings/interrupt-controller/arm-gic.h | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h
>> index 35b6f69b7db6..9c06248446b7 100644
>> --- a/include/dt-bindings/interrupt-controller/arm-gic.h
>> +++ b/include/dt-bindings/interrupt-controller/arm-gic.h
>> @@ -12,6 +12,7 @@
>>  
>>  #define GIC_SPI 0
>>  #define GIC_PPI 1
>> +#define GIC_ESPI 2
>>  
>>  /*
>>   * Interrupt specifier cell 2.
>> -- 
>> 2.34.1
>>

Re: [PATCH 21/22] ARM: dt: GIC: add extended SPI specifier

[Rob Herring]

On Thu, Aug 29, 2024 at 2:02 PM Nikunj Kela <quic_nkela@quicinc.com> wrote:
>
>
> On 8/29/2024 11:52 AM, Rob Herring wrote:
> > On Wed, Aug 28, 2024 at 01:37:20PM -0700, Nikunj Kela wrote:
> >> Add interrupt specifier for extended SPI interrupts.
> > What's an "extended SPI"? Is this a GIC spec thing? If so, what version?
>
> Extended SPI is an extended range of SPI interrupts supported by GIC.
>
> Excerpt below from
> Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
>
> "The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
> interrupts, 2 for interrupts in the Extended SPI range, 3 for the
> Extended PPI range. Other values are reserved for future use."
>
> "The 2nd cell contains the interrupt number for the interrupt type. SPI
> interrupts are in the range [0-987]. PPI interrupts are in the range
> [0-15]. Extented SPI interrupts are in the range [0-1023]. Extended PPI
> interrupts are in the range [0-127]."

Looks like you should add EPPI define too while you're here.

Rob

Re: [PATCH 21/22] ARM: dt: GIC: add extended SPI specifier

[Nikunj Kela]

On 8/30/2024 7:44 AM, Rob Herring wrote:
> On Thu, Aug 29, 2024 at 2:02 PM Nikunj Kela <quic_nkela@quicinc.com> wrote:
>>
>> On 8/29/2024 11:52 AM, Rob Herring wrote:
>>> On Wed, Aug 28, 2024 at 01:37:20PM -0700, Nikunj Kela wrote:
>>>> Add interrupt specifier for extended SPI interrupts.
>>> What's an "extended SPI"? Is this a GIC spec thing? If so, what version?
>> Extended SPI is an extended range of SPI interrupts supported by GIC.
>>
>> Excerpt below from
>> Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
>>
>> "The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
>> interrupts, 2 for interrupts in the Extended SPI range, 3 for the
>> Extended PPI range. Other values are reserved for future use."
>>
>> "The 2nd cell contains the interrupt number for the interrupt type. SPI
>> interrupts are in the range [0-987]. PPI interrupts are in the range
>> [0-15]. Extented SPI interrupts are in the range [0-1023]. Extended PPI
>> interrupts are in the range [0-127]."
> Looks like you should add EPPI define too while you're here.
>
> Rob

Sure Rob. I can add that. Generally, there is an ask for a usecase
before we push anything that is used in DT. I won't have any usecase to
show for EPPI.

[PATCH 22/22] arm64: dts: qcom: Add reduced functional DT for SA8255p Ride platform

[Nikunj Kela]

SA8255p Ride platform is an automotive virtual platform. This platform
abstracts resources such as clocks, regulators etc. in the firmware VM.
The device drivers request resources operations over SCMI using power,
performance, reset and sensor protocols.

Multiple virtual SCMI instances are being employed for greater parallelism.
These instances are tied to devices such that devices can have dedicated
SCMI channel. Firmware VM (runs SCMI platform stack) is SMP enabled and
can process requests from agents in parallel. Qualcomm smc transport is
used for communication between SCMI agent and platform.

Let's add the reduced functional support for SA8255p Ride board.
Subsequently, the support for PCIe, USB, UFS, Ethernet will be added.

Co-developed-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 arch/arm64/boot/dts/qcom/Makefile           |    1 +
 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi |   80 +
 arch/arm64/boot/dts/qcom/sa8255p-ride.dts   |  149 ++
 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi  | 2312 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/sa8255p.dtsi       | 2405 +++++++++++++++++++
 5 files changed, 4947 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 197ab325c0b9..a4ae24e55c48 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -119,6 +119,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= qrb5165-rb5.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qrb5165-rb5-vision-mezzanine.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qru1000-idp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sa8155p-adp.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= sa8255p-ride.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sa8295p-adp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sa8540p-ride.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sa8775p-ride.dtb
diff --git a/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
new file mode 100644
index 000000000000..fb268d13b997
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/ {
+	thermal-zones {
+		pmm8654au_0_thermal: pm8255-0-thermal {
+			polling-delay-passive = <100>;
+
+			trips {
+				trip0 {
+					temperature = <105000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		pmm8654au_1_thermal: pm8255-1-thermal {
+			polling-delay-passive = <100>;
+
+			trips {
+				trip0 {
+					temperature = <105000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		pmm8654au_2_thermal: pm8255-2-thermal {
+			polling-delay-passive = <100>;
+
+			trips {
+				trip0 {
+					temperature = <105000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		pmm8654au_3_thermal: pm8255-3-thermal {
+			polling-delay-passive = <100>;
+
+			trips {
+				trip0 {
+					temperature = <105000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/sa8255p-ride.dts b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts
new file mode 100644
index 000000000000..1dc03051ad92
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "sa8255p.dtsi"
+#include "sa8255p-pmics.dtsi"
+#include "sa8255p-scmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SA8255P Ride";
+	compatible = "qcom,sa8255p-ride", "qcom,sa8255p";
+
+	aliases {
+		i2c11 = &i2c11;
+		i2c18 = &i2c18;
+		serial0 = &uart10;
+		serial1 = &uart4;
+		spi16 = &spi16;
+		scmichannels = &scmichannels;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&adreno_smmu {
+	power-domains = <&scmi15_pd 0>;
+
+	status = "okay";
+};
+
+&gpll0_board_clk {
+	clock-frequency = <300000000>;
+};
+
+&i2c11 {
+	clock-frequency = <400000>;
+	power-domains = <&scmi9_pd 11>;
+
+	status = "okay";
+};
+
+&i2c18 {
+	clock-frequency = <400000>;
+	power-domains = <&scmi9_pd 18>;
+
+	status = "okay";
+};
+
+&pmm8654au_0_thermal {
+	thermal-sensors = <&scmi23_sensor 0>;
+};
+
+&pmm8654au_1_thermal {
+	thermal-sensors = <&scmi23_sensor 1>;
+};
+
+&pmm8654au_2_thermal {
+	thermal-sensors = <&scmi23_sensor 2>;
+};
+
+&pmm8654au_3_thermal {
+	thermal-sensors = <&scmi23_sensor 3>;
+};
+
+&qupv3_id_0 {
+	status = "okay";
+};
+
+&qupv3_id_1 {
+	status = "okay";
+};
+
+&qupv3_id_2 {
+	status = "okay";
+};
+
+&scmi9 {
+	status = "okay";
+};
+
+&scmi10 {
+	status = "okay";
+};
+
+&scmi11 {
+	status = "okay";
+};
+
+&scmi15 {
+	status = "okay";
+};
+
+&scmi23 {
+	status = "okay";
+};
+
+&sleep_clk {
+	clock-frequency = <32000>;
+};
+
+&spi16 {
+	power-domains = <&scmi10_pd 16>, <&scmi10_dvfs 16>;
+	power-domain-names = "power", "perf";
+
+	status = "okay";
+};
+
+&tlmm {
+	ethernet0_default: ethernet0-default-state {
+		ethernet0_mdc: ethernet0-mdc-pins {
+			pins = "gpio8";
+			function = "emac0_mdc";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+
+		ethernet0_mdio: ethernet0-mdio-pins {
+			pins = "gpio9";
+			function = "emac0_mdio";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+	};
+};
+
+&uart4 {
+	power-domains = <&scmi11_pd 4>, <&scmi11_dvfs 4>;
+	power-domain-names = "power", "perf";
+
+	status = "okay";
+};
+
+&uart10 {
+	power-domains = <&scmi11_pd 10>, <&scmi11_dvfs 10>;
+	power-domain-names = "power", "perf";
+
+	status = "okay";
+};
+
+&xo_board_clk {
+	clock-frequency = <38400000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi b/arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi
new file mode 100644
index 000000000000..1e2db91711c6
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi
@@ -0,0 +1,2312 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&firmware {
+	scmi0: scmi0 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem0>;
+
+		interrupts = <GIC_SPI 963 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi0_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi0_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi0_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi1: scmi1 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem1>;
+
+		interrupts = <GIC_SPI 964 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi1_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi1_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi1_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi2: scmi2 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem2>;
+
+		interrupts = <GIC_SPI 965 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi2_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi2_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi2_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi3: scmi3 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem3>;
+
+		interrupts = <GIC_SPI 966 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi3_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi3_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi3_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi4: scmi4 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem4>;
+
+		interrupts = <GIC_SPI 967 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi4_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi4_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi4_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi5: scmi5 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem5>;
+
+		interrupts = <GIC_SPI 968 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi5_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi5_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi5_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi6: scmi6 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem6>;
+
+		interrupts = <GIC_SPI 969 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi6_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi6_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi6_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi7: scmi7 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem7>;
+
+		interrupts = <GIC_SPI 970 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi7_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi7_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi7_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi8: scmi8 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem8>;
+
+		interrupts = <GIC_SPI 971 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi8_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi8_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi8_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi9: scmi9 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem9>;
+
+		interrupts = <GIC_SPI 972 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi9_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi9_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi9_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi10: scmi10 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem10>;
+
+		interrupts = <GIC_SPI 973 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi10_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi10_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi10_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi11: scmi11 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem11>;
+
+		interrupts = <GIC_SPI 974 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi11_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi11_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi11_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi12: scmi12 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem12>;
+
+		interrupts = <GIC_SPI 975 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi12_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi12_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi12_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi13: scmi13 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem13>;
+
+		interrupts = <GIC_SPI 976 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi13_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi13_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi13_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi14: scmi14 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem14>;
+
+		interrupts = <GIC_SPI 977 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi14_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi14_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi14_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi15: scmi15 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem15>;
+
+		interrupts = <GIC_SPI 978 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi15_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi15_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi15_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi16: scmi16 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem16>;
+
+		interrupts = <GIC_SPI 979 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi16_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi16_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi16_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi17: scmi17 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem17>;
+
+		interrupts = <GIC_SPI 980 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi17_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi17_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi17_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi18: scmi18 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem18>;
+
+		interrupts = <GIC_SPI 981 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi18_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi18_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi18_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi19: scmi19 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem19>;
+
+		interrupts = <GIC_SPI 982 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi19_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi19_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi19_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi20: scmi20 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem20>;
+
+		interrupts = <GIC_SPI 983 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi20_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi20_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi20_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi21: scmi21 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem21>;
+
+		interrupts = <GIC_SPI 984 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi21_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi21_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi21_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi22: scmi22 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem22>;
+
+		interrupts = <GIC_SPI 985 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi22_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi22_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi22_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi23: scmi23 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem23>;
+
+		interrupts = <GIC_SPI 986 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi23_sensor: protocol@15 {
+			reg = <0x15>;
+			#thermal-sensor-cells = <1>;
+		};
+	};
+
+	scmi24: scmi24 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem24>;
+
+		interrupts = <GIC_SPI 987 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi24_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi24_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi24_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi25: scmi25 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem25>;
+
+		interrupts = <GIC_ESPI 0 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi25_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi25_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi25_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi26: scmi26 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem26>;
+
+		interrupts = <GIC_ESPI 1 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi26_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi26_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi26_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi27: scmi27 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem27>;
+
+		interrupts = <GIC_ESPI 2 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi27_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi27_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi27_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi28: scmi28 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem28>;
+
+		interrupts = <GIC_ESPI 3 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi28_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi28_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi28_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi29: scmi29 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem29>;
+
+		interrupts = <GIC_ESPI 4 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi29_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi29_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi29_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi30: scmi30 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem30>;
+
+		interrupts = <GIC_ESPI 5 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi30_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi30_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi30_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi31: scmi31 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem31>;
+
+		interrupts = <GIC_ESPI 6 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi31_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi31_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi31_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi32: scmi32 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem32>;
+
+		interrupts = <GIC_ESPI 7 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi32_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi32_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi32_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi33: scmi33 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem33>;
+
+		interrupts = <GIC_ESPI 8 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi33_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi33_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi33_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi34: scmi34 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem34>;
+
+		interrupts = <GIC_ESPI 9 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi34_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi34_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi34_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi35: scmi35 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem35>;
+
+		interrupts = <GIC_ESPI 10 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi35_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi35_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi35_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi36: scmi36 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem36>;
+
+		interrupts = <GIC_ESPI 11 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi36_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi36_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi36_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi37: scmi37 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem37>;
+
+		interrupts = <GIC_ESPI 12 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi37_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi37_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi37_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi38: scmi38 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem38>;
+
+		interrupts = <GIC_ESPI 13 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi38_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi38_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi38_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi39: scmi39 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem39>;
+
+		interrupts = <GIC_ESPI 14 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi39_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi39_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi39_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi40: scmi40 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem40>;
+
+		interrupts = <GIC_ESPI 15 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi40_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi40_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi40_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi41: scmi41 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem41>;
+
+		interrupts = <GIC_ESPI 16 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi41_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi41_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi41_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi42: scmi42 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem42>;
+
+		interrupts = <GIC_ESPI 17 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi42_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi42_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi42_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi43: scmi43 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem43>;
+
+		interrupts = <GIC_ESPI 18 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi43_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi43_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi43_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi44: scmi44 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem44>;
+
+		interrupts = <GIC_ESPI 19 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi44_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi44_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi44_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi45: scmi45 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem45>;
+
+		interrupts = <GIC_ESPI 20 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi45_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi45_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi45_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi46: scmi46 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem46>;
+
+		interrupts = <GIC_ESPI 21 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi46_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi46_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi46_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi47: scmi47 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem47>;
+
+		interrupts = <GIC_ESPI 22 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi47_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi47_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi47_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi48: scmi48 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem48>;
+
+		interrupts = <GIC_ESPI 23 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi48_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi48_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi48_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi49: scmi49 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem49>;
+
+		interrupts = <GIC_ESPI 24 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi49_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi49_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi49_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi50: scmi50 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem50>;
+
+		interrupts = <GIC_ESPI 25 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi50_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi50_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi50_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi51: scmi51 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem51>;
+
+		interrupts = <GIC_ESPI 26 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi51_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi51_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi51_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi52: scmi52 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem52>;
+
+		interrupts = <GIC_ESPI 27 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi52_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi52_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi52_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi53: scmi53 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem53>;
+
+		interrupts = <GIC_ESPI 28 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi53_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi53_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi53_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi54: scmi54 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem54>;
+
+		interrupts = <GIC_ESPI 29 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi54_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi54_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi54_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi55: scmi55 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem55>;
+
+		interrupts = <GIC_ESPI 30 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi55_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi55_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi55_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi56: scmi56 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem56>;
+
+		interrupts = <GIC_ESPI 31 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi56_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi56_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi56_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi57: scmi57 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem57>;
+
+		interrupts = <GIC_ESPI 32 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi57_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi57_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi57_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi58: scmi58 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem58>;
+
+		interrupts = <GIC_ESPI 33 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi58_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi58_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi58_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi59: scmi59 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem59>;
+
+		interrupts = <GIC_ESPI 34 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi59_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi59_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi59_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi60: scmi60 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem60>;
+
+		interrupts = <GIC_ESPI 35 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi60_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi60_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi60_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi61: scmi61 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem61>;
+
+		interrupts = <GIC_ESPI 36 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi61_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi61_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi61_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi62: scmi62 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem62>;
+
+		interrupts = <GIC_ESPI 37 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi62_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi62_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi62_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi63: scmi63 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem63>;
+
+		interrupts = <GIC_ESPI 38 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		scmi63_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi63_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi63_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+};
+
+&soc {
+	scmichannels: sram@d0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "mmio-sram";
+		reg = <0x0 0xd0000000 0x0 0x40000>;
+		ranges = <0x0 0x0 0x0 0xffffffff>;
+
+		shmem0: scmi-sram@d0000000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0000000 0x1000>;
+		};
+
+		shmem1: scmi-sram@d0001000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0001000 0x1000>;
+		};
+
+		shmem2: scmi-sram@d0002000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0002000 0x1000>;
+		};
+
+		shmem3: scmi-sram@d0003000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0003000 0x1000>;
+		};
+
+		shmem4: scmi-sram@d0004000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0004000 0x1000>;
+		};
+
+		shmem5: scmi-sram@d0005000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0005000 0x1000>;
+		};
+
+		shmem6: scmi-sram@d0006000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0006000 0x1000>;
+		};
+
+		shmem7: scmi-sram@d0007000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0007000 0x1000>;
+		};
+
+		shmem8: scmi-sram@d0008000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0008000 0x1000>;
+		};
+
+		shmem9: scmi-sram@d0009000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0009000 0x1000>;
+		};
+
+		shmem10: scmi-sram@d000a000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd000a000 0x1000>;
+		};
+
+		shmem11: scmi-sram@d000b000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd000b000 0x1000>;
+		};
+
+		shmem12: scmi-sram@d000c000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd000c000 0x1000>;
+		};
+
+		shmem13: scmi-sram@d000d000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd000d000 0x1000>;
+		};
+
+		shmem14: scmi-sram@d000e000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd000e000 0x1000>;
+		};
+
+		shmem15: scmi-sram@d000f000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd000f000 0x1000>;
+		};
+
+		shmem16: scmi-sram@d0010000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0010000 0x1000>;
+		};
+
+		shmem17: scmi-sram@d0011000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0011000 0x1000>;
+		};
+
+		shmem18: scmi-sram@d0012000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0012000 0x1000>;
+		};
+
+		shmem19: scmi-sram@d0013000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0013000 0x1000>;
+		};
+
+		shmem20: scmi-sram@d0014000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0014000 0x1000>;
+		};
+
+		shmem21: scmi-sram@d0015000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0015000 0x1000>;
+		};
+
+		shmem22: scmi-sram@d0016000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0016000 0x1000>;
+		};
+
+		shmem23: scmi-sram@d0017000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0017000 0x1000>;
+		};
+
+		shmem24: scmi-sram@d0018000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0018000 0x1000>;
+		};
+
+		shmem25: scmi-sram@d0019000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0019000 0x1000>;
+		};
+
+		shmem26: scmi-sram@d001a000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd001a000 0x1000>;
+		};
+
+		shmem27: scmi-sram@d001b000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd001b000 0x1000>;
+		};
+
+		shmem28: scmi-sram@d001c000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd001c000 0x1000>;
+		};
+
+		shmem29: scmi-sram@d001d000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd001d000 0x1000>;
+		};
+
+		shmem30: scmi-sram@d001e000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd001e000 0x1000>;
+		};
+
+		shmem31: scmi-sram@d001f000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd001f000 0x1000>;
+		};
+
+		shmem32: scmi-sram@d0020000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0020000 0x1000>;
+		};
+
+		shmem33: scmi-sram@d0021000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0021000 0x1000>;
+		};
+
+		shmem34: scmi-sram@d0022000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0022000 0x1000>;
+		};
+
+		shmem35: scmi-sram@d0023000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0023000 0x1000>;
+		};
+
+		shmem36: scmi-sram@d0024000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0024000 0x1000>;
+		};
+
+		shmem37: scmi-sram@d0025000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0025000 0x1000>;
+		};
+
+		shmem38: scmi-sram@d0026000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0026000 0x1000>;
+		};
+
+		shmem39: scmi-sram@d0027000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0027000 0x1000>;
+		};
+
+		shmem40: scmi-sram@d0028000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0028000 0x1000>;
+		};
+
+		shmem41: scmi-sram@d0029000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0029000 0x1000>;
+		};
+
+		shmem42: scmi-sram@d002a000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd002a000 0x1000>;
+		};
+
+		shmem43: scmi-sram@d002b000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd002b000 0x1000>;
+		};
+
+		shmem44: scmi-sram@d002c000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd002c000 0x1000>;
+		};
+
+		shmem45: scmi-sram@d002d000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd002d000 0x1000>;
+		};
+
+		shmem46: scmi-sram@d002e000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd002e000 0x1000>;
+		};
+
+		shmem47: scmi-sram@d002f000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd002f000 0x1000>;
+		};
+
+		shmem48: scmi-sram@d0030000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0030000 0x1000>;
+		};
+
+		shmem49: scmi-sram@d0031000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0031000 0x1000>;
+		};
+
+		shmem50: scmi-sram@d0032000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0032000 0x1000>;
+		};
+
+		shmem51: scmi-sram@d0033000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0033000 0x1000>;
+		};
+
+		shmem52: scmi-sram@d0034000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0034000 0x1000>;
+		};
+
+		shmem53: scmi-sram@d0035000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0035000 0x1000>;
+		};
+
+		shmem54: scmi-sram@d0036000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0036000 0x1000>;
+		};
+
+		shmem55: scmi-sram@d0037000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0037000 0x1000>;
+		};
+
+		shmem56: scmi-sram@d0038000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0038000 0x1000>;
+		};
+
+		shmem57: scmi-sram@d0039000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0039000 0x1000>;
+		};
+
+		shmem58: scmi-sram@d003a000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd003a000 0x1000>;
+		};
+
+		shmem59: scmi-sram@d003b000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd003b000 0x1000>;
+		};
+
+		shmem60: scmi-sram@d003c000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd003c000 0x1000>;
+		};
+
+		shmem61: scmi-sram@d003d000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd003d000 0x1000>;
+		};
+
+		shmem62: scmi-sram@d003e000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd003e000 0x1000>;
+		};
+
+		shmem63: scmi-sram@d003f000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd003f000 0x1000>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/sa8255p.dtsi b/arch/arm64/boot/dts/qcom/sa8255p.dtsi
new file mode 100644
index 000000000000..c354f76ffa5e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sa8255p.dtsi
@@ -0,0 +1,2405 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	clocks {
+		xo_board_clk: xo-board-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		gpll0_board_clk: gpll0-board-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		bi_tcxo_div2: bi-tcxo-div2-clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&xo_board_clk>;
+			clock-mult = <1>;
+			clock-div = <2>;
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			next-level-cache = <&L2_0>;
+			L2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+				L3_0: l3-cache {
+					compatible = "cache";
+					cache-level = <3>;
+					cache-unified;
+				};
+			};
+		};
+
+		CPU1: cpu@100 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			next-level-cache = <&L2_1>;
+			L2_1: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU2: cpu@200 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			next-level-cache = <&L2_2>;
+			L2_2: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU3: cpu@300 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			next-level-cache = <&L2_3>;
+			L2_3: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		CPU4: cpu@10000 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x10000>;
+			enable-method = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1>;
+			next-level-cache = <&L2_4>;
+			L2_4: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_1>;
+				L3_1: l3-cache {
+					compatible = "cache";
+					cache-level = <3>;
+					cache-unified;
+				};
+
+			};
+		};
+
+		CPU5: cpu@10100 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x10100>;
+			enable-method = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1>;
+			next-level-cache = <&L2_5>;
+			L2_5: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_1>;
+			};
+		};
+
+		CPU6: cpu@10200 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x10200>;
+			enable-method = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1>;
+			next-level-cache = <&L2_6>;
+			L2_6: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_1>;
+			};
+		};
+
+		CPU7: cpu@10300 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x10300>;
+			enable-method = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1>;
+			next-level-cache = <&L2_7>;
+			L2_7: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_1>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&CPU0>;
+				};
+
+				core1 {
+					cpu = <&CPU1>;
+				};
+
+				core2 {
+					cpu = <&CPU2>;
+				};
+
+				core3 {
+					cpu = <&CPU3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&CPU4>;
+				};
+
+				core1 {
+					cpu = <&CPU5>;
+				};
+
+				core2 {
+					cpu = <&CPU6>;
+				};
+
+				core3 {
+					cpu = <&CPU7>;
+				};
+			};
+		};
+	};
+
+	firmware: firmware {
+		scm {
+			compatible = "qcom,scm-sa8255p", "qcom,scm";
+			memory-region = <&tz_ffi_mem>;
+			qcom,dload-mode = <&tcsr 0x13000>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x0>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		sail_ss_mem: sail-ss@80000000 {
+			reg = <0x0 0x80000000 0x0 0x10000000>;
+			no-map;
+		};
+
+		hyp_mem: hyp@90000000 {
+			reg = <0x0 0x90000000 0x0 0x600000>;
+			no-map;
+		};
+
+		xbl_boot_mem: xbl-boot@90600000 {
+			reg = <0x0 0x90600000 0x0 0x200000>;
+			no-map;
+		};
+
+		aop_image_mem: aop-image@90800000 {
+			reg = <0x0 0x90800000 0x0 0x60000>;
+			no-map;
+		};
+
+		aop_cmd_db_mem: aop-cmd-db@90860000 {
+			compatible = "qcom,cmd-db";
+			reg = <0x0 0x90860000 0x0 0x20000>;
+			no-map;
+		};
+
+		uefi_log: uefi-log@908b0000 {
+			reg = <0x0 0x908b0000 0x0 0x10000>;
+			no-map;
+		};
+
+		ddr_training_checksum: ddr-training-checksum@908c0000 {
+			reg = <0x0 0x908c0000 0x0 0x1000>;
+			no-map;
+		};
+
+		reserved_mem: reserved@908f0000 {
+			reg = <0x0 0x908f0000 0x0 0xe000>;
+			no-map;
+		};
+
+		secdata_apss_mem: secdata-apss@908fe000 {
+			reg = <0x0 0x908fe000 0x0 0x2000>;
+			no-map;
+		};
+
+		smem_mem: smem@90900000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x90900000 0x0 0x200000>;
+			no-map;
+			hwlocks = <&tcsr_mutex 3>;
+		};
+
+		tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 {
+			reg = <0x0 0x90c00000 0x0 0x100000>;
+			no-map;
+		};
+
+		sail_mailbox_mem: sail-ss@90d00000 {
+			reg = <0x0 0x90d00000 0x0 0x100000>;
+			no-map;
+		};
+
+		sail_ota_mem: sail-ss@90e00000 {
+			reg = <0x0 0x90e00000 0x0 0x300000>;
+			no-map;
+		};
+
+		aoss_backup_mem: aoss-backup@91b00000 {
+			reg = <0x0 0x91b00000 0x0 0x40000>;
+			no-map;
+		};
+
+		cpucp_backup_mem: cpucp-backup@91b40000 {
+			reg = <0x0 0x91b40000 0x0 0x40000>;
+			no-map;
+		};
+
+		tz_config_backup_mem: tz-config-backup@91b80000 {
+			reg = <0x0 0x91b80000 0x0 0x10000>;
+			no-map;
+		};
+
+		ddr_training_data_mem: ddr-training-data@91b90000 {
+			reg = <0x0 0x91b90000 0x0 0x10000>;
+			no-map;
+		};
+
+		cdt_data_backup_mem: cdt-data-backup@91ba0000 {
+			reg = <0x0 0x91ba0000 0x0 0x1000>;
+			no-map;
+		};
+
+		tz_ffi_mem: tz-ffi@91c00000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0x91c00000 0x0 0x1400000>;
+			no-map;
+		};
+
+		lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
+			reg = <0x0 0x93b00000 0x0 0xf00000>;
+			no-map;
+		};
+
+		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
+			reg = <0x0 0x94a00000 0x0 0x800000>;
+			no-map;
+		};
+
+		pil_camera_mem: pil-camera@95200000 {
+			reg = <0x0 0x95200000 0x0 0x500000>;
+			no-map;
+		};
+
+		pil_adsp_mem: pil-adsp@95c00000 {
+			reg = <0x0 0x95c00000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		pil_gdsp0_mem: pil-gdsp0@97b00000 {
+			reg = <0x0 0x97b00000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		pil_gdsp1_mem: pil-gdsp1@99900000 {
+			reg = <0x0 0x99900000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		pil_cdsp0_mem: pil-cdsp0@9b800000 {
+			reg = <0x0 0x9b800000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		pil_gpu_mem: pil-gpu@9d600000 {
+			reg = <0x0 0x9d600000 0x0 0x2000>;
+			no-map;
+		};
+
+		pil_cdsp1_mem: pil-cdsp1@9d700000 {
+			reg = <0x0 0x9d700000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		pil_cvp_mem: pil-cvp@9f500000 {
+			reg = <0x0 0x9f500000 0x0 0x700000>;
+			no-map;
+		};
+
+		pil_video_mem: pil-video@9fc00000 {
+			reg = <0x0 0x9fc00000 0x0 0x700000>;
+			no-map;
+		};
+
+		audio_mdf_mem: audio-mdf-region@ae000000 {
+			reg = <0x0 0xae000000 0x0 0x1000000>;
+			no-map;
+		};
+
+		firmware_mem: firmware-region@b0000000 {
+			reg = <0x0 0xb0000000 0x0 0x800000>;
+			no-map;
+		};
+
+		hyptz_reserved_mem: hyptz-reserved@beb00000 {
+			reg = <0x0 0xbeb00000 0x0 0x11500000>;
+			no-map;
+		};
+
+		scmi_mem: scmi-region@d0000000 {
+			reg = <0x0 0xd0000000 0x0 0x40000>;
+			no-map;
+		};
+
+		firmware_logs_mem: firmware-logs@d0040000 {
+			reg = <0x0 0xd0040000 0x0 0x10000>;
+			no-map;
+		};
+
+		firmware_audio_mem: firmware-audio@d0050000 {
+			reg = <0x0 0xd0050000 0x0 0x4000>;
+			no-map;
+		};
+
+		firmware_reserved_mem: firmware-reserved@d0054000 {
+			reg = <0x0 0xd0054000 0x0 0x9c000>;
+			no-map;
+		};
+
+		firmware_quantum_test_mem: firmware-quantum-test@d00f0000 {
+			reg = <0x0 0xd00f0000 0x0 0x10000>;
+			no-map;
+		};
+
+		tags_mem: tags@d0100000 {
+			reg = <0x0 0xd0100000 0x0 0x1200000>;
+			no-map;
+		};
+
+		qtee_mem: qtee@d1300000 {
+			reg = <0x0 0xd1300000 0x0 0x500000>;
+			no-map;
+		};
+
+		deepsleep_backup_mem: deepsleep-backup@d1800000 {
+			reg = <0x0 0xd1800000 0x0 0x100000>;
+			no-map;
+		};
+
+		trusted_apps_mem: trusted-apps@d1900000 {
+			reg = <0x0 0xd1900000 0x0 0x3800000>;
+			no-map;
+		};
+
+		tz_stat_mem: tz-stat@db100000 {
+			reg = <0x0 0xdb100000 0x0 0x100000>;
+			no-map;
+		};
+
+		cpucp_fw_mem: cpucp-fw@db200000 {
+			reg = <0x0 0xdb200000 0x0 0x100000>;
+			no-map;
+		};
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x2000000>;
+			linux,cma-default;
+		};
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0 0 0 0 0x10 0>;
+
+		ipcc0: mailbox@408000 {
+			compatible = "qcom,sa8255p-ipcc", "qcom,ipcc";
+			reg = <0x0 0x00408000 0x0 0x1000>;
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#mbox-cells = <2>;
+		};
+
+		ipcc1: mailbox@488000 {
+			compatible = "qcom,sa8255p-ipcc", "qcom,ipcc";
+			reg = <0x0 0x00488000 0x0 0x1000>;
+			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#mbox-cells = <2>;
+			status = "disabled";
+		};
+
+		qupv3_id_2: geniqup@8c0000 {
+			compatible = "qcom,sa8255p-geni-se-qup";
+			reg = <0x0 0x008c0000 0x0 0x6000>;
+			ranges;
+			iommus = <&apps_smmu 0x5a3 0x0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+
+			i2c14: i2c@880000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x880000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi14: spi@880000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x880000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart14: serial@880000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00880000 0x0 0x4000>;
+				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c15: i2c@884000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x884000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi15: spi@884000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x884000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart15: serial@884000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00884000 0x0 0x4000>;
+				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c16: i2c@888000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x888000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi16: spi@888000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x00888000 0x0 0x4000>;
+				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart16: serial@888000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00888000 0x0 0x4000>;
+				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c17: i2c@88c000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x88c000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi17: spi@88c000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x88c000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart17: serial@88c000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x0088c000 0x0 0x4000>;
+				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c18: i2c@890000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x00890000 0x0 0x4000>;
+				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi18: spi@890000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x890000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart18: serial@890000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00890000 0x0 0x4000>;
+				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c19: i2c@894000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x894000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi19: spi@894000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x894000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart19: serial@894000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00894000 0x0 0x4000>;
+				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c20: i2c@898000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x898000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi20: spi@898000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x898000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart20: serial@898000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00898000 0x0 0x4000>;
+				interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		qupv3_id_0: geniqup@9c0000 {
+			compatible = "qcom,sa8255p-geni-se-qup";
+			reg = <0x0 0x9c0000 0x0 0x6000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			iommus = <&apps_smmu 0x403 0x0>;
+			status = "disabled";
+
+			i2c0: i2c@980000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x980000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi0: spi@980000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x980000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart0: serial@980000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x980000 0x0 0x4000>;
+				interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@984000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x984000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi1: spi@984000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x984000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart1: serial@984000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x984000 0x0 0x4000>;
+				interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c2: i2c@988000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x988000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi2: spi@988000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x988000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart2: serial@988000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x988000 0x0 0x4000>;
+				interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@98c000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x98c000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi3: spi@98c000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x98c000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart3: serial@98c000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x98c000 0x0 0x4000>;
+				interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c4: i2c@990000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x990000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi4: spi@990000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x990000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart4: serial@990000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x990000 0x0 0x4000>;
+				interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c5: i2c@994000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x994000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi5: spi@994000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x994000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart5: serial@994000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x994000 0x0 0x4000>;
+				interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		qupv3_id_1: geniqup@ac0000 {
+			compatible = "qcom,sa8255p-geni-se-qup";
+			reg = <0x0 0x00ac0000 0x0 0x6000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			iommus = <&apps_smmu 0x443 0x0>;
+			status = "disabled";
+
+			i2c7: i2c@a80000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0xa80000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi7: spi@a80000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0xa80000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart7: serial@a80000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00a80000 0x0 0x4000>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c8: i2c@a84000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0xa84000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi8: spi@a84000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0xa84000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart8: serial@a84000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00a84000 0x0 0x4000>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c9: i2c@a88000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0xa88000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi9: spi@a88000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0xa88000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart9: serial@a88000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0xa88000 0x0 0x4000>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c10: i2c@a8c000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0xa8c000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi10: spi@a8c000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0xa8c000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart10: serial@a8c000 {
+				compatible = "qcom,sa8255p-geni-debug-uart";
+				reg = <0x0 0x00a8c000 0x0 0x4000>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c11: i2c@a90000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0xa90000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi11: spi@a90000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0xa90000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart11: serial@a90000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00a90000 0x0 0x4000>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c12: i2c@a94000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0xa94000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi12: spi@a94000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0xa94000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart12: serial@a94000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00a94000 0x0 0x4000>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c13: i2c@a98000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0xa98000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		qupv3_id_3: geniqup@bc0000 {
+			compatible = "qcom,sa8255p-geni-se-qup";
+			reg = <0x0 0xbc0000 0x0 0x6000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			iommus = <&apps_smmu 0x43 0x0>;
+			status = "disabled";
+
+			i2c21: i2c@b80000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0xb80000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi21: spi@b80000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0xb80000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart21: serial@b80000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00b80000 0x0 0x4000>;
+				interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		rng: rng@10d2000 {
+			compatible = "qcom,sa8255p-trng", "qcom,trng";
+			reg = <0x0 0x010d2000 0x0 0x1000>;
+		};
+
+		tcsr_mutex: hwlock@1f40000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x0 0x01f40000 0x0 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		tcsr: syscon@1fc0000 {
+			compatible = "qcom,sa8255p-tcsr", "syscon";
+			reg = <0x0 0x1fc0000 0x0 0x30000>;
+		};
+
+		adreno_smmu: iommu@3da0000 {
+			compatible = "qcom,sa8255p-smmu-500", "qcom,adreno-smmu",
+				     "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x03da0000 0x0 0x20000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <2>;
+			dma-coherent;
+			interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pdc: interrupt-controller@b220000 {
+			compatible = "qcom,sa8255p-pdc", "qcom,pdc";
+			reg = <0x0 0x0b220000 0x0 0x30000>,
+			      <0x0 0x17c000f0 0x0 0x64>;
+			qcom,pdc-ranges = <0 480 40>,
+					  <40 140 14>,
+					  <54 263 1>,
+					  <55 306 4>,
+					  <59 312 3>,
+					  <62 374 2>,
+					  <64 434 2>,
+					  <66 438 2>,
+					  <70 520 1>,
+					  <73 523 1>,
+					  <118 568 6>,
+					  <124 609 3>,
+					  <159 638 1>,
+					  <160 720 3>,
+					  <169 728 30>,
+					  <199 416 2>,
+					  <201 449 1>,
+					  <202 89 1>,
+					  <203 451 1>,
+					  <204 462 1>,
+					  <205 264 1>,
+					  <206 579 1>,
+					  <207 653 1>,
+					  <208 656 1>,
+					  <209 659 1>,
+					  <210 122 1>,
+					  <211 699 1>,
+					  <212 705 1>,
+					  <213 450 1>,
+					  <214 643 2>,
+					  <216 646 5>,
+					  <221 390 5>,
+					  <226 700 2>,
+					  <228 440 1>,
+					  <229 663 1>,
+					  <230 524 2>,
+					  <232 612 3>,
+					  <235 723 5>;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupt-controller;
+		};
+
+		tsens2: thermal-sensor@c251000 {
+			compatible = "qcom,sa8255p-tsens", "qcom,tsens-v2";
+			reg = <0x0 0x0c251000 0x0 0x1ff>,
+			      <0x0 0x0c224000 0x0 0x8>;
+			interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
+			#qcom,sensors = <13>;
+			interrupt-names = "uplow", "critical";
+			#thermal-sensor-cells = <1>;
+		};
+
+		tsens3: thermal-sensor@c252000 {
+			compatible = "qcom,sa8255p-tsens", "qcom,tsens-v2";
+			reg = <0x0 0x0c252000 0x0 0x1ff>,
+			      <0x0 0x0c225000 0x0 0x8>;
+			interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
+			#qcom,sensors = <13>;
+			interrupt-names = "uplow", "critical";
+			#thermal-sensor-cells = <1>;
+		};
+
+		tsens0: thermal-sensor@c263000 {
+			compatible = "qcom,sa8255p-tsens", "qcom,tsens-v2";
+			reg = <0x0 0x0c263000 0x0 0x1ff>,
+			      <0x0 0x0c222000 0x0 0x8>;
+			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+			#qcom,sensors = <12>;
+			interrupt-names = "uplow", "critical";
+			#thermal-sensor-cells = <1>;
+		};
+
+		tsens1: thermal-sensor@c265000 {
+			compatible = "qcom,sa8255p-tsens", "qcom,tsens-v2";
+			reg = <0x0 0x0c265000 0x0 0x1ff>,
+			      <0x0 0x0c223000 0x0 0x8>;
+			interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+			#qcom,sensors = <12>;
+			interrupt-names = "uplow", "critical";
+			#thermal-sensor-cells = <1>;
+		};
+
+		aoss_qmp: power-management@c300000 {
+			compatible = "qcom,sa8255p-aoss-qmp", "qcom,aoss-qmp";
+			reg = <0x0 0x0c300000 0x0 0x400>;
+			interrupts-extended = <&ipcc0 IPCC_CLIENT_AOP
+					       IPCC_MPROC_SIGNAL_GLINK_QMP
+					       IRQ_TYPE_EDGE_RISING>;
+			mboxes = <&ipcc0 IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			#clock-cells = <0>;
+		};
+
+		tlmm: pinctrl@f000000 {
+			compatible = "qcom,sa8255p-tlmm";
+			reg = <0x0 0x0f000000 0x0 0x1000000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 149>;
+			wakeup-parent = <&pdc>;
+		};
+
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,sa8255p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x15000000 0x0 0x100000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <2>;
+
+			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		intc: interrupt-controller@17a00000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x17a00000 0x0 0x10000>,	/* GICD */
+			      <0x0 0x17a60000 0x0 0x100000>;	/* GICR * 8 */
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x20000>;
+		};
+
+		watchdog@17c10000 {
+			compatible = "qcom,apss-wdt-sa8255p", "qcom,kpss-wdt";
+			reg = <0x0 0x17c10000 0x0 0x1000>;
+			clocks = <&sleep_clk>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		memtimer: timer@17c20000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0 0x17c20000 0x0 0x1000>;
+			ranges = <0x0 0x0 0x0 0x20000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			frame@17c21000 {
+				reg = <0x17c21000 0x1000>,
+				      <0x17c22000 0x1000>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <0>;
+			};
+
+			frame@17c23000 {
+				reg = <0x17c23000 0x1000>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <1>;
+				status = "disabled";
+			};
+
+			frame@17c25000 {
+				reg = <0x17c25000 0x1000>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <2>;
+				status = "disabled";
+			};
+
+			frame@17c27000 {
+				reg = <0x17c27000 0x1000>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <3>;
+				status = "disabled";
+			};
+
+			frame@17c29000 {
+				reg = <0x17c29000 0x1000>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <4>;
+				status = "disabled";
+			};
+
+			frame@17c2b000 {
+				reg = <0x17c2b000 0x1000>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <5>;
+				status = "disabled";
+			};
+
+			frame@17c2d000 {
+				reg = <0x17c2d000 0x1000>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <6>;
+				status = "disabled";
+			};
+		};
+
+		cpufreq_hw: cpufreq@18591000 {
+			compatible = "qcom,sa8255p-cpufreq-epss",
+				     "qcom,cpufreq-epss";
+			reg = <0x0 0x18591000 0x0 0x1000>,
+			      <0x0 0x18593000 0x0 0x1000>;
+			reg-names = "freq-domain0", "freq-domain1";
+
+			clocks = <&bi_tcxo_div2>, <&gpll0_board_clk>;
+			clock-names = "xo", "alternate";
+
+			#freq-domain-cells = <1>;
+		};
+	};
+
+	thermal-zones {
+		aoss-0-thermal {
+			thermal-sensors = <&tsens0 0>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-0-0-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens0 1>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-0-1-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens0 2>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-0-2-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens0 3>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-0-3-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens0 4>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		gpuss-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens0 5>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		gpuss-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens0 6>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		gpuss-2-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens0 7>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		audio-thermal {
+			thermal-sensors = <&tsens0 8>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		camss-0-thermal {
+			thermal-sensors = <&tsens0 9>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		pcie-0-thermal {
+			thermal-sensors = <&tsens0 10>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpuss-0-0-thermal {
+			thermal-sensors = <&tsens0 11>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		aoss-1-thermal {
+			thermal-sensors = <&tsens1 0>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-0-0-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens1 1>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-0-1-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens1 2>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-0-2-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens1 3>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-0-3-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens1 4>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		gpuss-3-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens1 5>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		gpuss-4-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens1 6>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		gpuss-5-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens1 7>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		video-thermal {
+			thermal-sensors = <&tsens1 8>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		camss-1-thermal {
+			thermal-sensors = <&tsens1 9>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		pcie-1-thermal {
+			thermal-sensors = <&tsens1 10>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpuss-0-1-thermal {
+			thermal-sensors = <&tsens1 11>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		aoss-2-thermal {
+			thermal-sensors = <&tsens2 0>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-1-0-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 1>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-1-1-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 2>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-1-2-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 3>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-1-3-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 4>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-0-0-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 5>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-0-1-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 6>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-0-2-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 7>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-1-0-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 8>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-1-1-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 9>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-1-2-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 10>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		ddrss-0-thermal {
+			thermal-sensors = <&tsens2 11>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpuss-1-0-thermal {
+			thermal-sensors = <&tsens2 12>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		aoss-3-thermal {
+			thermal-sensors = <&tsens3 0>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-1-0-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 1>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-1-1-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 2>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-1-2-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 3>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-1-3-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 4>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-0-0-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 5>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-0-1-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 6>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-0-2-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 7>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-1-0-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 8>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-1-1-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 9>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-1-2-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 10>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		ddrss-1-thermal {
+			thermal-sensors = <&tsens3 11>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpuss-1-1-thermal {
+			thermal-sensors = <&tsens3 12>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
-- 
2.34.1

Re: [PATCH 22/22] arm64: dts: qcom: Add reduced functional DT for SA8255p Ride platform

[Krzysztof Kozlowski]

On 28/08/2024 22:37, Nikunj Kela wrote:
> SA8255p Ride platform is an automotive virtual platform. This platform
> abstracts resources such as clocks, regulators etc. in the firmware VM.
> The device drivers request resources operations over SCMI using power,
> performance, reset and sensor protocols.
> 
> Multiple virtual SCMI instances are being employed for greater parallelism.
> These instances are tied to devices such that devices can have dedicated
> SCMI channel. Firmware VM (runs SCMI platform stack) is SMP enabled and
> can process requests from agents in parallel. Qualcomm smc transport is
> used for communication between SCMI agent and platform.
> 
> Let's add the reduced functional support for SA8255p Ride board.
> Subsequently, the support for PCIe, USB, UFS, Ethernet will be added.
> 
> Co-developed-by: Shazad Hussain <quic_shazhuss@quicinc.com>
> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/Makefile           |    1 +
>  arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi |   80 +
>  arch/arm64/boot/dts/qcom/sa8255p-ride.dts   |  149 ++
>  arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi  | 2312 ++++++++++++++++++
>  arch/arm64/boot/dts/qcom/sa8255p.dtsi       | 2405 +++++++++++++++++++
>  5 files changed, 4947 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts
>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi
>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi
> 

...

> diff --git a/arch/arm64/boot/dts/qcom/sa8255p-ride.dts b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts
> new file mode 100644
> index 000000000000..1dc03051ad92
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts
> @@ -0,0 +1,149 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +#include "sa8255p.dtsi"
> +#include "sa8255p-pmics.dtsi"
> +#include "sa8255p-scmi.dtsi"
> +
> +/ {
> +	model = "Qualcomm Technologies, Inc. SA8255P Ride";
> +	compatible = "qcom,sa8255p-ride", "qcom,sa8255p";
> +
> +	aliases {
> +		i2c11 = &i2c11;
> +		i2c18 = &i2c18;
> +		serial0 = &uart10;
> +		serial1 = &uart4;
> +		spi16 = &spi16;
> +		scmichannels = &scmichannels;

Nothing parses this.



> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +&firmware {
> +	scmi0: scmi0 {

scmi-0


> +		compatible = "qcom,scmi-smc";
> +		arm,smc-id = <0xc6008012>;
> +		shmem = <&shmem0>;
> +
> +		interrupts = <GIC_SPI 963 IRQ_TYPE_EDGE_RISING>;
> +		interrupt-names = "a2p";
> +
> +		max-rx-timeout-ms = <3000>;
> +
> +		status = "disabled";

status is the last property (from properties)


...

> +
> +&soc {
> +	scmichannels: sram@d0000000 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "mmio-sram";
> +		reg = <0x0 0xd0000000 0x0 0x40000>;
> +		ranges = <0x0 0x0 0x0 0xffffffff>;
> +
> +		shmem0: scmi-sram@d0000000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0000000 0x1000>;
> +		};
> +
> +		shmem1: scmi-sram@d0001000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0001000 0x1000>;
> +		};
> +
> +		shmem2: scmi-sram@d0002000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0002000 0x1000>;
> +		};
> +
> +		shmem3: scmi-sram@d0003000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0003000 0x1000>;
> +		};
> +
> +		shmem4: scmi-sram@d0004000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0004000 0x1000>;
> +		};
> +
> +		shmem5: scmi-sram@d0005000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0005000 0x1000>;
> +		};
> +
> +		shmem6: scmi-sram@d0006000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0006000 0x1000>;
> +		};
> +
> +		shmem7: scmi-sram@d0007000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0007000 0x1000>;
> +		};
> +
> +		shmem8: scmi-sram@d0008000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0008000 0x1000>;
> +		};
> +
> +		shmem9: scmi-sram@d0009000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0009000 0x1000>;
> +		};
> +
> +		shmem10: scmi-sram@d000a000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd000a000 0x1000>;
> +		};
> +
> +		shmem11: scmi-sram@d000b000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd000b000 0x1000>;
> +		};
> +
> +		shmem12: scmi-sram@d000c000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd000c000 0x1000>;
> +		};
> +
> +		shmem13: scmi-sram@d000d000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd000d000 0x1000>;
> +		};
> +
> +		shmem14: scmi-sram@d000e000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd000e000 0x1000>;
> +		};
> +
> +		shmem15: scmi-sram@d000f000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd000f000 0x1000>;
> +		};
> +
> +		shmem16: scmi-sram@d0010000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0010000 0x1000>;
> +		};
> +
> +		shmem17: scmi-sram@d0011000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0011000 0x1000>;
> +		};
> +
> +		shmem18: scmi-sram@d0012000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0012000 0x1000>;
> +		};
> +
> +		shmem19: scmi-sram@d0013000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0013000 0x1000>;
> +		};
> +
> +		shmem20: scmi-sram@d0014000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0014000 0x1000>;
> +		};
> +
> +		shmem21: scmi-sram@d0015000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0015000 0x1000>;
> +		};
> +
> +		shmem22: scmi-sram@d0016000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0016000 0x1000>;
> +		};
> +
> +		shmem23: scmi-sram@d0017000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0017000 0x1000>;
> +		};
> +
> +		shmem24: scmi-sram@d0018000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0018000 0x1000>;
> +		};
> +
> +		shmem25: scmi-sram@d0019000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0019000 0x1000>;
> +		};
> +
> +		shmem26: scmi-sram@d001a000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd001a000 0x1000>;
> +		};
> +
> +		shmem27: scmi-sram@d001b000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd001b000 0x1000>;
> +		};
> +
> +		shmem28: scmi-sram@d001c000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd001c000 0x1000>;
> +		};
> +
> +		shmem29: scmi-sram@d001d000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd001d000 0x1000>;
> +		};
> +
> +		shmem30: scmi-sram@d001e000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd001e000 0x1000>;
> +		};
> +
> +		shmem31: scmi-sram@d001f000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd001f000 0x1000>;
> +		};
> +
> +		shmem32: scmi-sram@d0020000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0020000 0x1000>;
> +		};
> +
> +		shmem33: scmi-sram@d0021000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0021000 0x1000>;
> +		};
> +
> +		shmem34: scmi-sram@d0022000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0022000 0x1000>;
> +		};
> +
> +		shmem35: scmi-sram@d0023000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0023000 0x1000>;
> +		};
> +
> +		shmem36: scmi-sram@d0024000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0024000 0x1000>;
> +		};
> +
> +		shmem37: scmi-sram@d0025000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0025000 0x1000>;
> +		};
> +
> +		shmem38: scmi-sram@d0026000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0026000 0x1000>;
> +		};
> +
> +		shmem39: scmi-sram@d0027000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0027000 0x1000>;
> +		};
> +
> +		shmem40: scmi-sram@d0028000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0028000 0x1000>;
> +		};
> +
> +		shmem41: scmi-sram@d0029000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0029000 0x1000>;
> +		};
> +
> +		shmem42: scmi-sram@d002a000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd002a000 0x1000>;
> +		};
> +
> +		shmem43: scmi-sram@d002b000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd002b000 0x1000>;
> +		};
> +
> +		shmem44: scmi-sram@d002c000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd002c000 0x1000>;
> +		};
> +
> +		shmem45: scmi-sram@d002d000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd002d000 0x1000>;
> +		};
> +
> +		shmem46: scmi-sram@d002e000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd002e000 0x1000>;
> +		};
> +
> +		shmem47: scmi-sram@d002f000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd002f000 0x1000>;
> +		};
> +
> +		shmem48: scmi-sram@d0030000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0030000 0x1000>;
> +		};
> +
> +		shmem49: scmi-sram@d0031000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0031000 0x1000>;
> +		};
> +
> +		shmem50: scmi-sram@d0032000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0032000 0x1000>;
> +		};
> +
> +		shmem51: scmi-sram@d0033000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0033000 0x1000>;
> +		};
> +
> +		shmem52: scmi-sram@d0034000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0034000 0x1000>;
> +		};
> +
> +		shmem53: scmi-sram@d0035000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0035000 0x1000>;
> +		};
> +
> +		shmem54: scmi-sram@d0036000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0036000 0x1000>;
> +		};
> +
> +		shmem55: scmi-sram@d0037000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0037000 0x1000>;
> +		};
> +
> +		shmem56: scmi-sram@d0038000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0038000 0x1000>;
> +		};
> +
> +		shmem57: scmi-sram@d0039000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd0039000 0x1000>;
> +		};
> +
> +		shmem58: scmi-sram@d003a000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd003a000 0x1000>;
> +		};
> +
> +		shmem59: scmi-sram@d003b000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd003b000 0x1000>;
> +		};
> +
> +		shmem60: scmi-sram@d003c000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd003c000 0x1000>;
> +		};
> +
> +		shmem61: scmi-sram@d003d000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd003d000 0x1000>;
> +		};
> +
> +		shmem62: scmi-sram@d003e000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd003e000 0x1000>;
> +		};
> +
> +		shmem63: scmi-sram@d003f000 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0xd003f000 0x1000>;
> +		};
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sa8255p.dtsi b/arch/arm64/boot/dts/qcom/sa8255p.dtsi
> new file mode 100644
> index 000000000000..c354f76ffa5e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sa8255p.dtsi
> @@ -0,0 +1,2405 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/mailbox/qcom-ipcc.h>
> +
> +/ {
> +	interrupt-parent = <&intc>;
> +
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	clocks {
> +		xo_board_clk: xo-board-clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +
> +		sleep_clk: sleep-clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +
> +		gpll0_board_clk: gpll0-board-clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +
> +		bi_tcxo_div2: bi-tcxo-div2-clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&xo_board_clk>;
> +			clock-mult = <1>;
> +			clock-div = <2>;
> +			#clock-cells = <0>;
> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		CPU0: cpu@0 {

Lowercase label.

...

Best regards,
Krzysztof

Re: [PATCH 22/22] arm64: dts: qcom: Add reduced functional DT for SA8255p Ride platform

[Nikunj Kela]

On 8/29/2024 12:49 AM, Krzysztof Kozlowski wrote:
> On 28/08/2024 22:37, Nikunj Kela wrote:
>> SA8255p Ride platform is an automotive virtual platform. This platform
>> abstracts resources such as clocks, regulators etc. in the firmware VM.
>> The device drivers request resources operations over SCMI using power,
>> performance, reset and sensor protocols.
>>
>> Multiple virtual SCMI instances are being employed for greater parallelism.
>> These instances are tied to devices such that devices can have dedicated
>> SCMI channel. Firmware VM (runs SCMI platform stack) is SMP enabled and
>> can process requests from agents in parallel. Qualcomm smc transport is
>> used for communication between SCMI agent and platform.
>>
>> Let's add the reduced functional support for SA8255p Ride board.
>> Subsequently, the support for PCIe, USB, UFS, Ethernet will be added.
>>
>> Co-developed-by: Shazad Hussain <quic_shazhuss@quicinc.com>
>> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>> ---
>>  arch/arm64/boot/dts/qcom/Makefile           |    1 +
>>  arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi |   80 +
>>  arch/arm64/boot/dts/qcom/sa8255p-ride.dts   |  149 ++
>>  arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi  | 2312 ++++++++++++++++++
>>  arch/arm64/boot/dts/qcom/sa8255p.dtsi       | 2405 +++++++++++++++++++
>>  5 files changed, 4947 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
>>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts
>>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi
>>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi
>>
> ...
>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8255p-ride.dts b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts
>> new file mode 100644
>> index 000000000000..1dc03051ad92
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts
>> @@ -0,0 +1,149 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +#include "sa8255p.dtsi"
>> +#include "sa8255p-pmics.dtsi"
>> +#include "sa8255p-scmi.dtsi"
>> +
>> +/ {
>> +	model = "Qualcomm Technologies, Inc. SA8255P Ride";
>> +	compatible = "qcom,sa8255p-ride", "qcom,sa8255p";
>> +
>> +	aliases {
>> +		i2c11 = &i2c11;
>> +		i2c18 = &i2c18;
>> +		serial0 = &uart10;
>> +		serial1 = &uart4;
>> +		spi16 = &spi16;
>> +		scmichannels = &scmichannels;
> Nothing parses this.
>
We are using this alias in bootloader to speed up the parsing. Since we
are using 64 SCMI instances and SCMI smc transport driver for
Qualcomm(drivers/firmware/arm_scmi/transports/smc.c) expects
cap-id(created by hypervisor at boot time), our bootloader gets those
cap-id for each channel and populate them. This alias is an optimization
to save boottime as in automotive, boot KPIs are critical.


>
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +&firmware {
>> +	scmi0: scmi0 {
> scmi-0
>
ACK!
>> +		compatible = "qcom,scmi-smc";
>> +		arm,smc-id = <0xc6008012>;
>> +		shmem = <&shmem0>;
>> +
>> +		interrupts = <GIC_SPI 963 IRQ_TYPE_EDGE_RISING>;
>> +		interrupt-names = "a2p";
>> +
>> +		max-rx-timeout-ms = <3000>;
>> +
>> +		status = "disabled";
> status is the last property (from properties)
>
ACK!
> ...
>
>> +
>> +&soc {
>> +	scmichannels: sram@d0000000 {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		compatible = "mmio-sram";
>> +		reg = <0x0 0xd0000000 0x0 0x40000>;
>> +		ranges = <0x0 0x0 0x0 0xffffffff>;
>> +
>> +		shmem0: scmi-sram@d0000000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0000000 0x1000>;
>> +		};
>> +
>> +		shmem1: scmi-sram@d0001000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0001000 0x1000>;
>> +		};
>> +
>> +		shmem2: scmi-sram@d0002000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0002000 0x1000>;
>> +		};
>> +
>> +		shmem3: scmi-sram@d0003000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0003000 0x1000>;
>> +		};
>> +
>> +		shmem4: scmi-sram@d0004000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0004000 0x1000>;
>> +		};
>> +
>> +		shmem5: scmi-sram@d0005000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0005000 0x1000>;
>> +		};
>> +
>> +		shmem6: scmi-sram@d0006000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0006000 0x1000>;
>> +		};
>> +
>> +		shmem7: scmi-sram@d0007000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0007000 0x1000>;
>> +		};
>> +
>> +		shmem8: scmi-sram@d0008000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0008000 0x1000>;
>> +		};
>> +
>> +		shmem9: scmi-sram@d0009000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0009000 0x1000>;
>> +		};
>> +
>> +		shmem10: scmi-sram@d000a000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd000a000 0x1000>;
>> +		};
>> +
>> +		shmem11: scmi-sram@d000b000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd000b000 0x1000>;
>> +		};
>> +
>> +		shmem12: scmi-sram@d000c000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd000c000 0x1000>;
>> +		};
>> +
>> +		shmem13: scmi-sram@d000d000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd000d000 0x1000>;
>> +		};
>> +
>> +		shmem14: scmi-sram@d000e000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd000e000 0x1000>;
>> +		};
>> +
>> +		shmem15: scmi-sram@d000f000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd000f000 0x1000>;
>> +		};
>> +
>> +		shmem16: scmi-sram@d0010000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0010000 0x1000>;
>> +		};
>> +
>> +		shmem17: scmi-sram@d0011000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0011000 0x1000>;
>> +		};
>> +
>> +		shmem18: scmi-sram@d0012000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0012000 0x1000>;
>> +		};
>> +
>> +		shmem19: scmi-sram@d0013000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0013000 0x1000>;
>> +		};
>> +
>> +		shmem20: scmi-sram@d0014000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0014000 0x1000>;
>> +		};
>> +
>> +		shmem21: scmi-sram@d0015000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0015000 0x1000>;
>> +		};
>> +
>> +		shmem22: scmi-sram@d0016000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0016000 0x1000>;
>> +		};
>> +
>> +		shmem23: scmi-sram@d0017000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0017000 0x1000>;
>> +		};
>> +
>> +		shmem24: scmi-sram@d0018000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0018000 0x1000>;
>> +		};
>> +
>> +		shmem25: scmi-sram@d0019000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0019000 0x1000>;
>> +		};
>> +
>> +		shmem26: scmi-sram@d001a000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd001a000 0x1000>;
>> +		};
>> +
>> +		shmem27: scmi-sram@d001b000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd001b000 0x1000>;
>> +		};
>> +
>> +		shmem28: scmi-sram@d001c000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd001c000 0x1000>;
>> +		};
>> +
>> +		shmem29: scmi-sram@d001d000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd001d000 0x1000>;
>> +		};
>> +
>> +		shmem30: scmi-sram@d001e000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd001e000 0x1000>;
>> +		};
>> +
>> +		shmem31: scmi-sram@d001f000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd001f000 0x1000>;
>> +		};
>> +
>> +		shmem32: scmi-sram@d0020000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0020000 0x1000>;
>> +		};
>> +
>> +		shmem33: scmi-sram@d0021000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0021000 0x1000>;
>> +		};
>> +
>> +		shmem34: scmi-sram@d0022000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0022000 0x1000>;
>> +		};
>> +
>> +		shmem35: scmi-sram@d0023000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0023000 0x1000>;
>> +		};
>> +
>> +		shmem36: scmi-sram@d0024000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0024000 0x1000>;
>> +		};
>> +
>> +		shmem37: scmi-sram@d0025000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0025000 0x1000>;
>> +		};
>> +
>> +		shmem38: scmi-sram@d0026000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0026000 0x1000>;
>> +		};
>> +
>> +		shmem39: scmi-sram@d0027000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0027000 0x1000>;
>> +		};
>> +
>> +		shmem40: scmi-sram@d0028000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0028000 0x1000>;
>> +		};
>> +
>> +		shmem41: scmi-sram@d0029000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0029000 0x1000>;
>> +		};
>> +
>> +		shmem42: scmi-sram@d002a000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd002a000 0x1000>;
>> +		};
>> +
>> +		shmem43: scmi-sram@d002b000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd002b000 0x1000>;
>> +		};
>> +
>> +		shmem44: scmi-sram@d002c000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd002c000 0x1000>;
>> +		};
>> +
>> +		shmem45: scmi-sram@d002d000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd002d000 0x1000>;
>> +		};
>> +
>> +		shmem46: scmi-sram@d002e000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd002e000 0x1000>;
>> +		};
>> +
>> +		shmem47: scmi-sram@d002f000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd002f000 0x1000>;
>> +		};
>> +
>> +		shmem48: scmi-sram@d0030000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0030000 0x1000>;
>> +		};
>> +
>> +		shmem49: scmi-sram@d0031000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0031000 0x1000>;
>> +		};
>> +
>> +		shmem50: scmi-sram@d0032000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0032000 0x1000>;
>> +		};
>> +
>> +		shmem51: scmi-sram@d0033000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0033000 0x1000>;
>> +		};
>> +
>> +		shmem52: scmi-sram@d0034000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0034000 0x1000>;
>> +		};
>> +
>> +		shmem53: scmi-sram@d0035000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0035000 0x1000>;
>> +		};
>> +
>> +		shmem54: scmi-sram@d0036000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0036000 0x1000>;
>> +		};
>> +
>> +		shmem55: scmi-sram@d0037000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0037000 0x1000>;
>> +		};
>> +
>> +		shmem56: scmi-sram@d0038000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0038000 0x1000>;
>> +		};
>> +
>> +		shmem57: scmi-sram@d0039000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd0039000 0x1000>;
>> +		};
>> +
>> +		shmem58: scmi-sram@d003a000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd003a000 0x1000>;
>> +		};
>> +
>> +		shmem59: scmi-sram@d003b000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd003b000 0x1000>;
>> +		};
>> +
>> +		shmem60: scmi-sram@d003c000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd003c000 0x1000>;
>> +		};
>> +
>> +		shmem61: scmi-sram@d003d000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd003d000 0x1000>;
>> +		};
>> +
>> +		shmem62: scmi-sram@d003e000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd003e000 0x1000>;
>> +		};
>> +
>> +		shmem63: scmi-sram@d003f000 {
>> +			compatible = "arm,scmi-shmem";
>> +			reg = <0xd003f000 0x1000>;
>> +		};
>> +	};
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/sa8255p.dtsi b/arch/arm64/boot/dts/qcom/sa8255p.dtsi
>> new file mode 100644
>> index 000000000000..c354f76ffa5e
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sa8255p.dtsi
>> @@ -0,0 +1,2405 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/mailbox/qcom-ipcc.h>
>> +
>> +/ {
>> +	interrupt-parent = <&intc>;
>> +
>> +	#address-cells = <2>;
>> +	#size-cells = <2>;
>> +
>> +	clocks {
>> +		xo_board_clk: xo-board-clk {
>> +			compatible = "fixed-clock";
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		sleep_clk: sleep-clk {
>> +			compatible = "fixed-clock";
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		gpll0_board_clk: gpll0-board-clk {
>> +			compatible = "fixed-clock";
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		bi_tcxo_div2: bi-tcxo-div2-clk {
>> +			compatible = "fixed-factor-clock";
>> +			clocks = <&xo_board_clk>;
>> +			clock-mult = <1>;
>> +			clock-div = <2>;
>> +			#clock-cells = <0>;
>> +		};
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <2>;
>> +		#size-cells = <0>;
>> +
>> +		CPU0: cpu@0 {
> Lowercase label.
ACK!
>
> ...
>
> Best regards,
> Krzysztof
>

Re: [PATCH 22/22] arm64: dts: qcom: Add reduced functional DT for SA8255p Ride platform

[Krzysztof Kozlowski]

On 29/08/2024 21:06, Nikunj Kela wrote:
> 
> On 8/29/2024 12:49 AM, Krzysztof Kozlowski wrote:
>> On 28/08/2024 22:37, Nikunj Kela wrote:
>>> SA8255p Ride platform is an automotive virtual platform. This platform
>>> abstracts resources such as clocks, regulators etc. in the firmware VM.
>>> The device drivers request resources operations over SCMI using power,
>>> performance, reset and sensor protocols.
>>>
>>> Multiple virtual SCMI instances are being employed for greater parallelism.
>>> These instances are tied to devices such that devices can have dedicated
>>> SCMI channel. Firmware VM (runs SCMI platform stack) is SMP enabled and
>>> can process requests from agents in parallel. Qualcomm smc transport is
>>> used for communication between SCMI agent and platform.
>>>
>>> Let's add the reduced functional support for SA8255p Ride board.
>>> Subsequently, the support for PCIe, USB, UFS, Ethernet will be added.
>>>
>>> Co-developed-by: Shazad Hussain <quic_shazhuss@quicinc.com>
>>> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
>>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>>> ---
>>>  arch/arm64/boot/dts/qcom/Makefile           |    1 +
>>>  arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi |   80 +
>>>  arch/arm64/boot/dts/qcom/sa8255p-ride.dts   |  149 ++
>>>  arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi  | 2312 ++++++++++++++++++
>>>  arch/arm64/boot/dts/qcom/sa8255p.dtsi       | 2405 +++++++++++++++++++
>>>  5 files changed, 4947 insertions(+)
>>>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
>>>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts
>>>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi
>>>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi
>>>
>> ...
>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sa8255p-ride.dts b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts
>>> new file mode 100644
>>> index 000000000000..1dc03051ad92
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts
>>> @@ -0,0 +1,149 @@
>>> +// SPDX-License-Identifier: BSD-3-Clause
>>> +/*
>>> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>>> + */
>>> +
>>> +/dts-v1/;
>>> +
>>> +#include <dt-bindings/gpio/gpio.h>
>>> +
>>> +#include "sa8255p.dtsi"
>>> +#include "sa8255p-pmics.dtsi"
>>> +#include "sa8255p-scmi.dtsi"
>>> +
>>> +/ {
>>> +	model = "Qualcomm Technologies, Inc. SA8255P Ride";
>>> +	compatible = "qcom,sa8255p-ride", "qcom,sa8255p";
>>> +
>>> +	aliases {
>>> +		i2c11 = &i2c11;
>>> +		i2c18 = &i2c18;
>>> +		serial0 = &uart10;
>>> +		serial1 = &uart4;
>>> +		spi16 = &spi16;
>>> +		scmichannels = &scmichannels;
>> Nothing parses this.
>>
> We are using this alias in bootloader to speed up the parsing. Since we

Then please provide link to the bindings in this open-source upstream
bootloader.

Otherwise it is a clear no-go for me. We don't add properties because
some downstream wants them. Imagine what would happen if we opened that
can of worms...

> are using 64 SCMI instances and SCMI smc transport driver for
> Qualcomm(drivers/firmware/arm_scmi/transports/smc.c) expects
> cap-id(created by hypervisor at boot time), our bootloader gets those
> cap-id for each channel and populate them. This alias is an optimization
> to save boottime as in automotive, boot KPIs are critical.

I will refrain about commenting on KPIs...



Best regards,
Krzysztof

Re: [PATCH 22/22] arm64: dts: qcom: Add reduced functional DT for SA8255p Ride platform

[Nikunj Kela]

On 8/30/2024 2:51 AM, Krzysztof Kozlowski wrote:
> On 29/08/2024 21:06, Nikunj Kela wrote:
>> On 8/29/2024 12:49 AM, Krzysztof Kozlowski wrote:
>>> On 28/08/2024 22:37, Nikunj Kela wrote:
>>>> SA8255p Ride platform is an automotive virtual platform. This platform
>>>> abstracts resources such as clocks, regulators etc. in the firmware VM.
>>>> The device drivers request resources operations over SCMI using power,
>>>> performance, reset and sensor protocols.
>>>>
>>>> Multiple virtual SCMI instances are being employed for greater parallelism.
>>>> These instances are tied to devices such that devices can have dedicated
>>>> SCMI channel. Firmware VM (runs SCMI platform stack) is SMP enabled and
>>>> can process requests from agents in parallel. Qualcomm smc transport is
>>>> used for communication between SCMI agent and platform.
>>>>
>>>> Let's add the reduced functional support for SA8255p Ride board.
>>>> Subsequently, the support for PCIe, USB, UFS, Ethernet will be added.
>>>>
>>>> Co-developed-by: Shazad Hussain <quic_shazhuss@quicinc.com>
>>>> Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
>>>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>>>> ---
>>>>  arch/arm64/boot/dts/qcom/Makefile           |    1 +
>>>>  arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi |   80 +
>>>>  arch/arm64/boot/dts/qcom/sa8255p-ride.dts   |  149 ++
>>>>  arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi  | 2312 ++++++++++++++++++
>>>>  arch/arm64/boot/dts/qcom/sa8255p.dtsi       | 2405 +++++++++++++++++++
>>>>  5 files changed, 4947 insertions(+)
>>>>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
>>>>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts
>>>>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi
>>>>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi
>>>>
>>> ...
>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sa8255p-ride.dts b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts
>>>> new file mode 100644
>>>> index 000000000000..1dc03051ad92
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts
>>>> @@ -0,0 +1,149 @@
>>>> +// SPDX-License-Identifier: BSD-3-Clause
>>>> +/*
>>>> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
>>>> + */
>>>> +
>>>> +/dts-v1/;
>>>> +
>>>> +#include <dt-bindings/gpio/gpio.h>
>>>> +
>>>> +#include "sa8255p.dtsi"
>>>> +#include "sa8255p-pmics.dtsi"
>>>> +#include "sa8255p-scmi.dtsi"
>>>> +
>>>> +/ {
>>>> +	model = "Qualcomm Technologies, Inc. SA8255P Ride";
>>>> +	compatible = "qcom,sa8255p-ride", "qcom,sa8255p";
>>>> +
>>>> +	aliases {
>>>> +		i2c11 = &i2c11;
>>>> +		i2c18 = &i2c18;
>>>> +		serial0 = &uart10;
>>>> +		serial1 = &uart4;
>>>> +		spi16 = &spi16;
>>>> +		scmichannels = &scmichannels;
>>> Nothing parses this.
>>>
>> We are using this alias in bootloader to speed up the parsing. Since we
> Then please provide link to the bindings in this open-source upstream
> bootloader.
>
> Otherwise it is a clear no-go for me. We don't add properties because
> some downstream wants them. Imagine what would happen if we opened that
> can of worms...

Point taken! I will remove this alias and label from DT in next version.
We can add it back if/once the bootloader changes are upstreamed. Thanks!


>> are using 64 SCMI instances and SCMI smc transport driver for
>> Qualcomm(drivers/firmware/arm_scmi/transports/smc.c) expects
>> cap-id(created by hypervisor at boot time), our bootloader gets those
>> cap-id for each channel and populate them. This alias is an optimization
>> to save boottime as in automotive, boot KPIs are critical.
> I will refrain about commenting on KPIs...
>
>
>
> Best regards,
> Krzysztof
>

Re: [PATCH 00/22] arm64: qcom: Introduce SA8255p Ride platform

[Krzysztof Kozlowski]

On 28/08/2024 22:36, Nikunj Kela wrote:
> This series enables the support for SA8255p Qualcomm SoC and Ride
> platform. This platform uses SCMI power, reset, performance, sensor
> protocols for resources(e.g. clocks, regulator, interconnect, phy etc.)
> management. SA8255p is a virtual platforms that uses Qualcomm smc/hvc
> transport driver.
> 

Who is supposed to merge it? The Cc-list is quite enormous and I got now
20 bounces:

"    Too many recipients to the message"

at least drop some non-maintainer related, I counted 5-7 Qualcomm ones
which should not be needed.

Best regards,
Krzysztof

Re: [PATCH 00/22] arm64: qcom: Introduce SA8255p Ride platform

[Nikunj Kela]

On 8/29/2024 12:57 AM, Krzysztof Kozlowski wrote:
> On 28/08/2024 22:36, Nikunj Kela wrote:
>> This series enables the support for SA8255p Qualcomm SoC and Ride
>> platform. This platform uses SCMI power, reset, performance, sensor
>> protocols for resources(e.g. clocks, regulator, interconnect, phy etc.)
>> management. SA8255p is a virtual platforms that uses Qualcomm smc/hvc
>> transport driver.
>>
> Who is supposed to merge it? The Cc-list is quite enormous and I got now
> 20 bounces:
>
> "    Too many recipients to the message"
>
> at least drop some non-maintainer related, I counted 5-7 Qualcomm ones
> which should not be needed.
>
> Best regards,
> Krzysztof

Hi Krzysztof,

I ran maintainers script to get all the emails. I kept maintainers,
reviewers and "in file" ones in addition to some Qualcomm leads. I will
drop "in file" and Qualcomm leads in next version.

Thanks,

-Nikunj

[PATCH v2 00/21] arm64: qcom: Introduce SA8255p Ride platform

[Nikunj Kela]

This series enables the support for SA8255p Qualcomm SoC and Ride
platform. This platform uses SCMI power, reset, performance, sensor
protocols for resources(e.g. clocks, regulator, interconnect, phy etc.)
management. SA8255p is a virtual platforms that uses Qualcomm smc/hvc
transport driver.

Multiple virtual SCMI instances are being used to achieve the parallelism.
SCMI platform stack runs in SMP enabled VM hence allows platform to service
multiple resource requests in parallel. Each device is assigned its own
dedicated SCMI channel and Tx/Rx doorbells.

Resource operations are grouped together to achieve better abstraction
and to reduce the number of requests being sent to SCMI platform(server)
thus improving boot time KPIs. This design approach was presented during
LinaroConnect 2024 conference[1].

Architecture:
------------
                                                          +--------------------+
                                                          |   Shared Memory    |
                                                          |                    |
                                                          | +----------------+ |                +----------------------------------+
     +----------------------------+                     +-+->  ufs-shmem     <-+---+            |            Linux VM              |
     |        Firmware VM         |                     | | +----------------+ |   |            |   +----------+   +----------+    |
     |                            |                     | |                    |   |            |   |   UFS    |   |   PCIe   |    |
     | +---------+ f +----------+ |                     | |                    |   |            |   |  Driver  |   |  Driver  |    |
     | |Drivers  <---+  SCMI    | |        e            | |         |          |   |            |   +--+----^--+   +----------+    |
     | | (clks,  | g | Server   +-+---------------------+ |                    |   |            |      |    |                      |
     | |  vreg,  +--->          | |        h              |         |          |  b|k           |     a|   l|                      |
     | |  gpio,  |   +--^-----+-+ |                       |                    |   |            |      |    |                      |
     | |  phy,   |      |     |   |                       |         |          |   |            |  +---v----+----+  +----------+   |
     | |  etc.)  |      |     |   |                       |                    |   +------------+--+  UFS SCMI   |  | PCIe SCMI|   |
     | +---------+      |     |   |                       |                    |                |  |  INSTANCE   |  | INSTANCE |   |
     |                  |     |   |                       |  +---------------+ |                |  +-^-----+-----+  +----------+   |
     |                  |     |   |                       |  |  pcie-shmem   | |                |    |     |                       |
     +------------------+-----+---+                       |  +---------------+ |                +----+-----+-----------------------+
                        |     |                           |                    |                     |     |
                        |     |                           +--------------------+                     |     |
                       d|IRQ i|HVC                                                                  j|IRQ c|HVC
                        |     |                                                                      |     |
                        |     |                                                                      |     |
+-----------------------+-----v----------------------------------------------------------------------+-----v------------------------------+
|                                                                                                                                         |
|                                                                                                                                         |
|                                                                                                                                         |
|                                                               HYPERVISOR                                                                |
|                                                                                                                                         |
|                                                                                                                                         |
+-----------------------------------------------------------------------------------------------------------------------------------------+

        +--------+   +--------+                                                                         +----------+  +-----------+
        | CLOCK  |   |  PHY   |                                                                         |   UFS    |  |   PCIe    |
        +--------+   +--------+                                                                         +----------+  +-----------+


This series is based on next-20240903.

[1]: https://resources.linaro.org/en/resource/wfnfEwBhRjLV1PEAJoDDte

---
Changes in v2:
  - Patch 1/21 - 11/21
    - Added Reviewed-by tag

  - Patch 12/21
    - Already applied in the maintainers tree

  - Patch 13/21
    - Modified subject line
    - Fixed schema to include fallback

  - Patch 14/21
    - Added constraints

  - Patch 15/21
    - Modified schema to remove useless text
   
  - Patch 16/21
    - Modified schema formatting
    - Amended schema definition as advised

  - Patch 17/21
    - Moved allOf block after required
    - Fixed formatting
    - Modified schema to remove useless text

  - Patch 18/21
    - Fixed clock property changes

  - Patch 19/21
    - Fixed scmi nodename pattern

  - Patch 20/21
    - Modified subject line and description
    - Added EPPI macro

  - Patch 21/21
    - Removed scmichannels label and alias
    - Modified scmi node name to conform to schema
    - Moved status property to be the last one in scmi instances
    - Changed to lower case for cpu labels
    - Added fallback compatible for tlmm node

Nikunj Kela (21):
  dt-bindings: arm: qcom: add the SoC ID for SA8255P
  soc: qcom: socinfo: add support for SA8255P
  dt-bindings: arm: qcom: add SA8255p Ride board
  dt-bindings: firmware: qcom,scm: document support for SA8255p
  dt-bindings: mailbox: qcom-ipcc: document the support for SA8255p
  dt-bindings: watchdog: qcom-wdt: document support on SA8255p
  dt-bindings: crypto: qcom,prng: document support for SA8255p
  dt-bindings: interrupt-controller: qcom-pdc: document support for
    SA8255p
  dt-bindings: soc: qcom: aoss-qmp: document support for SA8255p
  dt-bindings: arm-smmu: document the support on SA8255p
  dt-bindings: mfd: qcom,tcsr: document support for SA8255p
  dt-bindings: thermal: tsens: document support on SA8255p
  dt-bindings: pinctrl: Add SA8255p TLMM
  dt-bindings: cpufreq: qcom-hw: document support for SA8255p
  dt-bindings: i2c: document support for SA8255p
  dt-bindings: spi: document support for SA8255p
  dt-bindings: serial: document support for SA8255p
  dt-bindings: qcom: geni-se: document support for SA8255P
  dt-bindings: firmware: arm,scmi: allow multiple virtual instances
  dt-bindings: arm: GIC: add ESPI and EPPI specifiers
  arm64: dts: qcom: Add reduced functional DT for SA8255p Ride platform

 .../devicetree/bindings/arm/qcom.yaml         |    6 +
 .../bindings/cpufreq/cpufreq-qcom-hw.yaml     |   16 +
 .../devicetree/bindings/crypto/qcom,prng.yaml |    1 +
 .../bindings/firmware/arm,scmi.yaml           |    2 +-
 .../bindings/firmware/qcom,scm.yaml           |    2 +
 .../bindings/i2c/qcom,i2c-geni-qcom.yaml      |   33 +-
 .../interrupt-controller/qcom,pdc.yaml        |    1 +
 .../devicetree/bindings/iommu/arm,smmu.yaml   |    3 +
 .../bindings/mailbox/qcom-ipcc.yaml           |    1 +
 .../devicetree/bindings/mfd/qcom,tcsr.yaml    |    1 +
 .../bindings/pinctrl/qcom,sa8775p-tlmm.yaml   |    8 +-
 .../serial/qcom,serial-geni-qcom.yaml         |   53 +-
 .../bindings/soc/qcom/qcom,aoss-qmp.yaml      |    1 +
 .../bindings/soc/qcom/qcom,geni-se.yaml       |   45 +-
 .../bindings/spi/qcom,spi-geni-qcom.yaml      |   60 +-
 .../bindings/thermal/qcom-tsens.yaml          |    1 +
 .../bindings/watchdog/qcom-wdt.yaml           |    1 +
 arch/arm64/boot/dts/qcom/Makefile             |    1 +
 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi   |   80 +
 arch/arm64/boot/dts/qcom/sa8255p-ride.dts     |  148 +
 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi    | 2312 ++++++++++++++++
 arch/arm64/boot/dts/qcom/sa8255p.dtsi         | 2405 +++++++++++++++++
 drivers/soc/qcom/socinfo.c                    |    1 +
 include/dt-bindings/arm/qcom,ids.h            |    1 +
 .../interrupt-controller/arm-gic.h            |    2 +
 25 files changed, 5169 insertions(+), 16 deletions(-)
 create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi


base-commit: 6804f0edbe7747774e6ae60f20cec4ee3ad7c187
-- 
2.34.1

[PATCH v2 01/21] dt-bindings: arm: qcom: add the SoC ID for SA8255P

[Nikunj Kela]

Add the SoC ID entry for SA8255P.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 include/dt-bindings/arm/qcom,ids.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h
index 8332f8d82f96..16f00ecdcc09 100644
--- a/include/dt-bindings/arm/qcom,ids.h
+++ b/include/dt-bindings/arm/qcom,ids.h
@@ -257,6 +257,7 @@
 #define QCOM_ID_QRB2210			524
 #define QCOM_ID_SM8475			530
 #define QCOM_ID_SM8475P			531
+#define QCOM_ID_SA8255P			532
 #define QCOM_ID_SA8775P			534
 #define QCOM_ID_QRU1000			539
 #define QCOM_ID_SM8475_2		540
-- 
2.34.1

[PATCH v2 02/21] soc: qcom: socinfo: add support for SA8255P

[Nikunj Kela]

Add SocInfo support for SA8255P.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 drivers/soc/qcom/socinfo.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c
index 24c3971f2ef1..5c3bd59eaa69 100644
--- a/drivers/soc/qcom/socinfo.c
+++ b/drivers/soc/qcom/socinfo.c
@@ -424,6 +424,7 @@ static const struct soc_id soc_id[] = {
 	{ qcom_board_id(QRB2210) },
 	{ qcom_board_id(SM8475) },
 	{ qcom_board_id(SM8475P) },
+	{ qcom_board_id(SA8255P) },
 	{ qcom_board_id(SA8775P) },
 	{ qcom_board_id(QRU1000) },
 	{ qcom_board_id(SM8475_2) },
-- 
2.34.1

[PATCH v2 03/21] dt-bindings: arm: qcom: add SA8255p Ride board

[Nikunj Kela]

Document the SA8255p SoC and its reference board: sa8255p-ride.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 5cb54d69af0b..07dd68f07845 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -50,6 +50,7 @@ description: |
         qrb4210
         qru1000
         sa8155p
+        sa8255p
         sa8540p
         sa8775p
         sc7180
@@ -900,6 +901,11 @@ properties:
               - qcom,sa8155p-adp
           - const: qcom,sa8155p
 
+      - items:
+          - enum:
+              - qcom,sa8255p-ride
+          - const: qcom,sa8255p
+
       - items:
           - enum:
               - qcom,sa8295p-adp
-- 
2.34.1

[PATCH v2 04/21] dt-bindings: firmware: qcom,scm: document support for SA8255p

[Nikunj Kela]

Add a compatible for the SA8255p platform's Secure Channel Manager
firmware interface.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
index 2cc83771d8e7..65057f5c8972 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml
@@ -43,6 +43,7 @@ properties:
           - qcom,scm-msm8998
           - qcom,scm-qcm2290
           - qcom,scm-qdu1000
+          - qcom,scm-sa8255p
           - qcom,scm-sa8775p
           - qcom,scm-sc7180
           - qcom,scm-sc7280
@@ -204,6 +205,7 @@ allOf:
           compatible:
             contains:
               enum:
+                - qcom,scm-sa8255p
                 - qcom,scm-sa8775p
     then:
       properties:
-- 
2.34.1

[PATCH v2 05/21] dt-bindings: mailbox: qcom-ipcc: document the support for SA8255p

[Nikunj Kela]

Add a compatible for the ipcc on SA8255p platforms.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
index 05e4e1d51713..bc108b8db9f4 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
@@ -25,6 +25,7 @@ properties:
     items:
       - enum:
           - qcom,qdu1000-ipcc
+          - qcom,sa8255p-ipcc
           - qcom,sa8775p-ipcc
           - qcom,sc7280-ipcc
           - qcom,sc8280xp-ipcc
-- 
2.34.1

[PATCH v2 06/21] dt-bindings: watchdog: qcom-wdt: document support on SA8255p

[Nikunj Kela]

Add a compatible for the SA8255p platform's KPSS watchdog.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
index 47587971fb0b..932393f8c649 100644
--- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
@@ -26,6 +26,7 @@ properties:
               - qcom,apss-wdt-msm8994
               - qcom,apss-wdt-qcm2290
               - qcom,apss-wdt-qcs404
+              - qcom,apss-wdt-sa8255p
               - qcom,apss-wdt-sa8775p
               - qcom,apss-wdt-sc7180
               - qcom,apss-wdt-sc7280
-- 
2.34.1

[PATCH v2 07/21] dt-bindings: crypto: qcom,prng: document support for SA8255p

[Nikunj Kela]

Document SA8255p compatible for the True Random Number Generator.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
index 89c88004b41b..048b769a73c0 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml
@@ -17,6 +17,7 @@ properties:
           - qcom,prng-ee  # 8996 and later using EE
       - items:
           - enum:
+              - qcom,sa8255p-trng
               - qcom,sa8775p-trng
               - qcom,sc7280-trng
               - qcom,sm8450-trng
-- 
2.34.1

[PATCH v2 08/21] dt-bindings: interrupt-controller: qcom-pdc: document support for SA8255p

[Nikunj Kela]

Add compatible for pdc interrupt controller representing support on
SA8255p.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 .../devicetree/bindings/interrupt-controller/qcom,pdc.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
index 985fa10abb99..b1ea08a41bb0 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
@@ -27,6 +27,7 @@ properties:
     items:
       - enum:
           - qcom,qdu1000-pdc
+          - qcom,sa8255p-pdc
           - qcom,sa8775p-pdc
           - qcom,sc7180-pdc
           - qcom,sc7280-pdc
-- 
2.34.1

[PATCH v2 09/21] dt-bindings: soc: qcom: aoss-qmp: document support for SA8255p

[Nikunj Kela]

Add compatible for AOSS QMP representing support on SA8255p.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
index 7afdb60edb22..bd873e7e4ae5 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
@@ -26,6 +26,7 @@ properties:
     items:
       - enum:
           - qcom,qdu1000-aoss-qmp
+          - qcom,sa8255p-aoss-qmp
           - qcom,sa8775p-aoss-qmp
           - qcom,sc7180-aoss-qmp
           - qcom,sc7280-aoss-qmp
-- 
2.34.1

[PATCH v2 10/21] dt-bindings: arm-smmu: document the support on SA8255p

[Nikunj Kela]

Add compatible for smmu representing support on SA8255p.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index 280b4e49f219..3353c2d37841 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -37,6 +37,7 @@ properties:
           - enum:
               - qcom,qcm2290-smmu-500
               - qcom,qdu1000-smmu-500
+              - qcom,sa8255p-smmu-500
               - qcom,sa8775p-smmu-500
               - qcom,sc7180-smmu-500
               - qcom,sc7280-smmu-500
@@ -84,6 +85,7 @@ properties:
         items:
           - enum:
               - qcom,qcm2290-smmu-500
+              - qcom,sa8255p-smmu-500
               - qcom,sa8775p-smmu-500
               - qcom,sc7280-smmu-500
               - qcom,sc8180x-smmu-500
@@ -553,6 +555,7 @@ allOf:
               - marvell,ap806-smmu-500
               - nvidia,smmu-500
               - qcom,qdu1000-smmu-500
+              - qcom,sa8255p-smmu-500
               - qcom,sc7180-smmu-500
               - qcom,sdm670-smmu-500
               - qcom,sdm845-smmu-500
-- 
2.34.1

[PATCH v2 11/21] dt-bindings: mfd: qcom,tcsr: document support for SA8255p

[Nikunj Kela]

Add compatible for tcsr representing support on SA8255p SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
index c6bd14ec5aa0..88f804bd7581 100644
--- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
+++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
@@ -21,6 +21,7 @@ properties:
           - qcom,msm8998-tcsr
           - qcom,qcm2290-tcsr
           - qcom,qcs404-tcsr
+          - qcom,sa8255p-tcsr
           - qcom,sc7180-tcsr
           - qcom,sc7280-tcsr
           - qcom,sc8280xp-tcsr
-- 
2.34.1

[PATCH v2 12/21] dt-bindings: thermal: tsens: document support on SA8255p

[Nikunj Kela]

Add compatible for sensors representing support on SA8255p.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
index 72048c5a0412..d45690d6a465 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
@@ -51,6 +51,7 @@ properties:
               - qcom,msm8996-tsens
               - qcom,msm8998-tsens
               - qcom,qcm2290-tsens
+              - qcom,sa8255p-tsens
               - qcom,sa8775p-tsens
               - qcom,sc7180-tsens
               - qcom,sc7280-tsens
-- 
2.34.1

Re: [PATCH v2 12/21] dt-bindings: thermal: tsens: document support on SA8255p

[Daniel Lezcano]

On 04/09/2024 00:02, Nikunj Kela wrote:
> Add compatible for sensors representing support on SA8255p.
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---

Applied, thanks


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[PATCH v2 13/21] dt-bindings: pinctrl: Add SA8255p TLMM

[Nikunj Kela]

Add compatible for TLMM block representing support on SA8255p.

SA8255p uses the same TLMM block as SA8775p however the ownership
of pins are split between Firmware VM and Linux VM on SA8255p. For
example, pins used by UART are owned and configured by Firmware VM
while pins used by ethernet are owned and configured by Linux VM.
Therefore, adding a sa8255p specific compatible to mark the difference.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 .../devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml    | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml
index e9abbf2c0689..b36b29dd3128 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml
@@ -17,7 +17,13 @@ allOf:
 
 properties:
   compatible:
-    const: qcom,sa8775p-tlmm
+    oneOf:
+      - items:
+        - enum:
+          - qcom,sa8255p-tlmm
+        - const: qcom,sa8775p-tlmm
+      - items:
+        - const: qcom,sa8775p-tlmm
 
   reg:
     maxItems: 1
-- 
2.34.1

Re: [PATCH v2 13/21] dt-bindings: pinctrl: Add SA8255p TLMM

[Rob Herring (Arm)]

On Tue, 03 Sep 2024 15:02:32 -0700, Nikunj Kela wrote:
> Add compatible for TLMM block representing support on SA8255p.
> 
> SA8255p uses the same TLMM block as SA8775p however the ownership
> of pins are split between Firmware VM and Linux VM on SA8255p. For
> example, pins used by UART are owned and configured by Firmware VM
> while pins used by ethernet are owned and configured by Linux VM.
> Therefore, adding a sa8255p specific compatible to mark the difference.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  .../devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml    | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:
./Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml:22:9: [warning] wrong indentation: expected 10 but found 8 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml:23:11: [warning] wrong indentation: expected 12 but found 10 (indentation)
./Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml:26:9: [warning] wrong indentation: expected 10 but found 8 (indentation)

dtschema/dtc warnings/errors:

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20240903220240.2594102-14-quic_nkela@quicinc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

[PATCH v2 14/21] dt-bindings: cpufreq: qcom-hw: document support for SA8255p

[Nikunj Kela]

Add compatible for the cpufreq engine representing support on SA8255p.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 .../bindings/cpufreq/cpufreq-qcom-hw.yaml        | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
index 1e9797f96410..84865e553c8b 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
@@ -34,6 +34,7 @@ properties:
         items:
           - enum:
               - qcom,qdu1000-cpufreq-epss
+              - qcom,sa8255p-cpufreq-epss
               - qcom,sa8775p-cpufreq-epss
               - qcom,sc7280-cpufreq-epss
               - qcom,sc8280xp-cpufreq-epss
@@ -206,6 +207,21 @@ allOf:
         interrupt-names:
           minItems: 2
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sa8255p-cpufreq-epss
+    then:
+      properties:
+        reg:
+          minItems: 2
+          maxItems: 2
+
+        reg-names:
+          minItems: 2
+          maxItems: 2
 
 examples:
   - |
-- 
2.34.1

Re: [PATCH v2 14/21] dt-bindings: cpufreq: qcom-hw: document support for SA8255p

[Krzysztof Kozlowski]

On Tue, Sep 03, 2024 at 03:02:33PM -0700, Nikunj Kela wrote:
> Add compatible for the cpufreq engine representing support on SA8255p.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  .../bindings/cpufreq/cpufreq-qcom-hw.yaml        | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
> index 1e9797f96410..84865e553c8b 100644
> --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
> @@ -34,6 +34,7 @@ properties:
>          items:
>            - enum:
>                - qcom,qdu1000-cpufreq-epss
> +              - qcom,sa8255p-cpufreq-epss
>                - qcom,sa8775p-cpufreq-epss
>                - qcom,sc7280-cpufreq-epss
>                - qcom,sc8280xp-cpufreq-epss
> @@ -206,6 +207,21 @@ allOf:
>          interrupt-names:
>            minItems: 2
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,sa8255p-cpufreq-epss
> +    then:
> +      properties:
> +        reg:
> +          minItems: 2
> +          maxItems: 2
> +
> +        reg-names:
> +          minItems: 2
> +          maxItems: 2

What about interrupts? You need to constrain each of such lists.

Best regards,
Krzysztof

Re: [PATCH v2 14/21] dt-bindings: cpufreq: qcom-hw: document support for SA8255p

[Nikunj Kela]

On 9/3/2024 11:26 PM, Krzysztof Kozlowski wrote:
> On Tue, Sep 03, 2024 at 03:02:33PM -0700, Nikunj Kela wrote:
>> Add compatible for the cpufreq engine representing support on SA8255p.
>>
>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>> ---
>>  .../bindings/cpufreq/cpufreq-qcom-hw.yaml        | 16 ++++++++++++++++
>>  1 file changed, 16 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
>> index 1e9797f96410..84865e553c8b 100644
>> --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
>> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
>> @@ -34,6 +34,7 @@ properties:
>>          items:
>>            - enum:
>>                - qcom,qdu1000-cpufreq-epss
>> +              - qcom,sa8255p-cpufreq-epss
>>                - qcom,sa8775p-cpufreq-epss
>>                - qcom,sc7280-cpufreq-epss
>>                - qcom,sc8280xp-cpufreq-epss
>> @@ -206,6 +207,21 @@ allOf:
>>          interrupt-names:
>>            minItems: 2
>>  
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            enum:
>> +              - qcom,sa8255p-cpufreq-epss
>> +    then:
>> +      properties:
>> +        reg:
>> +          minItems: 2
>> +          maxItems: 2
>> +
>> +        reg-names:
>> +          minItems: 2
>> +          maxItems: 2
> What about interrupts? You need to constrain each of such lists.
>
> Best regards,
> Krzysztof

Interrupts are not required, I still need to put constraints for
interrupts? BTW, there is no if block for SA8775p binding in this file.

Thanks,

-Nikunj

Re: [PATCH v2 14/21] dt-bindings: cpufreq: qcom-hw: document support for SA8255p

[Krzysztof Kozlowski]

On 04/09/2024 14:27, Nikunj Kela wrote:
> 
> On 9/3/2024 11:26 PM, Krzysztof Kozlowski wrote:
>> On Tue, Sep 03, 2024 at 03:02:33PM -0700, Nikunj Kela wrote:
>>> Add compatible for the cpufreq engine representing support on SA8255p.
>>>
>>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>>> ---
>>>  .../bindings/cpufreq/cpufreq-qcom-hw.yaml        | 16 ++++++++++++++++
>>>  1 file changed, 16 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
>>> index 1e9797f96410..84865e553c8b 100644
>>> --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
>>> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
>>> @@ -34,6 +34,7 @@ properties:
>>>          items:
>>>            - enum:
>>>                - qcom,qdu1000-cpufreq-epss
>>> +              - qcom,sa8255p-cpufreq-epss
>>>                - qcom,sa8775p-cpufreq-epss
>>>                - qcom,sc7280-cpufreq-epss
>>>                - qcom,sc8280xp-cpufreq-epss
>>> @@ -206,6 +207,21 @@ allOf:
>>>          interrupt-names:
>>>            minItems: 2
>>>  
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            enum:
>>> +              - qcom,sa8255p-cpufreq-epss
>>> +    then:
>>> +      properties:
>>> +        reg:
>>> +          minItems: 2
>>> +          maxItems: 2
>>> +
>>> +        reg-names:
>>> +          minItems: 2
>>> +          maxItems: 2
>> What about interrupts? You need to constrain each of such lists.
>>
>> Best regards,
>> Krzysztof
> 
> Interrupts are not required, I still need to put constraints for

It's irrelevant whether they are required or not. Each property should
be narrowed.

> interrupts? BTW, there is no if block for SA8775p binding in this file.



Best regards,
Krzysztof

Re: [PATCH v2 14/21] dt-bindings: cpufreq: qcom-hw: document support for SA8255p

[Nikunj Kela]

On 9/4/2024 6:17 AM, Krzysztof Kozlowski wrote:
> On 04/09/2024 14:27, Nikunj Kela wrote:
>> On 9/3/2024 11:26 PM, Krzysztof Kozlowski wrote:
>>> On Tue, Sep 03, 2024 at 03:02:33PM -0700, Nikunj Kela wrote:
>>>> Add compatible for the cpufreq engine representing support on SA8255p.
>>>>
>>>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>>>> ---
>>>>  .../bindings/cpufreq/cpufreq-qcom-hw.yaml        | 16 ++++++++++++++++
>>>>  1 file changed, 16 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
>>>> index 1e9797f96410..84865e553c8b 100644
>>>> --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
>>>> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
>>>> @@ -34,6 +34,7 @@ properties:
>>>>          items:
>>>>            - enum:
>>>>                - qcom,qdu1000-cpufreq-epss
>>>> +              - qcom,sa8255p-cpufreq-epss
>>>>                - qcom,sa8775p-cpufreq-epss
>>>>                - qcom,sc7280-cpufreq-epss
>>>>                - qcom,sc8280xp-cpufreq-epss
>>>> @@ -206,6 +207,21 @@ allOf:
>>>>          interrupt-names:
>>>>            minItems: 2
>>>>  
>>>> +  - if:
>>>> +      properties:
>>>> +        compatible:
>>>> +          contains:
>>>> +            enum:
>>>> +              - qcom,sa8255p-cpufreq-epss
>>>> +    then:
>>>> +      properties:
>>>> +        reg:
>>>> +          minItems: 2
>>>> +          maxItems: 2
>>>> +
>>>> +        reg-names:
>>>> +          minItems: 2
>>>> +          maxItems: 2
>>> What about interrupts? You need to constrain each of such lists.
>>>
>>> Best regards,
>>> Krzysztof
>> Interrupts are not required, I still need to put constraints for
> It's irrelevant whether they are required or not. Each property should
> be narrowed.

So evenif we don't use interrupts property in our DT(patch#21), we need
to mention interrupts here? You suggest we put interrupts with maxItems: 0?

I wonder why SA8775p compatible is not in constraint list..

>> interrupts? BTW, there is no if block for SA8775p binding in this file.
>
>
> Best regards,
> Krzysztof
>

Re: [PATCH v2 14/21] dt-bindings: cpufreq: qcom-hw: document support for SA8255p

[Krzysztof Kozlowski]

On 04/09/2024 16:19, Nikunj Kela wrote:
> 
> On 9/4/2024 6:17 AM, Krzysztof Kozlowski wrote:
>> On 04/09/2024 14:27, Nikunj Kela wrote:
>>> On 9/3/2024 11:26 PM, Krzysztof Kozlowski wrote:
>>>> On Tue, Sep 03, 2024 at 03:02:33PM -0700, Nikunj Kela wrote:
>>>>> Add compatible for the cpufreq engine representing support on SA8255p.
>>>>>
>>>>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>>>>> ---
>>>>>  .../bindings/cpufreq/cpufreq-qcom-hw.yaml        | 16 ++++++++++++++++
>>>>>  1 file changed, 16 insertions(+)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
>>>>> index 1e9797f96410..84865e553c8b 100644
>>>>> --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
>>>>> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
>>>>> @@ -34,6 +34,7 @@ properties:
>>>>>          items:
>>>>>            - enum:
>>>>>                - qcom,qdu1000-cpufreq-epss
>>>>> +              - qcom,sa8255p-cpufreq-epss
>>>>>                - qcom,sa8775p-cpufreq-epss
>>>>>                - qcom,sc7280-cpufreq-epss
>>>>>                - qcom,sc8280xp-cpufreq-epss
>>>>> @@ -206,6 +207,21 @@ allOf:
>>>>>          interrupt-names:
>>>>>            minItems: 2
>>>>>  
>>>>> +  - if:
>>>>> +      properties:
>>>>> +        compatible:
>>>>> +          contains:
>>>>> +            enum:
>>>>> +              - qcom,sa8255p-cpufreq-epss
>>>>> +    then:
>>>>> +      properties:
>>>>> +        reg:
>>>>> +          minItems: 2
>>>>> +          maxItems: 2
>>>>> +
>>>>> +        reg-names:
>>>>> +          minItems: 2
>>>>> +          maxItems: 2
>>>> What about interrupts? You need to constrain each of such lists.
>>>>
>>>> Best regards,
>>>> Krzysztof
>>> Interrupts are not required, I still need to put constraints for
>> It's irrelevant whether they are required or not. Each property should
>> be narrowed.
> 
> So evenif we don't use interrupts property in our DT(patch#21), we need
> to mention interrupts here? You suggest we put interrupts with maxItems: 0?

I don't understand. You use three quite separate statements. "Not
required", "don't use" and here "maxItems: 0" which means not allowed.

All of these mean something else and I keep guessing and responding
according to what you write. Probably half of my advises are just trash,
because it turns out it is something entirely else than what I read.

Make a decision how the hardware looks like.

> 
> I wonder why SA8775p compatible is not in constraint list..
> 
>>> interrupts? BTW, there is no if block for SA8775p binding in this file.
>>
>>
>> Best regards,
>> Krzysztof
>>

Best regards,
Krzysztof

[PATCH v2 15/21] dt-bindings: i2c: document support for SA8255p

[Nikunj Kela]

Add compatible representing i2c support on SA8255p.

Clocks and interconnects are being configured in Firmware VM
on SA8255p, therefore making them optional.

CC: Praveen Talari <quic_ptalari@quicinc.com>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 .../bindings/i2c/qcom,i2c-geni-qcom.yaml      | 33 +++++++++++++++++--
 1 file changed, 31 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
index 9f66a3bb1f80..b477fae734b6 100644
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
@@ -15,6 +15,7 @@ properties:
     enum:
       - qcom,geni-i2c
       - qcom,geni-i2c-master-hub
+      - qcom,sa8255p-geni-i2c
 
   clocks:
     minItems: 1
@@ -69,8 +70,6 @@ properties:
 required:
   - compatible
   - interrupts
-  - clocks
-  - clock-names
   - reg
 
 allOf:
@@ -81,6 +80,10 @@ allOf:
           contains:
             const: qcom,geni-i2c-master-hub
     then:
+      required:
+        - clocks
+        - clock-names
+
       properties:
         clocks:
           minItems: 2
@@ -100,7 +103,21 @@ allOf:
           items:
             - const: qup-core
             - const: qup-config
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: qcom,sa8255p-geni-i2c
+    then:
+      required:
+        - power-domains
+
     else:
+      required:
+        - clocks
+        - clock-names
+
       properties:
         clocks:
           maxItems: 1
@@ -143,4 +160,16 @@ examples:
         power-domains = <&rpmhpd SC7180_CX>;
         required-opps = <&rpmhpd_opp_low_svs>;
     };
+
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    i2c@a90000 {
+        compatible = "qcom,sa8255p-geni-i2c";
+        reg = <0xa90000 0x4000>;
+        interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        power-domains = <&scmi9_pd 11>;
+    };
 ...
-- 
2.34.1

Re: [PATCH v2 15/21] dt-bindings: i2c: document support for SA8255p

[Krzysztof Kozlowski]

On Tue, Sep 03, 2024 at 03:02:34PM -0700, Nikunj Kela wrote:
> Add compatible representing i2c support on SA8255p.
> 
> Clocks and interconnects are being configured in Firmware VM
> on SA8255p, therefore making them optional.
> 
> CC: Praveen Talari <quic_ptalari@quicinc.com>
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  .../bindings/i2c/qcom,i2c-geni-qcom.yaml      | 33 +++++++++++++++++--
>  1 file changed, 31 insertions(+), 2 deletions(-)
> 

I don't know what to do with this patch. Using specific compatibles next
to generic compatible is just wrong, although mistake was probably
allowing generic compatible. The patch does not explain the differences
in interface which would explain why devices are not compatible. In the
same time my advice of separate binding was not followed, because maybe
these devices are compatible? But then it should be expressed...

You have entire commit msg to explain what and why.

> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
> index 9f66a3bb1f80..b477fae734b6 100644
> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
> @@ -15,6 +15,7 @@ properties:
>      enum:
>        - qcom,geni-i2c
>        - qcom,geni-i2c-master-hub
> +      - qcom,sa8255p-geni-i2c
>  
>    clocks:
>      minItems: 1
> @@ -69,8 +70,6 @@ properties:
>  required:
>    - compatible
>    - interrupts
> -  - clocks
> -  - clock-names
>    - reg
>  
>  allOf:
> @@ -81,6 +80,10 @@ allOf:
>            contains:
>              const: qcom,geni-i2c-master-hub
>      then:
> +      required:
> +        - clocks
> +        - clock-names


So it is required here?

> +
>        properties:
>          clocks:
>            minItems: 2
> @@ -100,7 +103,21 @@ allOf:
>            items:
>              - const: qup-core
>              - const: qup-config
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: qcom,sa8255p-geni-i2c
> +    then:
> +      required:
> +        - power-domains
> +

And possible here? I assume with the same clocks? The same for
interconnects - same values are valid?

>      else:
> +      required:
> +        - clocks
> +        - clock-names

And clocks are required again?

> +
>        properties:
>          clocks:
>            maxItems: 1

Eeee? So now all other variants have max 1 clock?

Nope, this wasn't ever tested on real DTS.

Best regards,
Krzysztof

Re: [PATCH v2 15/21] dt-bindings: i2c: document support for SA8255p

[Nikunj Kela]

On 9/3/2024 11:31 PM, Krzysztof Kozlowski wrote:
> On Tue, Sep 03, 2024 at 03:02:34PM -0700, Nikunj Kela wrote:
>> Add compatible representing i2c support on SA8255p.
>>
>> Clocks and interconnects are being configured in Firmware VM
>> on SA8255p, therefore making them optional.
>>
>> CC: Praveen Talari <quic_ptalari@quicinc.com>
>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>> ---
>>  .../bindings/i2c/qcom,i2c-geni-qcom.yaml      | 33 +++++++++++++++++--
>>  1 file changed, 31 insertions(+), 2 deletions(-)
>>
> I don't know what to do with this patch. Using specific compatibles next
> to generic compatible is just wrong, although mistake was probably
> allowing generic compatible. The patch does not explain the differences
> in interface which would explain why devices are not compatible.

I mentioned in the description that clocks and interconnects on this
platform are configured in Firmware VM(over SCMI using power and perf
domains) therefore this is not compatible with existing generic compatible.


>  In the
> same time my advice of separate binding was not followed, because maybe
> these devices are compatible? But then it should be expressed...

Sorry, I missed that. You want me to use 'oneOf' expression with this
compatible?


>
> You have entire commit msg to explain what and why.

Will put more details in description.


>> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
>> index 9f66a3bb1f80..b477fae734b6 100644
>> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
>> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
>> @@ -15,6 +15,7 @@ properties:
>>      enum:
>>        - qcom,geni-i2c
>>        - qcom,geni-i2c-master-hub
>> +      - qcom,sa8255p-geni-i2c
>>  
>>    clocks:
>>      minItems: 1
>> @@ -69,8 +70,6 @@ properties:
>>  required:
>>    - compatible
>>    - interrupts
>> -  - clocks
>> -  - clock-names
>>    - reg
>>  
>>  allOf:
>> @@ -81,6 +80,10 @@ allOf:
>>            contains:
>>              const: qcom,geni-i2c-master-hub
>>      then:
>> +      required:
>> +        - clocks
>> +        - clock-names
>
> So it is required here?

We are removing clocks from generic required list and enforcing rules
for all compatibles other than sa8255p.


>> +
>>        properties:
>>          clocks:
>>            minItems: 2
>> @@ -100,7 +103,21 @@ allOf:
>>            items:
>>              - const: qup-core
>>              - const: qup-config
>> +
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            const: qcom,sa8255p-geni-i2c
>> +    then:
>> +      required:
>> +        - power-domains
>> +
> And possible here? I assume with the same clocks? The same for
> interconnects - same values are valid?

I guess I need to put here the same description as in the cover letter
to make it more clear. We are not using clocks and interconnects in this
platform in Linux. Instead, sending request to Firmware VM over
SCMI(using power and perf protocols)


>
>>      else:
>> +      required:
>> +        - clocks
>> +        - clock-names
> And clocks are required again?
Explained above.
>> +
>>        properties:
>>          clocks:
>>            maxItems: 1
> Eeee? So now all other variants have max 1 clock?

I will make if block for sa8255p up so else is not applied to rest of
the platforms.


>
> Nope, this wasn't ever tested on real DTS.

This is tested on SA8255p DTS and I ran DT schema check on SA8775p DT as
well.


>
> Best regards,
> Krzysztof
>

Re: [PATCH v2 15/21] dt-bindings: i2c: document support for SA8255p

[Krzysztof Kozlowski]

On 04/09/2024 14:41, Nikunj Kela wrote:
> 
> On 9/3/2024 11:31 PM, Krzysztof Kozlowski wrote:
>> On Tue, Sep 03, 2024 at 03:02:34PM -0700, Nikunj Kela wrote:
>>> Add compatible representing i2c support on SA8255p.
>>>
>>> Clocks and interconnects are being configured in Firmware VM
>>> on SA8255p, therefore making them optional.
>>>
>>> CC: Praveen Talari <quic_ptalari@quicinc.com>
>>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>>> ---
>>>  .../bindings/i2c/qcom,i2c-geni-qcom.yaml      | 33 +++++++++++++++++--
>>>  1 file changed, 31 insertions(+), 2 deletions(-)
>>>
>> I don't know what to do with this patch. Using specific compatibles next
>> to generic compatible is just wrong, although mistake was probably
>> allowing generic compatible. The patch does not explain the differences
>> in interface which would explain why devices are not compatible.
> 
> I mentioned in the description that clocks and interconnects on this
> platform are configured in Firmware VM(over SCMI using power and perf
> domains) therefore this is not compatible with existing generic compatible.

It is not obvious to me. I doubt it is obvious to others. Commit msg
does not say they are compatible and usually difference in
clocks/interconnects is not reason of incompatibility. So why suddenly
here we would understand it differently?


> 
> 
>>  In the
>> same time my advice of separate binding was not followed, because maybe
>> these devices are compatible? But then it should be expressed...
> 
> Sorry, I missed that. You want me to use 'oneOf' expression with this
> compatible?

I proposed separate binding file. But your commit msg suggested these
are compatible. Lack of driver change is also proof of that.

I don't want to keep discussing this because it does not lead to
anywhere. We keep repeating the same.

> 
> 
>>
>> You have entire commit msg to explain what and why.
> 
> Will put more details in description.
> 
> 
>>> diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
>>> index 9f66a3bb1f80..b477fae734b6 100644
>>> --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
>>> +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml
>>> @@ -15,6 +15,7 @@ properties:
>>>      enum:
>>>        - qcom,geni-i2c
>>>        - qcom,geni-i2c-master-hub
>>> +      - qcom,sa8255p-geni-i2c
>>>  
>>>    clocks:
>>>      minItems: 1
>>> @@ -69,8 +70,6 @@ properties:
>>>  required:
>>>    - compatible
>>>    - interrupts
>>> -  - clocks
>>> -  - clock-names
>>>    - reg
>>>  
>>>  allOf:
>>> @@ -81,6 +80,10 @@ allOf:
>>>            contains:
>>>              const: qcom,geni-i2c-master-hub
>>>      then:
>>> +      required:
>>> +        - clocks
>>> +        - clock-names
>>
>> So it is required here?
> 
> We are removing clocks from generic required list and enforcing rules
> for all compatibles other than sa8255p.
> 
> 
>>> +
>>>        properties:
>>>          clocks:
>>>            minItems: 2
>>> @@ -100,7 +103,21 @@ allOf:
>>>            items:
>>>              - const: qup-core
>>>              - const: qup-config
>>> +
>>> +  - if:
>>> +      properties:
>>> +        compatible:
>>> +          contains:
>>> +            const: qcom,sa8255p-geni-i2c
>>> +    then:
>>> +      required:
>>> +        - power-domains
>>> +
>> And possible here? I assume with the same clocks? The same for
>> interconnects - same values are valid?
> 
> I guess I need to put here the same description as in the cover letter
> to make it more clear. We are not using clocks and interconnects in this
> platform in Linux. Instead, sending request to Firmware VM over
> SCMI(using power and perf protocols)
> 
> 
>>
>>>      else:
>>> +      required:
>>> +        - clocks
>>> +        - clock-names
>> And clocks are required again?
> Explained above.
>>> +
>>>        properties:
>>>          clocks:
>>>            maxItems: 1
>> Eeee? So now all other variants have max 1 clock?
> 
> I will make if block for sa8255p up so else is not applied to rest of
> the platforms.
> 
> 
>>
>> Nope, this wasn't ever tested on real DTS.
> 
> This is tested on SA8255p DTS and I ran DT schema check on SA8775p DT as
> well.

You just affected all the DTS everywhere. It's your task to check all
DTS everywhere. Not ours.

Best regards,
Krzysztof

Re: [PATCH v2 15/21] dt-bindings: i2c: document support for SA8255p

[Krzysztof Kozlowski]

On 04/09/2024 00:02, Nikunj Kela wrote:
> Add compatible representing i2c support on SA8255p.
> 
> Clocks and interconnects are being configured in Firmware VM
> on SA8255p, therefore making them optional.
> 
> CC: Praveen Talari <quic_ptalari@quicinc.com>
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  .../bindings/i2c/qcom,i2c-geni-qcom.yaml      | 33 +++++++++++++++++--
>  1 file changed, 31 insertions(+), 2 deletions(-)
> 

Just to clarify to I2C maintainers:
This is incomplete. Missing driver changes.

Best regards,
Krzysztof

Re: [PATCH v2 15/21] dt-bindings: i2c: document support for SA8255p

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 106 bytes --]


> Just to clarify to I2C maintainers:
> This is incomplete. Missing driver changes.

Thanks, Krzysztof!


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH v2 15/21] dt-bindings: i2c: document support for SA8255p

[Nikunj Kela]

On 9/4/2024 12:55 AM, Wolfram Sang wrote:
>> Just to clarify to I2C maintainers:
>> This is incomplete. Missing driver changes.
> Thanks, Krzysztof!

Driver changes are going through internal review and will soon be
posted. For your reference, we have pushed driver changes in CodeLinaro
git branch(nkela/sa8255p_v6_11_rc2)  in kernel-qcom repo [1]. You can
take a look at the changes that are in pipeline and will follow soon.

[1]:
https://git.codelinaro.org/clo/linux-kernel/kernel-qcom/-/tree/nkela/sa8255p_v6_11_rc2?ref_type=heads

Re: [PATCH v2 15/21] dt-bindings: i2c: document support for SA8255p

[Krzysztof Kozlowski]

On 04/09/2024 14:45, Nikunj Kela wrote:
> 
> On 9/4/2024 12:55 AM, Wolfram Sang wrote:
>>> Just to clarify to I2C maintainers:
>>> This is incomplete. Missing driver changes.
>> Thanks, Krzysztof!
> 
> Driver changes are going through internal review and will soon be
> posted. For your reference, we have pushed driver changes in CodeLinaro
> git branch(nkela/sa8255p_v6_11_rc2)  in kernel-qcom repo [1]. You can
> take a look at the changes that are in pipeline and will follow soon.
> 

Sorry, we are not reviewing other repos. Post patches ONLY when they are
ready. Sending one piece without driver is not correct and it does not
make any, absolutely any sense.

Best regards,
Krzysztof

Re: [PATCH v2 15/21] dt-bindings: i2c: document support for SA8255p

[Andi Shyti]

Hi Nikunj,

On Wed, Sep 04, 2024 at 05:45:05AM GMT, Nikunj Kela wrote:
> 
> On 9/4/2024 12:55 AM, Wolfram Sang wrote:
> >> Just to clarify to I2C maintainers:
> >> This is incomplete. Missing driver changes.
> > Thanks, Krzysztof!
> 
> Driver changes are going through internal review and will soon be
> posted. For your reference, we have pushed driver changes in CodeLinaro
> git branch(nkela/sa8255p_v6_11_rc2)  in kernel-qcom repo [1]. You can
> take a look at the changes that are in pipeline and will follow soon.

Please post here driver changes along with the DTS updates.

Thanks Krzysztof for being active here!

Andi

[PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Nikunj Kela]

Add compatible representing spi support on SA8255p.

Clocks and interconnects are being configured in firmware VM
on SA8255p platform, therefore making them optional.

CC: Praveen Talari <quic_ptalari@quicinc.com>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 .../bindings/spi/qcom,spi-geni-qcom.yaml      | 60 +++++++++++++++++--
 1 file changed, 56 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
index 2e20ca313ec1..75b52c0a7440 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
@@ -25,10 +25,45 @@ description:
 
 allOf:
   - $ref: /schemas/spi/spi-controller.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: qcom,sa8255p-geni-spi
+    then:
+      required:
+        - power-domains
+        - power-domain-names
+
+      properties:
+        power-domains:
+          minItems: 2
+
+    else:
+      required:
+        - clocks
+        - clock-names
+
+      properties:
+        power-domains:
+          maxItems: 1
+
+        interconnects:
+          minItems: 2
+          maxItems: 3
+
+        interconnect-names:
+          minItems: 2
+          items:
+            - const: qup-core
+            - const: qup-config
+            - const: qup-memory
 
 properties:
   compatible:
-    const: qcom,geni-spi
+    enum:
+      - qcom,geni-spi
+      - qcom,sa8255p-geni-spi
 
   clocks:
     maxItems: 1
@@ -61,15 +96,19 @@ properties:
   operating-points-v2: true
 
   power-domains:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
+
+  power-domain-names:
+    items:
+      - const: power
+      - const: perf
 
   reg:
     maxItems: 1
 
 required:
   - compatible
-  - clocks
-  - clock-names
   - interrupts
   - reg
 
@@ -116,3 +155,16 @@ examples:
         #address-cells = <1>;
         #size-cells = <0>;
     };
+
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    spi@888000 {
+        compatible = "qcom,sa8255p-geni-spi";
+        reg = <0x888000 0x4000>;
+        interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        power-domains = <&scmi10_pd 16>, <&scmi10_dvfs 16>;
+        power-domain-names = "power", "perf";
+    };
-- 
2.34.1

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Krzysztof Kozlowski]

On Tue, Sep 03, 2024 at 03:02:35PM -0700, Nikunj Kela wrote:
> Add compatible representing spi support on SA8255p.
> 
> Clocks and interconnects are being configured in firmware VM
> on SA8255p platform, therefore making them optional.
> 

Please use standard email subjects, so with the PATCH keyword in the
title.  helps here to create proper versioned patches.
Another useful tool is b4. Skipping the PATCH keyword makes filtering of
emails more difficult thus making the review process less convenient.


> CC: Praveen Talari <quic_ptalari@quicinc.com>
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  .../bindings/spi/qcom,spi-geni-qcom.yaml      | 60 +++++++++++++++++--
>  1 file changed, 56 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
> index 2e20ca313ec1..75b52c0a7440 100644
> --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
> @@ -25,10 +25,45 @@ description:
>  
>  allOf:
>    - $ref: /schemas/spi/spi-controller.yaml#
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: qcom,sa8255p-geni-spi

Not much improved. All my previous (v1) and other patch (i2c) comments
apply.

> +    then:
> +      required:
> +        - power-domains
> +        - power-domain-names
> +
> +      properties:
> +        power-domains:
> +          minItems: 2
> +
> +    else:
> +      required:
> +        - clocks
> +        - clock-names
> +
> +      properties:
> +        power-domains:
> +          maxItems: 1
> +
> +        interconnects:
> +          minItems: 2
> +          maxItems: 3
> +
> +        interconnect-names:
> +          minItems: 2
> +          items:
> +            - const: qup-core
> +            - const: qup-config
> +            - const: qup-memory
>  
>  properties:
>    compatible:
> -    const: qcom,geni-spi
> +    enum:
> +      - qcom,geni-spi
> +      - qcom,sa8255p-geni-spi

You have entire commit msg to explain why this device's programming
model is not compatible with existing generic compatible which must
cover all variants (because it is crazy generic).

Best regards,
Krzysztof

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Nikunj Kela]

On 9/3/2024 11:34 PM, Krzysztof Kozlowski wrote:
> On Tue, Sep 03, 2024 at 03:02:35PM -0700, Nikunj Kela wrote:
>> Add compatible representing spi support on SA8255p.
>>
>> Clocks and interconnects are being configured in firmware VM
>> on SA8255p platform, therefore making them optional.
>>
> Please use standard email subjects, so with the PATCH keyword in the
> title.  helps here to create proper versioned patches.
Where did I miss PATCH keyword in the subject here? It says "[PATCH v2
16/21] dt-bindings: spi: document support for SA8255p"
> Another useful tool is b4. Skipping the PATCH keyword makes filtering of
> emails more difficult thus making the review process less convenient.
>
>
>> CC: Praveen Talari <quic_ptalari@quicinc.com>
>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>> ---
>>  .../bindings/spi/qcom,spi-geni-qcom.yaml      | 60 +++++++++++++++++--
>>  1 file changed, 56 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
>> index 2e20ca313ec1..75b52c0a7440 100644
>> --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
>> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml
>> @@ -25,10 +25,45 @@ description:
>>  
>>  allOf:
>>    - $ref: /schemas/spi/spi-controller.yaml#
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            const: qcom,sa8255p-geni-spi
> Not much improved. All my previous (v1) and other patch (i2c) comments
> apply.
>> +    then:
>> +      required:
>> +        - power-domains
>> +        - power-domain-names
>> +
>> +      properties:
>> +        power-domains:
>> +          minItems: 2
>> +
>> +    else:
>> +      required:
>> +        - clocks
>> +        - clock-names
>> +
>> +      properties:
>> +        power-domains:
>> +          maxItems: 1
>> +
>> +        interconnects:
>> +          minItems: 2
>> +          maxItems: 3
>> +
>> +        interconnect-names:
>> +          minItems: 2
>> +          items:
>> +            - const: qup-core
>> +            - const: qup-config
>> +            - const: qup-memory
>>  
>>  properties:
>>    compatible:
>> -    const: qcom,geni-spi
>> +    enum:
>> +      - qcom,geni-spi
>> +      - qcom,sa8255p-geni-spi
> You have entire commit msg to explain why this device's programming
> model is not compatible with existing generic compatible which must
> cover all variants (because it is crazy generic).
>
> Best regards,
> Krzysztof

I will put more details in the description of the patch, though, I had
put the description in the cover letter for this entire series.


>

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Krzysztof Kozlowski]

On 04/09/2024 14:48, Nikunj Kela wrote:
> 
> On 9/3/2024 11:34 PM, Krzysztof Kozlowski wrote:
>> On Tue, Sep 03, 2024 at 03:02:35PM -0700, Nikunj Kela wrote:
>>> Add compatible representing spi support on SA8255p.
>>>
>>> Clocks and interconnects are being configured in firmware VM
>>> on SA8255p platform, therefore making them optional.
>>>
>> Please use standard email subjects, so with the PATCH keyword in the
>> title.  helps here to create proper versioned patches.
> Where did I miss PATCH keyword in the subject here? It says "[PATCH v2
> 16/21] dt-bindings: spi: document support for SA8255p"

Oh, wrong template. It was about spi prefix, should be this one:

Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters

>>

Best regards,
Krzysztof

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Nikunj Kela]

On 9/4/2024 6:21 AM, Krzysztof Kozlowski wrote:
> On 04/09/2024 14:48, Nikunj Kela wrote:
>> On 9/3/2024 11:34 PM, Krzysztof Kozlowski wrote:
>>> On Tue, Sep 03, 2024 at 03:02:35PM -0700, Nikunj Kela wrote:
>>>> Add compatible representing spi support on SA8255p.
>>>>
>>>> Clocks and interconnects are being configured in firmware VM
>>>> on SA8255p platform, therefore making them optional.
>>>>
>>> Please use standard email subjects, so with the PATCH keyword in the
>>> title.  helps here to create proper versioned patches.
>> Where did I miss PATCH keyword in the subject here? It says "[PATCH v2
>> 16/21] dt-bindings: spi: document support for SA8255p"
> Oh, wrong template. It was about spi prefix, should be this one:

Sorry, didn't realize SPI uses different subject format than other
subsystems. Will fix in v3. Thanks


> Please use subject prefixes matching the subsystem. You can get them for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
> your patch is touching. For bindings, the preferred subjects are
> explained here:
> https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
>
> Best regards,
> Krzysztof
>

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Andrew Lunn]

> Sorry, didn't realize SPI uses different subject format than other
> subsystems. Will fix in v3. Thanks

Each subsystem is free to use its own form. e.g for netdev you will
want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos:

This is another reason why you should be splitting these patches per
subsystem, and submitting both the DT bindings and the code changes as
a two patch patchset. You can then learn how each subsystem names its
patches.

Please pick one victim subsystem and work on the patches for just that
subsystem. Once you have them correct, you can use everything you
learned to fixup all your other patches, one by one.

	Andrew      	 

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Nikunj Kela]

On 9/4/2024 9:58 AM, Andrew Lunn wrote:
>> Sorry, didn't realize SPI uses different subject format than other
>> subsystems. Will fix in v3. Thanks
> Each subsystem is free to use its own form. e.g for netdev you will
> want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos:
of course they are! No one is disputing that.
>
> This is another reason why you should be splitting these patches per
> subsystem, and submitting both the DT bindings and the code changes as
> a two patch patchset. You can then learn how each subsystem names its
> patches.

Qualcomm QUPs chips have serial engines that can be configured as
UART/I2C/SPI so QUPs changes require to be pushed in one series for all
3 subsystems as they all are dependent.


>
> Please pick one victim subsystem and work on the patches for just that
> subsystem. Once you have them correct, you can use everything you
> learned to fixup all your other patches, one by one.
>
> 	Andrew      	 

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Andrew Lunn]

> Qualcomm QUPs chips have serial engines that can be configured as
> UART/I2C/SPI so QUPs changes require to be pushed in one series for all
> 3 subsystems as they all are dependent.

So leave that until later. And when you do, explicit mention why you
are cross posting to three subsystems, because the hardware is
designed like that. And suggest a way it could be merged, which
subsystem should take the lead, and the others just need to provide
Acked-by. The Maintainers might disagree, want to do it differently,
but i find it always helps to state this from the beginning, otherwise
sometimes no Maintainer take the lead role.

But this patchset appears to be much more than QUPs. You should be
able the break the rest up into smaller patchsets, one per subsystem.

	Andrew

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Krzysztof Kozlowski]

On 04/09/2024 23:06, Nikunj Kela wrote:
> 
> On 9/4/2024 9:58 AM, Andrew Lunn wrote:
>>> Sorry, didn't realize SPI uses different subject format than other
>>> subsystems. Will fix in v3. Thanks
>> Each subsystem is free to use its own form. e.g for netdev you will
>> want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos:
> of course they are! No one is disputing that.
>>
>> This is another reason why you should be splitting these patches per
>> subsystem, and submitting both the DT bindings and the code changes as
>> a two patch patchset. You can then learn how each subsystem names its
>> patches.
> 
> Qualcomm QUPs chips have serial engines that can be configured as
> UART/I2C/SPI so QUPs changes require to be pushed in one series for all
> 3 subsystems as they all are dependent.

No, they are not dependent. They have never been. Look how all other
upstreaming process worked in the past.


Best regards,
Krzysztof

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Nikunj Kela]

On 9/5/2024 1:04 AM, Krzysztof Kozlowski wrote:
> On 04/09/2024 23:06, Nikunj Kela wrote:
>> On 9/4/2024 9:58 AM, Andrew Lunn wrote:
>>>> Sorry, didn't realize SPI uses different subject format than other
>>>> subsystems. Will fix in v3. Thanks
>>> Each subsystem is free to use its own form. e.g for netdev you will
>>> want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos:
>> of course they are! No one is disputing that.
>>> This is another reason why you should be splitting these patches per
>>> subsystem, and submitting both the DT bindings and the code changes as
>>> a two patch patchset. You can then learn how each subsystem names its
>>> patches.
>> Qualcomm QUPs chips have serial engines that can be configured as
>> UART/I2C/SPI so QUPs changes require to be pushed in one series for all
>> 3 subsystems as they all are dependent.
> No, they are not dependent. They have never been. Look how all other
> upstreaming process worked in the past.

Top level QUP node(patch#18) includes i2c,spi,uart nodes.
soc/qcom/qcom,geni-se.yaml validate those subnodes against respective
yaml. The example that is added in YAML file for QUP node will not find
sa8255p compatibles if all 4 yaml(qup, i2c, spi, serial nodes) are not
included in the same series.


>
> Best regards,
> Krzysztof
>

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Krzysztof Kozlowski]

On 05/09/2024 16:03, Nikunj Kela wrote:
> 
> On 9/5/2024 1:04 AM, Krzysztof Kozlowski wrote:
>> On 04/09/2024 23:06, Nikunj Kela wrote:
>>> On 9/4/2024 9:58 AM, Andrew Lunn wrote:
>>>>> Sorry, didn't realize SPI uses different subject format than other
>>>>> subsystems. Will fix in v3. Thanks
>>>> Each subsystem is free to use its own form. e.g for netdev you will
>>>> want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos:
>>> of course they are! No one is disputing that.
>>>> This is another reason why you should be splitting these patches per
>>>> subsystem, and submitting both the DT bindings and the code changes as
>>>> a two patch patchset. You can then learn how each subsystem names its
>>>> patches.
>>> Qualcomm QUPs chips have serial engines that can be configured as
>>> UART/I2C/SPI so QUPs changes require to be pushed in one series for all
>>> 3 subsystems as they all are dependent.
>> No, they are not dependent. They have never been. Look how all other
>> upstreaming process worked in the past.
> 
> Top level QUP node(patch#18) includes i2c,spi,uart nodes.
> soc/qcom/qcom,geni-se.yaml validate those subnodes against respective
> yaml. The example that is added in YAML file for QUP node will not find
> sa8255p compatibles if all 4 yaml(qup, i2c, spi, serial nodes) are not
> included in the same series.
> 

So where is the dependency? I don't see it. Anyway, if you insist,
provide reasons why this should be the only one patchset - from all
SoCs, all companies, all developers - getting an exception from standard
merging practice and from explicit rule about driver change. See
submitting bindings.

This was re-iterated over and over, but you keep claiming you need some
sort of special treatment. If so, please provide arguments WHY this
requires special treatment and *all* other contributions are fine with it.

Best regards,
Krzysztof

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Nikunj Kela]

On 9/5/2024 7:09 AM, Krzysztof Kozlowski wrote:
> On 05/09/2024 16:03, Nikunj Kela wrote:
>> On 9/5/2024 1:04 AM, Krzysztof Kozlowski wrote:
>>> On 04/09/2024 23:06, Nikunj Kela wrote:
>>>> On 9/4/2024 9:58 AM, Andrew Lunn wrote:
>>>>>> Sorry, didn't realize SPI uses different subject format than other
>>>>>> subsystems. Will fix in v3. Thanks
>>>>> Each subsystem is free to use its own form. e.g for netdev you will
>>>>> want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos:
>>>> of course they are! No one is disputing that.
>>>>> This is another reason why you should be splitting these patches per
>>>>> subsystem, and submitting both the DT bindings and the code changes as
>>>>> a two patch patchset. You can then learn how each subsystem names its
>>>>> patches.
>>>> Qualcomm QUPs chips have serial engines that can be configured as
>>>> UART/I2C/SPI so QUPs changes require to be pushed in one series for all
>>>> 3 subsystems as they all are dependent.
>>> No, they are not dependent. They have never been. Look how all other
>>> upstreaming process worked in the past.
>> Top level QUP node(patch#18) includes i2c,spi,uart nodes.
>> soc/qcom/qcom,geni-se.yaml validate those subnodes against respective
>> yaml. The example that is added in YAML file for QUP node will not find
>> sa8255p compatibles if all 4 yaml(qup, i2c, spi, serial nodes) are not
>> included in the same series.
>>
> So where is the dependency? I don't see it. 

Ok, what is your suggestion on dt-schema check failure in that case as I
mentioned above? Shall we remove examples from yaml that we added?


> Anyway, if you insist,
> provide reasons why this should be the only one patchset - from all
> SoCs, all companies, all developers - getting an exception from standard
> merging practice and from explicit rule about driver change. See
> submitting bindings.
>
> This was re-iterated over and over, but you keep claiming you need some
> sort of special treatment. If so, please provide arguments WHY this
> requires special treatment and *all* other contributions are fine with it.
>
> Best regards,
> Krzysztof
>

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Krzysztof Kozlowski]

On 05/09/2024 16:15, Nikunj Kela wrote:
> 
> On 9/5/2024 7:09 AM, Krzysztof Kozlowski wrote:
>> On 05/09/2024 16:03, Nikunj Kela wrote:
>>> On 9/5/2024 1:04 AM, Krzysztof Kozlowski wrote:
>>>> On 04/09/2024 23:06, Nikunj Kela wrote:
>>>>> On 9/4/2024 9:58 AM, Andrew Lunn wrote:
>>>>>>> Sorry, didn't realize SPI uses different subject format than other
>>>>>>> subsystems. Will fix in v3. Thanks
>>>>>> Each subsystem is free to use its own form. e.g for netdev you will
>>>>>> want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos:
>>>>> of course they are! No one is disputing that.
>>>>>> This is another reason why you should be splitting these patches per
>>>>>> subsystem, and submitting both the DT bindings and the code changes as
>>>>>> a two patch patchset. You can then learn how each subsystem names its
>>>>>> patches.
>>>>> Qualcomm QUPs chips have serial engines that can be configured as
>>>>> UART/I2C/SPI so QUPs changes require to be pushed in one series for all
>>>>> 3 subsystems as they all are dependent.
>>>> No, they are not dependent. They have never been. Look how all other
>>>> upstreaming process worked in the past.
>>> Top level QUP node(patch#18) includes i2c,spi,uart nodes.
>>> soc/qcom/qcom,geni-se.yaml validate those subnodes against respective
>>> yaml. The example that is added in YAML file for QUP node will not find
>>> sa8255p compatibles if all 4 yaml(qup, i2c, spi, serial nodes) are not
>>> included in the same series.
>>>
>> So where is the dependency? I don't see it. 
> 
> Ok, what is your suggestion on dt-schema check failure in that case as I
> mentioned above? Shall we remove examples from yaml that we added?

I don't understand what sort of failure you want to fix and why examples
have any problem here. I said it multiple times already but I think you
never confirmed. Do you understand how patches are merged? That they go
via different trees but everything must be 100% bisectable?

Best regards,
Krzysztof

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Nikunj Kela]

On 9/5/2024 7:39 AM, Krzysztof Kozlowski wrote:
> On 05/09/2024 16:15, Nikunj Kela wrote:
>> On 9/5/2024 7:09 AM, Krzysztof Kozlowski wrote:
>>> On 05/09/2024 16:03, Nikunj Kela wrote:
>>>> On 9/5/2024 1:04 AM, Krzysztof Kozlowski wrote:
>>>>> On 04/09/2024 23:06, Nikunj Kela wrote:
>>>>>> On 9/4/2024 9:58 AM, Andrew Lunn wrote:
>>>>>>>> Sorry, didn't realize SPI uses different subject format than other
>>>>>>>> subsystems. Will fix in v3. Thanks
>>>>>>> Each subsystem is free to use its own form. e.g for netdev you will
>>>>>>> want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos:
>>>>>> of course they are! No one is disputing that.
>>>>>>> This is another reason why you should be splitting these patches per
>>>>>>> subsystem, and submitting both the DT bindings and the code changes as
>>>>>>> a two patch patchset. You can then learn how each subsystem names its
>>>>>>> patches.
>>>>>> Qualcomm QUPs chips have serial engines that can be configured as
>>>>>> UART/I2C/SPI so QUPs changes require to be pushed in one series for all
>>>>>> 3 subsystems as they all are dependent.
>>>>> No, they are not dependent. They have never been. Look how all other
>>>>> upstreaming process worked in the past.
>>>> Top level QUP node(patch#18) includes i2c,spi,uart nodes.
>>>> soc/qcom/qcom,geni-se.yaml validate those subnodes against respective
>>>> yaml. The example that is added in YAML file for QUP node will not find
>>>> sa8255p compatibles if all 4 yaml(qup, i2c, spi, serial nodes) are not
>>>> included in the same series.
>>>>
>>> So where is the dependency? I don't see it. 
>> Ok, what is your suggestion on dt-schema check failure in that case as I
>> mentioned above? Shall we remove examples from yaml that we added?
> I don't understand what sort of failure you want to fix and why examples
> have any problem here. 

If the QUPs yaml changes are not included in the same series with
i2c,serial yaml changes, you see these errors:

/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: serial@990000:compatible:0: 'qcom,sa8255p-geni-uart' is not one of ['qcom,geni-uart', 'qcom,geni-debug-uart']
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: i2c@984000:compatible:0: 'qcom,sa8255p-geni-i2c' is not one of ['qcom,geni-i2c', 'qcom,geni-i2c-master-hub']

> I said it multiple times already but I think you
> never confirmed. Do you understand how patches are merged? That they go
> via different trees but everything must be 100% bisectable?
>
> Best regards,
> Krzysztof
>

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Andrew Lunn]

> If the QUPs yaml changes are not included in the same series with
> i2c,serial yaml changes, you see these errors:
> 
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: serial@990000:compatible:0: 'qcom,sa8255p-geni-uart' is not one of ['qcom,geni-uart', 'qcom,geni-debug-uart']
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: i2c@984000:compatible:0: 'qcom,sa8255p-geni-i2c' is not one of ['qcom,geni-i2c', 'qcom,geni-i2c-master-hub']

So you have a couple of options:

1) It sounds like you should get the QUP changes merged first. Then
   submit the i2c,serial changes. Is there a reason you cannot do
   this? Is there a mutual dependency between these two series, or
   just a one way dependency?

2) Explain in the commit message that following errors are expected
   because ... And explain in detail why the dependency cannot be
   broken to avoid the errors.

Andrew

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Nikunj Kela]

On 9/5/2024 9:23 AM, Andrew Lunn wrote:
>> If the QUPs yaml changes are not included in the same series with
>> i2c,serial yaml changes, you see these errors:
>>
>> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: serial@990000:compatible:0: 'qcom,sa8255p-geni-uart' is not one of ['qcom,geni-uart', 'qcom,geni-debug-uart']
>> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: i2c@984000:compatible:0: 'qcom,sa8255p-geni-i2c' is not one of ['qcom,geni-i2c', 'qcom,geni-i2c-master-hub']
> So you have a couple of options:
>
> 1) It sounds like you should get the QUP changes merged first. Then
>    submit the i2c,serial changes. Is there a reason you cannot do
>    this? Is there a mutual dependency between these two series, or
>    just a one way dependency?

The ask in this thread is to create new yaml files since existing one is
using generic compatibles. With new yaml, we would need to provide
example and can't avoid it. If we have to provide example of QUP node,
IMO, we should provide a few subnodes as well since just QUP node
without subnodes(i2c/serial/spi)  will not be very useful.

We can possibly skip all 3 subnode and only keep one subsystem(e.g.
serial) so QUP and UART yaml can go together(still need two subsystems)
while SPI and I2C can go independently after QUP series is accepted. Not
sure if that is acceptable to maintainers though. QUP node in actual DT
will have all 3 types of subnodes(i2c,spi, serial) so example in this
case won't be complete.

>
> 2) Explain in the commit message that following errors are expected
>    because ... And explain in detail why the dependency cannot be
>    broken to avoid the errors.
>
> Andrew

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Andrew Lunn]

On Thu, Sep 05, 2024 at 09:39:54AM -0700, Nikunj Kela wrote:
> 
> On 9/5/2024 9:23 AM, Andrew Lunn wrote:
> >> If the QUPs yaml changes are not included in the same series with
> >> i2c,serial yaml changes, you see these errors:
> >>
> >> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: serial@990000:compatible:0: 'qcom,sa8255p-geni-uart' is not one of ['qcom,geni-uart', 'qcom,geni-debug-uart']
> >> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: i2c@984000:compatible:0: 'qcom,sa8255p-geni-i2c' is not one of ['qcom,geni-i2c', 'qcom,geni-i2c-master-hub']
> > So you have a couple of options:
> >
> > 1) It sounds like you should get the QUP changes merged first. Then
> >    submit the i2c,serial changes. Is there a reason you cannot do
> >    this? Is there a mutual dependency between these two series, or
> >    just a one way dependency?
> 
> The ask in this thread is to create new yaml files since existing one is
> using generic compatibles. With new yaml, we would need to provide
> example and can't avoid it. If we have to provide example of QUP node,
> IMO, we should provide a few subnodes as well since just QUP node
> without subnodes(i2c/serial/spi)  will not be very useful.

Does it need to be useful, at the beginning? Was the development done
all at once, i2c, serial and spi all mixed together, inseparable? More
likely, you have a set of patches adding some sort of base, and
hopefully a DT binding patch for that base. Then you add a driver in
drivers/tty/serial, with patches which extend the DT binding with the
serial port. You then add a driver in driver/i2c/busses and extend the
DT binding for I2C. And then add a driver for SPI in drivers/spi,
which again extends the DT binding?

This would be typical for how an MFD would be posted. Please go search
the lists for examples of MFDs you might be able to follow.

	Andrew

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Krzysztof Kozlowski]

On 05/09/2024 18:08, Nikunj Kela wrote:
> 
> On 9/5/2024 7:39 AM, Krzysztof Kozlowski wrote:
>> On 05/09/2024 16:15, Nikunj Kela wrote:
>>> On 9/5/2024 7:09 AM, Krzysztof Kozlowski wrote:
>>>> On 05/09/2024 16:03, Nikunj Kela wrote:
>>>>> On 9/5/2024 1:04 AM, Krzysztof Kozlowski wrote:
>>>>>> On 04/09/2024 23:06, Nikunj Kela wrote:
>>>>>>> On 9/4/2024 9:58 AM, Andrew Lunn wrote:
>>>>>>>>> Sorry, didn't realize SPI uses different subject format than other
>>>>>>>>> subsystems. Will fix in v3. Thanks
>>>>>>>> Each subsystem is free to use its own form. e.g for netdev you will
>>>>>>>> want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos:
>>>>>>> of course they are! No one is disputing that.
>>>>>>>> This is another reason why you should be splitting these patches per
>>>>>>>> subsystem, and submitting both the DT bindings and the code changes as
>>>>>>>> a two patch patchset. You can then learn how each subsystem names its
>>>>>>>> patches.
>>>>>>> Qualcomm QUPs chips have serial engines that can be configured as
>>>>>>> UART/I2C/SPI so QUPs changes require to be pushed in one series for all
>>>>>>> 3 subsystems as they all are dependent.
>>>>>> No, they are not dependent. They have never been. Look how all other
>>>>>> upstreaming process worked in the past.
>>>>> Top level QUP node(patch#18) includes i2c,spi,uart nodes.
>>>>> soc/qcom/qcom,geni-se.yaml validate those subnodes against respective
>>>>> yaml. The example that is added in YAML file for QUP node will not find
>>>>> sa8255p compatibles if all 4 yaml(qup, i2c, spi, serial nodes) are not
>>>>> included in the same series.
>>>>>
>>>> So where is the dependency? I don't see it. 
>>> Ok, what is your suggestion on dt-schema check failure in that case as I
>>> mentioned above? Shall we remove examples from yaml that we added?
>> I don't understand what sort of failure you want to fix and why examples
>> have any problem here. 
> 
> If the QUPs yaml changes are not included in the same series with

They cannot be included in the same series. You just think that
including here solves the problem so go ahead, simulate the merging:
1. Bjorn applies soc/qcom/qcom,geni-se.yaml patch and tests. His tree
MUST build, so it also must pass dt_binding_check.
Does it pass? No.

2. SPI maintainer... ah, no point even going there.

> i2c,serial yaml changes, you see these errors:
> 
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: serial@990000:compatible:0: 'qcom,sa8255p-geni-uart' is not one of ['qcom,geni-uart', 'qcom,geni-debug-uart']
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: i2c@984000:compatible:0: 'qcom,sa8255p-geni-i2c' is not one of ['qcom,geni-i2c', 'qcom,geni-i2c-master-hub']

Don't grow examples if not needed. Or create dependencies and ask
maintainers to cross-merge.

Best regards,
Krzysztof

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Krzysztof Kozlowski]

On 05/09/2024 18:56, Krzysztof Kozlowski wrote:
> On 05/09/2024 18:08, Nikunj Kela wrote:
>>
>> On 9/5/2024 7:39 AM, Krzysztof Kozlowski wrote:
>>> On 05/09/2024 16:15, Nikunj Kela wrote:
>>>> On 9/5/2024 7:09 AM, Krzysztof Kozlowski wrote:
>>>>> On 05/09/2024 16:03, Nikunj Kela wrote:
>>>>>> On 9/5/2024 1:04 AM, Krzysztof Kozlowski wrote:
>>>>>>> On 04/09/2024 23:06, Nikunj Kela wrote:
>>>>>>>> On 9/4/2024 9:58 AM, Andrew Lunn wrote:
>>>>>>>>>> Sorry, didn't realize SPI uses different subject format than other
>>>>>>>>>> subsystems. Will fix in v3. Thanks
>>>>>>>>> Each subsystem is free to use its own form. e.g for netdev you will
>>>>>>>>> want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos:
>>>>>>>> of course they are! No one is disputing that.
>>>>>>>>> This is another reason why you should be splitting these patches per
>>>>>>>>> subsystem, and submitting both the DT bindings and the code changes as
>>>>>>>>> a two patch patchset. You can then learn how each subsystem names its
>>>>>>>>> patches.
>>>>>>>> Qualcomm QUPs chips have serial engines that can be configured as
>>>>>>>> UART/I2C/SPI so QUPs changes require to be pushed in one series for all
>>>>>>>> 3 subsystems as they all are dependent.
>>>>>>> No, they are not dependent. They have never been. Look how all other
>>>>>>> upstreaming process worked in the past.
>>>>>> Top level QUP node(patch#18) includes i2c,spi,uart nodes.
>>>>>> soc/qcom/qcom,geni-se.yaml validate those subnodes against respective
>>>>>> yaml. The example that is added in YAML file for QUP node will not find
>>>>>> sa8255p compatibles if all 4 yaml(qup, i2c, spi, serial nodes) are not
>>>>>> included in the same series.
>>>>>>
>>>>> So where is the dependency? I don't see it. 
>>>> Ok, what is your suggestion on dt-schema check failure in that case as I
>>>> mentioned above? Shall we remove examples from yaml that we added?
>>> I don't understand what sort of failure you want to fix and why examples
>>> have any problem here. 
>>
>> If the QUPs yaml changes are not included in the same series with
> 
> They cannot be included in the same series. You just think that
> including here solves the problem so go ahead, simulate the merging:
> 1. Bjorn applies soc/qcom/qcom,geni-se.yaml patch and tests. His tree
> MUST build, so it also must pass dt_binding_check.
> Does it pass? No.
> 
> 2. SPI maintainer... ah, no point even going there.
> 
>> i2c,serial yaml changes, you see these errors:
>>
>> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: serial@990000:compatible:0: 'qcom,sa8255p-geni-uart' is not one of ['qcom,geni-uart', 'qcom,geni-debug-uart']
>> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dtb: geniqup@9c0000: i2c@984000:compatible:0: 'qcom,sa8255p-geni-i2c' is not one of ['qcom,geni-i2c', 'qcom,geni-i2c-master-hub']
> 
> Don't grow examples if not needed. Or create dependencies and ask
> maintainers to cross-merge.

Or soc/geni-se binding could be also converted to just list compatibles
instead of referencing other schema, just like MDSS.

Best regards,
Krzysztof

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Andrew Lunn]

> Ok, what is your suggestion on dt-schema check failure in that case as I
> mentioned above? Shall we remove examples from yaml that we added?

As Krzysztof keeps saying, Commit message. You have an unlimited
amount of space to document why this SoC is special, how it is
special, maybe include some ASCII art showing how it is special.
Justify it being special. Once it is clear it is special, has
dependencies which are real, we are likely to accept the patches. We
know SoC vendors do weird things, and sometimes mainline processes
just don't work. But you need to clear, upfront, and state, the
process does not work because... in your commit message. Maybe put it
below the ---.

Something i often say to Mainline newbies. The code is easy, it is the
processes which are hard. The commit message is part of the
process. You want to try to anticipate all the questions Reviewers are
going to ask and answer them in the commit message, before they ask
them. It is process that you split patches by subsystem. It is process
that binding changes and driver changes go together in the
patchset. Your 'code review' should include all this, not just the
lines of actual code. And to begin with, process is probably a lot
more important than the actual code. So please concentrate on
processes, get them right.

	Andrew

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Krzysztof Kozlowski]

On 05/09/2024 16:15, Nikunj Kela wrote:
> 
> On 9/5/2024 7:09 AM, Krzysztof Kozlowski wrote:
>> On 05/09/2024 16:03, Nikunj Kela wrote:
>>> On 9/5/2024 1:04 AM, Krzysztof Kozlowski wrote:
>>>> On 04/09/2024 23:06, Nikunj Kela wrote:
>>>>> On 9/4/2024 9:58 AM, Andrew Lunn wrote:
>>>>>>> Sorry, didn't realize SPI uses different subject format than other
>>>>>>> subsystems. Will fix in v3. Thanks
>>>>>> Each subsystem is free to use its own form. e.g for netdev you will
>>>>>> want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos:
>>>>> of course they are! No one is disputing that.
>>>>>> This is another reason why you should be splitting these patches per
>>>>>> subsystem, and submitting both the DT bindings and the code changes as
>>>>>> a two patch patchset. You can then learn how each subsystem names its
>>>>>> patches.
>>>>> Qualcomm QUPs chips have serial engines that can be configured as
>>>>> UART/I2C/SPI so QUPs changes require to be pushed in one series for all
>>>>> 3 subsystems as they all are dependent.
>>>> No, they are not dependent. They have never been. Look how all other
>>>> upstreaming process worked in the past.
>>> Top level QUP node(patch#18) includes i2c,spi,uart nodes.
>>> soc/qcom/qcom,geni-se.yaml validate those subnodes against respective
>>> yaml. The example that is added in YAML file for QUP node will not find
>>> sa8255p compatibles if all 4 yaml(qup, i2c, spi, serial nodes) are not
>>> included in the same series.
>>>
>> So where is the dependency? I don't see it. 
> 
> Ok, what is your suggestion on dt-schema check failure in that case as I
> mentioned above? Shall we remove examples from yaml that we added?
> 
> 
>> Anyway, if you insist,
>> provide reasons why this should be the only one patchset - from all
>> SoCs, all companies, all developers - getting an exception from standard
>> merging practice and from explicit rule about driver change. See
>> submitting bindings.
>>
>> This was re-iterated over and over, but you keep claiming you need some
>> sort of special treatment. If so, please provide arguments WHY this
>> requires special treatment and *all* other contributions are fine with it.

You did not respond to above about explaining why this patchset needs
special treatment, so I assume there is no exception here to be granted
so any new version will follow standard process (see submitting bindings
/ writing bindings).

Best regards,
Krzysztof

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Nikunj Kela]

On 9/5/2024 7:49 AM, Krzysztof Kozlowski wrote:
> On 05/09/2024 16:15, Nikunj Kela wrote:
>> On 9/5/2024 7:09 AM, Krzysztof Kozlowski wrote:
>>> On 05/09/2024 16:03, Nikunj Kela wrote:
>>>> On 9/5/2024 1:04 AM, Krzysztof Kozlowski wrote:
>>>>> On 04/09/2024 23:06, Nikunj Kela wrote:
>>>>>> On 9/4/2024 9:58 AM, Andrew Lunn wrote:
>>>>>>>> Sorry, didn't realize SPI uses different subject format than other
>>>>>>>> subsystems. Will fix in v3. Thanks
>>>>>>> Each subsystem is free to use its own form. e.g for netdev you will
>>>>>>> want the prefix [PATCH net-next v42] net: stmmac: dwmac-qcom-ethqos:
>>>>>> of course they are! No one is disputing that.
>>>>>>> This is another reason why you should be splitting these patches per
>>>>>>> subsystem, and submitting both the DT bindings and the code changes as
>>>>>>> a two patch patchset. You can then learn how each subsystem names its
>>>>>>> patches.
>>>>>> Qualcomm QUPs chips have serial engines that can be configured as
>>>>>> UART/I2C/SPI so QUPs changes require to be pushed in one series for all
>>>>>> 3 subsystems as they all are dependent.
>>>>> No, they are not dependent. They have never been. Look how all other
>>>>> upstreaming process worked in the past.
>>>> Top level QUP node(patch#18) includes i2c,spi,uart nodes.
>>>> soc/qcom/qcom,geni-se.yaml validate those subnodes against respective
>>>> yaml. The example that is added in YAML file for QUP node will not find
>>>> sa8255p compatibles if all 4 yaml(qup, i2c, spi, serial nodes) are not
>>>> included in the same series.
>>>>
>>> So where is the dependency? I don't see it. 
>> Ok, what is your suggestion on dt-schema check failure in that case as I
>> mentioned above? Shall we remove examples from yaml that we added?
>>
>>
>>> Anyway, if you insist,
>>> provide reasons why this should be the only one patchset - from all
>>> SoCs, all companies, all developers - getting an exception from standard
>>> merging practice and from explicit rule about driver change. See
>>> submitting bindings.
>>>
>>> This was re-iterated over and over, but you keep claiming you need some
>>> sort of special treatment. If so, please provide arguments WHY this
>>> requires special treatment and *all* other contributions are fine with it.
> You did not respond to above about explaining why this patchset needs
> special treatment, so I assume there is no exception here to be granted
> so any new version will follow standard process (see submitting bindings
> / writing bindings).
>
> Best regards,
> Krzysztof

Things will be clear after you see the driver changes. Without looking
at the code, this discussion won't lead to anything constructive. So I
deferred the QUP related discussion until driver patches are posted.

Thanks,

-Nikunj


>

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Nikunj Kela]

On 9/4/2024 6:21 AM, Krzysztof Kozlowski wrote:
> On 04/09/2024 14:48, Nikunj Kela wrote:
>> On 9/3/2024 11:34 PM, Krzysztof Kozlowski wrote:
>>> On Tue, Sep 03, 2024 at 03:02:35PM -0700, Nikunj Kela wrote:
>>>> Add compatible representing spi support on SA8255p.
>>>>
>>>> Clocks and interconnects are being configured in firmware VM
>>>> on SA8255p platform, therefore making them optional.
>>>>
>>> Please use standard email subjects, so with the PATCH keyword in the
>>> title.  helps here to create proper versioned patches.
>> Where did I miss PATCH keyword in the subject here? It says "[PATCH v2
>> 16/21] dt-bindings: spi: document support for SA8255p"
> Oh, wrong template. It was about spi prefix, 

These are the latest 4 commits in linux-next for spi:

12736adc43b7 dt-bindings: spi: nxp-fspi: add imx8ulp support
b0cdf9cc0895 spi: dt-bindings: Add rockchip,rk3576-spi compatible
d6d0af1b9eff dt-bindings: spi: add PIC64GX SPI/QSPI compatibility to
MPFS SPI/QSPI bindings
1c4d834e4e81 spi: dt-bindings: convert spi-sc18is602.txt to yaml format

Now I am confused which prefix format shall I use? first spi or first
dt-bindings?


> should be this one:
>
> Please use subject prefixes matching the subsystem. You can get them for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
> your patch is touching. For bindings, the preferred subjects are
> explained here:
> https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
>
> Best regards,
> Krzysztof
>

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 162 bytes --]

On Mon, Sep 09, 2024 at 01:29:37PM -0700, Nikunj Kela wrote:

> Now I am confused which prefix format shall I use? first spi or first
> dt-bindings?

spi: first.

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Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Dmitry Baryshkov]

On Wed, Sep 04, 2024 at 05:48:35AM GMT, Nikunj Kela wrote:
> 
> On 9/3/2024 11:34 PM, Krzysztof Kozlowski wrote:
> > On Tue, Sep 03, 2024 at 03:02:35PM -0700, Nikunj Kela wrote:
> >> Add compatible representing spi support on SA8255p.
> >>
> >> Clocks and interconnects are being configured in firmware VM
> >> on SA8255p platform, therefore making them optional.
> >>
> > Please use standard email subjects, so with the PATCH keyword in the
> > title.  helps here to create proper versioned patches.
> Where did I miss PATCH keyword in the subject here? It says "[PATCH v2
> 16/21] dt-bindings: spi: document support for SA8255p"
> > Another useful tool is b4. Skipping the PATCH keyword makes filtering of
> > emails more difficult thus making the review process less convenient.
> >
> >
> >> CC: Praveen Talari <quic_ptalari@quicinc.com>
> >> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> >> ---
> >>  .../bindings/spi/qcom,spi-geni-qcom.yaml      | 60 +++++++++++++++++--
> >>  1 file changed, 56 insertions(+), 4 deletions(-)

> >>  
> >>  properties:
> >>    compatible:
> >> -    const: qcom,geni-spi
> >> +    enum:
> >> +      - qcom,geni-spi
> >> +      - qcom,sa8255p-geni-spi
> > You have entire commit msg to explain why this device's programming
> > model is not compatible with existing generic compatible which must
> > cover all variants (because it is crazy generic).
> >
> > Best regards,
> > Krzysztof
> 
> I will put more details in the description of the patch, though, I had
> put the description in the cover letter for this entire series.

Cover letters do not land in the git repo, so the next person coming to
perform modifications can not understand what was so special about this
platform. Please always provide all reasoning for a change in the commit
message.

-- 
With best wishes
Dmitry

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Krzysztof Kozlowski]

On 04/09/2024 00:02, Nikunj Kela wrote:
> Add compatible representing spi support on SA8255p.
> 
> Clocks and interconnects are being configured in firmware VM
> on SA8255p platform, therefore making them optional.
> 
> CC: Praveen Talari <quic_ptalari@quicinc.com>
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>

Also this is incomplete - adding compatible without driver change is not
expected. It cannot even work.

Best regards,
Krzysztof

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Nikunj Kela]

On 9/4/2024 12:48 AM, Krzysztof Kozlowski wrote:
> On 04/09/2024 00:02, Nikunj Kela wrote:
>> Add compatible representing spi support on SA8255p.
>>
>> Clocks and interconnects are being configured in firmware VM
>> on SA8255p platform, therefore making them optional.
>>
>> CC: Praveen Talari <quic_ptalari@quicinc.com>
>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> Also this is incomplete - adding compatible without driver change is not
> expected. It cannot even work.
>
> Best regards,
> Krzysztof

Link for CLO branch is provided in I2C patch series. The driver changes
will soon follow.

Re: [PATCH v2 16/21] dt-bindings: spi: document support for SA8255p

[Dmitry Baryshkov]

On Wed, Sep 04, 2024 at 05:49:40AM GMT, Nikunj Kela wrote:
> 
> On 9/4/2024 12:48 AM, Krzysztof Kozlowski wrote:
> > On 04/09/2024 00:02, Nikunj Kela wrote:
> >> Add compatible representing spi support on SA8255p.
> >>
> >> Clocks and interconnects are being configured in firmware VM
> >> on SA8255p platform, therefore making them optional.
> >>
> >> CC: Praveen Talari <quic_ptalari@quicinc.com>
> >> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> > Also this is incomplete - adding compatible without driver change is not
> > expected. It cannot even work.
> >
> > Best regards,
> > Krzysztof
> 
> Link for CLO branch is provided in I2C patch series. The driver changes
> will soon follow.

So, what's the point of posting the dt-bindings without corresponding
driver changes?

-- 
With best wishes
Dmitry

[PATCH v2 17/21] dt-bindings: serial: document support for SA8255p

[Nikunj Kela]

Add compatibles representing UART support on SA8255p.

Clocks and interconnects are being configured in the firmware VM
on SA8255p platform, therefore making them optional.

CC: Praveen Talari <quic_ptalari@quicinc.com>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 .../serial/qcom,serial-geni-qcom.yaml         | 53 ++++++++++++++++---
 1 file changed, 47 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
index dd33794b3534..b63c984684f3 100644
--- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
+++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
@@ -10,14 +10,13 @@ maintainers:
   - Andy Gross <agross@kernel.org>
   - Bjorn Andersson <bjorn.andersson@linaro.org>
 
-allOf:
-  - $ref: /schemas/serial/serial.yaml#
-
 properties:
   compatible:
     enum:
       - qcom,geni-uart
       - qcom,geni-debug-uart
+      - qcom,sa8255p-geni-uart
+      - qcom,sa8255p-geni-debug-uart
 
   clocks:
     maxItems: 1
@@ -51,18 +50,49 @@ properties:
       - const: sleep
 
   power-domains:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
+
+  power-domain-names:
+    items:
+      - const: power
+      - const: perf
 
   reg:
     maxItems: 1
 
 required:
   - compatible
-  - clocks
-  - clock-names
   - interrupts
   - reg
 
+allOf:
+  - $ref: /schemas/serial/serial.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,sa8255p-geni-uart
+              - qcom,sa8255p-geni-debug-uart
+    then:
+      required:
+        - power-domains
+        - power-domain-names
+
+      properties:
+        power-domains:
+          minItems: 2
+
+    else:
+      required:
+        - clocks
+        - clock-names
+
+      properties:
+        power-domains:
+          maxItems: 1
+
 unevaluatedProperties: false
 
 examples:
@@ -83,4 +113,15 @@ examples:
                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
         interconnect-names = "qup-core", "qup-config";
     };
+
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    serial@990000 {
+        compatible = "qcom,sa8255p-geni-uart";
+        reg = <0x990000 0x4000>;
+        interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
+        power-domains = <&scmi11_pd 4>, <&scmi11_dvfs 4>;
+        power-domain-names = "power", "perf";
+    };
 ...
-- 
2.34.1

Re: [PATCH v2 17/21] dt-bindings: serial: document support for SA8255p

[Krzysztof Kozlowski]

On Tue, Sep 03, 2024 at 03:02:36PM -0700, Nikunj Kela wrote:
> Add compatibles representing UART support on SA8255p.
> 
> Clocks and interconnects are being configured in the firmware VM
> on SA8255p platform, therefore making them optional.
> 
> CC: Praveen Talari <quic_ptalari@quicinc.com>
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  .../serial/qcom,serial-geni-qcom.yaml         | 53 ++++++++++++++++---
>  1 file changed, 47 insertions(+), 6 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
> index dd33794b3534..b63c984684f3 100644
> --- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
> +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
> @@ -10,14 +10,13 @@ maintainers:
>    - Andy Gross <agross@kernel.org>
>    - Bjorn Andersson <bjorn.andersson@linaro.org>
>  
> -allOf:
> -  - $ref: /schemas/serial/serial.yaml#
> -
>  properties:
>    compatible:
>      enum:
>        - qcom,geni-uart
>        - qcom,geni-debug-uart
> +      - qcom,sa8255p-geni-uart
> +      - qcom,sa8255p-geni-debug-uart

Why devices are not compatible? What changed in programming model?

>  
>    clocks:
>      maxItems: 1
> @@ -51,18 +50,49 @@ properties:
>        - const: sleep
>  
>    power-domains:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 2
> +
> +  power-domain-names:

This does not match power-domains anymore.

> +    items:
> +      - const: power
> +      - const: perf
>  
>    reg:
>      maxItems: 1
>  
>  required:
>    - compatible
> -  - clocks
> -  - clock-names
>    - interrupts
>    - reg
>  
> +allOf:
> +  - $ref: /schemas/serial/serial.yaml#
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - qcom,sa8255p-geni-uart
> +              - qcom,sa8255p-geni-debug-uart
> +    then:
> +      required:
> +        - power-domains
> +        - power-domain-names
> +
> +      properties:
> +        power-domains:
> +          minItems: 2
> +
> +    else:
> +      required:
> +        - clocks
> +        - clock-names
> +
> +      properties:
> +        power-domains:
> +          maxItems: 1
> +
>  unevaluatedProperties: false
>  
>  examples:
> @@ -83,4 +113,15 @@ examples:
>                          <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
>          interconnect-names = "qup-core", "qup-config";
>      };
> +
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    serial@990000 {
> +        compatible = "qcom,sa8255p-geni-uart";
> +        reg = <0x990000 0x4000>;
> +        interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
> +        power-domains = <&scmi11_pd 4>, <&scmi11_dvfs 4>;
> +        power-domain-names = "power", "perf";
> +    };
>  ...
> -- 
> 2.34.1
> 

Re: [PATCH v2 17/21] dt-bindings: serial: document support for SA8255p

[Nikunj Kela]

On 9/3/2024 11:36 PM, Krzysztof Kozlowski wrote:
> On Tue, Sep 03, 2024 at 03:02:36PM -0700, Nikunj Kela wrote:
>> Add compatibles representing UART support on SA8255p.
>>
>> Clocks and interconnects are being configured in the firmware VM
>> on SA8255p platform, therefore making them optional.
>>
>> CC: Praveen Talari <quic_ptalari@quicinc.com>
>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>> ---
>>  .../serial/qcom,serial-geni-qcom.yaml         | 53 ++++++++++++++++---
>>  1 file changed, 47 insertions(+), 6 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>> index dd33794b3534..b63c984684f3 100644
>> --- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>> +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>> @@ -10,14 +10,13 @@ maintainers:
>>    - Andy Gross <agross@kernel.org>
>>    - Bjorn Andersson <bjorn.andersson@linaro.org>
>>  
>> -allOf:
>> -  - $ref: /schemas/serial/serial.yaml#
>> -
>>  properties:
>>    compatible:
>>      enum:
>>        - qcom,geni-uart
>>        - qcom,geni-debug-uart
>> +      - qcom,sa8255p-geni-uart
>> +      - qcom,sa8255p-geni-debug-uart
> Why devices are not compatible? What changed in programming model?

The cover-letter explains what is changed for devices in this platform.
I will add the description in this patch too.


>
>>  
>>    clocks:
>>      maxItems: 1
>> @@ -51,18 +50,49 @@ properties:
>>        - const: sleep
>>  
>>    power-domains:
>> -    maxItems: 1
>> +    minItems: 1
>> +    maxItems: 2
>> +
>> +  power-domain-names:
> This does not match power-domains anymore.

Single power domain doesn't need to use power-domain-names binding as it
is not needed however for multiple(in this case 2), you need to provide
names. I will add this property to if block and only keep maxItems here.


>
>> +    items:
>> +      - const: power
>> +      - const: perf
>>  
>>    reg:
>>      maxItems: 1
>>  
>>  required:
>>    - compatible
>> -  - clocks
>> -  - clock-names
>>    - interrupts
>>    - reg
>>  
>> +allOf:
>> +  - $ref: /schemas/serial/serial.yaml#
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          contains:
>> +            enum:
>> +              - qcom,sa8255p-geni-uart
>> +              - qcom,sa8255p-geni-debug-uart
>> +    then:
>> +      required:
>> +        - power-domains
>> +        - power-domain-names
>> +
>> +      properties:
>> +        power-domains:
>> +          minItems: 2
>> +
>> +    else:
>> +      required:
>> +        - clocks
>> +        - clock-names
>> +
>> +      properties:
>> +        power-domains:
>> +          maxItems: 1
>> +
>>  unevaluatedProperties: false
>>  
>>  examples:
>> @@ -83,4 +113,15 @@ examples:
>>                          <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
>>          interconnect-names = "qup-core", "qup-config";
>>      };
>> +
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +    serial@990000 {
>> +        compatible = "qcom,sa8255p-geni-uart";
>> +        reg = <0x990000 0x4000>;
>> +        interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
>> +        power-domains = <&scmi11_pd 4>, <&scmi11_dvfs 4>;
>> +        power-domain-names = "power", "perf";
>> +    };
>>  ...
>> -- 
>> 2.34.1
>>

Re: [PATCH v2 17/21] dt-bindings: serial: document support for SA8255p

[Krzysztof Kozlowski]

On 04/09/2024 14:54, Nikunj Kela wrote:
> 
> On 9/3/2024 11:36 PM, Krzysztof Kozlowski wrote:
>> On Tue, Sep 03, 2024 at 03:02:36PM -0700, Nikunj Kela wrote:
>>> Add compatibles representing UART support on SA8255p.
>>>
>>> Clocks and interconnects are being configured in the firmware VM
>>> on SA8255p platform, therefore making them optional.
>>>
>>> CC: Praveen Talari <quic_ptalari@quicinc.com>
>>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>>> ---
>>>  .../serial/qcom,serial-geni-qcom.yaml         | 53 ++++++++++++++++---
>>>  1 file changed, 47 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>>> index dd33794b3534..b63c984684f3 100644
>>> --- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>>> +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>>> @@ -10,14 +10,13 @@ maintainers:
>>>    - Andy Gross <agross@kernel.org>
>>>    - Bjorn Andersson <bjorn.andersson@linaro.org>
>>>  
>>> -allOf:
>>> -  - $ref: /schemas/serial/serial.yaml#
>>> -
>>>  properties:
>>>    compatible:
>>>      enum:
>>>        - qcom,geni-uart
>>>        - qcom,geni-debug-uart
>>> +      - qcom,sa8255p-geni-uart
>>> +      - qcom,sa8255p-geni-debug-uart
>> Why devices are not compatible? What changed in programming model?
> 
> The cover-letter explains what is changed for devices in this platform.
> I will add the description in this patch too.

Many of us do not read cover letters. They don't really matter,
especially that serial tree will not include it. Each commit must stand
on its own.

> 
> 
>>
>>>  
>>>    clocks:
>>>      maxItems: 1
>>> @@ -51,18 +50,49 @@ properties:
>>>        - const: sleep
>>>  
>>>    power-domains:
>>> -    maxItems: 1
>>> +    minItems: 1
>>> +    maxItems: 2
>>> +
>>> +  power-domain-names:
>> This does not match power-domains anymore.
> 
> Single power domain doesn't need to use power-domain-names binding as it
> is not needed however for multiple(in this case 2), you need to provide
> names. I will add this property to if block and only keep maxItems here.

The xxx and xxx-names properties always go in sync. Otherwise we do not
really know what is the power domain for other variants.

You are allowed to be unspecific about power domain (so maxItems: 1) if
it is obvious. You now made it non-obvious, so above flexibility does
not apply anymore.

Best regards,
Krzysztof

Re: [PATCH v2 17/21] dt-bindings: serial: document support for SA8255p

[Krzysztof Kozlowski]

On 04/09/2024 00:02, Nikunj Kela wrote:
> Add compatibles representing UART support on SA8255p.
> 
> Clocks and interconnects are being configured in the firmware VM
> on SA8255p platform, therefore making them optional.
> 
> CC: Praveen Talari <quic_ptalari@quicinc.com>
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  .../serial/qcom,serial-geni-qcom.yaml         | 53 ++++++++++++++++---
>  1 file changed, 47 insertions(+), 6 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
> index dd33794b3534..b63c984684f3 100644
> --- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
> +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
> @@ -10,14 +10,13 @@ maintainers:
>    - Andy Gross <agross@kernel.org>
>    - Bjorn Andersson <bjorn.andersson@linaro.org>
>  
> -allOf:
> -  - $ref: /schemas/serial/serial.yaml#
> -
>  properties:
>    compatible:
>      enum:
>        - qcom,geni-uart
>        - qcom,geni-debug-uart
> +      - qcom,sa8255p-geni-uart
> +      - qcom,sa8255p-geni-debug-uart


Anyway, the entire patchset is organized wrong. Or you sent only subset.

Where is the driver change? This cannot work. To remind bindings go with
the driver (nothing new here).

Best regards,
Krzysztof

Re: [PATCH v2 17/21] dt-bindings: serial: document support for SA8255p

[Nikunj Kela]

On 9/4/2024 12:47 AM, Krzysztof Kozlowski wrote:
> On 04/09/2024 00:02, Nikunj Kela wrote:
>> Add compatibles representing UART support on SA8255p.
>>
>> Clocks and interconnects are being configured in the firmware VM
>> on SA8255p platform, therefore making them optional.
>>
>> CC: Praveen Talari <quic_ptalari@quicinc.com>
>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>> ---
>>  .../serial/qcom,serial-geni-qcom.yaml         | 53 ++++++++++++++++---
>>  1 file changed, 47 insertions(+), 6 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>> index dd33794b3534..b63c984684f3 100644
>> --- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>> +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>> @@ -10,14 +10,13 @@ maintainers:
>>    - Andy Gross <agross@kernel.org>
>>    - Bjorn Andersson <bjorn.andersson@linaro.org>
>>  
>> -allOf:
>> -  - $ref: /schemas/serial/serial.yaml#
>> -
>>  properties:
>>    compatible:
>>      enum:
>>        - qcom,geni-uart
>>        - qcom,geni-debug-uart
>> +      - qcom,sa8255p-geni-uart
>> +      - qcom,sa8255p-geni-debug-uart
>
> Anyway, the entire patchset is organized wrong. Or you sent only subset.
>
> Where is the driver change? This cannot work. To remind bindings go with
> the driver (nothing new here).
>
> Best regards,
> Krzysztof

The driver changes will soon be posted. They are being reviewed
internally. For a quick look on what is coming next, you can refer to
CodeLinaro git repo[1]

[1]:
https://git.codelinaro.org/clo/linux-kernel/kernel-qcom/-/tree/nkela/sa8255p_v6_11_rc2?ref_type=heads

Re: [PATCH v2 17/21] dt-bindings: serial: document support for SA8255p

[Krzysztof Kozlowski]

On 04/09/2024 14:56, Nikunj Kela wrote:
> 
> On 9/4/2024 12:47 AM, Krzysztof Kozlowski wrote:
>> On 04/09/2024 00:02, Nikunj Kela wrote:
>>> Add compatibles representing UART support on SA8255p.
>>>
>>> Clocks and interconnects are being configured in the firmware VM
>>> on SA8255p platform, therefore making them optional.
>>>
>>> CC: Praveen Talari <quic_ptalari@quicinc.com>
>>> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
>>> ---
>>>  .../serial/qcom,serial-geni-qcom.yaml         | 53 ++++++++++++++++---
>>>  1 file changed, 47 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>>> index dd33794b3534..b63c984684f3 100644
>>> --- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>>> +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml
>>> @@ -10,14 +10,13 @@ maintainers:
>>>    - Andy Gross <agross@kernel.org>
>>>    - Bjorn Andersson <bjorn.andersson@linaro.org>
>>>  
>>> -allOf:
>>> -  - $ref: /schemas/serial/serial.yaml#
>>> -
>>>  properties:
>>>    compatible:
>>>      enum:
>>>        - qcom,geni-uart
>>>        - qcom,geni-debug-uart
>>> +      - qcom,sa8255p-geni-uart
>>> +      - qcom,sa8255p-geni-debug-uart
>>
>> Anyway, the entire patchset is organized wrong. Or you sent only subset.
>>
>> Where is the driver change? This cannot work. To remind bindings go with
>> the driver (nothing new here).
>>
>> Best regards,
>> Krzysztof
> 
> The driver changes will soon be posted. They are being reviewed
> internally. For a quick look on what is coming next, you can refer to
> CodeLinaro git repo[1]

Upstream does not work like that. This patch is just wrong and pointless
without driver change. Never send such stuff separately from the driver.
Or fix the binding, if the intention was there is no driver.

Best regards,
Krzysztof

Re: [PATCH v2 17/21] dt-bindings: serial: document support for SA8255p

[Andrew Lunn]

> The driver changes will soon be posted. They are being reviewed
> internally.

And what do you do when internal reviewers tell you that everything is
wrong and you need to change the binding? You just wasted a lot of
peoples time.

Please don't post patches until you know they are correct, complete,
build W=1, and pass all the standard static analysers.

I suggest you try to find an experience Mainline developer who can
mentor you.

	Andrew

Re: [PATCH v2 17/21] dt-bindings: serial: document support for SA8255p

[Nikunj Kela]

On 9/4/2024 10:05 AM, Andrew Lunn wrote:
>> The driver changes will soon be posted. They are being reviewed
>> internally.
> And what do you do when internal reviewers tell you that everything is
> wrong and you need to change the binding? You just wasted a lot of
> peoples time.

Let me clarify here, the patches have already been through multiple
rounds of review and since this is new architecture that we are using,
we want to make sure this gets reviewed internally as much as possible.
While, we will be posting them soon, they are available on public git
repo for anyone to take a feel of the amount of changes. Let's not be
judgemental here.


> Please don't post patches until you know they are correct, complete,
> build W=1, and pass all the standard static analysers.
>
> I suggest you try to find an experience Mainline developer who can
> mentor you.

No one is born with experience. You learn as you go. Please note that
this series has gone through internal review before I posted it in
upstream.


> 	Andrew

Re: [PATCH v2 17/21] dt-bindings: serial: document support for SA8255p

[Andrew Lunn]

> No one is born with experience. You learn as you go. Please note that
> this series has gone through internal review before I posted it in
> upstream.

Then i'm surprise you were not told to submit lots of smaller
patchsets, one per subsystem, which are complete.

I get nobody is born with experience, but for a company the size of
Qualcomm, they can easily hire a few experienced mainline developers
who can mentor you, rather than having overloaded Maintainers teach
you the basics, and getting frustrated in the process.

	Andrew

Re: [PATCH v2 17/21] dt-bindings: serial: document support for SA8255p

[Krzysztof Kozlowski]

On 04/09/2024 23:54, Andrew Lunn wrote:
>> No one is born with experience. You learn as you go. Please note that
>> this series has gone through internal review before I posted it in
>> upstream.
> 
> Then i'm surprise you were not told to submit lots of smaller
> patchsets, one per subsystem, which are complete.

We did... multiple times. We gave examples how entire new Qualcomm SoC
should be upstreamed, how this process should be organized. We gave
trainings. Some listen, some not. Sometimes people do not even come to a
training (for free). But there will be always an excuse for patchset
doing something entirely different than community expects...

The patchset here is a result of some misconceptions and not
understanding what is the dependency (claiming there is while there is
no) and what are the maintainer trees.

> 
> I get nobody is born with experience, but for a company the size of
> Qualcomm, they can easily hire a few experienced mainline developers
> who can mentor you, rather than having overloaded Maintainers teach
> you the basics, and getting frustrated in the process.

Best regards,
Krzysztof

[PATCH v2 18/21] dt-bindings: qcom: geni-se: document support for SA8255P

[Nikunj Kela]

Add "qcom,sa8255p-geni-se-qup" compatible for representing QUP on
SA8255p.

Clocks are being managed by the firmware VM and not required on
SA8255p Linux VM hence removing it from required list.

CC: Praveen Talari <quic_ptalari@quicinc.com>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 .../bindings/soc/qcom/qcom,geni-se.yaml       | 45 ++++++++++++++++++-
 1 file changed, 43 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
index 7b031ef09669..86eb2b3832cb 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
@@ -22,6 +22,7 @@ properties:
     enum:
       - qcom,geni-se-qup
       - qcom,geni-se-i2c-master-hub
+      - qcom,sa8255p-geni-se-qup
 
   reg:
     description: QUP wrapper common register address and length.
@@ -57,8 +58,6 @@ properties:
 required:
   - compatible
   - reg
-  - clock-names
-  - clocks
   - "#address-cells"
   - "#size-cells"
   - ranges
@@ -83,6 +82,17 @@ patternProperties:
     $ref: /schemas/serial/qcom,serial-geni-qcom.yaml#
 
 allOf:
+  - if:
+      not:
+        properties:
+          compatible:
+            contains:
+              const: qcom,sa8255p-geni-se-qup
+    then:
+      required:
+        - clocks
+        - clock-names
+
   - if:
       properties:
         compatible:
@@ -162,4 +172,35 @@ examples:
         };
     };
 
+  - |
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        geniqup@9c0000 {
+            compatible = "qcom,sa8255p-geni-se-qup";
+            reg = <0 0x9c0000 0 0x6000>;
+            #address-cells = <2>;
+            #size-cells = <2>;
+            ranges;
+
+            i2c1: i2c@984000 {
+                compatible = "qcom,sa8255p-geni-i2c";
+                reg = <0 0x984000 0 0x4000>;
+                interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                power-domains = <&scmi9_pd 1>;
+            };
+
+            uart4: serial@990000 {
+                compatible = "qcom,sa8255p-geni-uart";
+                reg = <0 0x990000 0 0x4000>;
+                interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
+                power-domains = <&scmi11_pd 4>, <&scmi11_dvfs 4>;
+                power-domain-names = "power", "perf";
+            };
+        };
+    };
 ...
-- 
2.34.1

[PATCH v2 19/21] dt-bindings: firmware: arm,scmi: allow multiple virtual instances

[Nikunj Kela]

This change extends scmi node name so as to allow multiple virtual
SCMI instances.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 Documentation/devicetree/bindings/firmware/arm,scmi.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
index 54d7d11bfed4..5d79b15a1610 100644
--- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
+++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
@@ -27,7 +27,7 @@ anyOf:
 
 properties:
   $nodename:
-    const: scmi
+    pattern: '^scmi(-[0-9]+)?$'
 
   compatible:
     oneOf:
-- 
2.34.1

Re: [PATCH v2 19/21] dt-bindings: firmware: arm,scmi: allow multiple virtual instances

[Krzysztof Kozlowski]

On Tue, Sep 03, 2024 at 03:02:38PM -0700, Nikunj Kela wrote:
> This change extends scmi node name so as to allow multiple virtual
> SCMI instances.
> 
> Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
> ---
>  Documentation/devicetree/bindings/firmware/arm,scmi.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH v2 20/21] dt-bindings: arm: GIC: add ESPI and EPPI specifiers

[Nikunj Kela]

Add interrupt specifier for extended SPI and extended PPI interrupts.

Qualcomm SA8255p platform uses extended SPI for SCMI 'a2p' doorbells.

Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 include/dt-bindings/interrupt-controller/arm-gic.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h
index 35b6f69b7db6..887f53363e8a 100644
--- a/include/dt-bindings/interrupt-controller/arm-gic.h
+++ b/include/dt-bindings/interrupt-controller/arm-gic.h
@@ -12,6 +12,8 @@
 
 #define GIC_SPI 0
 #define GIC_PPI 1
+#define GIC_ESPI 2
+#define GIC_EPPI 3
 
 /*
  * Interrupt specifier cell 2.
-- 
2.34.1

[PATCH v2 21/21] arm64: dts: qcom: Add reduced functional DT for SA8255p Ride platform

[Nikunj Kela]

SA8255p Ride platform is an automotive virtual platform. This platform
abstracts resources such as clocks, regulators etc. in the firmware VM.
The device drivers request resources operations over SCMI using power,
performance, reset and sensor protocols.

Multiple virtual SCMI instances are being employed for greater parallelism.
These instances are tied to devices such that devices can have dedicated
SCMI channel. Firmware VM (runs SCMI platform stack) is SMP enabled and
can process requests from agents in parallel. Qualcomm smc transport is
used for communication between SCMI agent and platform.

Let's add the reduced functional support for SA8255p Ride board.
Subsequently, the support for PCIe, USB, UFS, Ethernet will be added.

Co-developed-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
---
 arch/arm64/boot/dts/qcom/Makefile           |    1 +
 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi |   80 +
 arch/arm64/boot/dts/qcom/sa8255p-ride.dts   |  148 ++
 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi  | 2312 ++++++++++++++++++
 arch/arm64/boot/dts/qcom/sa8255p.dtsi       | 2405 +++++++++++++++++++
 5 files changed, 4946 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts
 create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi
 create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index ae002c7cf126..38e9bf09961d 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -119,6 +119,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= qrb5165-rb5.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qrb5165-rb5-vision-mezzanine.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qru1000-idp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sa8155p-adp.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= sa8255p-ride.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sa8295p-adp.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sa8540p-ride.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= sa8775p-ride.dtb
diff --git a/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
new file mode 100644
index 000000000000..fb268d13b997
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/ {
+	thermal-zones {
+		pmm8654au_0_thermal: pm8255-0-thermal {
+			polling-delay-passive = <100>;
+
+			trips {
+				trip0 {
+					temperature = <105000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		pmm8654au_1_thermal: pm8255-1-thermal {
+			polling-delay-passive = <100>;
+
+			trips {
+				trip0 {
+					temperature = <105000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		pmm8654au_2_thermal: pm8255-2-thermal {
+			polling-delay-passive = <100>;
+
+			trips {
+				trip0 {
+					temperature = <105000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+
+		pmm8654au_3_thermal: pm8255-3-thermal {
+			polling-delay-passive = <100>;
+
+			trips {
+				trip0 {
+					temperature = <105000>;
+					hysteresis = <0>;
+					type = "passive";
+				};
+
+				trip1 {
+					temperature = <125000>;
+					hysteresis = <0>;
+					type = "critical";
+				};
+			};
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/sa8255p-ride.dts b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts
new file mode 100644
index 000000000000..771e8a21484f
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "sa8255p.dtsi"
+#include "sa8255p-pmics.dtsi"
+#include "sa8255p-scmi.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. SA8255P Ride";
+	compatible = "qcom,sa8255p-ride", "qcom,sa8255p";
+
+	aliases {
+		i2c11 = &i2c11;
+		i2c18 = &i2c18;
+		serial0 = &uart10;
+		serial1 = &uart4;
+		spi16 = &spi16;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&adreno_smmu {
+	power-domains = <&scmi15_pd 0>;
+
+	status = "okay";
+};
+
+&gpll0_board_clk {
+	clock-frequency = <300000000>;
+};
+
+&i2c11 {
+	clock-frequency = <400000>;
+	power-domains = <&scmi9_pd 11>;
+
+	status = "okay";
+};
+
+&i2c18 {
+	clock-frequency = <400000>;
+	power-domains = <&scmi9_pd 18>;
+
+	status = "okay";
+};
+
+&pmm8654au_0_thermal {
+	thermal-sensors = <&scmi23_sensor 0>;
+};
+
+&pmm8654au_1_thermal {
+	thermal-sensors = <&scmi23_sensor 1>;
+};
+
+&pmm8654au_2_thermal {
+	thermal-sensors = <&scmi23_sensor 2>;
+};
+
+&pmm8654au_3_thermal {
+	thermal-sensors = <&scmi23_sensor 3>;
+};
+
+&qupv3_id_0 {
+	status = "okay";
+};
+
+&qupv3_id_1 {
+	status = "okay";
+};
+
+&qupv3_id_2 {
+	status = "okay";
+};
+
+&scmi9 {
+	status = "okay";
+};
+
+&scmi10 {
+	status = "okay";
+};
+
+&scmi11 {
+	status = "okay";
+};
+
+&scmi15 {
+	status = "okay";
+};
+
+&scmi23 {
+	status = "okay";
+};
+
+&sleep_clk {
+	clock-frequency = <32000>;
+};
+
+&spi16 {
+	power-domains = <&scmi10_pd 16>, <&scmi10_dvfs 16>;
+	power-domain-names = "power", "perf";
+
+	status = "okay";
+};
+
+&tlmm {
+	ethernet0_default: ethernet0-default-state {
+		ethernet0_mdc: ethernet0-mdc-pins {
+			pins = "gpio8";
+			function = "emac0_mdc";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+
+		ethernet0_mdio: ethernet0-mdio-pins {
+			pins = "gpio9";
+			function = "emac0_mdio";
+			drive-strength = <16>;
+			bias-pull-up;
+		};
+	};
+};
+
+&uart4 {
+	power-domains = <&scmi11_pd 4>, <&scmi11_dvfs 4>;
+	power-domain-names = "power", "perf";
+
+	status = "okay";
+};
+
+&uart10 {
+	power-domains = <&scmi11_pd 10>, <&scmi11_dvfs 10>;
+	power-domain-names = "power", "perf";
+
+	status = "okay";
+};
+
+&xo_board_clk {
+	clock-frequency = <38400000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi b/arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi
new file mode 100644
index 000000000000..a470b68ea4de
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi
@@ -0,0 +1,2312 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&firmware {
+	scmi0: scmi-0 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem0>;
+
+		interrupts = <GIC_SPI 963 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi0_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi0_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi0_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi1: scmi-1 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem1>;
+
+		interrupts = <GIC_SPI 964 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi1_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi1_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi1_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi2: scmi-2 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem2>;
+
+		interrupts = <GIC_SPI 965 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi2_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi2_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi2_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi3: scmi-3 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem3>;
+
+		interrupts = <GIC_SPI 966 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi3_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi3_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi3_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi4: scmi-4 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem4>;
+
+		interrupts = <GIC_SPI 967 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi4_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi4_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi4_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi5: scmi-5 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem5>;
+
+		interrupts = <GIC_SPI 968 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi5_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi5_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi5_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi6: scmi-6 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem6>;
+
+		interrupts = <GIC_SPI 969 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi6_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi6_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi6_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi7: scmi-7 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem7>;
+
+		interrupts = <GIC_SPI 970 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi7_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi7_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi7_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi8: scmi-8 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem8>;
+
+		interrupts = <GIC_SPI 971 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi8_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi8_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi8_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi9: scmi-9 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem9>;
+
+		interrupts = <GIC_SPI 972 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi9_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi9_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi9_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi10: scmi-10 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem10>;
+
+		interrupts = <GIC_SPI 973 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi10_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi10_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi10_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi11: scmi-11 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem11>;
+
+		interrupts = <GIC_SPI 974 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi11_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi11_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi11_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi12: scmi-12 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem12>;
+
+		interrupts = <GIC_SPI 975 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi12_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi12_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi12_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi13: scmi-13 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem13>;
+
+		interrupts = <GIC_SPI 976 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi13_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi13_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi13_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi14: scmi-14 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem14>;
+
+		interrupts = <GIC_SPI 977 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi14_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi14_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi14_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi15: scmi-15 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem15>;
+
+		interrupts = <GIC_SPI 978 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi15_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi15_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi15_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi16: scmi-16 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem16>;
+
+		interrupts = <GIC_SPI 979 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi16_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi16_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi16_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi17: scmi-17 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem17>;
+
+		interrupts = <GIC_SPI 980 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi17_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi17_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi17_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi18: scmi-18 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem18>;
+
+		interrupts = <GIC_SPI 981 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi18_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi18_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi18_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi19: scmi-19 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem19>;
+
+		interrupts = <GIC_SPI 982 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi19_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi19_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi19_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi20: scmi-20 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem20>;
+
+		interrupts = <GIC_SPI 983 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi20_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi20_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi20_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi21: scmi-21 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem21>;
+
+		interrupts = <GIC_SPI 984 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi21_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi21_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi21_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi22: scmi-22 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem22>;
+
+		interrupts = <GIC_SPI 985 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi22_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi22_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi22_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi23: scmi-23 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem23>;
+
+		interrupts = <GIC_SPI 986 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi23_sensor: protocol@15 {
+			reg = <0x15>;
+			#thermal-sensor-cells = <1>;
+		};
+	};
+
+	scmi24: scmi-24 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem24>;
+
+		interrupts = <GIC_SPI 987 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi24_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi24_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi24_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi25: scmi-25 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem25>;
+
+		interrupts = <GIC_ESPI 0 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi25_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi25_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi25_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi26: scmi-26 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem26>;
+
+		interrupts = <GIC_ESPI 1 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi26_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi26_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi26_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi27: scmi-27 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem27>;
+
+		interrupts = <GIC_ESPI 2 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi27_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi27_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi27_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi28: scmi-28 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem28>;
+
+		interrupts = <GIC_ESPI 3 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi28_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi28_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi28_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi29: scmi-29 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem29>;
+
+		interrupts = <GIC_ESPI 4 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi29_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi29_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi29_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi30: scmi-30 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem30>;
+
+		interrupts = <GIC_ESPI 5 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi30_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi30_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi30_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi31: scmi-31 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem31>;
+
+		interrupts = <GIC_ESPI 6 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi31_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi31_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi31_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi32: scmi-32 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem32>;
+
+		interrupts = <GIC_ESPI 7 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi32_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi32_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi32_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi33: scmi-33 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem33>;
+
+		interrupts = <GIC_ESPI 8 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi33_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi33_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi33_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi34: scmi-34 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem34>;
+
+		interrupts = <GIC_ESPI 9 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi34_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi34_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi34_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi35: scmi-35 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem35>;
+
+		interrupts = <GIC_ESPI 10 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi35_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi35_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi35_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi36: scmi-36 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem36>;
+
+		interrupts = <GIC_ESPI 11 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi36_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi36_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi36_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi37: scmi-37 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem37>;
+
+		interrupts = <GIC_ESPI 12 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi37_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi37_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi37_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi38: scmi-38 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem38>;
+
+		interrupts = <GIC_ESPI 13 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi38_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi38_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi38_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi39: scmi-39 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem39>;
+
+		interrupts = <GIC_ESPI 14 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi39_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi39_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi39_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi40: scmi-40 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem40>;
+
+		interrupts = <GIC_ESPI 15 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi40_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi40_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi40_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi41: scmi-41 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem41>;
+
+		interrupts = <GIC_ESPI 16 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi41_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi41_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi41_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi42: scmi-42 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem42>;
+
+		interrupts = <GIC_ESPI 17 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi42_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi42_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi42_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi43: scmi-43 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem43>;
+
+		interrupts = <GIC_ESPI 18 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi43_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi43_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi43_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi44: scmi-44 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem44>;
+
+		interrupts = <GIC_ESPI 19 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi44_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi44_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi44_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi45: scmi-45 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem45>;
+
+		interrupts = <GIC_ESPI 20 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi45_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi45_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi45_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi46: scmi-46 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem46>;
+
+		interrupts = <GIC_ESPI 21 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi46_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi46_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi46_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi47: scmi-47 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem47>;
+
+		interrupts = <GIC_ESPI 22 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi47_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi47_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi47_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi48: scmi-48 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem48>;
+
+		interrupts = <GIC_ESPI 23 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi48_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi48_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi48_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi49: scmi-49 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem49>;
+
+		interrupts = <GIC_ESPI 24 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi49_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi49_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi49_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi50: scmi-50 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem50>;
+
+		interrupts = <GIC_ESPI 25 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi50_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi50_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi50_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi51: scmi-51 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem51>;
+
+		interrupts = <GIC_ESPI 26 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi51_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi51_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi51_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi52: scmi-52 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem52>;
+
+		interrupts = <GIC_ESPI 27 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi52_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi52_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi52_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi53: scmi-53 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem53>;
+
+		interrupts = <GIC_ESPI 28 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi53_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi53_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi53_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi54: scmi-54 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem54>;
+
+		interrupts = <GIC_ESPI 29 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi54_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi54_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi54_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi55: scmi-55 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem55>;
+
+		interrupts = <GIC_ESPI 30 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi55_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi55_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi55_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi56: scmi-56 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem56>;
+
+		interrupts = <GIC_ESPI 31 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi56_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi56_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi56_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi57: scmi-57 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem57>;
+
+		interrupts = <GIC_ESPI 32 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi57_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi57_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi57_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi58: scmi-58 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem58>;
+
+		interrupts = <GIC_ESPI 33 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi58_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi58_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi58_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi59: scmi-59 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem59>;
+
+		interrupts = <GIC_ESPI 34 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi59_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi59_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi59_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi60: scmi-60 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem60>;
+
+		interrupts = <GIC_ESPI 35 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi60_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi60_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi60_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi61: scmi-61 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem61>;
+
+		interrupts = <GIC_ESPI 36 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi61_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi61_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi61_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi62: scmi-62 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem62>;
+
+		interrupts = <GIC_ESPI 37 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi62_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi62_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi62_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+
+	scmi63: scmi-63 {
+		compatible = "qcom,scmi-smc";
+		arm,smc-id = <0xc6008012>;
+		shmem = <&shmem63>;
+
+		interrupts = <GIC_ESPI 38 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "a2p";
+
+		max-rx-timeout-ms = <3000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		status = "disabled";
+
+		scmi63_pd: protocol@11 {
+			reg = <0x11>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi63_dvfs: protocol@13 {
+			reg = <0x13>;
+			#power-domain-cells = <1>;
+		};
+
+		scmi63_rst: protocol@16 {
+			reg = <0x16>;
+			#reset-cells = <1>;
+		};
+	};
+};
+
+&soc {
+	sram@d0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "mmio-sram";
+		reg = <0x0 0xd0000000 0x0 0x40000>;
+		ranges = <0x0 0x0 0x0 0xffffffff>;
+
+		shmem0: scmi-sram@d0000000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0000000 0x1000>;
+		};
+
+		shmem1: scmi-sram@d0001000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0001000 0x1000>;
+		};
+
+		shmem2: scmi-sram@d0002000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0002000 0x1000>;
+		};
+
+		shmem3: scmi-sram@d0003000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0003000 0x1000>;
+		};
+
+		shmem4: scmi-sram@d0004000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0004000 0x1000>;
+		};
+
+		shmem5: scmi-sram@d0005000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0005000 0x1000>;
+		};
+
+		shmem6: scmi-sram@d0006000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0006000 0x1000>;
+		};
+
+		shmem7: scmi-sram@d0007000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0007000 0x1000>;
+		};
+
+		shmem8: scmi-sram@d0008000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0008000 0x1000>;
+		};
+
+		shmem9: scmi-sram@d0009000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0009000 0x1000>;
+		};
+
+		shmem10: scmi-sram@d000a000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd000a000 0x1000>;
+		};
+
+		shmem11: scmi-sram@d000b000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd000b000 0x1000>;
+		};
+
+		shmem12: scmi-sram@d000c000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd000c000 0x1000>;
+		};
+
+		shmem13: scmi-sram@d000d000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd000d000 0x1000>;
+		};
+
+		shmem14: scmi-sram@d000e000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd000e000 0x1000>;
+		};
+
+		shmem15: scmi-sram@d000f000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd000f000 0x1000>;
+		};
+
+		shmem16: scmi-sram@d0010000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0010000 0x1000>;
+		};
+
+		shmem17: scmi-sram@d0011000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0011000 0x1000>;
+		};
+
+		shmem18: scmi-sram@d0012000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0012000 0x1000>;
+		};
+
+		shmem19: scmi-sram@d0013000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0013000 0x1000>;
+		};
+
+		shmem20: scmi-sram@d0014000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0014000 0x1000>;
+		};
+
+		shmem21: scmi-sram@d0015000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0015000 0x1000>;
+		};
+
+		shmem22: scmi-sram@d0016000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0016000 0x1000>;
+		};
+
+		shmem23: scmi-sram@d0017000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0017000 0x1000>;
+		};
+
+		shmem24: scmi-sram@d0018000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0018000 0x1000>;
+		};
+
+		shmem25: scmi-sram@d0019000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0019000 0x1000>;
+		};
+
+		shmem26: scmi-sram@d001a000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd001a000 0x1000>;
+		};
+
+		shmem27: scmi-sram@d001b000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd001b000 0x1000>;
+		};
+
+		shmem28: scmi-sram@d001c000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd001c000 0x1000>;
+		};
+
+		shmem29: scmi-sram@d001d000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd001d000 0x1000>;
+		};
+
+		shmem30: scmi-sram@d001e000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd001e000 0x1000>;
+		};
+
+		shmem31: scmi-sram@d001f000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd001f000 0x1000>;
+		};
+
+		shmem32: scmi-sram@d0020000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0020000 0x1000>;
+		};
+
+		shmem33: scmi-sram@d0021000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0021000 0x1000>;
+		};
+
+		shmem34: scmi-sram@d0022000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0022000 0x1000>;
+		};
+
+		shmem35: scmi-sram@d0023000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0023000 0x1000>;
+		};
+
+		shmem36: scmi-sram@d0024000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0024000 0x1000>;
+		};
+
+		shmem37: scmi-sram@d0025000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0025000 0x1000>;
+		};
+
+		shmem38: scmi-sram@d0026000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0026000 0x1000>;
+		};
+
+		shmem39: scmi-sram@d0027000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0027000 0x1000>;
+		};
+
+		shmem40: scmi-sram@d0028000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0028000 0x1000>;
+		};
+
+		shmem41: scmi-sram@d0029000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0029000 0x1000>;
+		};
+
+		shmem42: scmi-sram@d002a000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd002a000 0x1000>;
+		};
+
+		shmem43: scmi-sram@d002b000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd002b000 0x1000>;
+		};
+
+		shmem44: scmi-sram@d002c000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd002c000 0x1000>;
+		};
+
+		shmem45: scmi-sram@d002d000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd002d000 0x1000>;
+		};
+
+		shmem46: scmi-sram@d002e000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd002e000 0x1000>;
+		};
+
+		shmem47: scmi-sram@d002f000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd002f000 0x1000>;
+		};
+
+		shmem48: scmi-sram@d0030000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0030000 0x1000>;
+		};
+
+		shmem49: scmi-sram@d0031000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0031000 0x1000>;
+		};
+
+		shmem50: scmi-sram@d0032000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0032000 0x1000>;
+		};
+
+		shmem51: scmi-sram@d0033000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0033000 0x1000>;
+		};
+
+		shmem52: scmi-sram@d0034000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0034000 0x1000>;
+		};
+
+		shmem53: scmi-sram@d0035000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0035000 0x1000>;
+		};
+
+		shmem54: scmi-sram@d0036000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0036000 0x1000>;
+		};
+
+		shmem55: scmi-sram@d0037000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0037000 0x1000>;
+		};
+
+		shmem56: scmi-sram@d0038000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0038000 0x1000>;
+		};
+
+		shmem57: scmi-sram@d0039000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd0039000 0x1000>;
+		};
+
+		shmem58: scmi-sram@d003a000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd003a000 0x1000>;
+		};
+
+		shmem59: scmi-sram@d003b000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd003b000 0x1000>;
+		};
+
+		shmem60: scmi-sram@d003c000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd003c000 0x1000>;
+		};
+
+		shmem61: scmi-sram@d003d000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd003d000 0x1000>;
+		};
+
+		shmem62: scmi-sram@d003e000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd003e000 0x1000>;
+		};
+
+		shmem63: scmi-sram@d003f000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0xd003f000 0x1000>;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/qcom/sa8255p.dtsi b/arch/arm64/boot/dts/qcom/sa8255p.dtsi
new file mode 100644
index 000000000000..0c85262a4337
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sa8255p.dtsi
@@ -0,0 +1,2405 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	clocks {
+		xo_board_clk: xo-board-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		gpll0_board_clk: gpll0-board-clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		bi_tcxo_div2: bi-tcxo-div2-clk {
+			compatible = "fixed-factor-clock";
+			clocks = <&xo_board_clk>;
+			clock-mult = <1>;
+			clock-div = <2>;
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			next-level-cache = <&L2_0>;
+			L2_0: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+				L3_0: l3-cache {
+					compatible = "cache";
+					cache-level = <3>;
+					cache-unified;
+				};
+			};
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x100>;
+			enable-method = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			next-level-cache = <&L2_1>;
+			L2_1: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x200>;
+			enable-method = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			next-level-cache = <&L2_2>;
+			L2_2: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x300>;
+			enable-method = "psci";
+			qcom,freq-domain = <&cpufreq_hw 0>;
+			next-level-cache = <&L2_3>;
+			L2_3: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_0>;
+			};
+		};
+
+		cpu4: cpu@10000 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x10000>;
+			enable-method = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1>;
+			next-level-cache = <&L2_4>;
+			L2_4: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_1>;
+				L3_1: l3-cache {
+					compatible = "cache";
+					cache-level = <3>;
+					cache-unified;
+				};
+
+			};
+		};
+
+		cpu5: cpu@10100 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x10100>;
+			enable-method = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1>;
+			next-level-cache = <&L2_5>;
+			L2_5: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_1>;
+			};
+		};
+
+		cpu6: cpu@10200 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x10200>;
+			enable-method = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1>;
+			next-level-cache = <&L2_6>;
+			L2_6: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_1>;
+			};
+		};
+
+		cpu7: cpu@10300 {
+			device_type = "cpu";
+			compatible = "qcom,kryo";
+			reg = <0x0 0x10300>;
+			enable-method = "psci";
+			qcom,freq-domain = <&cpufreq_hw 1>;
+			next-level-cache = <&L2_7>;
+			L2_7: l2-cache {
+				compatible = "cache";
+				cache-level = <2>;
+				cache-unified;
+				next-level-cache = <&L3_1>;
+			};
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+
+			cluster1 {
+				core0 {
+					cpu = <&cpu4>;
+				};
+
+				core1 {
+					cpu = <&cpu5>;
+				};
+
+				core2 {
+					cpu = <&cpu6>;
+				};
+
+				core3 {
+					cpu = <&cpu7>;
+				};
+			};
+		};
+	};
+
+	firmware: firmware {
+		scm {
+			compatible = "qcom,scm-sa8255p", "qcom,scm";
+			memory-region = <&tz_ffi_mem>;
+			qcom,dload-mode = <&tcsr 0x13000>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x0>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		sail_ss_mem: sail-ss@80000000 {
+			reg = <0x0 0x80000000 0x0 0x10000000>;
+			no-map;
+		};
+
+		hyp_mem: hyp@90000000 {
+			reg = <0x0 0x90000000 0x0 0x600000>;
+			no-map;
+		};
+
+		xbl_boot_mem: xbl-boot@90600000 {
+			reg = <0x0 0x90600000 0x0 0x200000>;
+			no-map;
+		};
+
+		aop_image_mem: aop-image@90800000 {
+			reg = <0x0 0x90800000 0x0 0x60000>;
+			no-map;
+		};
+
+		aop_cmd_db_mem: aop-cmd-db@90860000 {
+			compatible = "qcom,cmd-db";
+			reg = <0x0 0x90860000 0x0 0x20000>;
+			no-map;
+		};
+
+		uefi_log: uefi-log@908b0000 {
+			reg = <0x0 0x908b0000 0x0 0x10000>;
+			no-map;
+		};
+
+		ddr_training_checksum: ddr-training-checksum@908c0000 {
+			reg = <0x0 0x908c0000 0x0 0x1000>;
+			no-map;
+		};
+
+		reserved_mem: reserved@908f0000 {
+			reg = <0x0 0x908f0000 0x0 0xe000>;
+			no-map;
+		};
+
+		secdata_apss_mem: secdata-apss@908fe000 {
+			reg = <0x0 0x908fe000 0x0 0x2000>;
+			no-map;
+		};
+
+		smem_mem: smem@90900000 {
+			compatible = "qcom,smem";
+			reg = <0x0 0x90900000 0x0 0x200000>;
+			no-map;
+			hwlocks = <&tcsr_mutex 3>;
+		};
+
+		tz_sail_mailbox_mem: tz-sail-mailbox@90c00000 {
+			reg = <0x0 0x90c00000 0x0 0x100000>;
+			no-map;
+		};
+
+		sail_mailbox_mem: sail-ss@90d00000 {
+			reg = <0x0 0x90d00000 0x0 0x100000>;
+			no-map;
+		};
+
+		sail_ota_mem: sail-ss@90e00000 {
+			reg = <0x0 0x90e00000 0x0 0x300000>;
+			no-map;
+		};
+
+		aoss_backup_mem: aoss-backup@91b00000 {
+			reg = <0x0 0x91b00000 0x0 0x40000>;
+			no-map;
+		};
+
+		cpucp_backup_mem: cpucp-backup@91b40000 {
+			reg = <0x0 0x91b40000 0x0 0x40000>;
+			no-map;
+		};
+
+		tz_config_backup_mem: tz-config-backup@91b80000 {
+			reg = <0x0 0x91b80000 0x0 0x10000>;
+			no-map;
+		};
+
+		ddr_training_data_mem: ddr-training-data@91b90000 {
+			reg = <0x0 0x91b90000 0x0 0x10000>;
+			no-map;
+		};
+
+		cdt_data_backup_mem: cdt-data-backup@91ba0000 {
+			reg = <0x0 0x91ba0000 0x0 0x1000>;
+			no-map;
+		};
+
+		tz_ffi_mem: tz-ffi@91c00000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0x91c00000 0x0 0x1400000>;
+			no-map;
+		};
+
+		lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
+			reg = <0x0 0x93b00000 0x0 0xf00000>;
+			no-map;
+		};
+
+		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
+			reg = <0x0 0x94a00000 0x0 0x800000>;
+			no-map;
+		};
+
+		pil_camera_mem: pil-camera@95200000 {
+			reg = <0x0 0x95200000 0x0 0x500000>;
+			no-map;
+		};
+
+		pil_adsp_mem: pil-adsp@95c00000 {
+			reg = <0x0 0x95c00000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		pil_gdsp0_mem: pil-gdsp0@97b00000 {
+			reg = <0x0 0x97b00000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		pil_gdsp1_mem: pil-gdsp1@99900000 {
+			reg = <0x0 0x99900000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		pil_cdsp0_mem: pil-cdsp0@9b800000 {
+			reg = <0x0 0x9b800000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		pil_gpu_mem: pil-gpu@9d600000 {
+			reg = <0x0 0x9d600000 0x0 0x2000>;
+			no-map;
+		};
+
+		pil_cdsp1_mem: pil-cdsp1@9d700000 {
+			reg = <0x0 0x9d700000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		pil_cvp_mem: pil-cvp@9f500000 {
+			reg = <0x0 0x9f500000 0x0 0x700000>;
+			no-map;
+		};
+
+		pil_video_mem: pil-video@9fc00000 {
+			reg = <0x0 0x9fc00000 0x0 0x700000>;
+			no-map;
+		};
+
+		audio_mdf_mem: audio-mdf-region@ae000000 {
+			reg = <0x0 0xae000000 0x0 0x1000000>;
+			no-map;
+		};
+
+		firmware_mem: firmware-region@b0000000 {
+			reg = <0x0 0xb0000000 0x0 0x800000>;
+			no-map;
+		};
+
+		hyptz_reserved_mem: hyptz-reserved@beb00000 {
+			reg = <0x0 0xbeb00000 0x0 0x11500000>;
+			no-map;
+		};
+
+		scmi_mem: scmi-region@d0000000 {
+			reg = <0x0 0xd0000000 0x0 0x40000>;
+			no-map;
+		};
+
+		firmware_logs_mem: firmware-logs@d0040000 {
+			reg = <0x0 0xd0040000 0x0 0x10000>;
+			no-map;
+		};
+
+		firmware_audio_mem: firmware-audio@d0050000 {
+			reg = <0x0 0xd0050000 0x0 0x4000>;
+			no-map;
+		};
+
+		firmware_reserved_mem: firmware-reserved@d0054000 {
+			reg = <0x0 0xd0054000 0x0 0x9c000>;
+			no-map;
+		};
+
+		firmware_quantum_test_mem: firmware-quantum-test@d00f0000 {
+			reg = <0x0 0xd00f0000 0x0 0x10000>;
+			no-map;
+		};
+
+		tags_mem: tags@d0100000 {
+			reg = <0x0 0xd0100000 0x0 0x1200000>;
+			no-map;
+		};
+
+		qtee_mem: qtee@d1300000 {
+			reg = <0x0 0xd1300000 0x0 0x500000>;
+			no-map;
+		};
+
+		deepsleep_backup_mem: deepsleep-backup@d1800000 {
+			reg = <0x0 0xd1800000 0x0 0x100000>;
+			no-map;
+		};
+
+		trusted_apps_mem: trusted-apps@d1900000 {
+			reg = <0x0 0xd1900000 0x0 0x3800000>;
+			no-map;
+		};
+
+		tz_stat_mem: tz-stat@db100000 {
+			reg = <0x0 0xdb100000 0x0 0x100000>;
+			no-map;
+		};
+
+		cpucp_fw_mem: cpucp-fw@db200000 {
+			reg = <0x0 0xdb200000 0x0 0x100000>;
+			no-map;
+		};
+
+		cma: linux,cma {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
+			reusable;
+			alignment = <0x0 0x400000>;
+			size = <0x0 0x2000000>;
+			linux,cma-default;
+		};
+	};
+
+	soc: soc@0 {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0 0 0 0 0x10 0>;
+
+		ipcc0: mailbox@408000 {
+			compatible = "qcom,sa8255p-ipcc", "qcom,ipcc";
+			reg = <0x0 0x00408000 0x0 0x1000>;
+			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#mbox-cells = <2>;
+		};
+
+		ipcc1: mailbox@488000 {
+			compatible = "qcom,sa8255p-ipcc", "qcom,ipcc";
+			reg = <0x0 0x00488000 0x0 0x1000>;
+			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#mbox-cells = <2>;
+			status = "disabled";
+		};
+
+		qupv3_id_2: geniqup@8c0000 {
+			compatible = "qcom,sa8255p-geni-se-qup";
+			reg = <0x0 0x008c0000 0x0 0x6000>;
+			ranges;
+			iommus = <&apps_smmu 0x5a3 0x0>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+
+			i2c14: i2c@880000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x880000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi14: spi@880000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x880000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart14: serial@880000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00880000 0x0 0x4000>;
+				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c15: i2c@884000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x884000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi15: spi@884000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x884000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart15: serial@884000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00884000 0x0 0x4000>;
+				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c16: i2c@888000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x888000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi16: spi@888000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x00888000 0x0 0x4000>;
+				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			uart16: serial@888000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00888000 0x0 0x4000>;
+				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c17: i2c@88c000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x88c000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi17: spi@88c000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x88c000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart17: serial@88c000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x0088c000 0x0 0x4000>;
+				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c18: i2c@890000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x00890000 0x0 0x4000>;
+				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			spi18: spi@890000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x890000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart18: serial@890000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00890000 0x0 0x4000>;
+				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c19: i2c@894000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x894000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi19: spi@894000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x894000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart19: serial@894000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00894000 0x0 0x4000>;
+				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c20: i2c@898000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x898000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi20: spi@898000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x898000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart20: serial@898000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00898000 0x0 0x4000>;
+				interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		qupv3_id_0: geniqup@9c0000 {
+			compatible = "qcom,sa8255p-geni-se-qup";
+			reg = <0x0 0x9c0000 0x0 0x6000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			iommus = <&apps_smmu 0x403 0x0>;
+			status = "disabled";
+
+			i2c0: i2c@980000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x980000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi0: spi@980000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x980000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart0: serial@980000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x980000 0x0 0x4000>;
+				interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@984000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x984000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi1: spi@984000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x984000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart1: serial@984000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x984000 0x0 0x4000>;
+				interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c2: i2c@988000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x988000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi2: spi@988000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x988000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart2: serial@988000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x988000 0x0 0x4000>;
+				interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@98c000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x98c000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi3: spi@98c000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x98c000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart3: serial@98c000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x98c000 0x0 0x4000>;
+				interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c4: i2c@990000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x990000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi4: spi@990000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x990000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart4: serial@990000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x990000 0x0 0x4000>;
+				interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c5: i2c@994000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0x994000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi5: spi@994000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0x994000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart5: serial@994000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x994000 0x0 0x4000>;
+				interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		qupv3_id_1: geniqup@ac0000 {
+			compatible = "qcom,sa8255p-geni-se-qup";
+			reg = <0x0 0x00ac0000 0x0 0x6000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			iommus = <&apps_smmu 0x443 0x0>;
+			status = "disabled";
+
+			i2c7: i2c@a80000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0xa80000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi7: spi@a80000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0xa80000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart7: serial@a80000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00a80000 0x0 0x4000>;
+				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c8: i2c@a84000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0xa84000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi8: spi@a84000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0xa84000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart8: serial@a84000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00a84000 0x0 0x4000>;
+				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c9: i2c@a88000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0xa88000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi9: spi@a88000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0xa88000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart9: serial@a88000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0xa88000 0x0 0x4000>;
+				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c10: i2c@a8c000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0xa8c000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi10: spi@a8c000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0xa8c000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart10: serial@a8c000 {
+				compatible = "qcom,sa8255p-geni-debug-uart";
+				reg = <0x0 0x00a8c000 0x0 0x4000>;
+				interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c11: i2c@a90000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0xa90000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi11: spi@a90000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0xa90000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart11: serial@a90000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00a90000 0x0 0x4000>;
+				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c12: i2c@a94000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0xa94000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi12: spi@a94000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0xa94000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart12: serial@a94000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00a94000 0x0 0x4000>;
+				interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			i2c13: i2c@a98000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0xa98000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		qupv3_id_3: geniqup@bc0000 {
+			compatible = "qcom,sa8255p-geni-se-qup";
+			reg = <0x0 0xbc0000 0x0 0x6000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+			iommus = <&apps_smmu 0x43 0x0>;
+			status = "disabled";
+
+			i2c21: i2c@b80000 {
+				compatible = "qcom,sa8255p-geni-i2c";
+				reg = <0x0 0xb80000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			spi21: spi@b80000 {
+				compatible = "qcom,sa8255p-geni-spi";
+				reg = <0x0 0xb80000 0x0 0x4000>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			uart21: serial@b80000 {
+				compatible = "qcom,sa8255p-geni-uart";
+				reg = <0x0 0x00b80000 0x0 0x4000>;
+				interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+
+		rng: rng@10d2000 {
+			compatible = "qcom,sa8255p-trng", "qcom,trng";
+			reg = <0x0 0x010d2000 0x0 0x1000>;
+		};
+
+		tcsr_mutex: hwlock@1f40000 {
+			compatible = "qcom,tcsr-mutex";
+			reg = <0x0 0x01f40000 0x0 0x20000>;
+			#hwlock-cells = <1>;
+		};
+
+		tcsr: syscon@1fc0000 {
+			compatible = "qcom,sa8255p-tcsr", "syscon";
+			reg = <0x0 0x1fc0000 0x0 0x30000>;
+		};
+
+		adreno_smmu: iommu@3da0000 {
+			compatible = "qcom,sa8255p-smmu-500", "qcom,adreno-smmu",
+				     "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x03da0000 0x0 0x20000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <2>;
+			dma-coherent;
+			interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pdc: interrupt-controller@b220000 {
+			compatible = "qcom,sa8255p-pdc", "qcom,pdc";
+			reg = <0x0 0x0b220000 0x0 0x30000>,
+			      <0x0 0x17c000f0 0x0 0x64>;
+			qcom,pdc-ranges = <0 480 40>,
+					  <40 140 14>,
+					  <54 263 1>,
+					  <55 306 4>,
+					  <59 312 3>,
+					  <62 374 2>,
+					  <64 434 2>,
+					  <66 438 2>,
+					  <70 520 1>,
+					  <73 523 1>,
+					  <118 568 6>,
+					  <124 609 3>,
+					  <159 638 1>,
+					  <160 720 3>,
+					  <169 728 30>,
+					  <199 416 2>,
+					  <201 449 1>,
+					  <202 89 1>,
+					  <203 451 1>,
+					  <204 462 1>,
+					  <205 264 1>,
+					  <206 579 1>,
+					  <207 653 1>,
+					  <208 656 1>,
+					  <209 659 1>,
+					  <210 122 1>,
+					  <211 699 1>,
+					  <212 705 1>,
+					  <213 450 1>,
+					  <214 643 2>,
+					  <216 646 5>,
+					  <221 390 5>,
+					  <226 700 2>,
+					  <228 440 1>,
+					  <229 663 1>,
+					  <230 524 2>,
+					  <232 612 3>,
+					  <235 723 5>;
+			#interrupt-cells = <2>;
+			interrupt-parent = <&intc>;
+			interrupt-controller;
+		};
+
+		tsens2: thermal-sensor@c251000 {
+			compatible = "qcom,sa8255p-tsens", "qcom,tsens-v2";
+			reg = <0x0 0x0c251000 0x0 0x1ff>,
+			      <0x0 0x0c224000 0x0 0x8>;
+			interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>;
+			#qcom,sensors = <13>;
+			interrupt-names = "uplow", "critical";
+			#thermal-sensor-cells = <1>;
+		};
+
+		tsens3: thermal-sensor@c252000 {
+			compatible = "qcom,sa8255p-tsens", "qcom,tsens-v2";
+			reg = <0x0 0x0c252000 0x0 0x1ff>,
+			      <0x0 0x0c225000 0x0 0x8>;
+			interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
+			#qcom,sensors = <13>;
+			interrupt-names = "uplow", "critical";
+			#thermal-sensor-cells = <1>;
+		};
+
+		tsens0: thermal-sensor@c263000 {
+			compatible = "qcom,sa8255p-tsens", "qcom,tsens-v2";
+			reg = <0x0 0x0c263000 0x0 0x1ff>,
+			      <0x0 0x0c222000 0x0 0x8>;
+			interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+			#qcom,sensors = <12>;
+			interrupt-names = "uplow", "critical";
+			#thermal-sensor-cells = <1>;
+		};
+
+		tsens1: thermal-sensor@c265000 {
+			compatible = "qcom,sa8255p-tsens", "qcom,tsens-v2";
+			reg = <0x0 0x0c265000 0x0 0x1ff>,
+			      <0x0 0x0c223000 0x0 0x8>;
+			interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+			#qcom,sensors = <12>;
+			interrupt-names = "uplow", "critical";
+			#thermal-sensor-cells = <1>;
+		};
+
+		aoss_qmp: power-management@c300000 {
+			compatible = "qcom,sa8255p-aoss-qmp", "qcom,aoss-qmp";
+			reg = <0x0 0x0c300000 0x0 0x400>;
+			interrupts-extended = <&ipcc0 IPCC_CLIENT_AOP
+					       IPCC_MPROC_SIGNAL_GLINK_QMP
+					       IRQ_TYPE_EDGE_RISING>;
+			mboxes = <&ipcc0 IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+			#clock-cells = <0>;
+		};
+
+		tlmm: pinctrl@f000000 {
+			compatible = "qcom,sa8255p-tlmm", "qcom,sa8775p-tlmm";
+			reg = <0x0 0x0f000000 0x0 0x1000000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 149>;
+			wakeup-parent = <&pdc>;
+		};
+
+		apps_smmu: iommu@15000000 {
+			compatible = "qcom,sa8255p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
+			reg = <0x0 0x15000000 0x0 0x100000>;
+			#iommu-cells = <2>;
+			#global-interrupts = <2>;
+
+			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		intc: interrupt-controller@17a00000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x17a00000 0x0 0x10000>,	/* GICD */
+			      <0x0 0x17a60000 0x0 0x100000>;	/* GICR * 8 */
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			#redistributor-regions = <1>;
+			redistributor-stride = <0x0 0x20000>;
+		};
+
+		watchdog@17c10000 {
+			compatible = "qcom,apss-wdt-sa8255p", "qcom,kpss-wdt";
+			reg = <0x0 0x17c10000 0x0 0x1000>;
+			clocks = <&sleep_clk>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
+		};
+
+		memtimer: timer@17c20000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0x0 0x17c20000 0x0 0x1000>;
+			ranges = <0x0 0x0 0x0 0x20000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			frame@17c21000 {
+				reg = <0x17c21000 0x1000>,
+				      <0x17c22000 0x1000>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <0>;
+			};
+
+			frame@17c23000 {
+				reg = <0x17c23000 0x1000>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <1>;
+				status = "disabled";
+			};
+
+			frame@17c25000 {
+				reg = <0x17c25000 0x1000>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <2>;
+				status = "disabled";
+			};
+
+			frame@17c27000 {
+				reg = <0x17c27000 0x1000>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <3>;
+				status = "disabled";
+			};
+
+			frame@17c29000 {
+				reg = <0x17c29000 0x1000>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <4>;
+				status = "disabled";
+			};
+
+			frame@17c2b000 {
+				reg = <0x17c2b000 0x1000>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <5>;
+				status = "disabled";
+			};
+
+			frame@17c2d000 {
+				reg = <0x17c2d000 0x1000>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				frame-number = <6>;
+				status = "disabled";
+			};
+		};
+
+		cpufreq_hw: cpufreq@18591000 {
+			compatible = "qcom,sa8255p-cpufreq-epss",
+				     "qcom,cpufreq-epss";
+			reg = <0x0 0x18591000 0x0 0x1000>,
+			      <0x0 0x18593000 0x0 0x1000>;
+			reg-names = "freq-domain0", "freq-domain1";
+
+			clocks = <&bi_tcxo_div2>, <&gpll0_board_clk>;
+			clock-names = "xo", "alternate";
+
+			#freq-domain-cells = <1>;
+		};
+	};
+
+	thermal-zones {
+		aoss-0-thermal {
+			thermal-sensors = <&tsens0 0>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-0-0-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens0 1>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-0-1-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens0 2>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-0-2-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens0 3>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-0-3-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens0 4>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		gpuss-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens0 5>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		gpuss-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens0 6>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		gpuss-2-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens0 7>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		audio-thermal {
+			thermal-sensors = <&tsens0 8>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		camss-0-thermal {
+			thermal-sensors = <&tsens0 9>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		pcie-0-thermal {
+			thermal-sensors = <&tsens0 10>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpuss-0-0-thermal {
+			thermal-sensors = <&tsens0 11>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		aoss-1-thermal {
+			thermal-sensors = <&tsens1 0>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-0-0-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens1 1>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-0-1-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens1 2>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-0-2-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens1 3>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-0-3-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens1 4>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		gpuss-3-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens1 5>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		gpuss-4-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens1 6>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		gpuss-5-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens1 7>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		video-thermal {
+			thermal-sensors = <&tsens1 8>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		camss-1-thermal {
+			thermal-sensors = <&tsens1 9>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		pcie-1-thermal {
+			thermal-sensors = <&tsens1 10>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpuss-0-1-thermal {
+			thermal-sensors = <&tsens1 11>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		aoss-2-thermal {
+			thermal-sensors = <&tsens2 0>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-1-0-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 1>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-1-1-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 2>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-1-2-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 3>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-1-3-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 4>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-0-0-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 5>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-0-1-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 6>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-0-2-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 7>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-1-0-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 8>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-1-1-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 9>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-1-2-0-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens2 10>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		ddrss-0-thermal {
+			thermal-sensors = <&tsens2 11>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpuss-1-0-thermal {
+			thermal-sensors = <&tsens2 12>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		aoss-3-thermal {
+			thermal-sensors = <&tsens3 0>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-1-0-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 1>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-1-1-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 2>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-1-2-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 3>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpu-1-3-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 4>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-0-0-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 5>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-0-1-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 6>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-0-2-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 7>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-1-0-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 8>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-1-1-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 9>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		nsp-1-2-1-thermal {
+			polling-delay-passive = <10>;
+
+			thermal-sensors = <&tsens3 10>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		ddrss-1-thermal {
+			thermal-sensors = <&tsens3 11>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+
+		cpuss-1-1-thermal {
+			thermal-sensors = <&tsens3 12>;
+
+			trips {
+				trip-point0 {
+					temperature = <105000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+
+				trip-point1 {
+					temperature = <115000>;
+					hysteresis = <5000>;
+					type = "passive";
+				};
+			};
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
-- 
2.34.1

Re: [PATCH v2 00/21] arm64: qcom: Introduce SA8255p Ride platform

[Krzysztof Kozlowski]

On Tue, Sep 03, 2024 at 03:02:19PM -0700, Nikunj Kela wrote:
> This series enables the support for SA8255p Qualcomm SoC and Ride
> platform. This platform uses SCMI power, reset, performance, sensor
> protocols for resources(e.g. clocks, regulator, interconnect, phy etc.)
> management. SA8255p is a virtual platforms that uses Qualcomm smc/hvc
> transport driver.
> 
> Multiple virtual SCMI instances are being used to achieve the parallelism.
> SCMI platform stack runs in SMP enabled VM hence allows platform to service
> multiple resource requests in parallel. Each device is assigned its own
> dedicated SCMI channel and Tx/Rx doorbells.
> 

Do not attach (thread) your patchsets to some other threads (unrelated
or older versions). This buries them deep in the mailbox and might
interfere with applying entire sets.

It does not look like you tested the bindings, at least after quick
look. Please run  (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).
Maybe you need to update your dtschema and yamllint.

Best regards,
Krzysztof

Re: [PATCH v2 00/21] arm64: qcom: Introduce SA8255p Ride platform

[Nikunj Kela]

On 9/3/2024 10:54 PM, Krzysztof Kozlowski wrote:
> On Tue, Sep 03, 2024 at 03:02:19PM -0700, Nikunj Kela wrote:
>> This series enables the support for SA8255p Qualcomm SoC and Ride
>> platform. This platform uses SCMI power, reset, performance, sensor
>> protocols for resources(e.g. clocks, regulator, interconnect, phy etc.)
>> management. SA8255p is a virtual platforms that uses Qualcomm smc/hvc
>> transport driver.
>>
>> Multiple virtual SCMI instances are being used to achieve the parallelism.
>> SCMI platform stack runs in SMP enabled VM hence allows platform to service
>> multiple resource requests in parallel. Each device is assigned its own
>> dedicated SCMI channel and Tx/Rx doorbells.
>>
> Do not attach (thread) your patchsets to some other threads (unrelated
> or older versions). This buries them deep in the mailbox and might
> interfere with applying entire sets.
>
> It does not look like you tested the bindings, at least after quick
> look. Please run  (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
> Maybe you need to update your dtschema and yamllint.
>
> Best regards,
> Krzysztof

Will fix spaces and send v3 in separate thread. Thanks

Re: [PATCH v2 00/21] arm64: qcom: Introduce SA8255p Ride platform

[Nikunj Kela]

Hi All,

I have decided to split this series into multiple smaller ones as follows:

- Patches 1/21 - 11/21, 13/21 - 14/21, 19/21: will split them to each
subsystem specific patch sets.

- Patches 15/21 - 18/21: will come in separate series along with QUPs
driver changes.

- Patches 20/21 - 21/21: will come in separate series after above two
sets are accepted.

Thanks,

-Nikunj


On 9/3/2024 3:02 PM, Nikunj Kela wrote:
> This series enables the support for SA8255p Qualcomm SoC and Ride
> platform. This platform uses SCMI power, reset, performance, sensor
> protocols for resources(e.g. clocks, regulator, interconnect, phy etc.)
> management. SA8255p is a virtual platforms that uses Qualcomm smc/hvc
> transport driver.
>
> Multiple virtual SCMI instances are being used to achieve the parallelism.
> SCMI platform stack runs in SMP enabled VM hence allows platform to service
> multiple resource requests in parallel. Each device is assigned its own
> dedicated SCMI channel and Tx/Rx doorbells.
>
> Resource operations are grouped together to achieve better abstraction
> and to reduce the number of requests being sent to SCMI platform(server)
> thus improving boot time KPIs. This design approach was presented during
> LinaroConnect 2024 conference[1].
>
> Architecture:
> ------------
>                                                           +--------------------+
>                                                           |   Shared Memory    |
>                                                           |                    |
>                                                           | +----------------+ |                +----------------------------------+
>      +----------------------------+                     +-+->  ufs-shmem     <-+---+            |            Linux VM              |
>      |        Firmware VM         |                     | | +----------------+ |   |            |   +----------+   +----------+    |
>      |                            |                     | |                    |   |            |   |   UFS    |   |   PCIe   |    |
>      | +---------+ f +----------+ |                     | |                    |   |            |   |  Driver  |   |  Driver  |    |
>      | |Drivers  <---+  SCMI    | |        e            | |         |          |   |            |   +--+----^--+   +----------+    |
>      | | (clks,  | g | Server   +-+---------------------+ |                    |   |            |      |    |                      |
>      | |  vreg,  +--->          | |        h              |         |          |  b|k           |     a|   l|                      |
>      | |  gpio,  |   +--^-----+-+ |                       |                    |   |            |      |    |                      |
>      | |  phy,   |      |     |   |                       |         |          |   |            |  +---v----+----+  +----------+   |
>      | |  etc.)  |      |     |   |                       |                    |   +------------+--+  UFS SCMI   |  | PCIe SCMI|   |
>      | +---------+      |     |   |                       |                    |                |  |  INSTANCE   |  | INSTANCE |   |
>      |                  |     |   |                       |  +---------------+ |                |  +-^-----+-----+  +----------+   |
>      |                  |     |   |                       |  |  pcie-shmem   | |                |    |     |                       |
>      +------------------+-----+---+                       |  +---------------+ |                +----+-----+-----------------------+
>                         |     |                           |                    |                     |     |
>                         |     |                           +--------------------+                     |     |
>                        d|IRQ i|HVC                                                                  j|IRQ c|HVC
>                         |     |                                                                      |     |
>                         |     |                                                                      |     |
> +-----------------------+-----v----------------------------------------------------------------------+-----v------------------------------+
> |                                                                                                                                         |
> |                                                                                                                                         |
> |                                                                                                                                         |
> |                                                               HYPERVISOR                                                                |
> |                                                                                                                                         |
> |                                                                                                                                         |
> +-----------------------------------------------------------------------------------------------------------------------------------------+
>
>         +--------+   +--------+                                                                         +----------+  +-----------+
>         | CLOCK  |   |  PHY   |                                                                         |   UFS    |  |   PCIe    |
>         +--------+   +--------+                                                                         +----------+  +-----------+
>
>
> This series is based on next-20240903.
>
> [1]: https://resources.linaro.org/en/resource/wfnfEwBhRjLV1PEAJoDDte
>
> ---
> Changes in v2:
>   - Patch 1/21 - 11/21
>     - Added Reviewed-by tag
>
>   - Patch 12/21
>     - Already applied in the maintainers tree
>
>   - Patch 13/21
>     - Modified subject line
>     - Fixed schema to include fallback
>
>   - Patch 14/21
>     - Added constraints
>
>   - Patch 15/21
>     - Modified schema to remove useless text
>    
>   - Patch 16/21
>     - Modified schema formatting
>     - Amended schema definition as advised
>
>   - Patch 17/21
>     - Moved allOf block after required
>     - Fixed formatting
>     - Modified schema to remove useless text
>
>   - Patch 18/21
>     - Fixed clock property changes
>
>   - Patch 19/21
>     - Fixed scmi nodename pattern
>
>   - Patch 20/21
>     - Modified subject line and description
>     - Added EPPI macro
>
>   - Patch 21/21
>     - Removed scmichannels label and alias
>     - Modified scmi node name to conform to schema
>     - Moved status property to be the last one in scmi instances
>     - Changed to lower case for cpu labels
>     - Added fallback compatible for tlmm node
>
> Nikunj Kela (21):
>   dt-bindings: arm: qcom: add the SoC ID for SA8255P
>   soc: qcom: socinfo: add support for SA8255P
>   dt-bindings: arm: qcom: add SA8255p Ride board
>   dt-bindings: firmware: qcom,scm: document support for SA8255p
>   dt-bindings: mailbox: qcom-ipcc: document the support for SA8255p
>   dt-bindings: watchdog: qcom-wdt: document support on SA8255p
>   dt-bindings: crypto: qcom,prng: document support for SA8255p
>   dt-bindings: interrupt-controller: qcom-pdc: document support for
>     SA8255p
>   dt-bindings: soc: qcom: aoss-qmp: document support for SA8255p
>   dt-bindings: arm-smmu: document the support on SA8255p
>   dt-bindings: mfd: qcom,tcsr: document support for SA8255p
>   dt-bindings: thermal: tsens: document support on SA8255p
>   dt-bindings: pinctrl: Add SA8255p TLMM
>   dt-bindings: cpufreq: qcom-hw: document support for SA8255p
>   dt-bindings: i2c: document support for SA8255p
>   dt-bindings: spi: document support for SA8255p
>   dt-bindings: serial: document support for SA8255p
>   dt-bindings: qcom: geni-se: document support for SA8255P
>   dt-bindings: firmware: arm,scmi: allow multiple virtual instances
>   dt-bindings: arm: GIC: add ESPI and EPPI specifiers
>   arm64: dts: qcom: Add reduced functional DT for SA8255p Ride platform
>
>  .../devicetree/bindings/arm/qcom.yaml         |    6 +
>  .../bindings/cpufreq/cpufreq-qcom-hw.yaml     |   16 +
>  .../devicetree/bindings/crypto/qcom,prng.yaml |    1 +
>  .../bindings/firmware/arm,scmi.yaml           |    2 +-
>  .../bindings/firmware/qcom,scm.yaml           |    2 +
>  .../bindings/i2c/qcom,i2c-geni-qcom.yaml      |   33 +-
>  .../interrupt-controller/qcom,pdc.yaml        |    1 +
>  .../devicetree/bindings/iommu/arm,smmu.yaml   |    3 +
>  .../bindings/mailbox/qcom-ipcc.yaml           |    1 +
>  .../devicetree/bindings/mfd/qcom,tcsr.yaml    |    1 +
>  .../bindings/pinctrl/qcom,sa8775p-tlmm.yaml   |    8 +-
>  .../serial/qcom,serial-geni-qcom.yaml         |   53 +-
>  .../bindings/soc/qcom/qcom,aoss-qmp.yaml      |    1 +
>  .../bindings/soc/qcom/qcom,geni-se.yaml       |   45 +-
>  .../bindings/spi/qcom,spi-geni-qcom.yaml      |   60 +-
>  .../bindings/thermal/qcom-tsens.yaml          |    1 +
>  .../bindings/watchdog/qcom-wdt.yaml           |    1 +
>  arch/arm64/boot/dts/qcom/Makefile             |    1 +
>  arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi   |   80 +
>  arch/arm64/boot/dts/qcom/sa8255p-ride.dts     |  148 +
>  arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi    | 2312 ++++++++++++++++
>  arch/arm64/boot/dts/qcom/sa8255p.dtsi         | 2405 +++++++++++++++++
>  drivers/soc/qcom/socinfo.c                    |    1 +
>  include/dt-bindings/arm/qcom,ids.h            |    1 +
>  .../interrupt-controller/arm-gic.h            |    2 +
>  25 files changed, 5169 insertions(+), 16 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-pmics.dtsi
>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts
>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-scmi.dtsi
>  create mode 100644 arch/arm64/boot/dts/qcom/sa8255p.dtsi
>
>
> base-commit: 6804f0edbe7747774e6ae60f20cec4ee3ad7c187

Re: [PATCH v2 00/21] arm64: qcom: Introduce SA8255p Ride platform

[Dmitry Baryshkov]

On Tue, Sep 03, 2024 at 03:02:19PM GMT, Nikunj Kela wrote:
> This series enables the support for SA8255p Qualcomm SoC and Ride
> platform. This platform uses SCMI power, reset, performance, sensor
> protocols for resources(e.g. clocks, regulator, interconnect, phy etc.)
> management. SA8255p is a virtual platforms that uses Qualcomm smc/hvc
> transport driver.
> 
> Multiple virtual SCMI instances are being used to achieve the parallelism.
> SCMI platform stack runs in SMP enabled VM hence allows platform to service
> multiple resource requests in parallel. Each device is assigned its own
> dedicated SCMI channel and Tx/Rx doorbells.
> 
> Resource operations are grouped together to achieve better abstraction
> and to reduce the number of requests being sent to SCMI platform(server)
> thus improving boot time KPIs. This design approach was presented during
> LinaroConnect 2024 conference[1].

Please don't send new revisions as a reply to the previous patchset.
Always start new thread for new submission. This is documented in your
internal 'upstreaming' documents. If it is not, please update them.

-- 
With best wishes
Dmitry