[PATCH 00/15] Add support for Renesas RZ/V2N SoC and EVK

[PATCH 00/15] Add support for Renesas RZ/V2N SoC and EVK

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

This patch series adds initial support for the Renesas RZ/V2N (R9A09G056)
SoC and its evaluation board (EVK). The Renesas RZ/V2N is a vision AI
microprocessor (MPU) designed for power-efficient AI inference and
real-time vision processing. It features Renesas' proprietary AI
accelerator (DRP-AI3), delivering up to 15 TOPS AI performance, making
it ideal for applications such as Driver Monitoring Systems (DMS),
industrial monitoring cameras, and mobile robots.

Key features of the RZ/V2N SoC:
  Processing Power:
    - Quad Arm Cortex-A55 cores at 1.8GHz for high-performance computing
    - Single Arm Cortex-M33 core at 200MHz for real-time processing
    - 1.5MB on-chip SRAM for fast data access
    - LPDDR4/LPDDR4X memory interface for high-speed RAM access

  AI and Vision Processing:
    - DRP-AI3 accelerator for low-power, high-efficiency AI inference
    - Arm Mali-C55 ISP (optional) for image signal processing
    - Dual MIPI CSI-2 camera interfaces for multi-camera support

  High-Speed Interfaces:
    - PCIe Gen3 (2-lane) 1ch for external device expansion
    - USB 3.2 (Gen2) 1ch (Host-only) for high-speed data transfer
    - USB 2.0 (Host/Function) 1ch for legacy connectivity
    - Gigabit Ethernet (2 channels) for network communication

  Industrial and Automotive Features:
    - 6x CAN FD channels for automotive and industrial networking
    - 24-channel ADC for sensor data acquisition

LINK: https://tinyurl.com/renesas-rz-v2n-soc

The series introduces:
- Device tree bindings for various subsystems (SYS, SCIF, SDHI, CPG, pinctrl).
- RZ/V2N SoC identification support.
- Clock and pinctrl driver updates for RZ/V2N.
- Initial DTSI and device tree for the RZ/V2N SoC and EVK.
- Enabling RZ/V2N SoC support in `arm64 defconfig`.

These patches have been tested on the RZ/V2N EVK with v6.14,
logs can be found here https://pastebin.com/8i3jgVby 

Cheers,
Prabhakar

Lad Prabhakar (15):
  dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants
  dt-bindings: soc: renesas: Document RZ/V2N EVK board
  soc: renesas: Add config option for RZ/V2N (R9A09G056) SoC
  dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
  soc: renesas: sysc: Add SoC identification for RZ/V2N SoC
  dt-bindings: serial: renesas: Document RZ/V2N SCIF
  dt-bindings: mmc: renesas,sdhi: Document RZ/V2N support
  dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
  clk: renesas: rzv2h-cpg: Sort compatible list based on SoC part number
  clk: renesas: rzv2h: Add support for RZ/V2N SoC
  dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
  pinctrl: renesas: rzg2l: Add support for RZ/V2N SoC
  arm64: dts: renesas: Add initial SoC DTSI for RZ/V2N
  arm64: dts: renesas: Add initial device tree for RZ/V2N EVK
  arm64: defconfig: Enable Renesas RZ/V2N SoC

 .../bindings/clock/renesas,rzv2h-cpg.yaml     |   5 +-
 .../devicetree/bindings/mmc/renesas,sdhi.yaml |   4 +-
 .../pinctrl/renesas,rzg2l-pinctrl.yaml        |   2 +
 .../bindings/serial/renesas,scif.yaml         |   1 +
 .../soc/renesas/renesas,r9a09g057-sys.yaml    |   1 +
 .../bindings/soc/renesas/renesas.yaml         |  15 +
 arch/arm64/boot/dts/renesas/Makefile          |   2 +
 arch/arm64/boot/dts/renesas/r9a09g056.dtsi    | 264 ++++++++++++++++++
 .../dts/renesas/r9a09g056n48-rzv2n-evk.dts    | 115 ++++++++
 arch/arm64/configs/defconfig                  |   1 +
 drivers/clk/renesas/Kconfig                   |   5 +
 drivers/clk/renesas/Makefile                  |   1 +
 drivers/clk/renesas/r9a09g056-cpg.c           | 152 ++++++++++
 drivers/clk/renesas/rzv2h-cpg.c               |  18 +-
 drivers/clk/renesas/rzv2h-cpg.h               |   1 +
 drivers/pinctrl/renesas/Kconfig               |   1 +
 drivers/pinctrl/renesas/pinctrl-rzg2l.c       |  36 ++-
 drivers/soc/renesas/Kconfig                   |  10 +
 drivers/soc/renesas/Makefile                  |   1 +
 drivers/soc/renesas/r9a09g056-sys.c           | 107 +++++++
 drivers/soc/renesas/rz-sysc.c                 |   3 +
 drivers/soc/renesas/rz-sysc.h                 |   1 +
 .../dt-bindings/clock/renesas,r9a09g056-cpg.h |  24 ++
 .../pinctrl/renesas,r9a09g056-pinctrl.h       |  30 ++
 24 files changed, 790 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g056.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
 create mode 100644 drivers/clk/renesas/r9a09g056-cpg.c
 create mode 100644 drivers/soc/renesas/r9a09g056-sys.c
 create mode 100644 include/dt-bindings/clock/renesas,r9a09g056-cpg.h
 create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g056-pinctrl.h

-- 
2.49.0

[PATCH 01/15] dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Document Renesas RZ/V2N (R9A09G056) SoC variants.

Add compatible strings for different RZ/V2N variants, distinguishing
between configurations with and without specific hardware features
such as GPU, ISP, and cryptographic extensions.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../devicetree/bindings/soc/renesas/renesas.yaml    | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index 51a4c48eea6d..3e61ce372a57 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -551,6 +551,19 @@ properties:
               - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Ethos-U55 (21mm BGA)
           - const: renesas,r9a09g047
 
+      - description: RZ/V2N (R9A09G056)
+        items:
+          - enum:
+              - renesas,r9a09g056n41 # RZ/V2N
+              - renesas,r9a09g056n42 # RZ/V2N with Mali-G31 support
+              - renesas,r9a09g056n43 # RZ/V2N with Mali-C55 support
+              - renesas,r9a09g056n44 # RZ/V2N with Mali-G31 + Mali-C55 support
+              - renesas,r9a09g056n45 # RZ/V2N with cryptographic extension support
+              - renesas,r9a09g056n46 # RZ/V2N with Mali-G31 + cryptographic extension support
+              - renesas,r9a09g056n47 # RZ/V2N with Mali-C55 + cryptographic extension support
+              - renesas,r9a09g056n48 # RZ/V2N with Mali-G31 + Mali-C55 + cryptographic extension support
+          - const: renesas,r9a09g056
+
       - description: RZ/V2H(P) (R9A09G057)
         items:
           - enum:
-- 
2.49.0

[PATCH 02/15] dt-bindings: soc: renesas: Document RZ/V2N EVK board

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add "renesas,rzv2n-evk" which targets the Renesas RZ/V2N ("R9A09G056")
EVK board.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index 3e61ce372a57..3e3987c9a82e 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -553,6 +553,8 @@ properties:
 
       - description: RZ/V2N (R9A09G056)
         items:
+          - enum:
+              - renesas,rzv2n-evk # RZ/V2N EVK
           - enum:
               - renesas,r9a09g056n41 # RZ/V2N
               - renesas,r9a09g056n42 # RZ/V2N with Mali-G31 support
-- 
2.49.0

[PATCH 03/15] soc: renesas: Add config option for RZ/V2N (R9A09G056) SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add a configuration option for the RZ/V2N (R9A09G056) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/soc/renesas/Kconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 49648cf28bd2..764aba6d1ae6 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -352,6 +352,11 @@ config ARCH_R9A09G047
 	help
 	  This enables support for the Renesas RZ/G3E SoC variants.
 
+config ARCH_R9A09G056
+	bool "ARM64 Platform support for RZ/V2N"
+	help
+	  This enables support for the Renesas RZ/V2N SoC variants.
+
 config ARCH_R9A09G057
 	bool "ARM64 Platform support for RZ/V2H(P)"
 	select RENESAS_RZV2H_ICU
-- 
2.49.0

[PATCH 04/15] dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add the RZ/V2N (R9A09G056) variant to the existing RZ/V2H(P) System
Controller (SYS) binding, as both IPs are very similar.

However, they have different SoC IDs, and the RZ/V2N does not have
PCIE1 configuration registers, unlike the RZ/V2H(P) SYS IP. To handle
these differences, introduce a new compatible string
`renesas,r9a09g056-sys`.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml   | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
index e0f7503a9f35..c41dcaea568a 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml
@@ -25,6 +25,7 @@ properties:
     items:
       - enum:
           - renesas,r9a09g047-sys # RZ/G3E
+          - renesas,r9a09g056-sys # RZ/V2N
           - renesas,r9a09g057-sys # RZ/V2H
 
   reg:
-- 
2.49.0

[PATCH 05/15] soc: renesas: sysc: Add SoC identification for RZ/V2N SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add SoC identification for the RZ/V2N SoC using the System Controller
(SYS) block.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/soc/renesas/Kconfig         |   5 ++
 drivers/soc/renesas/Makefile        |   1 +
 drivers/soc/renesas/r9a09g056-sys.c | 107 ++++++++++++++++++++++++++++
 drivers/soc/renesas/rz-sysc.c       |   3 +
 drivers/soc/renesas/rz-sysc.h       |   1 +
 5 files changed, 117 insertions(+)
 create mode 100644 drivers/soc/renesas/r9a09g056-sys.c

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 764aba6d1ae6..14888db23556 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -354,6 +354,7 @@ config ARCH_R9A09G047
 
 config ARCH_R9A09G056
 	bool "ARM64 Platform support for RZ/V2N"
+	select SYS_R9A09G056
 	help
 	  This enables support for the Renesas RZ/V2N SoC variants.
 
@@ -402,6 +403,10 @@ config SYS_R9A09G047
 	bool "Renesas RZ/G3E System controller support" if COMPILE_TEST
 	select SYSC_RZ
 
+config SYS_R9A09G056
+	bool "Renesas RZ/V2N System controller support" if COMPILE_TEST
+	select SYSC_RZ
+
 config SYS_R9A09G057
 	bool "Renesas RZ/V2H System controller support" if COMPILE_TEST
 	select SYSC_RZ
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 81d4c5726e4c..3bdcc6a395d5 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_R9A06G032)	+= r9a06g032-smp.o
 endif
 obj-$(CONFIG_SYSC_R9A08G045)	+= r9a08g045-sysc.o
 obj-$(CONFIG_SYS_R9A09G047)	+= r9a09g047-sys.o
+obj-$(CONFIG_SYS_R9A09G056)	+= r9a09g056-sys.o
 obj-$(CONFIG_SYS_R9A09G057)	+= r9a09g057-sys.o
 
 # Family
diff --git a/drivers/soc/renesas/r9a09g056-sys.c b/drivers/soc/renesas/r9a09g056-sys.c
new file mode 100644
index 000000000000..3bea674c785e
--- /dev/null
+++ b/drivers/soc/renesas/r9a09g056-sys.c
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/V2N System controller (SYS) driver
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/string.h>
+
+#include "rz-sysc.h"
+
+/* Register Offsets */
+#define SYS_LSI_MODE		0x300
+#define SYS_LSI_MODE_SEC_EN	BIT(16)
+/*
+ * BOOTPLLCA[1:0]
+ *	    [0,0] => 1.1GHZ
+ *	    [0,1] => 1.5GHZ
+ *	    [1,0] => 1.6GHZ
+ *	    [1,1] => 1.7GHZ
+ */
+#define SYS_LSI_MODE_STAT_BOOTPLLCA55	GENMASK(12, 11)
+#define SYS_LSI_MODE_CA55_1_7GHZ	0x3
+
+#define SYS_LSI_PRR			0x308
+#define SYS_LSI_PRR_GPU_DIS		BIT(0)
+#define SYS_LSI_PRR_ISP_DIS		BIT(4)
+
+#define SYS_RZV2N_FEATURE_G31		BIT(0)
+#define SYS_RZV2N_FEATURE_C55		BIT(1)
+#define SYS_RZV2N_FEATURE_SEC		BIT(2)
+
+static void rzv2n_sys_print_id(struct device *dev,
+			       void __iomem *sysc_base,
+			       struct soc_device_attribute *soc_dev_attr)
+{
+	unsigned int part_number;
+	char features[75] = "";
+	u32 prr_val, mode_val;
+	u8 feature_flags;
+
+	prr_val = readl(sysc_base + SYS_LSI_PRR);
+	mode_val = readl(sysc_base + SYS_LSI_MODE);
+
+	/* Check GPU, ISP and Cryptographic configuration */
+	feature_flags = !(prr_val & SYS_LSI_PRR_GPU_DIS) ? SYS_RZV2N_FEATURE_G31 : 0;
+	feature_flags |= !(prr_val & SYS_LSI_PRR_ISP_DIS) ? SYS_RZV2N_FEATURE_C55 : 0;
+	feature_flags |= (mode_val & SYS_LSI_MODE_SEC_EN) ? SYS_RZV2N_FEATURE_SEC : 0;
+
+	part_number = 41;
+	if (feature_flags & SYS_RZV2N_FEATURE_G31)
+		part_number++;
+	if (feature_flags & SYS_RZV2N_FEATURE_C55)
+		part_number += 2;
+	if (feature_flags & SYS_RZV2N_FEATURE_SEC)
+		part_number += 4;
+
+	if (feature_flags) {
+		unsigned int features_len = sizeof(features);
+
+		strscpy(features, "with ");
+		if (feature_flags & SYS_RZV2N_FEATURE_G31)
+			strlcat(features, "GE3D (Mali-G31)", features_len);
+
+		if (feature_flags == (SYS_RZV2N_FEATURE_G31 |
+				      SYS_RZV2N_FEATURE_C55 |
+				      SYS_RZV2N_FEATURE_SEC))
+			strlcat(features, ", ", features_len);
+		else if ((feature_flags & SYS_RZV2N_FEATURE_G31) &&
+			 (feature_flags & (SYS_RZV2N_FEATURE_C55 | SYS_RZV2N_FEATURE_SEC)))
+			strlcat(features, " and ", features_len);
+
+		if (feature_flags & SYS_RZV2N_FEATURE_SEC)
+			strlcat(features, "Cryptographic engine", features_len);
+
+		if ((feature_flags & SYS_RZV2N_FEATURE_SEC) &&
+		    (feature_flags & SYS_RZV2N_FEATURE_C55))
+			strlcat(features, " and ", features_len);
+
+		if (feature_flags & SYS_RZV2N_FEATURE_C55)
+			strlcat(features, "ISP (Mali-C55)", features_len);
+	}
+	dev_info(dev, "Detected Renesas %s %sn%d Rev %s %s\n", soc_dev_attr->family,
+		 soc_dev_attr->soc_id, part_number, soc_dev_attr->revision, features);
+
+	/* Check CA55 PLL configuration */
+	if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) != SYS_LSI_MODE_CA55_1_7GHZ)
+		dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n");
+}
+
+static const struct rz_sysc_soc_id_init_data rzv2n_sys_soc_id_init_data __initconst = {
+	.family = "RZ/V2N",
+	.id = 0x867d447,
+	.devid_offset = 0x304,
+	.revision_mask = GENMASK(31, 28),
+	.specific_id_mask = GENMASK(27, 0),
+	.print_id = rzv2n_sys_print_id,
+};
+
+const struct rz_sysc_init_data rzv2n_sys_init_data = {
+	.soc_id_init_data = &rzv2n_sys_soc_id_init_data,
+};
diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c
index 14db508f669f..ffa65fb4dade 100644
--- a/drivers/soc/renesas/rz-sysc.c
+++ b/drivers/soc/renesas/rz-sysc.c
@@ -88,6 +88,9 @@ static const struct of_device_id rz_sysc_match[] = {
 #ifdef CONFIG_SYS_R9A09G047
 	{ .compatible = "renesas,r9a09g047-sys", .data = &rzg3e_sys_init_data },
 #endif
+#ifdef CONFIG_SYS_R9A09G056
+	{ .compatible = "renesas,r9a09g056-sys", .data = &rzv2n_sys_init_data },
+#endif
 #ifdef CONFIG_SYS_R9A09G057
 	{ .compatible = "renesas,r9a09g057-sys", .data = &rzv2h_sys_init_data },
 #endif
diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h
index aa83948c5117..56bc047a1bff 100644
--- a/drivers/soc/renesas/rz-sysc.h
+++ b/drivers/soc/renesas/rz-sysc.h
@@ -42,5 +42,6 @@ struct rz_sysc_init_data {
 extern const struct rz_sysc_init_data rzg3e_sys_init_data;
 extern const struct rz_sysc_init_data rzg3s_sysc_init_data;
 extern const struct rz_sysc_init_data rzv2h_sys_init_data;
+extern const struct rz_sysc_init_data rzv2n_sys_init_data;
 
 #endif /* __SOC_RENESAS_RZ_SYSC_H__ */
-- 
2.49.0

[PATCH 06/15] dt-bindings: serial: renesas: Document RZ/V2N SCIF

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Document SCIF bindings for the Renesas RZ/V2N (a.k.a R9A09G056) SoC.
The SCIF interface in Renesas RZ/V2N is identical to the one available
in RZ/V2H(P), so `renesas,scif-r9a09g057` will be used as a fallback,
allowing reuse of the existing driver without modifications.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
index 8e82999e6acb..24819b204ebf 100644
--- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
@@ -86,6 +86,7 @@ properties:
       - items:
           - enum:
               - renesas,scif-r9a09g047      # RZ/G3E
+              - renesas,scif-r9a09g056      # RZ/V2N
           - const: renesas,scif-r9a09g057   # RZ/V2H fallback
 
   reg:
-- 
2.49.0

[PATCH 07/15] dt-bindings: mmc: renesas,sdhi: Document RZ/V2N support

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add SDHI bindings for the Renesas RZ/V2N (a.k.a R9A09G056) SoC. Use
`renesas,sdhi-r9a09g057` as a fallback since the SD/MMC block on
RZ/V2N is identical to the one on RZ/V2H(P), allowing reuse of the
existing driver without modifications.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
index 773baa6c2656..7563623876fc 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
@@ -69,7 +69,9 @@ properties:
               - renesas,sdhi-r9a09g011 # RZ/V2M
           - const: renesas,rzg2l-sdhi
       - items:
-          - const: renesas,sdhi-r9a09g047 # RZ/G3E
+          - enum:
+              - renesas,sdhi-r9a09g047 # RZ/G3E
+              - renesas,sdhi-r9a09g056 # RZ/V2N
           - const: renesas,sdhi-r9a09g057 # RZ/V2H(P)
 
   reg:
-- 
2.49.0

[PATCH 08/15] dt-bindings: clock: renesas: Document RZ/V2N SoC CPG

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Document the device tree bindings for the Renesas RZ/V2N (R9A09G056)
SoC Clock Pulse Generator (CPG).

Update `renesas,rzv2h-cpg.yaml` to include the compatible string for
RZ/V2N SoC and adjust the title and description accordingly.

Additionally, introduce `renesas,r9a09g056-cpg.h` to define core clock
constants for the RZ/V2N SoC. Note the existing RZ/V2H(P) family-specific
clock driver will be reused for this SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../bindings/clock/renesas,rzv2h-cpg.yaml     |  5 ++--
 .../dt-bindings/clock/renesas,r9a09g056-cpg.h | 24 +++++++++++++++++++
 2 files changed, 27 insertions(+), 2 deletions(-)
 create mode 100644 include/dt-bindings/clock/renesas,r9a09g056-cpg.h

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
index c3fe76abd549..f261445bf341 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
@@ -4,13 +4,13 @@
 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG)
+title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG)
 
 maintainers:
   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 
 description:
-  On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles
+  On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) handles
   generation and control of clock signals for the IP modules, generation and
   control of resets, and control over booting, low power consumption and power
   supply domains.
@@ -19,6 +19,7 @@ properties:
   compatible:
     enum:
       - renesas,r9a09g047-cpg # RZ/G3E
+      - renesas,r9a09g056-cpg # RZ/V2N
       - renesas,r9a09g057-cpg # RZ/V2H
 
   reg:
diff --git a/include/dt-bindings/clock/renesas,r9a09g056-cpg.h b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h
new file mode 100644
index 000000000000..f4905b27f8d9
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* Core Clock list */
+#define R9A09G056_SYS_0_PCLK			0
+#define R9A09G056_CA55_0_CORE_CLK0		1
+#define R9A09G056_CA55_0_CORE_CLK1		2
+#define R9A09G056_CA55_0_CORE_CLK2		3
+#define R9A09G056_CA55_0_CORE_CLK3		4
+#define R9A09G056_CA55_0_PERIPHCLK		5
+#define R9A09G056_CM33_CLK0			6
+#define R9A09G056_CST_0_SWCLKTCK		7
+#define R9A09G056_IOTOP_0_SHCLK			8
+#define R9A09G056_USB2_0_CLK_CORE0		9
+#define R9A09G056_GBETH_0_CLK_PTP_REF_I		10
+#define R9A09G056_GBETH_1_CLK_PTP_REF_I		11
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */
-- 
2.49.0

[PATCH 09/15] clk: renesas: rzv2h-cpg: Sort compatible list based on SoC part number

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Reorder the compatible entries in `rzv2h_cpg_match[]` to follow a
numerical sequence based on the SoC part numbers.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/rzv2h-cpg.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 4c0247de6cb0..88ab26a077ae 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -1367,17 +1367,17 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id rzv2h_cpg_match[] = {
-#ifdef CONFIG_CLK_R9A09G057
-	{
-		.compatible = "renesas,r9a09g057-cpg",
-		.data = &r9a09g057_cpg_info,
-	},
-#endif
 #ifdef CONFIG_CLK_R9A09G047
 	{
 		.compatible = "renesas,r9a09g047-cpg",
 		.data = &r9a09g047_cpg_info,
 	},
+#endif
+#ifdef CONFIG_CLK_R9A09G057
+	{
+		.compatible = "renesas,r9a09g057-cpg",
+		.data = &r9a09g057_cpg_info,
+	},
 #endif
 	{ /* sentinel */ }
 };
-- 
2.49.0

[PATCH 10/15] clk: renesas: rzv2h: Add support for RZ/V2N SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The clock structure for RZ/V2N is almost identical to RZ/V2H(P) SoC
with less IP blocks compared to RZ/V2H(P). For eg: CRU2/3 are present
only on the RZ/V2H(P) SoC.

Add minimal clock and reset entries required to boot the Renesas
RZ/V2N EVK and binds it with the RZ/V2H CPG family driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/Kconfig         |   5 +
 drivers/clk/renesas/Makefile        |   1 +
 drivers/clk/renesas/r9a09g056-cpg.c | 152 ++++++++++++++++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.c     |   6 ++
 drivers/clk/renesas/rzv2h-cpg.h     |   1 +
 5 files changed, 165 insertions(+)
 create mode 100644 drivers/clk/renesas/r9a09g056-cpg.c

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 5a4bc3f94d49..50c20119d12a 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -41,6 +41,7 @@ config CLK_RENESAS
 	select CLK_R9A08G045 if ARCH_R9A08G045
 	select CLK_R9A09G011 if ARCH_R9A09G011
 	select CLK_R9A09G047 if ARCH_R9A09G047
+	select CLK_R9A09G056 if ARCH_R9A09G056
 	select CLK_R9A09G057 if ARCH_R9A09G057
 	select CLK_SH73A0 if ARCH_SH73A0
 
@@ -199,6 +200,10 @@ config CLK_R9A09G047
        bool "RZ/G3E clock support" if COMPILE_TEST
        select CLK_RZV2H
 
+config CLK_R9A09G056
+       bool "RZ/V2N clock support" if COMPILE_TEST
+       select CLK_RZV2H
+
 config CLK_R9A09G057
        bool "RZ/V2H(P) clock support" if COMPILE_TEST
        select CLK_RZV2H
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 2d6e746939c4..f9075bca6e95 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_CLK_R9A07G054)		+= r9a07g044-cpg.o
 obj-$(CONFIG_CLK_R9A08G045)		+= r9a08g045-cpg.o
 obj-$(CONFIG_CLK_R9A09G011)		+= r9a09g011-cpg.o
 obj-$(CONFIG_CLK_R9A09G047)		+= r9a09g047-cpg.o
+obj-$(CONFIG_CLK_R9A09G056)		+= r9a09g056-cpg.o
 obj-$(CONFIG_CLK_R9A09G057)		+= r9a09g057-cpg.o
 obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o
 
diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c
new file mode 100644
index 000000000000..e2712a25c43a
--- /dev/null
+++ b/drivers/clk/renesas/r9a09g056-cpg.c
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/V2N CPG driver
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
+
+#include "rzv2h-cpg.h"
+
+enum clk_ids {
+	/* Core Clock Outputs exported to DT */
+	LAST_DT_CORE_CLK = R9A09G056_GBETH_1_CLK_PTP_REF_I,
+
+	/* External Input Clocks */
+	CLK_AUDIO_EXTAL,
+	CLK_RTXIN,
+	CLK_QEXTAL,
+
+	/* PLL Clocks */
+	CLK_PLLCM33,
+	CLK_PLLCLN,
+	CLK_PLLDTY,
+	CLK_PLLCA55,
+
+	/* Internal Core Clocks */
+	CLK_PLLCM33_DIV16,
+	CLK_PLLCLN_DIV2,
+	CLK_PLLCLN_DIV8,
+	CLK_PLLDTY_ACPU,
+	CLK_PLLDTY_ACPU_DIV4,
+
+	/* Module Clocks */
+	MOD_CLK_BASE,
+};
+
+static const struct clk_div_table dtable_1_8[] = {
+	{0, 1},
+	{1, 2},
+	{2, 4},
+	{3, 8},
+	{0, 0},
+};
+
+static const struct clk_div_table dtable_2_64[] = {
+	{0, 2},
+	{1, 4},
+	{2, 8},
+	{3, 16},
+	{4, 64},
+	{0, 0},
+};
+
+static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = {
+	/* External Clock Inputs */
+	DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
+	DEF_INPUT("rtxin", CLK_RTXIN),
+	DEF_INPUT("qextal", CLK_QEXTAL),
+
+	/* PLL Clocks */
+	DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
+	DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
+	DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
+	DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
+
+	/* Internal Core Clocks */
+	DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
+
+	DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2),
+	DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),
+
+	DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
+	DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
+
+	/* Core Clocks */
+	DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
+	DEF_DDIV("ca55_0_coreclk0", R9A09G056_CA55_0_CORE_CLK0, CLK_PLLCA55,
+		 CDDIV1_DIVCTL0, dtable_1_8),
+	DEF_DDIV("ca55_0_coreclk1", R9A09G056_CA55_0_CORE_CLK1, CLK_PLLCA55,
+		 CDDIV1_DIVCTL1, dtable_1_8),
+	DEF_DDIV("ca55_0_coreclk2", R9A09G056_CA55_0_CORE_CLK2, CLK_PLLCA55,
+		 CDDIV1_DIVCTL2, dtable_1_8),
+	DEF_DDIV("ca55_0_coreclk3", R9A09G056_CA55_0_CORE_CLK3, CLK_PLLCA55,
+		 CDDIV1_DIVCTL3, dtable_1_8),
+	DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
+};
+
+static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
+	DEF_MOD_CRITICAL("gic_0_gicclk",	CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
+						BUS_MSTOP(3, BIT(5))),
+	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15,
+						BUS_MSTOP(3, BIT(14))),
+	DEF_MOD("sdhi_0_imclk",			CLK_PLLCLN_DIV8, 10, 3, 5, 3,
+						BUS_MSTOP(8, BIT(2))),
+	DEF_MOD("sdhi_0_imclk2",		CLK_PLLCLN_DIV8, 10, 4, 5, 4,
+						BUS_MSTOP(8, BIT(2))),
+	DEF_MOD("sdhi_0_clk_hs",		CLK_PLLCLN_DIV2, 10, 5, 5, 5,
+						BUS_MSTOP(8, BIT(2))),
+	DEF_MOD("sdhi_0_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6,
+						BUS_MSTOP(8, BIT(2))),
+	DEF_MOD("sdhi_1_imclk",			CLK_PLLCLN_DIV8, 10, 7, 5, 7,
+						BUS_MSTOP(8, BIT(3))),
+	DEF_MOD("sdhi_1_imclk2",		CLK_PLLCLN_DIV8, 10, 8, 5, 8,
+						BUS_MSTOP(8, BIT(3))),
+	DEF_MOD("sdhi_1_clk_hs",		CLK_PLLCLN_DIV2, 10, 9, 5, 9,
+						BUS_MSTOP(8, BIT(3))),
+	DEF_MOD("sdhi_1_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10,
+						BUS_MSTOP(8, BIT(3))),
+	DEF_MOD("sdhi_2_imclk",			CLK_PLLCLN_DIV8, 10, 11, 5, 11,
+						BUS_MSTOP(8, BIT(4))),
+	DEF_MOD("sdhi_2_imclk2",		CLK_PLLCLN_DIV8, 10, 12, 5, 12,
+						BUS_MSTOP(8, BIT(4))),
+	DEF_MOD("sdhi_2_clk_hs",		CLK_PLLCLN_DIV2, 10, 13, 5, 13,
+						BUS_MSTOP(8, BIT(4))),
+	DEF_MOD("sdhi_2_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
+						BUS_MSTOP(8, BIT(4))),
+};
+
+static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
+	DEF_RST(3, 0, 1, 1),		/* SYS_0_PRESETN */
+	DEF_RST(3, 8, 1, 9),		/* GIC_0_GICRESET_N */
+	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */
+	DEF_RST(9, 5, 4, 6),		/* SCIF_0_RST_SYSTEM_N */
+	DEF_RST(10, 7, 4, 24),		/* SDHI_0_IXRST */
+	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */
+	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */
+};
+
+const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst = {
+	/* Core Clocks */
+	.core_clks = r9a09g056_core_clks,
+	.num_core_clks = ARRAY_SIZE(r9a09g056_core_clks),
+	.last_dt_core_clk = LAST_DT_CORE_CLK,
+	.num_total_core_clks = MOD_CLK_BASE,
+
+	/* Module Clocks */
+	.mod_clks = r9a09g056_mod_clks,
+	.num_mod_clks = ARRAY_SIZE(r9a09g056_mod_clks),
+	.num_hw_mod_clks = 25 * 16,
+
+	/* Resets */
+	.resets = r9a09g056_resets,
+	.num_resets = ARRAY_SIZE(r9a09g056_resets),
+
+	.num_mstop_bits = 192,
+};
diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index 88ab26a077ae..34a3145d72eb 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -1373,6 +1373,12 @@ static const struct of_device_id rzv2h_cpg_match[] = {
 		.data = &r9a09g047_cpg_info,
 	},
 #endif
+#ifdef CONFIG_CLK_R9A09G056
+	{
+		.compatible = "renesas,r9a09g056-cpg",
+		.data = &r9a09g056_cpg_info,
+	},
+#endif
 #ifdef CONFIG_CLK_R9A09G057
 	{
 		.compatible = "renesas,r9a09g057-cpg",
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index a7aa1da181e5..8a2466f10deb 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -326,6 +326,7 @@ struct rzv2h_cpg_info {
 };
 
 extern const struct rzv2h_cpg_info r9a09g047_cpg_info;
+extern const struct rzv2h_cpg_info r9a09g056_cpg_info;
 extern const struct rzv2h_cpg_info r9a09g057_cpg_info;
 
 #endif	/* __RENESAS_RZV2H_CPG_H__ */
-- 
2.49.0

[PATCH 11/15] dt-bindings: pinctrl: renesas: Document RZ/V2N SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add documentation for the pin controller found on the Renesas RZ/V2N
(R9A09G056) SoC. The RZ/V2N PFC differs slightly from the RZ/G2L family
and is almost identical to the RZ/V2H(P) SoC, except that the RZ/V2H(P) SoC
has an additional dedicated pin.

To account for this, a SoC-specific compatible string,
'renesas,r9a09g056-pinctrl', is introduced for the RZ/V2N SoC.

Also add `renesas,r9a09g056-pinctrl.h` header file which define pins
that will be used by the driver and board DTS files.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../pinctrl/renesas,rzg2l-pinctrl.yaml        |  2 ++
 .../pinctrl/renesas,r9a09g056-pinctrl.h       | 30 +++++++++++++++++++
 2 files changed, 32 insertions(+)
 create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g056-pinctrl.h

diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
index 768bb3c2b456..5156d54b240b 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml
@@ -27,6 +27,7 @@ properties:
               - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
               - renesas,r9a08g045-pinctrl # RZ/G3S
               - renesas,r9a09g047-pinctrl # RZ/G3E
+              - renesas,r9a09g056-pinctrl # RZ/V2N
               - renesas,r9a09g057-pinctrl # RZ/V2H(P)
 
       - items:
@@ -145,6 +146,7 @@ allOf:
           contains:
             enum:
               - renesas,r9a09g047-pinctrl
+              - renesas,r9a09g056-pinctrl
               - renesas,r9a09g057-pinctrl
     then:
       properties:
diff --git a/include/dt-bindings/pinctrl/renesas,r9a09g056-pinctrl.h b/include/dt-bindings/pinctrl/renesas,r9a09g056-pinctrl.h
new file mode 100644
index 000000000000..206bba07c288
--- /dev/null
+++ b/include/dt-bindings/pinctrl/renesas,r9a09g056-pinctrl.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/V2N SoC pinctrl bindings.
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G056_PINCTRL_H__
+#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G056_PINCTRL_H__
+
+#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
+
+/* RZV2N_Px = Offset address of PFC_P_mn  - 0x20 */
+#define RZV2N_P0	0
+#define RZV2N_P1	1
+#define RZV2N_P2	2
+#define RZV2N_P3	3
+#define RZV2N_P4	4
+#define RZV2N_P5	5
+#define RZV2N_P6	6
+#define RZV2N_P7	7
+#define RZV2N_P8	8
+#define RZV2N_P9	9
+#define RZV2N_PA	10
+#define RZV2N_PB	11
+
+#define RZV2N_PORT_PINMUX(b, p, f)	RZG2L_PORT_PINMUX(RZV2N_P##b, p, f)
+#define RZV2N_GPIO(port, pin)		RZG2L_GPIO(RZV2N_P##port, pin)
+
+#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G056_PINCTRL_H__ */
-- 
2.49.0

[PATCH 12/15] pinctrl: renesas: rzg2l: Add support for RZ/V2N SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add pinctrl support for the Renesas RZ/V2N SoC by reusing the existing
RZ/V2H(P) pin configuration data. The PFC block is nearly identical, with
the only difference being the absence of `PCIE1_RSTOUTB` on RZ/V2N.

To accommodate this, move the `PCIE1_RSTOUTB` entry to the end of the
`rzv2h_dedicated_pins` array and set `.n_dedicated_pins` to
`ARRAY_SIZE(rzv2h_dedicated_pins) - 1` in the RZ/V2N OF data.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pinctrl/renesas/Kconfig         |  1 +
 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 36 ++++++++++++++++++++++++-
 2 files changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 3c18d908b21e..e16034fc1bbf 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -42,6 +42,7 @@ config PINCTRL_RENESAS
 	select PINCTRL_RZG2L if ARCH_RZG2L
 	select PINCTRL_RZV2M if ARCH_R9A09G011
 	select PINCTRL_RZG2L if ARCH_R9A09G047
+	select PINCTRL_RZG2L if ARCH_R9A09G056
 	select PINCTRL_RZG2L if ARCH_R9A09G057
 	select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
 	select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index c72e250f4a15..ae5e040f3276 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -2304,7 +2304,6 @@ static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
 	{ "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
 						    PIN_CFG_IEN | PIN_CFG_PUPD)) },
 	{ "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
-	{ "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
 	{ "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
 						     PIN_CFG_IEN | PIN_CFG_PUPD)) },
 	{ "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR |
@@ -2359,6 +2358,14 @@ static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
 	{ "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) },
 	{ "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) },
 	{ "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
+
+	/*
+	 * This pin is only available on the RZ/V2H(P) SoC and not on the RZ/V2N.
+	 * Since this array is shared with the RZ/V2N SoC, this entry should be placed
+	 * at the end. This ensures that on the RZ/V2N, we can set
+	 * `.n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins) - 1,`.
+	 */
+	{ "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
 };
 
 static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = {
@@ -3349,6 +3356,29 @@ static struct rzg2l_pinctrl_data r9a09g047_data = {
 	.bias_param_to_hw = &rzv2h_bias_param_to_hw,
 };
 
+static struct rzg2l_pinctrl_data r9a09g056_data = {
+	.port_pins = rzv2h_gpio_names,
+	.port_pin_configs = r9a09g057_gpio_configs,
+	.n_ports = ARRAY_SIZE(r9a09g057_gpio_configs),
+	.dedicated_pins = rzv2h_dedicated_pins,
+	.n_port_pins = ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT,
+	.n_dedicated_pins = ARRAY_SIZE(rzv2h_dedicated_pins) - 1,
+	.hwcfg = &rzv2h_hwcfg,
+	.variable_pin_cfg = r9a09g057_variable_pin_cfg,
+	.n_variable_pin_cfg = ARRAY_SIZE(r9a09g057_variable_pin_cfg),
+	.num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
+	.custom_params = renesas_rzv2h_custom_bindings,
+#ifdef CONFIG_DEBUG_FS
+	.custom_conf_items = renesas_rzv2h_conf_items,
+#endif
+	.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
+	.pmc_writeb = &rzv2h_pmc_writeb,
+	.oen_read = &rzv2h_oen_read,
+	.oen_write = &rzv2h_oen_write,
+	.hw_to_bias_param = &rzv2h_hw_to_bias_param,
+	.bias_param_to_hw = &rzv2h_bias_param_to_hw,
+};
+
 static struct rzg2l_pinctrl_data r9a09g057_data = {
 	.port_pins = rzv2h_gpio_names,
 	.port_pin_configs = r9a09g057_gpio_configs,
@@ -3389,6 +3419,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = {
 		.compatible = "renesas,r9a09g047-pinctrl",
 		.data = &r9a09g047_data,
 	},
+	{
+		.compatible = "renesas,r9a09g056-pinctrl",
+		.data = &r9a09g056_data,
+	},
 	{
 		.compatible = "renesas,r9a09g057-pinctrl",
 		.data = &r9a09g057_data,
-- 
2.49.0

[PATCH 13/15] arm64: dts: renesas: Add initial SoC DTSI for RZ/V2N

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add the initial Device Tree Source Include (DTSI) file for the Renesas
RZ/V2N (R9A09G056) SoC. Include support for the following components:

- CPU (Cortex-A55 cores with operating points)
- External clocks (audio, qextal, rtxin)
- Pin controller (GPIO support)
- Clock Pulse Generator (CPG)
- System controller (SYS)
- Serial Communication Interface (SCIF)
- Secure Digital Host Interface (SDHI 0/1/2)
- Generic Interrupt Controller (GIC)
- ARMv8 timer

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Note, dtbs_check complains about missing interrupt properties for pinctrl.
This is because, as part of the initial support, the ICU has not been
added yet. The interrupt-related properties will be added to the pinctrl
node along with ICU support.
---
 arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 264 +++++++++++++++++++++
 1 file changed, 264 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g056.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
new file mode 100644
index 000000000000..a807dd90913f
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
@@ -0,0 +1,264 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2N SoC
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r9a09g056";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	audio_extal_clk: audio-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	/*
+	 * The default cluster table is based on the assumption that the PLLCA55 clock
+	 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
+	 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
+	 * clocked to 1.8GHz as well). The table below should be overridden in the board
+	 * DTS based on the PLLCA55 clock frequency.
+	 */
+	cluster0_opp: opp-table-0 {
+		compatible = "operating-points-v2";
+
+		opp-1700000000 {
+			opp-hz = /bits/ 64 <1700000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-850000000 {
+			opp-hz = /bits/ 64 <850000000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-425000000 {
+			opp-hz = /bits/ 64 <425000000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <300000>;
+		};
+		opp-212500000 {
+			opp-hz = /bits/ 64 <212500000>;
+			opp-microvolt = <800000>;
+			clock-latency-ns = <300000>;
+			opp-suspend;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a55";
+			reg = <0>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>;
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		cpu1: cpu@100 {
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>;
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		cpu2: cpu@200 {
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>;
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		cpu3: cpu@300 {
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+			clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>;
+			operating-points-v2 = <&cluster0_opp>;
+		};
+
+		L3_CA55: cache-controller-0 {
+			compatible = "cache";
+			cache-unified;
+			cache-size = <0x100000>;
+			cache-level = <3>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	qextal_clk: qextal-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	rtxin_clk: rtxin-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		pinctrl: pinctrl@10410000 {
+			compatible = "renesas,r9a09g056-pinctrl";
+			reg = <0 0x10410000 0 0x10000>;
+			clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pinctrl 0 0 96>;
+			power-domains = <&cpg>;
+			resets = <&cpg 0xa5>, <&cpg 0xa6>;
+		};
+
+		cpg: clock-controller@10420000 {
+			compatible = "renesas,r9a09g056-cpg";
+			reg = <0 0x10420000 0 0x10000>;
+			clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
+			clock-names = "audio_extal", "rtxin", "qextal";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		sys: system-controller@10430000 {
+			compatible = "renesas,r9a09g056-sys";
+			reg = <0 0x10430000 0 0x10000>;
+			clocks = <&cpg CPG_CORE R9A09G056_SYS_0_PCLK>;
+			resets = <&cpg 0x30>;
+		};
+
+		scif: serial@11c01400 {
+			compatible = "renesas,scif-r9a09g056",
+				     "renesas,scif-r9a09g057";
+			reg = <0 0x11c01400 0 0x400>;
+			interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "eri", "rxi", "txi", "bri", "dri",
+					  "tei", "tei-dri", "rxi-edge", "txi-edge";
+			clocks = <&cpg CPG_MOD 0x8f>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg 0x95>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@14900000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x14900000 0 0x20000>,
+			      <0x0 0x14940000 0 0x80000>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+		};
+
+		sdhi0: mmc@15c00000  {
+			compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
+			reg = <0x0 0x15c00000 0 0x10000>;
+			interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>,
+				 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>;
+			clock-names = "core", "clkh", "cd", "aclk";
+			resets = <&cpg 0xa7>;
+			power-domains = <&cpg>;
+			status = "disabled";
+
+			sdhi0_vqmmc: vqmmc-regulator {
+				regulator-name = "SDHI0-VQMMC";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				status = "disabled";
+			};
+		};
+
+		sdhi1: mmc@15c10000 {
+			compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
+			reg = <0x0 0x15c10000 0 0x10000>;
+			interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>,
+				 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>;
+			clock-names = "core", "clkh", "cd", "aclk";
+			resets = <&cpg 0xa8>;
+			power-domains = <&cpg>;
+			status = "disabled";
+
+			sdhi1_vqmmc: vqmmc-regulator {
+				regulator-name = "SDHI1-VQMMC";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				status = "disabled";
+			};
+		};
+
+		sdhi2: mmc@15c20000 {
+			compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057";
+			reg = <0x0 0x15c20000 0 0x10000>;
+			interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>,
+				 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>;
+			clock-names = "core", "clkh", "cd", "aclk";
+			resets = <&cpg 0xa9>;
+			power-domains = <&cpg>;
+			status = "disabled";
+
+			sdhi2_vqmmc: vqmmc-regulator {
+				regulator-name = "SDHI2-VQMMC";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				status = "disabled";
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+				      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
+	};
+};
-- 
2.49.0

[PATCH 14/15] arm64: dts: renesas: Add initial device tree for RZ/V2N EVK

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add the initial device tree for the Renesas RZ/V2N EVK board, based on
the R9A09G056N48 SoC. Enable basic board functionality, including:

- Memory mapping (reserve the first 128MB for the secure area)
- Clock inputs (QEXTAL, RTXIN, AUDIO_EXTAL)
- PINCTRL configurations for peripherals
- Serial console (SCIF)
- SDHI1 with power control and UHS modes

Update the Makefile to include the new DTB.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile          |   2 +
 .../dts/renesas/r9a09g056n48-rzv2n-evk.dts    | 115 ++++++++++++++++++
 2 files changed, 117 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index d25e665ee4bf..d8a8d7ca4c58 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -152,6 +152,8 @@ dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
 
 dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb
 
+dtb-$(CONFIG_ARCH_R9A09G056) += r9a09g056n48-rzv2n-evk.dtb
+
 dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb
 dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h48-kakip.dtb
 
diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
new file mode 100644
index 000000000000..aee4748a7618
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/V2N EVK board
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pinctrl/renesas,r9a09g056-pinctrl.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "r9a09g056.dtsi"
+
+/ {
+	model = "Renesas RZ/V2N EVK Board based on r9a09g056n48";
+	compatible = "renesas,rzv2n-evk", "renesas,r9a09g056n48", "renesas,r9a09g056";
+
+	aliases {
+		mmc1 = &sdhi1;
+		serial0 = &scif;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x1 0xf8000000>;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vqmmc_sdhi1: regulator-vqmmc-sdhi1 {
+		compatible = "regulator-gpio";
+		regulator-name = "SDHI1 VqmmC";
+		gpios = <&pinctrl RZV2N_GPIO(A, 2) GPIO_ACTIVE_HIGH>;
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		gpios-states = <0>;
+		states = <3300000 0>, <1800000 1>;
+	};
+};
+
+&audio_extal_clk {
+	clock-frequency = <22579200>;
+};
+
+&pinctrl {
+	scif_pins: scif {
+		pins = "SCIF_TXD", "SCIF_RXD";
+		renesas,output-impedance = <1>;
+	};
+
+	sd1-pwr-en-hog {
+		gpio-hog;
+		gpios = <RZV2N_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
+		output-high;
+		line-name = "sd1_pwr_en";
+	};
+
+	sdhi1_pins: sd1 {
+		sd1_dat_cmd {
+			pins = "SD1DAT0", "SD1DAT1", "SD1DAT2", "SD1DAT3", "SD1CMD";
+			input-enable;
+			renesas,output-impedance = <3>;
+			slew-rate = <0>;
+		};
+
+		sd1_clk {
+			pins = "SD1CLK";
+			renesas,output-impedance = <3>;
+			slew-rate = <0>;
+		};
+
+		sd1_cd {
+			pinmux = <RZV2N_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
+		};
+	};
+};
+
+&qextal_clk {
+	clock-frequency = <24000000>;
+};
+
+&rtxin_clk {
+	clock-frequency = <32768>;
+};
+
+&scif {
+	pinctrl-0 = <&scif_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&sdhi1 {
+	pinctrl-0 = <&sdhi1_pins>;
+	pinctrl-1 = <&sdhi1_pins>;
+	pinctrl-names = "default", "state_uhs";
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&vqmmc_sdhi1>;
+	bus-width = <4>;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	status = "okay";
+};
-- 
2.49.0

[PATCH 15/15] arm64: defconfig: Enable Renesas RZ/V2N SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Enable support for the Renesas RZ/V2N (R9A09G056) SoC in the ARM64
defconfig.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 11e7d0ad8656..c7b41f86c128 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1483,6 +1483,7 @@ CONFIG_ARCH_R9A07G054=y
 CONFIG_ARCH_R9A08G045=y
 CONFIG_ARCH_R9A09G011=y
 CONFIG_ARCH_R9A09G047=y
+CONFIG_ARCH_R9A09G056=y
 CONFIG_ARCH_R9A09G057=y
 CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_ARCH_TEGRA_132_SOC=y
-- 
2.49.0

Re: [PATCH 00/15] Add support for Renesas RZ/V2N SoC and EVK

[Rob Herring (Arm)]

On Wed, 26 Mar 2025 14:39:30 +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> This patch series adds initial support for the Renesas RZ/V2N (R9A09G056)
> SoC and its evaluation board (EVK). The Renesas RZ/V2N is a vision AI
> microprocessor (MPU) designed for power-efficient AI inference and
> real-time vision processing. It features Renesas' proprietary AI
> accelerator (DRP-AI3), delivering up to 15 TOPS AI performance, making
> it ideal for applications such as Driver Monitoring Systems (DMS),
> industrial monitoring cameras, and mobile robots.
> 
> Key features of the RZ/V2N SoC:
>   Processing Power:
>     - Quad Arm Cortex-A55 cores at 1.8GHz for high-performance computing
>     - Single Arm Cortex-M33 core at 200MHz for real-time processing
>     - 1.5MB on-chip SRAM for fast data access
>     - LPDDR4/LPDDR4X memory interface for high-speed RAM access
> 
>   AI and Vision Processing:
>     - DRP-AI3 accelerator for low-power, high-efficiency AI inference
>     - Arm Mali-C55 ISP (optional) for image signal processing
>     - Dual MIPI CSI-2 camera interfaces for multi-camera support
> 
>   High-Speed Interfaces:
>     - PCIe Gen3 (2-lane) 1ch for external device expansion
>     - USB 3.2 (Gen2) 1ch (Host-only) for high-speed data transfer
>     - USB 2.0 (Host/Function) 1ch for legacy connectivity
>     - Gigabit Ethernet (2 channels) for network communication
> 
>   Industrial and Automotive Features:
>     - 6x CAN FD channels for automotive and industrial networking
>     - 24-channel ADC for sensor data acquisition
> 
> LINK: https://tinyurl.com/renesas-rz-v2n-soc
> 
> The series introduces:
> - Device tree bindings for various subsystems (SYS, SCIF, SDHI, CPG, pinctrl).
> - RZ/V2N SoC identification support.
> - Clock and pinctrl driver updates for RZ/V2N.
> - Initial DTSI and device tree for the RZ/V2N SoC and EVK.
> - Enabling RZ/V2N SoC support in `arm64 defconfig`.
> 
> These patches have been tested on the RZ/V2N EVK with v6.14,
> logs can be found here https://pastebin.com/8i3jgVby
> 
> Cheers,
> Prabhakar
> 
> Lad Prabhakar (15):
>   dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants
>   dt-bindings: soc: renesas: Document RZ/V2N EVK board
>   soc: renesas: Add config option for RZ/V2N (R9A09G056) SoC
>   dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
>   soc: renesas: sysc: Add SoC identification for RZ/V2N SoC
>   dt-bindings: serial: renesas: Document RZ/V2N SCIF
>   dt-bindings: mmc: renesas,sdhi: Document RZ/V2N support
>   dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
>   clk: renesas: rzv2h-cpg: Sort compatible list based on SoC part number
>   clk: renesas: rzv2h: Add support for RZ/V2N SoC
>   dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
>   pinctrl: renesas: rzg2l: Add support for RZ/V2N SoC
>   arm64: dts: renesas: Add initial SoC DTSI for RZ/V2N
>   arm64: dts: renesas: Add initial device tree for RZ/V2N EVK
>   arm64: defconfig: Enable Renesas RZ/V2N SoC
> 
>  .../bindings/clock/renesas,rzv2h-cpg.yaml     |   5 +-
>  .../devicetree/bindings/mmc/renesas,sdhi.yaml |   4 +-
>  .../pinctrl/renesas,rzg2l-pinctrl.yaml        |   2 +
>  .../bindings/serial/renesas,scif.yaml         |   1 +
>  .../soc/renesas/renesas,r9a09g057-sys.yaml    |   1 +
>  .../bindings/soc/renesas/renesas.yaml         |  15 +
>  arch/arm64/boot/dts/renesas/Makefile          |   2 +
>  arch/arm64/boot/dts/renesas/r9a09g056.dtsi    | 264 ++++++++++++++++++
>  .../dts/renesas/r9a09g056n48-rzv2n-evk.dts    | 115 ++++++++
>  arch/arm64/configs/defconfig                  |   1 +
>  drivers/clk/renesas/Kconfig                   |   5 +
>  drivers/clk/renesas/Makefile                  |   1 +
>  drivers/clk/renesas/r9a09g056-cpg.c           | 152 ++++++++++
>  drivers/clk/renesas/rzv2h-cpg.c               |  18 +-
>  drivers/clk/renesas/rzv2h-cpg.h               |   1 +
>  drivers/pinctrl/renesas/Kconfig               |   1 +
>  drivers/pinctrl/renesas/pinctrl-rzg2l.c       |  36 ++-
>  drivers/soc/renesas/Kconfig                   |  10 +
>  drivers/soc/renesas/Makefile                  |   1 +
>  drivers/soc/renesas/r9a09g056-sys.c           | 107 +++++++
>  drivers/soc/renesas/rz-sysc.c                 |   3 +
>  drivers/soc/renesas/rz-sysc.h                 |   1 +
>  .../dt-bindings/clock/renesas,r9a09g056-cpg.h |  24 ++
>  .../pinctrl/renesas,r9a09g056-pinctrl.h       |  30 ++
>  24 files changed, 790 insertions(+), 10 deletions(-)
>  create mode 100644 arch/arm64/boot/dts/renesas/r9a09g056.dtsi
>  create mode 100644 arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
>  create mode 100644 drivers/clk/renesas/r9a09g056-cpg.c
>  create mode 100644 drivers/soc/renesas/r9a09g056-sys.c
>  create mode 100644 include/dt-bindings/clock/renesas,r9a09g056-cpg.h
>  create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g056-pinctrl.h
> 
> --
> 2.49.0
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: attempting to guess base-commit...
 Base: tags/next-20250326 (best guess, 15/18 blobs matched)

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/renesas/' for 20250326143945.82142-1-prabhakar.mahadev-lad.rj@bp.renesas.com:

arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dtb: pinctrl@10410000: 'interrupt-controller' is a required property
	from schema $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dtb: pinctrl@10410000: '#interrupt-cells' is a required property
	from schema $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#

Re: [PATCH 00/15] Add support for Renesas RZ/V2N SoC and EVK

[Lad, Prabhakar]

Hi Rob,

On Wed, Mar 26, 2025 at 7:11 PM Rob Herring (Arm) <robh@kernel.org> wrote:
>
>
> On Wed, 26 Mar 2025 14:39:30 +0000, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > This patch series adds initial support for the Renesas RZ/V2N (R9A09G056)
> > SoC and its evaluation board (EVK). The Renesas RZ/V2N is a vision AI
> > microprocessor (MPU) designed for power-efficient AI inference and
> > real-time vision processing. It features Renesas' proprietary AI
> > accelerator (DRP-AI3), delivering up to 15 TOPS AI performance, making
> > it ideal for applications such as Driver Monitoring Systems (DMS),
> > industrial monitoring cameras, and mobile robots.
> >
> > Key features of the RZ/V2N SoC:
> >   Processing Power:
> >     - Quad Arm Cortex-A55 cores at 1.8GHz for high-performance computing
> >     - Single Arm Cortex-M33 core at 200MHz for real-time processing
> >     - 1.5MB on-chip SRAM for fast data access
> >     - LPDDR4/LPDDR4X memory interface for high-speed RAM access
> >
> >   AI and Vision Processing:
> >     - DRP-AI3 accelerator for low-power, high-efficiency AI inference
> >     - Arm Mali-C55 ISP (optional) for image signal processing
> >     - Dual MIPI CSI-2 camera interfaces for multi-camera support
> >
> >   High-Speed Interfaces:
> >     - PCIe Gen3 (2-lane) 1ch for external device expansion
> >     - USB 3.2 (Gen2) 1ch (Host-only) for high-speed data transfer
> >     - USB 2.0 (Host/Function) 1ch for legacy connectivity
> >     - Gigabit Ethernet (2 channels) for network communication
> >
> >   Industrial and Automotive Features:
> >     - 6x CAN FD channels for automotive and industrial networking
> >     - 24-channel ADC for sensor data acquisition
> >
> > LINK: https://tinyurl.com/renesas-rz-v2n-soc
> >
> > The series introduces:
> > - Device tree bindings for various subsystems (SYS, SCIF, SDHI, CPG, pinctrl).
> > - RZ/V2N SoC identification support.
> > - Clock and pinctrl driver updates for RZ/V2N.
> > - Initial DTSI and device tree for the RZ/V2N SoC and EVK.
> > - Enabling RZ/V2N SoC support in `arm64 defconfig`.
> >
> > These patches have been tested on the RZ/V2N EVK with v6.14,
> > logs can be found here https://pastebin.com/8i3jgVby
> >
> > Cheers,
> > Prabhakar
> >
> > Lad Prabhakar (15):
> >   dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants
> >   dt-bindings: soc: renesas: Document RZ/V2N EVK board
> >   soc: renesas: Add config option for RZ/V2N (R9A09G056) SoC
> >   dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC
> >   soc: renesas: sysc: Add SoC identification for RZ/V2N SoC
> >   dt-bindings: serial: renesas: Document RZ/V2N SCIF
> >   dt-bindings: mmc: renesas,sdhi: Document RZ/V2N support
> >   dt-bindings: clock: renesas: Document RZ/V2N SoC CPG
> >   clk: renesas: rzv2h-cpg: Sort compatible list based on SoC part number
> >   clk: renesas: rzv2h: Add support for RZ/V2N SoC
> >   dt-bindings: pinctrl: renesas: Document RZ/V2N SoC
> >   pinctrl: renesas: rzg2l: Add support for RZ/V2N SoC
> >   arm64: dts: renesas: Add initial SoC DTSI for RZ/V2N
> >   arm64: dts: renesas: Add initial device tree for RZ/V2N EVK
> >   arm64: defconfig: Enable Renesas RZ/V2N SoC
> >
> >  .../bindings/clock/renesas,rzv2h-cpg.yaml     |   5 +-
> >  .../devicetree/bindings/mmc/renesas,sdhi.yaml |   4 +-
> >  .../pinctrl/renesas,rzg2l-pinctrl.yaml        |   2 +
> >  .../bindings/serial/renesas,scif.yaml         |   1 +
> >  .../soc/renesas/renesas,r9a09g057-sys.yaml    |   1 +
> >  .../bindings/soc/renesas/renesas.yaml         |  15 +
> >  arch/arm64/boot/dts/renesas/Makefile          |   2 +
> >  arch/arm64/boot/dts/renesas/r9a09g056.dtsi    | 264 ++++++++++++++++++
> >  .../dts/renesas/r9a09g056n48-rzv2n-evk.dts    | 115 ++++++++
> >  arch/arm64/configs/defconfig                  |   1 +
> >  drivers/clk/renesas/Kconfig                   |   5 +
> >  drivers/clk/renesas/Makefile                  |   1 +
> >  drivers/clk/renesas/r9a09g056-cpg.c           | 152 ++++++++++
> >  drivers/clk/renesas/rzv2h-cpg.c               |  18 +-
> >  drivers/clk/renesas/rzv2h-cpg.h               |   1 +
> >  drivers/pinctrl/renesas/Kconfig               |   1 +
> >  drivers/pinctrl/renesas/pinctrl-rzg2l.c       |  36 ++-
> >  drivers/soc/renesas/Kconfig                   |  10 +
> >  drivers/soc/renesas/Makefile                  |   1 +
> >  drivers/soc/renesas/r9a09g056-sys.c           | 107 +++++++
> >  drivers/soc/renesas/rz-sysc.c                 |   3 +
> >  drivers/soc/renesas/rz-sysc.h                 |   1 +
> >  .../dt-bindings/clock/renesas,r9a09g056-cpg.h |  24 ++
> >  .../pinctrl/renesas,r9a09g056-pinctrl.h       |  30 ++
> >  24 files changed, 790 insertions(+), 10 deletions(-)
> >  create mode 100644 arch/arm64/boot/dts/renesas/r9a09g056.dtsi
> >  create mode 100644 arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts
> >  create mode 100644 drivers/clk/renesas/r9a09g056-cpg.c
> >  create mode 100644 drivers/soc/renesas/r9a09g056-sys.c
> >  create mode 100644 include/dt-bindings/clock/renesas,r9a09g056-cpg.h
> >  create mode 100644 include/dt-bindings/pinctrl/renesas,r9a09g056-pinctrl.h
> >
> > --
> > 2.49.0
> >
> >
> >
>
>
> My bot found new DTB warnings on the .dts files added or changed in this
> series.
>
> Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
> are fixed by another series. Ultimately, it is up to the platform
> maintainer whether these warnings are acceptable or not. No need to reply
> unless the platform maintainer has comments.
>
> If you already ran DT checks and didn't see these error(s), then
> make sure dt-schema is up to date:
>
>   pip3 install dtschema --upgrade
>
>
> This patch series was applied (using b4) to base:
>  Base: attempting to guess base-commit...
>  Base: tags/next-20250326 (best guess, 15/18 blobs matched)
>
> If this is not the correct base, please add 'base-commit' tag
> (or use b4 which does this automatically)
>
> New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/renesas/' for 20250326143945.82142-1-prabhakar.mahadev-lad.rj@bp.renesas.com:
>
> arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dtb: pinctrl@10410000: 'interrupt-controller' is a required property
>         from schema $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
> arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dtb: pinctrl@10410000: '#interrupt-cells' is a required property
>         from schema $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
>
>
As mentioned in patch 13/15 [0] the above warnings are expected this
is because as part of the initial support, the ICU has not been added
yet. The interrupt-related properties will be added to the pinctrl
node along with ICU support.

[0] https://lore.kernel.org/all/20250326143945.82142-14-prabhakar.mahadev-lad.rj@bp.renesas.com/

Cheers,
Prabhakar

Re: [PATCH 02/15] dt-bindings: soc: renesas: Document RZ/V2N EVK board

[Krzysztof Kozlowski]

On 26/03/2025 15:39, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add "renesas,rzv2n-evk" which targets the Renesas RZ/V2N ("R9A09G056")
> EVK board.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
Squash, previous patch makes no sense on its own.

You, Renesas, already received exactly that feedback!

Best regards,
Krzysztof

Re: [PATCH 15/15] arm64: defconfig: Enable Renesas RZ/V2N SoC

[Krzysztof Kozlowski]

On 26/03/2025 15:39, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Enable support for the Renesas RZ/V2N (R9A09G056) SoC in the ARM64
> defconfig.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  arch/arm64/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 11e7d0ad8656..c7b41f86c128 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -1483,6 +1483,7 @@ CONFIG_ARCH_R9A07G054=y
>  CONFIG_ARCH_R9A08G045=y
>  CONFIG_ARCH_R9A09G011=y
>  CONFIG_ARCH_R9A09G047=y
> +CONFIG_ARCH_R9A09G056=y

So the pattern will keep growing and none of you will ever bother to fix
it, because you have your patchset to throw over the wall.

My previous comments stand.

NAK

Best regards,
Krzysztof

Re: [PATCH 14/15] arm64: dts: renesas: Add initial device tree for RZ/V2N EVK

[Krzysztof Kozlowski]

On 26/03/2025 15:39, Prabhakar wrote:
> +
> +	sd1-pwr-en-hog {
> +		gpio-hog;
> +		gpios = <RZV2N_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
> +		output-high;
> +		line-name = "sd1_pwr_en";
> +	};
> +
> +	sdhi1_pins: sd1 {
> +		sd1_dat_cmd {
Follow DTS coding style.

Best regards,
Krzysztof

Re: [PATCH 11/15] dt-bindings: pinctrl: renesas: Document RZ/V2N SoC

[Krzysztof Kozlowski]

On 26/03/2025 15:39, Prabhakar wrote:
> +#define RZV2N_P3	3
> +#define RZV2N_P4	4
> +#define RZV2N_P5	5
> +#define RZV2N_P6	6
> +#define RZV2N_P7	7
> +#define RZV2N_P8	8
> +#define RZV2N_P9	9
> +#define RZV2N_PA	10
> +#define RZV2N_PB	11

Same comments as before - not useful to repeat the name.

It is the third patch in this patchset, which receives exactly the same
comments as given before.

I expect that given feedback somehow stays within group of contributions
or company in form of internal knowledge. Or just read other people's
patchset to learn from them and do not make the same mistakes.

> +
> +#define RZV2N_PORT_PINMUX(b, p, f)	RZG2L_PORT_PINMUX(RZV2N_P##b, p, f)
> +#define RZV2N_GPIO(port, pin)		RZG2L_GPIO(RZV2N_P##port, pin)

Not a binding. If you claim otherwise, point me to the line of driver
code using this binding.

Best regards,
Krzysztof

Re: [PATCH 15/15] arm64: defconfig: Enable Renesas RZ/V2N SoC

[Geert Uytterhoeven]

Hi Krzysztof,

On Thu, 27 Mar 2025 at 08:43, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On 26/03/2025 15:39, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Enable support for the Renesas RZ/V2N (R9A09G056) SoC in the ARM64
> > defconfig.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> >  arch/arm64/configs/defconfig | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> > index 11e7d0ad8656..c7b41f86c128 100644
> > --- a/arch/arm64/configs/defconfig
> > +++ b/arch/arm64/configs/defconfig
> > @@ -1483,6 +1483,7 @@ CONFIG_ARCH_R9A07G054=y
> >  CONFIG_ARCH_R9A08G045=y
> >  CONFIG_ARCH_R9A09G011=y
> >  CONFIG_ARCH_R9A09G047=y
> > +CONFIG_ARCH_R9A09G056=y
>
> So the pattern will keep growing and none of you will ever bother to fix
> it, because you have your patchset to throw over the wall.

Yes, the pattern will keep on growing.
Just like the minimum kernel size will keep on growing, especially if
you can no longer compile a kernel without support for SoCs you do not
intend to run the kernel on.  Not everyone has GiBs of RAM to spare...

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 15/15] arm64: defconfig: Enable Renesas RZ/V2N SoC

[Geert Uytterhoeven]

On Thu, 27 Mar 2025 at 09:55, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Thu, 27 Mar 2025 at 08:43, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> > On 26/03/2025 15:39, Prabhakar wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Enable support for the Renesas RZ/V2N (R9A09G056) SoC in the ARM64
> > > defconfig.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > >  arch/arm64/configs/defconfig | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> > > index 11e7d0ad8656..c7b41f86c128 100644
> > > --- a/arch/arm64/configs/defconfig
> > > +++ b/arch/arm64/configs/defconfig
> > > @@ -1483,6 +1483,7 @@ CONFIG_ARCH_R9A07G054=y
> > >  CONFIG_ARCH_R9A08G045=y
> > >  CONFIG_ARCH_R9A09G011=y
> > >  CONFIG_ARCH_R9A09G047=y
> > > +CONFIG_ARCH_R9A09G056=y
> >
> > So the pattern will keep growing and none of you will ever bother to fix
> > it, because you have your patchset to throw over the wall.
>
> Yes, the pattern will keep on growing.
> Just like the minimum kernel size will keep on growing, especially if
> you can no longer compile a kernel without support for SoCs you do not
> intend to run the kernel on.  Not everyone has GiBs of RAM to spare...

<pling! :->

/me remembers
https://lore.kernel.org/all/6323eb7a-03e9-4678-ac4f-f90052d0aace@kernel.org/

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 15/15] arm64: defconfig: Enable Renesas RZ/V2N SoC

[Wolfram Sang]

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> So the pattern will keep growing and none of you will ever bother to fix
> it, because you have your patchset to throw over the wall.

I dare to say us Renesas people are not too bad at fixing stuff. In this
particular case, I don't see a wide consensus that the above stuff is
considered broken? Please point me to it if there is such. We are happy
to discuss.


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Re: [PATCH 15/15] arm64: defconfig: Enable Renesas RZ/V2N SoC

[Krzysztof Kozlowski]

On 27/03/2025 10:08, Geert Uytterhoeven wrote:
> On Thu, 27 Mar 2025 at 09:55, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>> On Thu, 27 Mar 2025 at 08:43, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>> On 26/03/2025 15:39, Prabhakar wrote:
>>>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>>>
>>>> Enable support for the Renesas RZ/V2N (R9A09G056) SoC in the ARM64
>>>> defconfig.
>>>>
>>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>>> ---
>>>>  arch/arm64/configs/defconfig | 1 +
>>>>  1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>>>> index 11e7d0ad8656..c7b41f86c128 100644
>>>> --- a/arch/arm64/configs/defconfig
>>>> +++ b/arch/arm64/configs/defconfig
>>>> @@ -1483,6 +1483,7 @@ CONFIG_ARCH_R9A07G054=y
>>>>  CONFIG_ARCH_R9A08G045=y
>>>>  CONFIG_ARCH_R9A09G011=y
>>>>  CONFIG_ARCH_R9A09G047=y
>>>> +CONFIG_ARCH_R9A09G056=y
>>>
>>> So the pattern will keep growing and none of you will ever bother to fix
>>> it, because you have your patchset to throw over the wall.
>>
>> Yes, the pattern will keep on growing.
>> Just like the minimum kernel size will keep on growing, especially if
>> you can no longer compile a kernel without support for SoCs you do not
>> intend to run the kernel on.  Not everyone has GiBs of RAM to spare...
> 
> <pling! :->
> 
> /me remembers
> https://lore.kernel.org/all/6323eb7a-03e9-4678-ac4f-f90052d0aace@kernel.org/

Exactly that discussion and that outcome.

Best regards,
Krzysztof

Re: [PATCH 15/15] arm64: defconfig: Enable Renesas RZ/V2N SoC

[Krzysztof Kozlowski]

On 27/03/2025 13:27, Wolfram Sang wrote:
> 
>> So the pattern will keep growing and none of you will ever bother to fix
>> it, because you have your patchset to throw over the wall.
> 
> I dare to say us Renesas people are not too bad at fixing stuff. In this
> particular case, I don't see a wide consensus that the above stuff is
> considered broken? Please point me to it if there is such. We are happy
> to discuss.
> 

You did not object to last discussion about this (a month ago) - neither
to my comments nor to resolution - so this patchset repeating the same
pattern from the same folks while ignoring previous talk is
contradicting "not too bad at fixing stuff".

Although of course no particular bug is here to fix - I should have used
"change". Anyway, it was long time ago consensus that arm64 does not
receive top-level ARCH_XXX per each SoC. And this is what is being added
here in this patchset.

Best regards,
Krzysztof

Re: [PATCH 15/15] arm64: defconfig: Enable Renesas RZ/V2N SoC

[Wolfram Sang]

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> You did not object to last discussion about this (a month ago) - neither
> to my comments nor to resolution - so this patchset repeating the same

Because I cannot follow every Renesas patch series there is. You are
long enough around to know that large companies have different entities,
groups whatsoever. It is quite a challenge to streamline this via one
group, we need to share work. We do try hard, though, and have a
ARM/RISC-V/RENESAS ARCHITECTURE maintainer. Geert does a *hell of a job*
getting all these submission into shape, and he surely does not accept
code thrown over the wall. And geez, the patch series was just sent
yesterday, you didn't give us even time to raise the issue internally.

> pattern from the same folks while ignoring previous talk is
> contradicting "not too bad at fixing stuff".

First, being a maintainer myself, I do understand the frustration of
patch review not being honored. I can also agree that this series did
not work out perfectly. But that does not mean that we don't care, in
general.  Despite all imperfection and possibly different opinions, we
try hard to be a good citizen and spend considerable time on doing
things right. Accusing us of throwing just "code over the wall" because
there is an issue somewhere which hasn't been worked on in one month is
plain unfair.

That all being said, we will fix it eventually.


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Re: [PATCH 15/15] arm64: defconfig: Enable Renesas RZ/V2N SoC

[Krzysztof Kozlowski]

On 27/03/2025 17:44, Wolfram Sang wrote:
> 
>> You did not object to last discussion about this (a month ago) - neither
>> to my comments nor to resolution - so this patchset repeating the same
> 
> Because I cannot follow every Renesas patch series there is. You are
> long enough around to know that large companies have different entities,
> groups whatsoever. It is quite a challenge to streamline this via one
> group, we need to share work. We do try hard, though, and have a
> ARM/RISC-V/RENESAS ARCHITECTURE maintainer. Geert does a *hell of a job*
> getting all these submission into shape, and he surely does not accept
> code thrown over the wall. And geez, the patch series was just sent
> yesterday, you didn't give us even time to raise the issue internally.
> 
>> pattern from the same folks while ignoring previous talk is
>> contradicting "not too bad at fixing stuff".
> 
> First, being a maintainer myself, I do understand the frustration of
> patch review not being honored. I can also agree that this series did
> not work out perfectly. But that does not mean that we don't care, in
> general.  Despite all imperfection and possibly different opinions, we
> try hard to be a good citizen and spend considerable time on doing
> things right. Accusing us of throwing just "code over the wall" because
> there is an issue somewhere which hasn't been worked on in one month is
> plain unfair.
We do not speak about same things. I speak of review being ignored for
multiple revisions in one patchset and then another patchset sending
exactly the same pattern.

Previous patchset receive my review about this. Thierry ignored it and
send v2 with same code. Then v3 with exactly the same code, but with a
remark in cover letter "but such a change is out of
scope for this patchset."

And now Pabhakar sends the same pattern.

Each of these contributors were not changing here anything, it's like
not their job. It looks like this will never get fixed, because each
person wants to just get their stuff merged, so let's ignore the
reviewers comments.

That's not how upstreaming works - you need to change some things, fix
some stuff, add more code, if you want to add your independent features.
That is how upstream was always. The easiest example is - one new driver
for some completely new feature is fine. Second new driver for similar
new feature receives feedback: please create subsystem to have common
set/handling of that new thingies.

Best regards,
Krzysztof

Re: [PATCH 15/15] arm64: defconfig: Enable Renesas RZ/V2N SoC

[Wolfram Sang]

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Hi Krzysztof,

> We do not speak about same things. I speak of review being ignored for
> multiple revisions in one patchset and then another patchset sending
> exactly the same pattern.

True, we are talking about two different things...

> Each of these contributors were not changing here anything, it's like
> not their job. It looks like this will never get fixed, because each
> person wants to just get their stuff merged, so let's ignore the
> reviewers comments.

... this is the technical part where you are correct. I am not arguing
against it and the issue is currently being worked on as I write this
mail.

Then, there is the communicative part which got me. A response like
"NAK, I am not applying this until you finally fix the issue. And I am
getting angry for being ignored the n-th time" is totally fine and clear
enough. We can escalate that internally. But generalizing Renesas and
ignoring that there are individual people there, trying to fix way more
issues than this particular one, is what I percieved from your responses
and what I considered above the line. And yes, I am aware that you are
also doing a hell of a job going through all these DT and binding
patches which I think are difficult to review.

For me, we are entering the space where we can leave it like this and
maybe discuss details over a drink at the next conference. You are
invited then!

Happy hacking,

   Wolfram


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Re: [PATCH 02/15] dt-bindings: soc: renesas: Document RZ/V2N EVK board

[Lad, Prabhakar]

Hi Krzysztof,

Thank you for the review.

On Thu, Mar 27, 2025 at 7:41 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 26/03/2025 15:39, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add "renesas,rzv2n-evk" which targets the Renesas RZ/V2N ("R9A09G056")
> > EVK board.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> Squash, previous patch makes no sense on its own.
>
Agreed, I will squash this as patch patch 1/15.

> You, Renesas, already received exactly that feedback!
>
I truly apologize for the oversight and appreciate your patience. I’ll
make sure this doesn’t happen again. Thank you for your understanding.

Cheers,
Prabhakar

Re: [PATCH 11/15] dt-bindings: pinctrl: renesas: Document RZ/V2N SoC

[Lad, Prabhakar]

Hi  Krzysztof,

Thank you for the review.

On Thu, Mar 27, 2025 at 7:48 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 26/03/2025 15:39, Prabhakar wrote:
> > +#define RZV2N_P3     3
> > +#define RZV2N_P4     4
> > +#define RZV2N_P5     5
> > +#define RZV2N_P6     6
> > +#define RZV2N_P7     7
> > +#define RZV2N_P8     8
> > +#define RZV2N_P9     9
> > +#define RZV2N_PA     10
> > +#define RZV2N_PB     11
>
> Same comments as before - not useful to repeat the name.
>
> It is the third patch in this patchset, which receives exactly the same
> comments as given before.
>
> I expect that given feedback somehow stays within group of contributions
> or company in form of internal knowledge. Or just read other people's
> patchset to learn from them and do not make the same mistakes.
>
For the RZ/V2H and RZ/G3E SoC similar changes were accepted, to keep
consistency with these SoCs this header file was added.

[0] https://lore.kernel.org/all/20241218192202.GA2184154-robh@kernel.org/

> > +
> > +#define RZV2N_PORT_PINMUX(b, p, f)   RZG2L_PORT_PINMUX(RZV2N_P##b, p, f)
> > +#define RZV2N_GPIO(port, pin)                RZG2L_GPIO(RZV2N_P##port, pin)
>
> Not a binding. If you claim otherwise, point me to the line of driver
> code using this binding.
>
Note, since OF data of V2H was mostly reused in the pinctrl driver due
to similarities there wasn't a need to include this header file in the
driver code. My intention here was to use this header file in DTS/I to
keep similarities. Maybe I'll create a
r9a09g056_variable_pin_cfg{} so that this header file gets included in
the driver.

Cheers,
Prabhakar

Re: [PATCH 14/15] arm64: dts: renesas: Add initial device tree for RZ/V2N EVK

[Lad, Prabhakar]

Hi Krzysztof,

Thank you for the review.

On Thu, Mar 27, 2025 at 7:44 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 26/03/2025 15:39, Prabhakar wrote:
> > +
> > +     sd1-pwr-en-hog {
> > +             gpio-hog;
> > +             gpios = <RZV2N_GPIO(A, 3) GPIO_ACTIVE_HIGH>;
> > +             output-high;
> > +             line-name = "sd1_pwr_en";
> > +     };
> > +
> > +     sdhi1_pins: sd1 {
> > +             sd1_dat_cmd {
> Follow DTS coding style.
>
Sure, I will do that.

Cheers,
Prabhakar

Re: [PATCH 15/15] arm64: defconfig: Enable Renesas RZ/V2N SoC

[Lad, Prabhakar]

Hi Krzysztof,

Thank you for the review.

On Thu, Mar 27, 2025 at 7:43 AM Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 26/03/2025 15:39, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Enable support for the Renesas RZ/V2N (R9A09G056) SoC in the ARM64
> > defconfig.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> >  arch/arm64/configs/defconfig | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> > index 11e7d0ad8656..c7b41f86c128 100644
> > --- a/arch/arm64/configs/defconfig
> > +++ b/arch/arm64/configs/defconfig
> > @@ -1483,6 +1483,7 @@ CONFIG_ARCH_R9A07G054=y
> >  CONFIG_ARCH_R9A08G045=y
> >  CONFIG_ARCH_R9A09G011=y
> >  CONFIG_ARCH_R9A09G047=y
> > +CONFIG_ARCH_R9A09G056=y
>
> So the pattern will keep growing and none of you will ever bother to fix
> it, because you have your patchset to throw over the wall.
>
We are working on this internally, upon approval this change won't be
needed anymore for the new Renesas SoCs.

Cheers,
Prabhakar

Re: [PATCH 04/15] dt-bindings: soc: renesas: Document SYS for RZ/V2N SoC

[Rob Herring (Arm)]

On Wed, 26 Mar 2025 14:39:34 +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add the RZ/V2N (R9A09G056) variant to the existing RZ/V2H(P) System
> Controller (SYS) binding, as both IPs are very similar.
> 
> However, they have different SoC IDs, and the RZ/V2N does not have
> PCIE1 configuration registers, unlike the RZ/V2H(P) SYS IP. To handle
> these differences, introduce a new compatible string
> `renesas,r9a09g056-sys`.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  .../devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml   | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 06/15] dt-bindings: serial: renesas: Document RZ/V2N SCIF

[Rob Herring (Arm)]

On Wed, 26 Mar 2025 14:39:36 +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Document SCIF bindings for the Renesas RZ/V2N (a.k.a R9A09G056) SoC.
> The SCIF interface in Renesas RZ/V2N is identical to the one available
> in RZ/V2H(P), so `renesas,scif-r9a09g057` will be used as a fallback,
> allowing reuse of the existing driver without modifications.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 07/15] dt-bindings: mmc: renesas,sdhi: Document RZ/V2N support

[Rob Herring (Arm)]

On Wed, 26 Mar 2025 14:39:37 +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add SDHI bindings for the Renesas RZ/V2N (a.k.a R9A09G056) SoC. Use
> `renesas,sdhi-r9a09g057` as a fallback since the SD/MMC block on
> RZ/V2N is identical to the one on RZ/V2H(P), allowing reuse of the
> existing driver without modifications.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 08/15] dt-bindings: clock: renesas: Document RZ/V2N SoC CPG

[Rob Herring (Arm)]

On Wed, 26 Mar 2025 14:39:38 +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Document the device tree bindings for the Renesas RZ/V2N (R9A09G056)
> SoC Clock Pulse Generator (CPG).
> 
> Update `renesas,rzv2h-cpg.yaml` to include the compatible string for
> RZ/V2N SoC and adjust the title and description accordingly.
> 
> Additionally, introduce `renesas,r9a09g056-cpg.h` to define core clock
> constants for the RZ/V2N SoC. Note the existing RZ/V2H(P) family-specific
> clock driver will be reused for this SoC.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  .../bindings/clock/renesas,rzv2h-cpg.yaml     |  5 ++--
>  .../dt-bindings/clock/renesas,r9a09g056-cpg.h | 24 +++++++++++++++++++
>  2 files changed, 27 insertions(+), 2 deletions(-)
>  create mode 100644 include/dt-bindings/clock/renesas,r9a09g056-cpg.h
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 07/15] dt-bindings: mmc: renesas,sdhi: Document RZ/V2N support

[Geert Uytterhoeven]

On Wed, 26 Mar 2025 at 15:40, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add SDHI bindings for the Renesas RZ/V2N (a.k.a R9A09G056) SoC. Use
> `renesas,sdhi-r9a09g057` as a fallback since the SD/MMC block on
> RZ/V2N is identical to the one on RZ/V2H(P), allowing reuse of the
> existing driver without modifications.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

JFTR
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds