[PATCH 0/3] Add pinctrl and GPIO support for MediaTek MT8901

[PATCH 0/3] Add pinctrl and GPIO support for MediaTek MT8901

[Lei Xue]

Dear maintainers,

This patch series contains three patches aimed at improving the
Linux kernel support for MediaTek platforms, specifically for
the MT8901 SoC. The details are as follows:

Add GPIO range record in MediaTek pinctrl driver
 - This patch introduces GPIO range recording in the MediaTek
   pinctrl driver, providing a foundation for proper GPIO
   identification and management.

Add ACPI support in MediaTek pinctrl driver
 - This patch adds ACPI support to the MediaTek pinctrl driver,
   enabling the driver to function correctly in ACPI environments
   and enhancing platform compatibility.

Add pinctrl driver for MediaTek MT8901
 - This patch adds a new pinctrl driver for the MT8901 SoC,
   defining the GPIO functions, register mappings, and multiplexing
   relationships to improve pin control capabilities for MT8901.

These patches will help enhance the mainline kernel support for MediaTek MT8901.
Your review and feedback are highly appreciated.

Thank you!


Lei Xue (3):
  pinctrl: mediatek: Add gpio-range record in pinctrl driver
  pinctrl: mediatek: Add acpi support
  pinctrl: mediatek: mt8901: Add pinctrl driver for MT8901

 drivers/pinctrl/mediatek/Kconfig              |   12 +
 drivers/pinctrl/mediatek/Makefile             |    1 +
 drivers/pinctrl/mediatek/mtk-eint.c           |    4 +
 drivers/pinctrl/mediatek/mtk-eint.h           |    1 +
 drivers/pinctrl/mediatek/pinctrl-mt8901.c     | 1460 +++++++++++
 .../pinctrl/mediatek/pinctrl-mtk-common-v2.c  |   24 +-
 .../pinctrl/mediatek/pinctrl-mtk-common-v2.h  |    1 +
 drivers/pinctrl/mediatek/pinctrl-mtk-mt8901.h | 2130 +++++++++++++++++
 drivers/pinctrl/mediatek/pinctrl-paris.c      |   21 +-
 9 files changed, 3647 insertions(+), 7 deletions(-)
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8901.c
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8901.h

-- 
2.45.2

[PATCH 1/3] pinctrl: mediatek: Add gpio-range record in pinctrl driver

[Lei Xue]

Kernel GPIO subsystem mapping hardware pin number to a different
range of gpio number. Add gpio-range structure to hold
the mapped gpio range in pinctrl driver. That enables the kernel
to search a range of mapped gpio range against a pinctrl device.

Signed-off-by: Lei Xue <lei.xue@mediatek.com>
---
 drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h |  1 +
 drivers/pinctrl/mediatek/pinctrl-paris.c         | 15 ++++++++++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
index fa7c0ed49346..df8dce14744f 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
@@ -302,6 +302,7 @@ struct mtk_pinctrl {
 	spinlock_t lock;
 	/* identify rsel setting by si unit or rsel define in dts node */
 	bool rsel_si_unit;
+	struct pinctrl_gpio_range	range;
 };
 
 void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set);
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c
index 6bf37d8085fa..2cf61cfe809e 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -3,7 +3,7 @@
  * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin
  * bindings for MediaTek SoC.
  *
- * Copyright (C) 2018 MediaTek Inc.
+ * Copyright (C) 2018-2025 MediaTek Inc.
  * Author: Sean Wang <sean.wang@mediatek.com>
  *	   Zhiyong Tao <zhiyong.tao@mediatek.com>
  *	   Hongzhou.Yang <hongzhou.yang@mediatek.com>
@@ -936,6 +936,15 @@ static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
 	return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
 }
 
+static void mtk_pinctrl_gpio_range_init(struct mtk_pinctrl *hw, struct gpio_chip *chip)
+{
+	hw->range.name = "mtk_pinctrl_gpio_range";
+	hw->range.id = 0;
+	hw->range.pin_base = 0;
+	hw->range.base = chip->base;
+	hw->range.npins = hw->soc->npins;
+}
+
 static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
 {
 	struct gpio_chip *chip = &hw->chip;
@@ -959,6 +968,8 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
 	if (ret < 0)
 		return ret;
 
+	mtk_pinctrl_gpio_range_init(hw, chip);
+
 	return 0;
 }
 
@@ -1077,6 +1088,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev)
 	if (err)
 		return dev_err_probe(dev, err, "Failed to add gpio_chip\n");
 
+	pinctrl_add_gpio_range(hw->pctrl, &hw->range);
+
 	platform_set_drvdata(pdev, hw);
 
 	return 0;
-- 
2.45.2

[PATCH 2/3] pinctrl: mediatek: Add acpi support

[Lei Xue]

Add acpi support in the common part of pinctrl driver. Parsing
hardware base addresses and irq number to initialize eint
accroding to the acpi table data.

Signed-off-by: Lei Xue <lei.xue@mediatek.com>
---
 .../pinctrl/mediatek/pinctrl-mtk-common-v2.c  | 24 +++++++++++++++----
 drivers/pinctrl/mediatek/pinctrl-paris.c      |  6 +++--
 2 files changed, 24 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
index 4918d38abfc2..afa406afead2 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -369,18 +369,30 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
 	int ret, i, j, count_reg_names;
+	struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev);
+	struct resource *res;
 
 	if (!IS_ENABLED(CONFIG_EINT_MTK))
 		return 0;
 
-	if (!of_property_read_bool(np, "interrupt-controller"))
+	if (is_of_node(fwnode) && !of_property_read_bool(np, "interrupt-controller"))
 		return -ENODEV;
 
 	hw->eint = devm_kzalloc(hw->dev, sizeof(*hw->eint), GFP_KERNEL);
 	if (!hw->eint)
 		return -ENOMEM;
 
-	count_reg_names = of_property_count_strings(np, "reg-names");
+	if (is_of_node(fwnode)) {
+		count_reg_names = of_property_count_strings(np, "reg-names");
+	} else {
+		count_reg_names = 0;
+		for (i = 0; i < pdev->num_resources; i++) {
+			struct resource *r = &pdev->resource[i];
+
+			if (resource_type(r) == IORESOURCE_MEM)
+				count_reg_names++;
+		}
+	}
 	if (count_reg_names < 0)
 		return -EINVAL;
 
@@ -396,14 +408,18 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev)
 	}
 
 	for (i = hw->soc->nbase_names, j = 0; i < count_reg_names; i++, j++) {
-		hw->eint->base[j] = of_iomap(np, i);
+		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+		hw->eint->base[j] = is_of_node(fwnode) ? of_iomap(np, i) :
+					ioremap(res->start, resource_size(res));
 		if (IS_ERR(hw->eint->base[j])) {
 			ret = PTR_ERR(hw->eint->base[j]);
 			goto err_free_eint;
 		}
 	}
 
-	hw->eint->irq = irq_of_parse_and_map(np, 0);
+	hw->eint->irq = is_of_node(fwnode)
+			? irq_of_parse_and_map(np, 0)
+			: platform_get_irq(pdev, 0);
 	if (!hw->eint->irq) {
 		ret = -EINVAL;
 		goto err_free_eint;
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c
index 2cf61cfe809e..9c2751b9b065 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -1008,6 +1008,7 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct pinctrl_pin_desc *pins;
 	struct mtk_pinctrl *hw;
+	struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev);
 	int err, i;
 
 	hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
@@ -1032,8 +1033,9 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	for (i = 0; i < hw->soc->nbase_names; i++) {
-		hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
-					hw->soc->base_names[i]);
+		hw->base[i] = is_of_node(fwnode)
+			? devm_platform_ioremap_resource_byname(pdev, hw->soc->base_names[i])
+			: devm_platform_get_and_ioremap_resource(pdev, i, NULL);
 		if (IS_ERR(hw->base[i]))
 			return PTR_ERR(hw->base[i]);
 	}
-- 
2.45.2

[PATCH 3/3] pinctrl: mediatek: mt8901: Add pinctrl driver for MT8901

[Lei Xue]

Add mt8901 pinctrl, gpio and eint driver implementation.

Signed-off-by: Lei Xue <lei.xue@mediatek.com>
---
 drivers/pinctrl/mediatek/Kconfig              |   12 +
 drivers/pinctrl/mediatek/Makefile             |    1 +
 drivers/pinctrl/mediatek/mtk-eint.c           |    4 +
 drivers/pinctrl/mediatek/mtk-eint.h           |    1 +
 drivers/pinctrl/mediatek/pinctrl-mt8901.c     | 1460 +++++++++++
 drivers/pinctrl/mediatek/pinctrl-mtk-mt8901.h | 2130 +++++++++++++++++
 6 files changed, 3608 insertions(+)
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8901.c
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8901.h

diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 4819617d9368..4820ae5197a0 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -321,6 +321,18 @@ config PINCTRL_MT8516
 	default ARM64 && ARCH_MEDIATEK
 	select PINCTRL_MTK
 
+config PINCTRL_MT8901
+	bool "MediaTek MT8901 pin control"
+	depends on ACPI
+	depends on ARM64 || COMPILE_TEST
+	default ARM64 && ARCH_MEDIATEK
+	select PINCTRL_MTK_PARIS
+	help
+	  Say yes here to support pin controller and gpio driver
+	  on MediaTek MT8901 SoC.
+	  In MTK platform, we support virtual gpio and use it to
+	  map specific eint which doesn't have real gpio pin.
+
 # For PMIC
 config PINCTRL_MT6397
 	bool "MediaTek MT6397 pin control"
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index ae765bd99965..57c69b1e5c2d 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -43,3 +43,4 @@ obj-$(CONFIG_PINCTRL_MT8196)		+= pinctrl-mt8196.o
 obj-$(CONFIG_PINCTRL_MT8365)		+= pinctrl-mt8365.o
 obj-$(CONFIG_PINCTRL_MT8516)		+= pinctrl-mt8516.o
 obj-$(CONFIG_PINCTRL_MT6397)		+= pinctrl-mt6397.o
+obj-$(CONFIG_PINCTRL_MT8901)		+= pinctrl-mt8901.o
diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c
index c8c5097c11c4..b5a5beebf9cd 100644
--- a/drivers/pinctrl/mediatek/mtk-eint.c
+++ b/drivers/pinctrl/mediatek/mtk-eint.c
@@ -71,6 +71,10 @@ const unsigned int debounce_time_mt6878[] = {
 };
 EXPORT_SYMBOL_GPL(debounce_time_mt6878);
 
+const unsigned int debounce_time_mt8901[] = {
+	156, 313, 625, 1250, 20000, 40000, 80000, 160000, 320000, 640000, 0};
+EXPORT_SYMBOL_GPL(debounce_time_mt8901);
+
 static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
 					 unsigned int eint_num,
 					 unsigned int offset)
diff --git a/drivers/pinctrl/mediatek/mtk-eint.h b/drivers/pinctrl/mediatek/mtk-eint.h
index 3cdd6f6310cd..1b185f660aff 100644
--- a/drivers/pinctrl/mediatek/mtk-eint.h
+++ b/drivers/pinctrl/mediatek/mtk-eint.h
@@ -53,6 +53,7 @@ extern const unsigned int debounce_time_mt2701[];
 extern const unsigned int debounce_time_mt6765[];
 extern const unsigned int debounce_time_mt6795[];
 extern const unsigned int debounce_time_mt6878[];
+extern const unsigned int debounce_time_mt8901[];
 
 struct mtk_eint;
 
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8901.c b/drivers/pinctrl/mediatek/pinctrl-mt8901.c
new file mode 100644
index 000000000000..77dec85fe29b
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8901.c
@@ -0,0 +1,1460 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ *
+ */
+
+#include <linux/acpi.h>
+#include <linux/module.h>
+#include "pinctrl-mtk-mt8901.h"
+#include "pinctrl-paris.h"
+
+#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits)  \
+	PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 0)
+#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \
+	PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, 32, 1)
+
+static const struct mtk_pin_field_calc mt8901_pin_mode_range[] = {
+	PIN_FIELD(0, 181, 0x0300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt8901_pin_dir_range[] = {
+	PIN_FIELD(0, 181, 0x0000, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8901_pin_di_range[] = {
+	PIN_FIELD(0, 181, 0x0200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8901_pin_do_range[] = {
+	PIN_FIELD(0, 181, 0x0100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8901_pin_smt_range[] = {
+	PIN_FIELD_BASE(0, 0, 8, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(1, 1, 8, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(2, 2, 8, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(3, 3, 8, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(4, 4, 8, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(5, 5, 8, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(6, 6, 8, 0x00c0, 0x10, 6, 1),
+	PIN_FIELD_BASE(7, 7, 8, 0x00c0, 0x10, 7, 1),
+	PIN_FIELD_BASE(8, 8, 2, 0x0120, 0x10, 13, 1),
+	PIN_FIELD_BASE(9, 9, 2, 0x0120, 0x10, 14, 1),
+	PIN_FIELD_BASE(10, 10, 2, 0x0120, 0x10, 15, 1),
+	PIN_FIELD_BASE(11, 11, 2, 0x0120, 0x10, 16, 1),
+	PIN_FIELD_BASE(12, 12, 1, 0x0140, 0x10, 17, 1),
+	PIN_FIELD_BASE(13, 13, 1, 0x0140, 0x10, 18, 1),
+	PIN_FIELD_BASE(14, 14, 1, 0x0140, 0x10, 14, 1),
+	PIN_FIELD_BASE(15, 15, 1, 0x0140, 0x10, 16, 1),
+	PIN_FIELD_BASE(16, 16, 1, 0x0140, 0x10, 19, 1),
+	PIN_FIELD_BASE(17, 17, 1, 0x0140, 0x10, 20, 1),
+	PIN_FIELD_BASE(18, 18, 1, 0x0140, 0x10, 21, 1),
+	PIN_FIELD_BASE(19, 19, 1, 0x0140, 0x10, 27, 1),
+	PIN_FIELD_BASE(20, 20, 1, 0x0140, 0x10, 28, 1),
+	PIN_FIELD_BASE(21, 21, 1, 0x0140, 0x10, 26, 1),
+	PIN_FIELD_BASE(22, 22, 1, 0x0140, 0x10, 25, 1),
+	PIN_FIELD_BASE(23, 23, 1, 0x0140, 0x10, 0, 1),
+	PIN_FIELD_BASE(24, 24, 1, 0x0140, 0x10, 1, 1),
+	PIN_FIELD_BASE(25, 25, 1, 0x0140, 0x10, 2, 1),
+	PIN_FIELD_BASE(26, 26, 1, 0x0140, 0x10, 3, 1),
+	PIN_FIELD_BASE(27, 27, 1, 0x0140, 0x10, 4, 1),
+	PIN_FIELD_BASE(28, 28, 1, 0x0140, 0x10, 5, 1),
+	PIN_FIELD_BASE(29, 29, 1, 0x0140, 0x10, 6, 1),
+	PIN_FIELD_BASE(30, 30, 1, 0x0140, 0x10, 7, 1),
+	PIN_FIELD_BASE(31, 31, 1, 0x0140, 0x10, 8, 1),
+	PIN_FIELD_BASE(32, 32, 9, 0x0100, 0x10, 0, 1),
+	PIN_FIELD_BASE(33, 33, 1, 0x0140, 0x10, 9, 1),
+	PIN_FIELD_BASE(34, 34, 1, 0x0140, 0x10, 10, 1),
+	PIN_FIELD_BASE(35, 35, 1, 0x0140, 0x10, 11, 1),
+	PIN_FIELD_BASE(36, 36, 9, 0x0100, 0x10, 8, 1),
+	PIN_FIELD_BASE(37, 37, 2, 0x0120, 0x10, 17, 1),
+	PIN_FIELD_BASE(38, 38, 2, 0x0120, 0x10, 18, 1),
+	PIN_FIELD_BASE(39, 39, 1, 0x0140, 0x10, 12, 1),
+	PIN_FIELD_BASE(40, 40, 2, 0x0120, 0x10, 1, 1),
+	PIN_FIELD_BASE(41, 41, 2, 0x0120, 0x10, 2, 1),
+	PIN_FIELD_BASE(42, 42, 2, 0x0120, 0x10, 3, 1),
+	PIN_FIELD_BASE(43, 43, 2, 0x0120, 0x10, 4, 1),
+	PIN_FIELD_BASE(44, 44, 2, 0x0120, 0x10, 5, 1),
+	PIN_FIELD_BASE(45, 45, 2, 0x0120, 0x10, 6, 1),
+	PIN_FIELD_BASE(46, 46, 1, 0x0140, 0x10, 13, 1),
+	PIN_FIELD_BASE(47, 47, 1, 0x0140, 0x10, 15, 1),
+	PIN_FIELD_BASE(48, 48, 2, 0x0120, 0x10, 7, 1),
+	PIN_FIELD_BASE(49, 49, 2, 0x0120, 0x10, 8, 1),
+	PIN_FIELD_BASE(50, 50, 2, 0x0120, 0x10, 9, 1),
+	PIN_FIELD_BASE(51, 51, 2, 0x0120, 0x10, 10, 1),
+	PIN_FIELD_BASE(52, 52, 2, 0x0120, 0x10, 11, 1),
+	PIN_FIELD_BASE(53, 53, 2, 0x0120, 0x10, 12, 1),
+	PIN_FIELD_BASE(54, 54, 5, 0x0120, 0x10, 10, 1),
+	PIN_FIELD_BASE(55, 55, 5, 0x0120, 0x10, 11, 1),
+	PIN_FIELD_BASE(56, 56, 1, 0x0140, 0x10, 22, 1),
+	PIN_FIELD_BASE(57, 57, 1, 0x0140, 0x10, 23, 1),
+	PIN_FIELD_BASE(58, 58, 1, 0x0140, 0x10, 24, 1),
+	PIN_FIELD_BASE(59, 59, 2, 0x0120, 0x10, 0, 1),
+	PIN_FIELD_BASE(60, 60, 9, 0x0100, 0x10, 1, 1),
+	PIN_FIELD_BASE(61, 61, 9, 0x0100, 0x10, 2, 1),
+	PIN_FIELD_BASE(62, 62, 9, 0x0100, 0x10, 3, 1),
+	PIN_FIELD_BASE(63, 63, 9, 0x0100, 0x10, 4, 1),
+	PIN_FIELD_BASE(64, 64, 9, 0x0100, 0x10, 5, 1),
+	PIN_FIELD_BASE(65, 65, 9, 0x0100, 0x10, 6, 1),
+	PIN_FIELD_BASE(66, 66, 5, 0x0120, 0x10, 0, 1),
+	PIN_FIELD_BASE(67, 67, 5, 0x0120, 0x10, 1, 1),
+	PIN_FIELD_BASE(68, 68, 9, 0x0100, 0x10, 7, 1),
+	PIN_FIELD_BASE(69, 69, 7, 0x0110, 0x10, 0, 1),
+	PIN_FIELD_BASE(70, 70, 7, 0x0110, 0x10, 1, 1),
+	PIN_FIELD_BASE(71, 71, 7, 0x0110, 0x10, 2, 1),
+	PIN_FIELD_BASE(72, 72, 7, 0x0110, 0x10, 3, 1),
+	PIN_FIELD_BASE(73, 73, 7, 0x0110, 0x10, 4, 1),
+	PIN_FIELD_BASE(74, 74, 7, 0x0110, 0x10, 5, 1),
+	PIN_FIELD_BASE(75, 75, 7, 0x0110, 0x10, 6, 1),
+	PIN_FIELD_BASE(76, 76, 7, 0x0110, 0x10, 7, 1),
+	PIN_FIELD_BASE(77, 77, 7, 0x0110, 0x10, 8, 1),
+	PIN_FIELD_BASE(78, 78, 7, 0x0110, 0x10, 9, 1),
+	PIN_FIELD_BASE(79, 79, 7, 0x0110, 0x10, 10, 1),
+	PIN_FIELD_BASE(80, 80, 7, 0x0110, 0x10, 11, 1),
+	PIN_FIELD_BASE(81, 81, 7, 0x0110, 0x10, 12, 1),
+	PIN_FIELD_BASE(82, 82, 7, 0x0110, 0x10, 13, 1),
+	PIN_FIELD_BASE(83, 83, 7, 0x0110, 0x10, 14, 1),
+	PIN_FIELD_BASE(84, 84, 7, 0x0110, 0x10, 15, 1),
+	PIN_FIELD_BASE(85, 85, 7, 0x0110, 0x10, 16, 1),
+	PIN_FIELD_BASE(86, 86, 7, 0x0110, 0x10, 17, 1),
+	PIN_FIELD_BASE(87, 87, 7, 0x0110, 0x10, 18, 1),
+	PIN_FIELD_BASE(88, 88, 7, 0x0110, 0x10, 19, 1),
+	PIN_FIELD_BASE(89, 89, 7, 0x0110, 0x10, 20, 1),
+	PIN_FIELD_BASE(90, 90, 7, 0x0110, 0x10, 21, 1),
+	PIN_FIELD_BASE(91, 91, 7, 0x0110, 0x10, 22, 1),
+	PIN_FIELD_BASE(92, 92, 3, 0x0130, 0x10, 16, 1),
+	PIN_FIELD_BASE(93, 93, 3, 0x0130, 0x10, 17, 1),
+	PIN_FIELD_BASE(94, 94, 3, 0x0130, 0x10, 18, 1),
+	PIN_FIELD_BASE(95, 95, 3, 0x0130, 0x10, 19, 1),
+	PIN_FIELD_BASE(96, 96, 3, 0x0130, 0x10, 20, 1),
+	PIN_FIELD_BASE(97, 97, 3, 0x0130, 0x10, 21, 1),
+	PIN_FIELD_BASE(98, 98, 3, 0x0130, 0x10, 22, 1),
+	PIN_FIELD_BASE(99, 99, 3, 0x0130, 0x10, 23, 1),
+	PIN_FIELD_BASE(100, 100, 3, 0x0130, 0x10, 24, 1),
+	PIN_FIELD_BASE(101, 101, 3, 0x0130, 0x10, 25, 1),
+	PIN_FIELD_BASE(102, 102, 3, 0x0130, 0x10, 26, 1),
+	PIN_FIELD_BASE(103, 103, 3, 0x0130, 0x10, 27, 1),
+	PIN_FIELD_BASE(104, 104, 3, 0x0130, 0x10, 28, 1),
+	PIN_FIELD_BASE(105, 105, 3, 0x0130, 0x10, 29, 1),
+	PIN_FIELD_BASE(106, 106, 8, 0x00c0, 0x10, 8, 1),
+	PIN_FIELD_BASE(107, 107, 8, 0x00c0, 0x10, 9, 1),
+	PIN_FIELD_BASE(108, 108, 8, 0x00c0, 0x10, 10, 1),
+	PIN_FIELD_BASE(109, 109, 8, 0x00c0, 0x10, 11, 1),
+	PIN_FIELD_BASE(110, 110, 8, 0x00c0, 0x10, 12, 1),
+	PIN_FIELD_BASE(111, 111, 8, 0x00c0, 0x10, 13, 1),
+	PIN_FIELD_BASE(112, 112, 5, 0x0120, 0x10, 15, 1),
+	PIN_FIELD_BASE(113, 113, 5, 0x0120, 0x10, 16, 1),
+	PIN_FIELD_BASE(114, 114, 5, 0x0120, 0x10, 17, 1),
+	PIN_FIELD_BASE(115, 115, 5, 0x0120, 0x10, 18, 1),
+	PIN_FIELD_BASE(116, 116, 5, 0x0120, 0x10, 19, 1),
+	PIN_FIELD_BASE(117, 117, 4, 0x0110, 0x10, 8, 1),
+	PIN_FIELD_BASE(118, 118, 4, 0x0110, 0x10, 9, 1),
+	PIN_FIELD_BASE(119, 119, 4, 0x0110, 0x10, 10, 1),
+	PIN_FIELD_BASE(120, 120, 4, 0x0110, 0x10, 11, 1),
+	PIN_FIELD_BASE(121, 121, 4, 0x0110, 0x10, 12, 1),
+	PIN_FIELD_BASE(122, 122, 4, 0x0110, 0x10, 13, 1),
+	PIN_FIELD_BASE(123, 123, 4, 0x0110, 0x10, 14, 1),
+	PIN_FIELD_BASE(124, 124, 4, 0x0110, 0x10, 15, 1),
+	PIN_FIELD_BASE(125, 125, 4, 0x0110, 0x10, 16, 1),
+	PIN_FIELD_BASE(126, 126, 5, 0x0120, 0x10, 6, 1),
+	PIN_FIELD_BASE(127, 127, 5, 0x0120, 0x10, 7, 1),
+	PIN_FIELD_BASE(128, 128, 5, 0x0120, 0x10, 8, 1),
+	PIN_FIELD_BASE(129, 129, 5, 0x0120, 0x10, 9, 1),
+	PIN_FIELD_BASE(130, 130, 4, 0x0110, 0x10, 17, 1),
+	PIN_FIELD_BASE(131, 131, 4, 0x0110, 0x10, 18, 1),
+	PIN_FIELD_BASE(132, 132, 4, 0x0110, 0x10, 19, 1),
+	PIN_FIELD_BASE(133, 133, 4, 0x0110, 0x10, 20, 1),
+	PIN_FIELD_BASE(134, 134, 3, 0x0130, 0x10, 0, 1),
+	PIN_FIELD_BASE(135, 135, 3, 0x0130, 0x10, 1, 1),
+	PIN_FIELD_BASE(136, 136, 3, 0x0130, 0x10, 2, 1),
+	PIN_FIELD_BASE(137, 137, 3, 0x0130, 0x10, 3, 1),
+	PIN_FIELD_BASE(138, 138, 3, 0x0130, 0x10, 4, 1),
+	PIN_FIELD_BASE(139, 139, 3, 0x0130, 0x10, 5, 1),
+	PIN_FIELD_BASE(140, 140, 3, 0x0130, 0x10, 6, 1),
+	PIN_FIELD_BASE(141, 141, 3, 0x0130, 0x10, 7, 1),
+	PIN_FIELD_BASE(142, 142, 3, 0x0130, 0x10, 8, 1),
+	PIN_FIELD_BASE(143, 143, 3, 0x0130, 0x10, 9, 1),
+	PIN_FIELD_BASE(144, 144, 3, 0x0130, 0x10, 10, 1),
+	PIN_FIELD_BASE(145, 145, 3, 0x0130, 0x10, 11, 1),
+	PIN_FIELD_BASE(146, 146, 3, 0x0130, 0x10, 12, 1),
+	PIN_FIELD_BASE(147, 147, 3, 0x0130, 0x10, 13, 1),
+	PIN_FIELD_BASE(148, 148, 3, 0x0130, 0x10, 14, 1),
+	PIN_FIELD_BASE(149, 149, 3, 0x0130, 0x10, 15, 1),
+	PIN_FIELD_BASE(150, 150, 4, 0x0110, 0x10, 21, 1),
+	PIN_FIELD_BASE(151, 151, 4, 0x0110, 0x10, 26, 1),
+	PIN_FIELD_BASE(152, 152, 4, 0x0110, 0x10, 25, 1),
+	PIN_FIELD_BASE(153, 153, 4, 0x0110, 0x10, 24, 1),
+	PIN_FIELD_BASE(154, 154, 4, 0x0110, 0x10, 22, 1),
+	PIN_FIELD_BASE(155, 155, 4, 0x0110, 0x10, 23, 1),
+	PIN_FIELD_BASE(156, 156, 4, 0x0110, 0x10, 0, 1),
+	PIN_FIELD_BASE(157, 157, 4, 0x0110, 0x10, 1, 1),
+	PIN_FIELD_BASE(158, 158, 4, 0x0110, 0x10, 2, 1),
+	PIN_FIELD_BASE(159, 159, 4, 0x0110, 0x10, 3, 1),
+	PIN_FIELD_BASE(160, 160, 4, 0x0110, 0x10, 4, 1),
+	PIN_FIELD_BASE(161, 161, 4, 0x0110, 0x10, 5, 1),
+	PIN_FIELD_BASE(162, 162, 4, 0x0110, 0x10, 6, 1),
+	PIN_FIELD_BASE(163, 163, 4, 0x0110, 0x10, 7, 1),
+	PIN_FIELD_BASE(164, 164, 5, 0x0120, 0x10, 12, 1),
+	PIN_FIELD_BASE(165, 165, 5, 0x0120, 0x10, 3, 1),
+	PIN_FIELD_BASE(166, 166, 5, 0x0120, 0x10, 4, 1),
+	PIN_FIELD_BASE(167, 167, 5, 0x0120, 0x10, 2, 1),
+	PIN_FIELD_BASE(168, 168, 5, 0x0120, 0x10, 13, 1),
+	PIN_FIELD_BASE(169, 169, 5, 0x0120, 0x10, 14, 1),
+	PIN_FIELD_BASE(170, 170, 5, 0x0120, 0x10, 5, 1),
+	PIN_FIELD_BASE(171, 171, 6, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(172, 172, 6, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(173, 173, 6, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(174, 174, 6, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(175, 175, 6, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(176, 176, 6, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(177, 177, 6, 0x00c0, 0x10, 6, 1),
+	PIN_FIELD_BASE(178, 178, 6, 0x00c0, 0x10, 7, 1),
+	PIN_FIELD_BASE(179, 179, 6, 0x00c0, 0x10, 8, 1),
+	PIN_FIELD_BASE(180, 180, 6, 0x00c0, 0x10, 9, 1),
+	PIN_FIELD_BASE(181, 181, 10, 0x0080, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8901_pin_ies_range[] = {
+	PIN_FIELD_BASE(0, 0, 8, 0x0050, 0x10, 0, 1),
+	PIN_FIELD_BASE(1, 1, 8, 0x0050, 0x10, 1, 1),
+	PIN_FIELD_BASE(2, 2, 8, 0x0050, 0x10, 2, 1),
+	PIN_FIELD_BASE(3, 3, 8, 0x0050, 0x10, 3, 1),
+	PIN_FIELD_BASE(4, 4, 8, 0x0050, 0x10, 4, 1),
+	PIN_FIELD_BASE(5, 5, 8, 0x0050, 0x10, 5, 1),
+	PIN_FIELD_BASE(6, 6, 8, 0x0050, 0x10, 6, 1),
+	PIN_FIELD_BASE(7, 7, 8, 0x0050, 0x10, 7, 1),
+	PIN_FIELD_BASE(8, 8, 2, 0x0070, 0x10, 13, 1),
+	PIN_FIELD_BASE(9, 9, 2, 0x0070, 0x10, 14, 1),
+	PIN_FIELD_BASE(10, 10, 2, 0x0070, 0x10, 15, 1),
+	PIN_FIELD_BASE(11, 11, 2, 0x0070, 0x10, 16, 1),
+	PIN_FIELD_BASE(12, 12, 1, 0x0080, 0x10, 17, 1),
+	PIN_FIELD_BASE(13, 13, 1, 0x0080, 0x10, 18, 1),
+	PIN_FIELD_BASE(14, 14, 1, 0x0080, 0x10, 14, 1),
+	PIN_FIELD_BASE(15, 15, 1, 0x0080, 0x10, 16, 1),
+	PIN_FIELD_BASE(16, 16, 1, 0x0080, 0x10, 19, 1),
+	PIN_FIELD_BASE(17, 17, 1, 0x0080, 0x10, 20, 1),
+	PIN_FIELD_BASE(18, 18, 1, 0x0080, 0x10, 21, 1),
+	PIN_FIELD_BASE(19, 19, 1, 0x0080, 0x10, 27, 1),
+	PIN_FIELD_BASE(20, 20, 1, 0x0080, 0x10, 28, 1),
+	PIN_FIELD_BASE(21, 21, 1, 0x0080, 0x10, 26, 1),
+	PIN_FIELD_BASE(22, 22, 1, 0x0080, 0x10, 25, 1),
+	PIN_FIELD_BASE(23, 23, 1, 0x0080, 0x10, 0, 1),
+	PIN_FIELD_BASE(24, 24, 1, 0x0080, 0x10, 1, 1),
+	PIN_FIELD_BASE(25, 25, 1, 0x0080, 0x10, 2, 1),
+	PIN_FIELD_BASE(26, 26, 1, 0x0080, 0x10, 3, 1),
+	PIN_FIELD_BASE(27, 27, 1, 0x0080, 0x10, 4, 1),
+	PIN_FIELD_BASE(28, 28, 1, 0x0080, 0x10, 5, 1),
+	PIN_FIELD_BASE(29, 29, 1, 0x0080, 0x10, 6, 1),
+	PIN_FIELD_BASE(30, 30, 1, 0x0080, 0x10, 7, 1),
+	PIN_FIELD_BASE(31, 31, 1, 0x0080, 0x10, 8, 1),
+	PIN_FIELD_BASE(32, 32, 9, 0x0060, 0x10, 0, 1),
+	PIN_FIELD_BASE(33, 33, 1, 0x0080, 0x10, 9, 1),
+	PIN_FIELD_BASE(34, 34, 1, 0x0080, 0x10, 10, 1),
+	PIN_FIELD_BASE(35, 35, 1, 0x0080, 0x10, 11, 1),
+	PIN_FIELD_BASE(36, 36, 9, 0x0060, 0x10, 8, 1),
+	PIN_FIELD_BASE(37, 37, 2, 0x0070, 0x10, 17, 1),
+	PIN_FIELD_BASE(38, 38, 2, 0x0070, 0x10, 18, 1),
+	PIN_FIELD_BASE(39, 39, 1, 0x0080, 0x10, 12, 1),
+	PIN_FIELD_BASE(40, 40, 2, 0x0070, 0x10, 1, 1),
+	PIN_FIELD_BASE(41, 41, 2, 0x0070, 0x10, 2, 1),
+	PIN_FIELD_BASE(42, 42, 2, 0x0070, 0x10, 3, 1),
+	PIN_FIELD_BASE(43, 43, 2, 0x0070, 0x10, 4, 1),
+	PIN_FIELD_BASE(44, 44, 2, 0x0070, 0x10, 5, 1),
+	PIN_FIELD_BASE(45, 45, 2, 0x0070, 0x10, 6, 1),
+	PIN_FIELD_BASE(46, 46, 1, 0x0080, 0x10, 13, 1),
+	PIN_FIELD_BASE(47, 47, 1, 0x0080, 0x10, 15, 1),
+	PIN_FIELD_BASE(48, 48, 2, 0x0070, 0x10, 7, 1),
+	PIN_FIELD_BASE(49, 49, 2, 0x0070, 0x10, 8, 1),
+	PIN_FIELD_BASE(50, 50, 2, 0x0070, 0x10, 9, 1),
+	PIN_FIELD_BASE(51, 51, 2, 0x0070, 0x10, 10, 1),
+	PIN_FIELD_BASE(52, 52, 2, 0x0070, 0x10, 11, 1),
+	PIN_FIELD_BASE(53, 53, 2, 0x0070, 0x10, 12, 1),
+	PIN_FIELD_BASE(54, 54, 5, 0x0060, 0x10, 10, 1),
+	PIN_FIELD_BASE(55, 55, 5, 0x0060, 0x10, 11, 1),
+	PIN_FIELD_BASE(56, 56, 1, 0x0080, 0x10, 22, 1),
+	PIN_FIELD_BASE(57, 57, 1, 0x0080, 0x10, 23, 1),
+	PIN_FIELD_BASE(58, 58, 1, 0x0080, 0x10, 24, 1),
+	PIN_FIELD_BASE(59, 59, 2, 0x0070, 0x10, 0, 1),
+	PIN_FIELD_BASE(60, 60, 9, 0x0060, 0x10, 1, 1),
+	PIN_FIELD_BASE(61, 61, 9, 0x0060, 0x10, 2, 1),
+	PIN_FIELD_BASE(62, 62, 9, 0x0060, 0x10, 3, 1),
+	PIN_FIELD_BASE(63, 63, 9, 0x0060, 0x10, 4, 1),
+	PIN_FIELD_BASE(64, 64, 9, 0x0060, 0x10, 5, 1),
+	PIN_FIELD_BASE(65, 65, 9, 0x0060, 0x10, 6, 1),
+	PIN_FIELD_BASE(66, 66, 5, 0x0060, 0x10, 0, 1),
+	PIN_FIELD_BASE(67, 67, 5, 0x0060, 0x10, 1, 1),
+	PIN_FIELD_BASE(68, 68, 9, 0x0060, 0x10, 7, 1),
+	PIN_FIELD_BASE(69, 69, 7, 0x0070, 0x10, 0, 1),
+	PIN_FIELD_BASE(70, 70, 7, 0x0070, 0x10, 1, 1),
+	PIN_FIELD_BASE(71, 71, 7, 0x0070, 0x10, 2, 1),
+	PIN_FIELD_BASE(72, 72, 7, 0x0070, 0x10, 3, 1),
+	PIN_FIELD_BASE(73, 73, 7, 0x0070, 0x10, 4, 1),
+	PIN_FIELD_BASE(74, 74, 7, 0x0070, 0x10, 5, 1),
+	PIN_FIELD_BASE(75, 75, 7, 0x0070, 0x10, 6, 1),
+	PIN_FIELD_BASE(76, 76, 7, 0x0070, 0x10, 7, 1),
+	PIN_FIELD_BASE(77, 77, 7, 0x0070, 0x10, 8, 1),
+	PIN_FIELD_BASE(78, 78, 7, 0x0070, 0x10, 9, 1),
+	PIN_FIELD_BASE(79, 79, 7, 0x0070, 0x10, 10, 1),
+	PIN_FIELD_BASE(80, 80, 7, 0x0070, 0x10, 11, 1),
+	PIN_FIELD_BASE(81, 81, 7, 0x0070, 0x10, 12, 1),
+	PIN_FIELD_BASE(82, 82, 7, 0x0070, 0x10, 13, 1),
+	PIN_FIELD_BASE(83, 83, 7, 0x0070, 0x10, 14, 1),
+	PIN_FIELD_BASE(84, 84, 7, 0x0070, 0x10, 15, 1),
+	PIN_FIELD_BASE(85, 85, 7, 0x0070, 0x10, 16, 1),
+	PIN_FIELD_BASE(86, 86, 7, 0x0070, 0x10, 17, 1),
+	PIN_FIELD_BASE(87, 87, 7, 0x0070, 0x10, 18, 1),
+	PIN_FIELD_BASE(88, 88, 7, 0x0070, 0x10, 19, 1),
+	PIN_FIELD_BASE(89, 89, 7, 0x0070, 0x10, 20, 1),
+	PIN_FIELD_BASE(90, 90, 7, 0x0070, 0x10, 21, 1),
+	PIN_FIELD_BASE(91, 91, 7, 0x0070, 0x10, 22, 1),
+	PIN_FIELD_BASE(92, 92, 3, 0x0080, 0x10, 16, 1),
+	PIN_FIELD_BASE(93, 93, 3, 0x0080, 0x10, 17, 1),
+	PIN_FIELD_BASE(94, 94, 3, 0x0080, 0x10, 18, 1),
+	PIN_FIELD_BASE(95, 95, 3, 0x0080, 0x10, 19, 1),
+	PIN_FIELD_BASE(96, 96, 3, 0x0080, 0x10, 20, 1),
+	PIN_FIELD_BASE(97, 97, 3, 0x0080, 0x10, 21, 1),
+	PIN_FIELD_BASE(98, 98, 3, 0x0080, 0x10, 22, 1),
+	PIN_FIELD_BASE(99, 99, 3, 0x0080, 0x10, 23, 1),
+	PIN_FIELD_BASE(100, 100, 3, 0x0080, 0x10, 24, 1),
+	PIN_FIELD_BASE(101, 101, 3, 0x0080, 0x10, 25, 1),
+	PIN_FIELD_BASE(102, 102, 3, 0x0080, 0x10, 26, 1),
+	PIN_FIELD_BASE(103, 103, 3, 0x0080, 0x10, 27, 1),
+	PIN_FIELD_BASE(104, 104, 3, 0x0080, 0x10, 28, 1),
+	PIN_FIELD_BASE(105, 105, 3, 0x0080, 0x10, 29, 1),
+	PIN_FIELD_BASE(106, 106, 8, 0x0050, 0x10, 8, 1),
+	PIN_FIELD_BASE(107, 107, 8, 0x0050, 0x10, 9, 1),
+	PIN_FIELD_BASE(108, 108, 8, 0x0050, 0x10, 10, 1),
+	PIN_FIELD_BASE(109, 109, 8, 0x0050, 0x10, 11, 1),
+	PIN_FIELD_BASE(110, 110, 8, 0x0050, 0x10, 12, 1),
+	PIN_FIELD_BASE(111, 111, 8, 0x0050, 0x10, 13, 1),
+	PIN_FIELD_BASE(112, 112, 5, 0x0060, 0x10, 15, 1),
+	PIN_FIELD_BASE(113, 113, 5, 0x0060, 0x10, 16, 1),
+	PIN_FIELD_BASE(114, 114, 5, 0x0060, 0x10, 17, 1),
+	PIN_FIELD_BASE(115, 115, 5, 0x0060, 0x10, 18, 1),
+	PIN_FIELD_BASE(116, 116, 5, 0x0060, 0x10, 19, 1),
+	PIN_FIELD_BASE(117, 117, 4, 0x0060, 0x10, 8, 1),
+	PIN_FIELD_BASE(118, 118, 4, 0x0060, 0x10, 9, 1),
+	PIN_FIELD_BASE(119, 119, 4, 0x0060, 0x10, 10, 1),
+	PIN_FIELD_BASE(120, 120, 4, 0x0060, 0x10, 11, 1),
+	PIN_FIELD_BASE(121, 121, 4, 0x0060, 0x10, 12, 1),
+	PIN_FIELD_BASE(122, 122, 4, 0x0060, 0x10, 13, 1),
+	PIN_FIELD_BASE(123, 123, 4, 0x0060, 0x10, 14, 1),
+	PIN_FIELD_BASE(124, 124, 4, 0x0060, 0x10, 15, 1),
+	PIN_FIELD_BASE(125, 125, 4, 0x0060, 0x10, 16, 1),
+	PIN_FIELD_BASE(126, 126, 5, 0x0060, 0x10, 6, 1),
+	PIN_FIELD_BASE(127, 127, 5, 0x0060, 0x10, 7, 1),
+	PIN_FIELD_BASE(128, 128, 5, 0x0060, 0x10, 8, 1),
+	PIN_FIELD_BASE(129, 129, 5, 0x0060, 0x10, 9, 1),
+	PIN_FIELD_BASE(130, 130, 4, 0x0060, 0x10, 17, 1),
+	PIN_FIELD_BASE(131, 131, 4, 0x0060, 0x10, 18, 1),
+	PIN_FIELD_BASE(132, 132, 4, 0x0060, 0x10, 19, 1),
+	PIN_FIELD_BASE(133, 133, 4, 0x0060, 0x10, 20, 1),
+	PIN_FIELD_BASE(134, 134, 3, 0x0080, 0x10, 0, 1),
+	PIN_FIELD_BASE(135, 135, 3, 0x0080, 0x10, 1, 1),
+	PIN_FIELD_BASE(136, 136, 3, 0x0080, 0x10, 2, 1),
+	PIN_FIELD_BASE(137, 137, 3, 0x0080, 0x10, 3, 1),
+	PIN_FIELD_BASE(138, 138, 3, 0x0080, 0x10, 4, 1),
+	PIN_FIELD_BASE(139, 139, 3, 0x0080, 0x10, 5, 1),
+	PIN_FIELD_BASE(140, 140, 3, 0x0080, 0x10, 6, 1),
+	PIN_FIELD_BASE(141, 141, 3, 0x0080, 0x10, 7, 1),
+	PIN_FIELD_BASE(142, 142, 3, 0x0080, 0x10, 8, 1),
+	PIN_FIELD_BASE(143, 143, 3, 0x0080, 0x10, 9, 1),
+	PIN_FIELD_BASE(144, 144, 3, 0x0080, 0x10, 10, 1),
+	PIN_FIELD_BASE(145, 145, 3, 0x0080, 0x10, 11, 1),
+	PIN_FIELD_BASE(146, 146, 3, 0x0080, 0x10, 12, 1),
+	PIN_FIELD_BASE(147, 147, 3, 0x0080, 0x10, 13, 1),
+	PIN_FIELD_BASE(148, 148, 3, 0x0080, 0x10, 14, 1),
+	PIN_FIELD_BASE(149, 149, 3, 0x0080, 0x10, 15, 1),
+	PIN_FIELD_BASE(150, 150, 4, 0x0060, 0x10, 21, 1),
+	PIN_FIELD_BASE(151, 151, 4, 0x0060, 0x10, 26, 1),
+	PIN_FIELD_BASE(152, 152, 4, 0x0060, 0x10, 25, 1),
+	PIN_FIELD_BASE(153, 153, 4, 0x0060, 0x10, 24, 1),
+	PIN_FIELD_BASE(154, 154, 4, 0x0060, 0x10, 22, 1),
+	PIN_FIELD_BASE(155, 155, 4, 0x0060, 0x10, 23, 1),
+	PIN_FIELD_BASE(156, 156, 4, 0x0060, 0x10, 0, 1),
+	PIN_FIELD_BASE(157, 157, 4, 0x0060, 0x10, 1, 1),
+	PIN_FIELD_BASE(158, 158, 4, 0x0060, 0x10, 2, 1),
+	PIN_FIELD_BASE(159, 159, 4, 0x0060, 0x10, 3, 1),
+	PIN_FIELD_BASE(160, 160, 4, 0x0060, 0x10, 4, 1),
+	PIN_FIELD_BASE(161, 161, 4, 0x0060, 0x10, 5, 1),
+	PIN_FIELD_BASE(162, 162, 4, 0x0060, 0x10, 6, 1),
+	PIN_FIELD_BASE(163, 163, 4, 0x0060, 0x10, 7, 1),
+	PIN_FIELD_BASE(164, 164, 5, 0x0060, 0x10, 12, 1),
+	PIN_FIELD_BASE(165, 165, 5, 0x0060, 0x10, 3, 1),
+	PIN_FIELD_BASE(166, 166, 5, 0x0060, 0x10, 4, 1),
+	PIN_FIELD_BASE(167, 167, 5, 0x0060, 0x10, 2, 1),
+	PIN_FIELD_BASE(168, 168, 5, 0x0060, 0x10, 13, 1),
+	PIN_FIELD_BASE(169, 169, 5, 0x0060, 0x10, 14, 1),
+	PIN_FIELD_BASE(170, 170, 5, 0x0060, 0x10, 5, 1),
+	PIN_FIELD_BASE(171, 171, 6, 0x0050, 0x10, 0, 1),
+	PIN_FIELD_BASE(172, 172, 6, 0x0050, 0x10, 1, 1),
+	PIN_FIELD_BASE(173, 173, 6, 0x0050, 0x10, 2, 1),
+	PIN_FIELD_BASE(174, 174, 6, 0x0050, 0x10, 3, 1),
+	PIN_FIELD_BASE(175, 175, 6, 0x0050, 0x10, 4, 1),
+	PIN_FIELD_BASE(176, 176, 6, 0x0050, 0x10, 5, 1),
+	PIN_FIELD_BASE(177, 177, 6, 0x0050, 0x10, 6, 1),
+	PIN_FIELD_BASE(178, 178, 6, 0x0050, 0x10, 7, 1),
+	PIN_FIELD_BASE(179, 179, 6, 0x0050, 0x10, 8, 1),
+	PIN_FIELD_BASE(180, 180, 6, 0x0050, 0x10, 9, 1),
+	PIN_FIELD_BASE(181, 181, 10, 0x0020, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8901_pin_pupd_range[] = {
+	PIN_FIELD_BASE(0, 0, 8, 0x0080, 0x10, 0, 1),
+	PIN_FIELD_BASE(1, 1, 8, 0x0080, 0x10, 1, 1),
+	PIN_FIELD_BASE(2, 2, 8, 0x0080, 0x10, 2, 1),
+	PIN_FIELD_BASE(3, 3, 8, 0x0080, 0x10, 3, 1),
+	PIN_FIELD_BASE(4, 4, 8, 0x0080, 0x10, 4, 1),
+	PIN_FIELD_BASE(5, 5, 8, 0x0080, 0x10, 5, 1),
+	PIN_FIELD_BASE(6, 6, 8, 0x0080, 0x10, 6, 1),
+	PIN_FIELD_BASE(7, 7, 8, 0x0080, 0x10, 7, 1),
+	PIN_FIELD_BASE(14, 14, 1, 0x00c0, 0x10, 14, 1),
+	PIN_FIELD_BASE(15, 15, 1, 0x00c0, 0x10, 16, 1),
+	PIN_FIELD_BASE(16, 16, 1, 0x00c0, 0x10, 17, 1),
+	PIN_FIELD_BASE(19, 19, 1, 0x00c0, 0x10, 21, 1),
+	PIN_FIELD_BASE(20, 20, 1, 0x00c0, 0x10, 22, 1),
+	PIN_FIELD_BASE(21, 21, 1, 0x00c0, 0x10, 20, 1),
+	PIN_FIELD_BASE(22, 22, 1, 0x00c0, 0x10, 19, 1),
+	PIN_FIELD_BASE(23, 23, 1, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(24, 24, 1, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(25, 25, 1, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(26, 26, 1, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(27, 27, 1, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(28, 28, 1, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(29, 29, 1, 0x00c0, 0x10, 6, 1),
+	PIN_FIELD_BASE(30, 30, 1, 0x00c0, 0x10, 7, 1),
+	PIN_FIELD_BASE(31, 31, 1, 0x00c0, 0x10, 8, 1),
+	PIN_FIELD_BASE(32, 32, 9, 0x00a0, 0x10, 0, 1),
+	PIN_FIELD_BASE(33, 33, 1, 0x00c0, 0x10, 9, 1),
+	PIN_FIELD_BASE(34, 34, 1, 0x00c0, 0x10, 10, 1),
+	PIN_FIELD_BASE(35, 35, 1, 0x00c0, 0x10, 11, 1),
+	PIN_FIELD_BASE(36, 36, 9, 0x00a0, 0x10, 6, 1),
+	PIN_FIELD_BASE(37, 37, 2, 0x00b0, 0x10, 10, 1),
+	PIN_FIELD_BASE(38, 38, 2, 0x00b0, 0x10, 11, 1),
+	PIN_FIELD_BASE(39, 39, 1, 0x00c0, 0x10, 12, 1),
+	PIN_FIELD_BASE(40, 40, 2, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(41, 41, 2, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(42, 42, 2, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(43, 43, 2, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(44, 44, 2, 0x00b0, 0x10, 4, 1),
+	PIN_FIELD_BASE(45, 45, 2, 0x00b0, 0x10, 5, 1),
+	PIN_FIELD_BASE(46, 46, 1, 0x00c0, 0x10, 13, 1),
+	PIN_FIELD_BASE(47, 47, 1, 0x00c0, 0x10, 15, 1),
+	PIN_FIELD_BASE(48, 48, 2, 0x00b0, 0x10, 6, 1),
+	PIN_FIELD_BASE(49, 49, 2, 0x00b0, 0x10, 7, 1),
+	PIN_FIELD_BASE(50, 50, 2, 0x00b0, 0x10, 8, 1),
+	PIN_FIELD_BASE(51, 51, 2, 0x00b0, 0x10, 9, 1),
+	PIN_FIELD_BASE(58, 58, 1, 0x00c0, 0x10, 18, 1),
+	PIN_FIELD_BASE(62, 62, 9, 0x00a0, 0x10, 1, 1),
+	PIN_FIELD_BASE(63, 63, 9, 0x00a0, 0x10, 2, 1),
+	PIN_FIELD_BASE(64, 64, 9, 0x00a0, 0x10, 3, 1),
+	PIN_FIELD_BASE(65, 65, 9, 0x00a0, 0x10, 4, 1),
+	PIN_FIELD_BASE(68, 68, 9, 0x00a0, 0x10, 5, 1),
+	PIN_FIELD_BASE(74, 74, 7, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(75, 75, 7, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(76, 76, 7, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(77, 77, 7, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(78, 78, 7, 0x00b0, 0x10, 4, 1),
+	PIN_FIELD_BASE(79, 79, 7, 0x00b0, 0x10, 5, 1),
+	PIN_FIELD_BASE(80, 80, 7, 0x00b0, 0x10, 6, 1),
+	PIN_FIELD_BASE(81, 81, 7, 0x00b0, 0x10, 7, 1),
+	PIN_FIELD_BASE(82, 82, 7, 0x00b0, 0x10, 8, 1),
+	PIN_FIELD_BASE(83, 83, 7, 0x00b0, 0x10, 9, 1),
+	PIN_FIELD_BASE(84, 84, 7, 0x00b0, 0x10, 10, 1),
+	PIN_FIELD_BASE(85, 85, 7, 0x00b0, 0x10, 11, 1),
+	PIN_FIELD_BASE(86, 86, 7, 0x00b0, 0x10, 12, 1),
+	PIN_FIELD_BASE(87, 87, 7, 0x00b0, 0x10, 13, 1),
+	PIN_FIELD_BASE(90, 90, 7, 0x00b0, 0x10, 14, 1),
+	PIN_FIELD_BASE(91, 91, 7, 0x00b0, 0x10, 15, 1),
+	PIN_FIELD_BASE(94, 94, 3, 0x00c0, 0x10, 12, 1),
+	PIN_FIELD_BASE(95, 95, 3, 0x00c0, 0x10, 13, 1),
+	PIN_FIELD_BASE(96, 96, 3, 0x00c0, 0x10, 14, 1),
+	PIN_FIELD_BASE(97, 97, 3, 0x00c0, 0x10, 15, 1),
+	PIN_FIELD_BASE(98, 98, 3, 0x00c0, 0x10, 16, 1),
+	PIN_FIELD_BASE(99, 99, 3, 0x00c0, 0x10, 17, 1),
+	PIN_FIELD_BASE(100, 100, 3, 0x00c0, 0x10, 18, 1),
+	PIN_FIELD_BASE(101, 101, 3, 0x00c0, 0x10, 19, 1),
+	PIN_FIELD_BASE(102, 102, 3, 0x00c0, 0x10, 20, 1),
+	PIN_FIELD_BASE(103, 103, 3, 0x00c0, 0x10, 21, 1),
+	PIN_FIELD_BASE(104, 104, 3, 0x00c0, 0x10, 22, 1),
+	PIN_FIELD_BASE(105, 105, 3, 0x00c0, 0x10, 23, 1),
+	PIN_FIELD_BASE(106, 106, 8, 0x0080, 0x10, 8, 1),
+	PIN_FIELD_BASE(107, 107, 8, 0x0080, 0x10, 9, 1),
+	PIN_FIELD_BASE(108, 108, 8, 0x0080, 0x10, 10, 1),
+	PIN_FIELD_BASE(109, 109, 8, 0x0080, 0x10, 11, 1),
+	PIN_FIELD_BASE(110, 110, 8, 0x0080, 0x10, 12, 1),
+	PIN_FIELD_BASE(111, 111, 8, 0x0080, 0x10, 13, 1),
+	PIN_FIELD_BASE(112, 112, 5, 0x00a0, 0x10, 5, 1),
+	PIN_FIELD_BASE(113, 113, 5, 0x00a0, 0x10, 6, 1),
+	PIN_FIELD_BASE(114, 114, 5, 0x00a0, 0x10, 7, 1),
+	PIN_FIELD_BASE(115, 115, 5, 0x00a0, 0x10, 8, 1),
+	PIN_FIELD_BASE(116, 116, 5, 0x00a0, 0x10, 9, 1),
+	PIN_FIELD_BASE(125, 125, 4, 0x00a0, 0x10, 8, 1),
+	PIN_FIELD_BASE(130, 130, 4, 0x00a0, 0x10, 9, 1),
+	PIN_FIELD_BASE(131, 131, 4, 0x00a0, 0x10, 10, 1),
+	PIN_FIELD_BASE(132, 132, 4, 0x00a0, 0x10, 11, 1),
+	PIN_FIELD_BASE(133, 133, 4, 0x00a0, 0x10, 12, 1),
+	PIN_FIELD_BASE(138, 138, 3, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(139, 139, 3, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(140, 140, 3, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(141, 141, 3, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(142, 142, 3, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(143, 143, 3, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(144, 144, 3, 0x00c0, 0x10, 6, 1),
+	PIN_FIELD_BASE(145, 145, 3, 0x00c0, 0x10, 7, 1),
+	PIN_FIELD_BASE(146, 146, 3, 0x00c0, 0x10, 8, 1),
+	PIN_FIELD_BASE(147, 147, 3, 0x00c0, 0x10, 9, 1),
+	PIN_FIELD_BASE(148, 148, 3, 0x00c0, 0x10, 10, 1),
+	PIN_FIELD_BASE(149, 149, 3, 0x00c0, 0x10, 11, 1),
+	PIN_FIELD_BASE(150, 150, 4, 0x00a0, 0x10, 13, 1),
+	PIN_FIELD_BASE(151, 151, 4, 0x00a0, 0x10, 18, 1),
+	PIN_FIELD_BASE(152, 152, 4, 0x00a0, 0x10, 17, 1),
+	PIN_FIELD_BASE(153, 153, 4, 0x00a0, 0x10, 16, 1),
+	PIN_FIELD_BASE(154, 154, 4, 0x00a0, 0x10, 14, 1),
+	PIN_FIELD_BASE(155, 155, 4, 0x00a0, 0x10, 15, 1),
+	PIN_FIELD_BASE(156, 156, 4, 0x00a0, 0x10, 0, 1),
+	PIN_FIELD_BASE(157, 157, 4, 0x00a0, 0x10, 1, 1),
+	PIN_FIELD_BASE(158, 158, 4, 0x00a0, 0x10, 2, 1),
+	PIN_FIELD_BASE(159, 159, 4, 0x00a0, 0x10, 3, 1),
+	PIN_FIELD_BASE(160, 160, 4, 0x00a0, 0x10, 4, 1),
+	PIN_FIELD_BASE(161, 161, 4, 0x00a0, 0x10, 5, 1),
+	PIN_FIELD_BASE(162, 162, 4, 0x00a0, 0x10, 6, 1),
+	PIN_FIELD_BASE(163, 163, 4, 0x00a0, 0x10, 7, 1),
+	PIN_FIELD_BASE(164, 164, 5, 0x00a0, 0x10, 2, 1),
+	PIN_FIELD_BASE(167, 167, 5, 0x00a0, 0x10, 0, 1),
+	PIN_FIELD_BASE(168, 168, 5, 0x00a0, 0x10, 3, 1),
+	PIN_FIELD_BASE(169, 169, 5, 0x00a0, 0x10, 4, 1),
+	PIN_FIELD_BASE(170, 170, 5, 0x00a0, 0x10, 1, 1),
+	PIN_FIELD_BASE(171, 171, 6, 0x0080, 0x10, 0, 1),
+	PIN_FIELD_BASE(172, 172, 6, 0x0080, 0x10, 1, 1),
+	PIN_FIELD_BASE(173, 173, 6, 0x0080, 0x10, 2, 1),
+	PIN_FIELD_BASE(174, 174, 6, 0x0080, 0x10, 3, 1),
+	PIN_FIELD_BASE(175, 175, 6, 0x0080, 0x10, 4, 1),
+	PIN_FIELD_BASE(176, 176, 6, 0x0080, 0x10, 5, 1),
+	PIN_FIELD_BASE(177, 177, 6, 0x0080, 0x10, 6, 1),
+	PIN_FIELD_BASE(178, 178, 6, 0x0080, 0x10, 7, 1),
+	PIN_FIELD_BASE(179, 179, 6, 0x0080, 0x10, 8, 1),
+	PIN_FIELD_BASE(180, 180, 6, 0x0080, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt8901_pin_r0_range[] = {
+	PIN_FIELD_BASE(0, 0, 8, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(1, 1, 8, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(2, 2, 8, 0x0090, 0x10, 2, 1),
+	PIN_FIELD_BASE(3, 3, 8, 0x0090, 0x10, 3, 1),
+	PIN_FIELD_BASE(4, 4, 8, 0x0090, 0x10, 4, 1),
+	PIN_FIELD_BASE(5, 5, 8, 0x0090, 0x10, 5, 1),
+	PIN_FIELD_BASE(6, 6, 8, 0x0090, 0x10, 6, 1),
+	PIN_FIELD_BASE(7, 7, 8, 0x0090, 0x10, 7, 1),
+	PIN_FIELD_BASE(14, 14, 1, 0x00e0, 0x10, 14, 1),
+	PIN_FIELD_BASE(15, 15, 1, 0x00e0, 0x10, 16, 1),
+	PIN_FIELD_BASE(16, 16, 1, 0x00e0, 0x10, 17, 1),
+	PIN_FIELD_BASE(19, 19, 1, 0x00e0, 0x10, 21, 1),
+	PIN_FIELD_BASE(20, 20, 1, 0x00e0, 0x10, 22, 1),
+	PIN_FIELD_BASE(21, 21, 1, 0x00e0, 0x10, 20, 1),
+	PIN_FIELD_BASE(22, 22, 1, 0x00e0, 0x10, 19, 1),
+	PIN_FIELD_BASE(23, 23, 1, 0x00e0, 0x10, 0, 1),
+	PIN_FIELD_BASE(24, 24, 1, 0x00e0, 0x10, 1, 1),
+	PIN_FIELD_BASE(25, 25, 1, 0x00e0, 0x10, 2, 1),
+	PIN_FIELD_BASE(26, 26, 1, 0x00e0, 0x10, 3, 1),
+	PIN_FIELD_BASE(27, 27, 1, 0x00e0, 0x10, 4, 1),
+	PIN_FIELD_BASE(28, 28, 1, 0x00e0, 0x10, 5, 1),
+	PIN_FIELD_BASE(29, 29, 1, 0x00e0, 0x10, 6, 1),
+	PIN_FIELD_BASE(30, 30, 1, 0x00e0, 0x10, 7, 1),
+	PIN_FIELD_BASE(31, 31, 1, 0x00e0, 0x10, 8, 1),
+	PIN_FIELD_BASE(32, 32, 9, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(33, 33, 1, 0x00e0, 0x10, 9, 1),
+	PIN_FIELD_BASE(34, 34, 1, 0x00e0, 0x10, 10, 1),
+	PIN_FIELD_BASE(35, 35, 1, 0x00e0, 0x10, 11, 1),
+	PIN_FIELD_BASE(36, 36, 9, 0x00c0, 0x10, 6, 1),
+	PIN_FIELD_BASE(37, 37, 2, 0x00d0, 0x10, 10, 1),
+	PIN_FIELD_BASE(38, 38, 2, 0x00d0, 0x10, 11, 1),
+	PIN_FIELD_BASE(39, 39, 1, 0x00e0, 0x10, 12, 1),
+	PIN_FIELD_BASE(40, 40, 2, 0x00d0, 0x10, 0, 1),
+	PIN_FIELD_BASE(41, 41, 2, 0x00d0, 0x10, 1, 1),
+	PIN_FIELD_BASE(42, 42, 2, 0x00d0, 0x10, 2, 1),
+	PIN_FIELD_BASE(43, 43, 2, 0x00d0, 0x10, 3, 1),
+	PIN_FIELD_BASE(44, 44, 2, 0x00d0, 0x10, 4, 1),
+	PIN_FIELD_BASE(45, 45, 2, 0x00d0, 0x10, 5, 1),
+	PIN_FIELD_BASE(46, 46, 1, 0x00e0, 0x10, 13, 1),
+	PIN_FIELD_BASE(47, 47, 1, 0x00e0, 0x10, 15, 1),
+	PIN_FIELD_BASE(48, 48, 2, 0x00d0, 0x10, 6, 1),
+	PIN_FIELD_BASE(49, 49, 2, 0x00d0, 0x10, 7, 1),
+	PIN_FIELD_BASE(50, 50, 2, 0x00d0, 0x10, 8, 1),
+	PIN_FIELD_BASE(51, 51, 2, 0x00d0, 0x10, 9, 1),
+	PIN_FIELD_BASE(58, 58, 1, 0x00e0, 0x10, 18, 1),
+	PIN_FIELD_BASE(62, 62, 9, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(63, 63, 9, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(64, 64, 9, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(65, 65, 9, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(68, 68, 9, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(74, 74, 7, 0x00d0, 0x10, 0, 1),
+	PIN_FIELD_BASE(75, 75, 7, 0x00d0, 0x10, 1, 1),
+	PIN_FIELD_BASE(76, 76, 7, 0x00d0, 0x10, 2, 1),
+	PIN_FIELD_BASE(77, 77, 7, 0x00d0, 0x10, 3, 1),
+	PIN_FIELD_BASE(78, 78, 7, 0x00d0, 0x10, 4, 1),
+	PIN_FIELD_BASE(79, 79, 7, 0x00d0, 0x10, 5, 1),
+	PIN_FIELD_BASE(80, 80, 7, 0x00d0, 0x10, 6, 1),
+	PIN_FIELD_BASE(81, 81, 7, 0x00d0, 0x10, 7, 1),
+	PIN_FIELD_BASE(82, 82, 7, 0x00d0, 0x10, 8, 1),
+	PIN_FIELD_BASE(83, 83, 7, 0x00d0, 0x10, 9, 1),
+	PIN_FIELD_BASE(84, 84, 7, 0x00d0, 0x10, 10, 1),
+	PIN_FIELD_BASE(85, 85, 7, 0x00d0, 0x10, 11, 1),
+	PIN_FIELD_BASE(86, 86, 7, 0x00d0, 0x10, 12, 1),
+	PIN_FIELD_BASE(87, 87, 7, 0x00d0, 0x10, 13, 1),
+	PIN_FIELD_BASE(90, 90, 7, 0x00d0, 0x10, 14, 1),
+	PIN_FIELD_BASE(91, 91, 7, 0x00d0, 0x10, 15, 1),
+	PIN_FIELD_BASE(94, 94, 3, 0x00e0, 0x10, 12, 1),
+	PIN_FIELD_BASE(95, 95, 3, 0x00e0, 0x10, 13, 1),
+	PIN_FIELD_BASE(96, 96, 3, 0x00e0, 0x10, 14, 1),
+	PIN_FIELD_BASE(97, 97, 3, 0x00e0, 0x10, 15, 1),
+	PIN_FIELD_BASE(98, 98, 3, 0x00e0, 0x10, 16, 1),
+	PIN_FIELD_BASE(99, 99, 3, 0x00e0, 0x10, 17, 1),
+	PIN_FIELD_BASE(100, 100, 3, 0x00e0, 0x10, 18, 1),
+	PIN_FIELD_BASE(101, 101, 3, 0x00e0, 0x10, 19, 1),
+	PIN_FIELD_BASE(102, 102, 3, 0x00e0, 0x10, 20, 1),
+	PIN_FIELD_BASE(103, 103, 3, 0x00e0, 0x10, 21, 1),
+	PIN_FIELD_BASE(104, 104, 3, 0x00e0, 0x10, 22, 1),
+	PIN_FIELD_BASE(105, 105, 3, 0x00e0, 0x10, 23, 1),
+	PIN_FIELD_BASE(106, 106, 8, 0x0090, 0x10, 8, 1),
+	PIN_FIELD_BASE(107, 107, 8, 0x0090, 0x10, 9, 1),
+	PIN_FIELD_BASE(108, 108, 8, 0x0090, 0x10, 10, 1),
+	PIN_FIELD_BASE(109, 109, 8, 0x0090, 0x10, 11, 1),
+	PIN_FIELD_BASE(110, 110, 8, 0x0090, 0x10, 12, 1),
+	PIN_FIELD_BASE(111, 111, 8, 0x0090, 0x10, 13, 1),
+	PIN_FIELD_BASE(112, 112, 5, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(113, 113, 5, 0x00c0, 0x10, 6, 1),
+	PIN_FIELD_BASE(114, 114, 5, 0x00c0, 0x10, 7, 1),
+	PIN_FIELD_BASE(115, 115, 5, 0x00c0, 0x10, 8, 1),
+	PIN_FIELD_BASE(116, 116, 5, 0x00c0, 0x10, 9, 1),
+	PIN_FIELD_BASE(125, 125, 4, 0x00c0, 0x10, 8, 1),
+	PIN_FIELD_BASE(130, 130, 4, 0x00c0, 0x10, 9, 1),
+	PIN_FIELD_BASE(131, 131, 4, 0x00c0, 0x10, 10, 1),
+	PIN_FIELD_BASE(132, 132, 4, 0x00c0, 0x10, 11, 1),
+	PIN_FIELD_BASE(133, 133, 4, 0x00c0, 0x10, 12, 1),
+	PIN_FIELD_BASE(138, 138, 3, 0x00e0, 0x10, 0, 1),
+	PIN_FIELD_BASE(139, 139, 3, 0x00e0, 0x10, 1, 1),
+	PIN_FIELD_BASE(140, 140, 3, 0x00e0, 0x10, 2, 1),
+	PIN_FIELD_BASE(141, 141, 3, 0x00e0, 0x10, 3, 1),
+	PIN_FIELD_BASE(142, 142, 3, 0x00e0, 0x10, 4, 1),
+	PIN_FIELD_BASE(143, 143, 3, 0x00e0, 0x10, 5, 1),
+	PIN_FIELD_BASE(144, 144, 3, 0x00e0, 0x10, 6, 1),
+	PIN_FIELD_BASE(145, 145, 3, 0x00e0, 0x10, 7, 1),
+	PIN_FIELD_BASE(146, 146, 3, 0x00e0, 0x10, 8, 1),
+	PIN_FIELD_BASE(147, 147, 3, 0x00e0, 0x10, 9, 1),
+	PIN_FIELD_BASE(148, 148, 3, 0x00e0, 0x10, 10, 1),
+	PIN_FIELD_BASE(149, 149, 3, 0x00e0, 0x10, 11, 1),
+	PIN_FIELD_BASE(150, 150, 4, 0x00c0, 0x10, 13, 1),
+	PIN_FIELD_BASE(151, 151, 4, 0x00c0, 0x10, 18, 1),
+	PIN_FIELD_BASE(152, 152, 4, 0x00c0, 0x10, 17, 1),
+	PIN_FIELD_BASE(153, 153, 4, 0x00c0, 0x10, 16, 1),
+	PIN_FIELD_BASE(154, 154, 4, 0x00c0, 0x10, 14, 1),
+	PIN_FIELD_BASE(155, 155, 4, 0x00c0, 0x10, 15, 1),
+	PIN_FIELD_BASE(156, 156, 4, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(157, 157, 4, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(158, 158, 4, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(159, 159, 4, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(160, 160, 4, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(161, 161, 4, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(162, 162, 4, 0x00c0, 0x10, 6, 1),
+	PIN_FIELD_BASE(163, 163, 4, 0x00c0, 0x10, 7, 1),
+	PIN_FIELD_BASE(164, 164, 5, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(167, 167, 5, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(168, 168, 5, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(169, 169, 5, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(170, 170, 5, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(171, 171, 6, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(172, 172, 6, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(173, 173, 6, 0x0090, 0x10, 2, 1),
+	PIN_FIELD_BASE(174, 174, 6, 0x0090, 0x10, 3, 1),
+	PIN_FIELD_BASE(175, 175, 6, 0x0090, 0x10, 4, 1),
+	PIN_FIELD_BASE(176, 176, 6, 0x0090, 0x10, 5, 1),
+	PIN_FIELD_BASE(177, 177, 6, 0x0090, 0x10, 6, 1),
+	PIN_FIELD_BASE(178, 178, 6, 0x0090, 0x10, 7, 1),
+	PIN_FIELD_BASE(179, 179, 6, 0x0090, 0x10, 8, 1),
+	PIN_FIELD_BASE(180, 180, 6, 0x0090, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt8901_pin_r1_range[] = {
+	PIN_FIELD_BASE(0, 0, 8, 0x00a0, 0x10, 0, 1),
+	PIN_FIELD_BASE(1, 1, 8, 0x00a0, 0x10, 1, 1),
+	PIN_FIELD_BASE(2, 2, 8, 0x00a0, 0x10, 2, 1),
+	PIN_FIELD_BASE(3, 3, 8, 0x00a0, 0x10, 3, 1),
+	PIN_FIELD_BASE(4, 4, 8, 0x00a0, 0x10, 4, 1),
+	PIN_FIELD_BASE(5, 5, 8, 0x00a0, 0x10, 5, 1),
+	PIN_FIELD_BASE(6, 6, 8, 0x00a0, 0x10, 6, 1),
+	PIN_FIELD_BASE(7, 7, 8, 0x00a0, 0x10, 7, 1),
+	PIN_FIELD_BASE(14, 14, 1, 0x00f0, 0x10, 14, 1),
+	PIN_FIELD_BASE(15, 15, 1, 0x00f0, 0x10, 16, 1),
+	PIN_FIELD_BASE(16, 16, 1, 0x00f0, 0x10, 17, 1),
+	PIN_FIELD_BASE(19, 19, 1, 0x00f0, 0x10, 21, 1),
+	PIN_FIELD_BASE(20, 20, 1, 0x00f0, 0x10, 22, 1),
+	PIN_FIELD_BASE(21, 21, 1, 0x00f0, 0x10, 20, 1),
+	PIN_FIELD_BASE(22, 22, 1, 0x00f0, 0x10, 19, 1),
+	PIN_FIELD_BASE(23, 23, 1, 0x00f0, 0x10, 0, 1),
+	PIN_FIELD_BASE(24, 24, 1, 0x00f0, 0x10, 1, 1),
+	PIN_FIELD_BASE(25, 25, 1, 0x00f0, 0x10, 2, 1),
+	PIN_FIELD_BASE(26, 26, 1, 0x00f0, 0x10, 3, 1),
+	PIN_FIELD_BASE(27, 27, 1, 0x00f0, 0x10, 4, 1),
+	PIN_FIELD_BASE(28, 28, 1, 0x00f0, 0x10, 5, 1),
+	PIN_FIELD_BASE(29, 29, 1, 0x00f0, 0x10, 6, 1),
+	PIN_FIELD_BASE(30, 30, 1, 0x00f0, 0x10, 7, 1),
+	PIN_FIELD_BASE(31, 31, 1, 0x00f0, 0x10, 8, 1),
+	PIN_FIELD_BASE(32, 32, 9, 0x00d0, 0x10, 0, 1),
+	PIN_FIELD_BASE(33, 33, 1, 0x00f0, 0x10, 9, 1),
+	PIN_FIELD_BASE(34, 34, 1, 0x00f0, 0x10, 10, 1),
+	PIN_FIELD_BASE(35, 35, 1, 0x00f0, 0x10, 11, 1),
+	PIN_FIELD_BASE(36, 36, 9, 0x00d0, 0x10, 6, 1),
+	PIN_FIELD_BASE(37, 37, 2, 0x00e0, 0x10, 10, 1),
+	PIN_FIELD_BASE(38, 38, 2, 0x00e0, 0x10, 11, 1),
+	PIN_FIELD_BASE(39, 39, 1, 0x00f0, 0x10, 12, 1),
+	PIN_FIELD_BASE(40, 40, 2, 0x00e0, 0x10, 0, 1),
+	PIN_FIELD_BASE(41, 41, 2, 0x00e0, 0x10, 1, 1),
+	PIN_FIELD_BASE(42, 42, 2, 0x00e0, 0x10, 2, 1),
+	PIN_FIELD_BASE(43, 43, 2, 0x00e0, 0x10, 3, 1),
+	PIN_FIELD_BASE(44, 44, 2, 0x00e0, 0x10, 4, 1),
+	PIN_FIELD_BASE(45, 45, 2, 0x00e0, 0x10, 5, 1),
+	PIN_FIELD_BASE(46, 46, 1, 0x00f0, 0x10, 13, 1),
+	PIN_FIELD_BASE(47, 47, 1, 0x00f0, 0x10, 15, 1),
+	PIN_FIELD_BASE(48, 48, 2, 0x00e0, 0x10, 6, 1),
+	PIN_FIELD_BASE(49, 49, 2, 0x00e0, 0x10, 7, 1),
+	PIN_FIELD_BASE(50, 50, 2, 0x00e0, 0x10, 8, 1),
+	PIN_FIELD_BASE(51, 51, 2, 0x00e0, 0x10, 9, 1),
+	PIN_FIELD_BASE(58, 58, 1, 0x00f0, 0x10, 18, 1),
+	PIN_FIELD_BASE(62, 62, 9, 0x00d0, 0x10, 1, 1),
+	PIN_FIELD_BASE(63, 63, 9, 0x00d0, 0x10, 2, 1),
+	PIN_FIELD_BASE(64, 64, 9, 0x00d0, 0x10, 3, 1),
+	PIN_FIELD_BASE(65, 65, 9, 0x00d0, 0x10, 4, 1),
+	PIN_FIELD_BASE(68, 68, 9, 0x00d0, 0x10, 5, 1),
+	PIN_FIELD_BASE(74, 74, 7, 0x00e0, 0x10, 0, 1),
+	PIN_FIELD_BASE(75, 75, 7, 0x00e0, 0x10, 1, 1),
+	PIN_FIELD_BASE(76, 76, 7, 0x00e0, 0x10, 2, 1),
+	PIN_FIELD_BASE(77, 77, 7, 0x00e0, 0x10, 3, 1),
+	PIN_FIELD_BASE(78, 78, 7, 0x00e0, 0x10, 4, 1),
+	PIN_FIELD_BASE(79, 79, 7, 0x00e0, 0x10, 5, 1),
+	PIN_FIELD_BASE(80, 80, 7, 0x00e0, 0x10, 6, 1),
+	PIN_FIELD_BASE(81, 81, 7, 0x00e0, 0x10, 7, 1),
+	PIN_FIELD_BASE(82, 82, 7, 0x00e0, 0x10, 8, 1),
+	PIN_FIELD_BASE(83, 83, 7, 0x00e0, 0x10, 9, 1),
+	PIN_FIELD_BASE(84, 84, 7, 0x00e0, 0x10, 10, 1),
+	PIN_FIELD_BASE(85, 85, 7, 0x00e0, 0x10, 11, 1),
+	PIN_FIELD_BASE(86, 86, 7, 0x00e0, 0x10, 12, 1),
+	PIN_FIELD_BASE(87, 87, 7, 0x00e0, 0x10, 13, 1),
+	PIN_FIELD_BASE(90, 90, 7, 0x00e0, 0x10, 14, 1),
+	PIN_FIELD_BASE(91, 91, 7, 0x00e0, 0x10, 15, 1),
+	PIN_FIELD_BASE(94, 94, 3, 0x00f0, 0x10, 12, 1),
+	PIN_FIELD_BASE(95, 95, 3, 0x00f0, 0x10, 13, 1),
+	PIN_FIELD_BASE(96, 96, 3, 0x00f0, 0x10, 14, 1),
+	PIN_FIELD_BASE(97, 97, 3, 0x00f0, 0x10, 15, 1),
+	PIN_FIELD_BASE(98, 98, 3, 0x00f0, 0x10, 16, 1),
+	PIN_FIELD_BASE(99, 99, 3, 0x00f0, 0x10, 17, 1),
+	PIN_FIELD_BASE(100, 100, 3, 0x00f0, 0x10, 18, 1),
+	PIN_FIELD_BASE(101, 101, 3, 0x00f0, 0x10, 19, 1),
+	PIN_FIELD_BASE(102, 102, 3, 0x00f0, 0x10, 20, 1),
+	PIN_FIELD_BASE(103, 103, 3, 0x00f0, 0x10, 21, 1),
+	PIN_FIELD_BASE(104, 104, 3, 0x00f0, 0x10, 22, 1),
+	PIN_FIELD_BASE(105, 105, 3, 0x00f0, 0x10, 23, 1),
+	PIN_FIELD_BASE(106, 106, 8, 0x00a0, 0x10, 8, 1),
+	PIN_FIELD_BASE(107, 107, 8, 0x00a0, 0x10, 9, 1),
+	PIN_FIELD_BASE(108, 108, 8, 0x00a0, 0x10, 10, 1),
+	PIN_FIELD_BASE(109, 109, 8, 0x00a0, 0x10, 11, 1),
+	PIN_FIELD_BASE(110, 110, 8, 0x00a0, 0x10, 12, 1),
+	PIN_FIELD_BASE(111, 111, 8, 0x00a0, 0x10, 13, 1),
+	PIN_FIELD_BASE(112, 112, 5, 0x00d0, 0x10, 5, 1),
+	PIN_FIELD_BASE(113, 113, 5, 0x00d0, 0x10, 6, 1),
+	PIN_FIELD_BASE(114, 114, 5, 0x00d0, 0x10, 7, 1),
+	PIN_FIELD_BASE(115, 115, 5, 0x00d0, 0x10, 8, 1),
+	PIN_FIELD_BASE(116, 116, 5, 0x00d0, 0x10, 9, 1),
+	PIN_FIELD_BASE(125, 125, 4, 0x00d0, 0x10, 8, 1),
+	PIN_FIELD_BASE(130, 130, 4, 0x00d0, 0x10, 9, 1),
+	PIN_FIELD_BASE(131, 131, 4, 0x00d0, 0x10, 10, 1),
+	PIN_FIELD_BASE(132, 132, 4, 0x00d0, 0x10, 11, 1),
+	PIN_FIELD_BASE(133, 133, 4, 0x00d0, 0x10, 12, 1),
+	PIN_FIELD_BASE(138, 138, 3, 0x00f0, 0x10, 0, 1),
+	PIN_FIELD_BASE(139, 139, 3, 0x00f0, 0x10, 1, 1),
+	PIN_FIELD_BASE(140, 140, 3, 0x00f0, 0x10, 2, 1),
+	PIN_FIELD_BASE(141, 141, 3, 0x00f0, 0x10, 3, 1),
+	PIN_FIELD_BASE(142, 142, 3, 0x00f0, 0x10, 4, 1),
+	PIN_FIELD_BASE(143, 143, 3, 0x00f0, 0x10, 5, 1),
+	PIN_FIELD_BASE(144, 144, 3, 0x00f0, 0x10, 6, 1),
+	PIN_FIELD_BASE(145, 145, 3, 0x00f0, 0x10, 7, 1),
+	PIN_FIELD_BASE(146, 146, 3, 0x00f0, 0x10, 8, 1),
+	PIN_FIELD_BASE(147, 147, 3, 0x00f0, 0x10, 9, 1),
+	PIN_FIELD_BASE(148, 148, 3, 0x00f0, 0x10, 10, 1),
+	PIN_FIELD_BASE(149, 149, 3, 0x00f0, 0x10, 11, 1),
+	PIN_FIELD_BASE(150, 150, 4, 0x00d0, 0x10, 13, 1),
+	PIN_FIELD_BASE(151, 151, 4, 0x00d0, 0x10, 18, 1),
+	PIN_FIELD_BASE(152, 152, 4, 0x00d0, 0x10, 17, 1),
+	PIN_FIELD_BASE(153, 153, 4, 0x00d0, 0x10, 16, 1),
+	PIN_FIELD_BASE(154, 154, 4, 0x00d0, 0x10, 14, 1),
+	PIN_FIELD_BASE(155, 155, 4, 0x00d0, 0x10, 15, 1),
+	PIN_FIELD_BASE(156, 156, 4, 0x00d0, 0x10, 0, 1),
+	PIN_FIELD_BASE(157, 157, 4, 0x00d0, 0x10, 1, 1),
+	PIN_FIELD_BASE(158, 158, 4, 0x00d0, 0x10, 2, 1),
+	PIN_FIELD_BASE(159, 159, 4, 0x00d0, 0x10, 3, 1),
+	PIN_FIELD_BASE(160, 160, 4, 0x00d0, 0x10, 4, 1),
+	PIN_FIELD_BASE(161, 161, 4, 0x00d0, 0x10, 5, 1),
+	PIN_FIELD_BASE(162, 162, 4, 0x00d0, 0x10, 6, 1),
+	PIN_FIELD_BASE(163, 163, 4, 0x00d0, 0x10, 7, 1),
+	PIN_FIELD_BASE(164, 164, 5, 0x00d0, 0x10, 2, 1),
+	PIN_FIELD_BASE(167, 167, 5, 0x00d0, 0x10, 0, 1),
+	PIN_FIELD_BASE(168, 168, 5, 0x00d0, 0x10, 3, 1),
+	PIN_FIELD_BASE(169, 169, 5, 0x00d0, 0x10, 4, 1),
+	PIN_FIELD_BASE(170, 170, 5, 0x00d0, 0x10, 1, 1),
+	PIN_FIELD_BASE(171, 171, 6, 0x00a0, 0x10, 0, 1),
+	PIN_FIELD_BASE(172, 172, 6, 0x00a0, 0x10, 1, 1),
+	PIN_FIELD_BASE(173, 173, 6, 0x00a0, 0x10, 2, 1),
+	PIN_FIELD_BASE(174, 174, 6, 0x00a0, 0x10, 3, 1),
+	PIN_FIELD_BASE(175, 175, 6, 0x00a0, 0x10, 4, 1),
+	PIN_FIELD_BASE(176, 176, 6, 0x00a0, 0x10, 5, 1),
+	PIN_FIELD_BASE(177, 177, 6, 0x00a0, 0x10, 6, 1),
+	PIN_FIELD_BASE(178, 178, 6, 0x00a0, 0x10, 7, 1),
+	PIN_FIELD_BASE(179, 179, 6, 0x00a0, 0x10, 8, 1),
+	PIN_FIELD_BASE(180, 180, 6, 0x00a0, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt8901_pin_pu_range[] = {
+	PIN_FIELD_BASE(8, 8, 2, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(9, 9, 2, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(10, 10, 2, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(11, 11, 2, 0x00c0, 0x10, 6, 1),
+	PIN_FIELD_BASE(12, 12, 1, 0x00d0, 0x10, 0, 1),
+	PIN_FIELD_BASE(13, 13, 1, 0x00d0, 0x10, 1, 1),
+	PIN_FIELD_BASE(17, 17, 1, 0x00d0, 0x10, 2, 1),
+	PIN_FIELD_BASE(18, 18, 1, 0x00d0, 0x10, 3, 1),
+	PIN_FIELD_BASE(52, 52, 2, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(53, 53, 2, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(54, 54, 5, 0x00b0, 0x10, 8, 1),
+	PIN_FIELD_BASE(55, 55, 5, 0x00b0, 0x10, 9, 1),
+	PIN_FIELD_BASE(56, 56, 1, 0x00d0, 0x10, 4, 1),
+	PIN_FIELD_BASE(57, 57, 1, 0x00d0, 0x10, 5, 1),
+	PIN_FIELD_BASE(59, 59, 2, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(60, 60, 9, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(61, 61, 9, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(66, 66, 5, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(67, 67, 5, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(69, 69, 7, 0x00c0, 0x10, 0, 1),
+	PIN_FIELD_BASE(70, 70, 7, 0x00c0, 0x10, 1, 1),
+	PIN_FIELD_BASE(71, 71, 7, 0x00c0, 0x10, 2, 1),
+	PIN_FIELD_BASE(72, 72, 7, 0x00c0, 0x10, 3, 1),
+	PIN_FIELD_BASE(73, 73, 7, 0x00c0, 0x10, 4, 1),
+	PIN_FIELD_BASE(88, 88, 7, 0x00c0, 0x10, 5, 1),
+	PIN_FIELD_BASE(89, 89, 7, 0x00c0, 0x10, 6, 1),
+	PIN_FIELD_BASE(92, 92, 3, 0x00d0, 0x10, 4, 1),
+	PIN_FIELD_BASE(93, 93, 3, 0x00d0, 0x10, 5, 1),
+	PIN_FIELD_BASE(117, 117, 4, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(118, 118, 4, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(119, 119, 4, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(120, 120, 4, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(121, 121, 4, 0x00b0, 0x10, 4, 1),
+	PIN_FIELD_BASE(122, 122, 4, 0x00b0, 0x10, 5, 1),
+	PIN_FIELD_BASE(123, 123, 4, 0x00b0, 0x10, 6, 1),
+	PIN_FIELD_BASE(124, 124, 4, 0x00b0, 0x10, 7, 1),
+	PIN_FIELD_BASE(126, 126, 5, 0x00b0, 0x10, 4, 1),
+	PIN_FIELD_BASE(127, 127, 5, 0x00b0, 0x10, 5, 1),
+	PIN_FIELD_BASE(128, 128, 5, 0x00b0, 0x10, 6, 1),
+	PIN_FIELD_BASE(129, 129, 5, 0x00b0, 0x10, 7, 1),
+	PIN_FIELD_BASE(134, 134, 3, 0x00d0, 0x10, 0, 1),
+	PIN_FIELD_BASE(135, 135, 3, 0x00d0, 0x10, 1, 1),
+	PIN_FIELD_BASE(136, 136, 3, 0x00d0, 0x10, 2, 1),
+	PIN_FIELD_BASE(137, 137, 3, 0x00d0, 0x10, 3, 1),
+	PIN_FIELD_BASE(165, 165, 5, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(166, 166, 5, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(181, 181, 10, 0x0060, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8901_pin_pd_range[] = {
+	PIN_FIELD_BASE(8, 8, 2, 0x00a0, 0x10, 3, 1),
+	PIN_FIELD_BASE(9, 9, 2, 0x00a0, 0x10, 4, 1),
+	PIN_FIELD_BASE(10, 10, 2, 0x00a0, 0x10, 5, 1),
+	PIN_FIELD_BASE(11, 11, 2, 0x00a0, 0x10, 6, 1),
+	PIN_FIELD_BASE(12, 12, 1, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(13, 13, 1, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(17, 17, 1, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(18, 18, 1, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(52, 52, 2, 0x00a0, 0x10, 1, 1),
+	PIN_FIELD_BASE(53, 53, 2, 0x00a0, 0x10, 2, 1),
+	PIN_FIELD_BASE(54, 54, 5, 0x0090, 0x10, 8, 1),
+	PIN_FIELD_BASE(55, 55, 5, 0x0090, 0x10, 9, 1),
+	PIN_FIELD_BASE(56, 56, 1, 0x00b0, 0x10, 4, 1),
+	PIN_FIELD_BASE(57, 57, 1, 0x00b0, 0x10, 5, 1),
+	PIN_FIELD_BASE(59, 59, 2, 0x00a0, 0x10, 0, 1),
+	PIN_FIELD_BASE(60, 60, 9, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(61, 61, 9, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(66, 66, 5, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(67, 67, 5, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(69, 69, 7, 0x00a0, 0x10, 0, 1),
+	PIN_FIELD_BASE(70, 70, 7, 0x00a0, 0x10, 1, 1),
+	PIN_FIELD_BASE(71, 71, 7, 0x00a0, 0x10, 2, 1),
+	PIN_FIELD_BASE(72, 72, 7, 0x00a0, 0x10, 3, 1),
+	PIN_FIELD_BASE(73, 73, 7, 0x00a0, 0x10, 4, 1),
+	PIN_FIELD_BASE(88, 88, 7, 0x00a0, 0x10, 5, 1),
+	PIN_FIELD_BASE(89, 89, 7, 0x00a0, 0x10, 6, 1),
+	PIN_FIELD_BASE(92, 92, 3, 0x00b0, 0x10, 4, 1),
+	PIN_FIELD_BASE(93, 93, 3, 0x00b0, 0x10, 5, 1),
+	PIN_FIELD_BASE(117, 117, 4, 0x0090, 0x10, 0, 1),
+	PIN_FIELD_BASE(118, 118, 4, 0x0090, 0x10, 1, 1),
+	PIN_FIELD_BASE(119, 119, 4, 0x0090, 0x10, 2, 1),
+	PIN_FIELD_BASE(120, 120, 4, 0x0090, 0x10, 3, 1),
+	PIN_FIELD_BASE(121, 121, 4, 0x0090, 0x10, 4, 1),
+	PIN_FIELD_BASE(122, 122, 4, 0x0090, 0x10, 5, 1),
+	PIN_FIELD_BASE(123, 123, 4, 0x0090, 0x10, 6, 1),
+	PIN_FIELD_BASE(124, 124, 4, 0x0090, 0x10, 7, 1),
+	PIN_FIELD_BASE(126, 126, 5, 0x0090, 0x10, 4, 1),
+	PIN_FIELD_BASE(127, 127, 5, 0x0090, 0x10, 5, 1),
+	PIN_FIELD_BASE(128, 128, 5, 0x0090, 0x10, 6, 1),
+	PIN_FIELD_BASE(129, 129, 5, 0x0090, 0x10, 7, 1),
+	PIN_FIELD_BASE(134, 134, 3, 0x00b0, 0x10, 0, 1),
+	PIN_FIELD_BASE(135, 135, 3, 0x00b0, 0x10, 1, 1),
+	PIN_FIELD_BASE(136, 136, 3, 0x00b0, 0x10, 2, 1),
+	PIN_FIELD_BASE(137, 137, 3, 0x00b0, 0x10, 3, 1),
+	PIN_FIELD_BASE(165, 165, 5, 0x0090, 0x10, 2, 1),
+	PIN_FIELD_BASE(166, 166, 5, 0x0090, 0x10, 3, 1),
+	PIN_FIELD_BASE(181, 181, 10, 0x0050, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8901_pin_drv_range[] = {
+	PIN_FIELD_BASE(0, 0, 8, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(1, 1, 8, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(2, 2, 8, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(3, 3, 8, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(4, 4, 8, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(5, 5, 8, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(6, 6, 8, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(7, 7, 8, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(8, 8, 2, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(9, 9, 2, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(10, 10, 2, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(11, 11, 2, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(12, 12, 1, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(13, 13, 1, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(14, 14, 1, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(15, 15, 1, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(16, 16, 1, 0x0010, 0x10, 27, 3),
+	PIN_FIELD_BASE(17, 17, 1, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(18, 18, 1, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(19, 19, 1, 0x0020, 0x10, 21, 3),
+	PIN_FIELD_BASE(20, 20, 1, 0x0020, 0x10, 24, 3),
+	PIN_FIELD_BASE(21, 21, 1, 0x0020, 0x10, 18, 3),
+	PIN_FIELD_BASE(22, 22, 1, 0x0020, 0x10, 15, 3),
+	PIN_FIELD_BASE(23, 23, 1, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(24, 24, 1, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(25, 25, 1, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(26, 26, 1, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(27, 27, 1, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(28, 28, 1, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(29, 29, 1, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(30, 30, 1, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(31, 31, 1, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(32, 32, 9, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(33, 33, 1, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(34, 34, 1, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(35, 35, 1, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(36, 36, 9, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(37, 37, 2, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(38, 38, 2, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(39, 39, 1, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(40, 40, 2, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(41, 41, 2, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(42, 42, 2, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(43, 43, 2, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(44, 44, 2, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(45, 45, 2, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(46, 46, 1, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(47, 47, 1, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(48, 48, 2, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(49, 49, 2, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(50, 50, 2, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(51, 51, 2, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(52, 52, 2, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(53, 53, 2, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(54, 54, 5, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(55, 55, 5, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(56, 56, 1, 0x0020, 0x10, 6, 3),
+	PIN_FIELD_BASE(57, 57, 1, 0x0020, 0x10, 9, 3),
+	PIN_FIELD_BASE(58, 58, 1, 0x0020, 0x10, 12, 3),
+	PIN_FIELD_BASE(59, 59, 2, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(60, 60, 9, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(61, 61, 9, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(62, 62, 9, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(63, 63, 9, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(64, 64, 9, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(65, 65, 9, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(66, 66, 5, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(67, 67, 5, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(68, 68, 9, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(69, 69, 7, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(70, 70, 7, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(71, 71, 7, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(72, 72, 7, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(73, 73, 7, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(74, 74, 7, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(75, 75, 7, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(76, 76, 7, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(77, 77, 7, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(78, 78, 7, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(79, 79, 7, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(80, 80, 7, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(81, 81, 7, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(82, 82, 7, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(83, 83, 7, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(84, 84, 7, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(85, 85, 7, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(86, 86, 7, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(87, 87, 7, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(88, 88, 7, 0x0010, 0x10, 27, 3),
+	PIN_FIELD_BASE(89, 89, 7, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(90, 90, 7, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(91, 91, 7, 0x0020, 0x10, 6, 3),
+	PIN_FIELD_BASE(92, 92, 3, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(93, 93, 3, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(94, 94, 3, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(95, 95, 3, 0x0010, 0x10, 27, 3),
+	PIN_FIELD_BASE(96, 96, 3, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(97, 97, 3, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(98, 98, 3, 0x0020, 0x10, 6, 3),
+	PIN_FIELD_BASE(99, 99, 3, 0x0020, 0x10, 9, 3),
+	PIN_FIELD_BASE(100, 100, 3, 0x0020, 0x10, 12, 3),
+	PIN_FIELD_BASE(101, 101, 3, 0x0020, 0x10, 15, 3),
+	PIN_FIELD_BASE(102, 102, 3, 0x0020, 0x10, 18, 3),
+	PIN_FIELD_BASE(103, 103, 3, 0x0020, 0x10, 21, 3),
+	PIN_FIELD_BASE(104, 104, 3, 0x0020, 0x10, 24, 3),
+	PIN_FIELD_BASE(105, 105, 3, 0x0020, 0x10, 27, 3),
+	PIN_FIELD_BASE(106, 106, 8, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(107, 107, 8, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(108, 108, 8, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(109, 109, 8, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(110, 110, 8, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(111, 111, 8, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(112, 112, 5, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(113, 113, 5, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(114, 114, 5, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(115, 115, 5, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(116, 116, 5, 0x0010, 0x10, 27, 3),
+	PIN_FIELD_BASE(117, 117, 4, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(118, 118, 4, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(119, 119, 4, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(120, 120, 4, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(121, 121, 4, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(122, 122, 4, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(123, 123, 4, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(124, 124, 4, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(125, 125, 4, 0x0010, 0x10, 18, 3),
+	PIN_FIELD_BASE(126, 126, 5, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(127, 127, 5, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(128, 128, 5, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(129, 129, 5, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(130, 130, 4, 0x0010, 0x10, 21, 3),
+	PIN_FIELD_BASE(131, 131, 4, 0x0010, 0x10, 24, 3),
+	PIN_FIELD_BASE(132, 132, 4, 0x0010, 0x10, 27, 3),
+	PIN_FIELD_BASE(133, 133, 4, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(134, 134, 3, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(135, 135, 3, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(136, 136, 3, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(137, 137, 3, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(138, 138, 3, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(139, 139, 3, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(140, 140, 3, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(141, 141, 3, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(142, 142, 3, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(143, 143, 3, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(144, 144, 3, 0x0010, 0x10, 0, 3),
+	PIN_FIELD_BASE(145, 145, 3, 0x0010, 0x10, 3, 3),
+	PIN_FIELD_BASE(146, 146, 3, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(147, 147, 3, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(148, 148, 3, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(149, 149, 3, 0x0010, 0x10, 15, 3),
+	PIN_FIELD_BASE(150, 150, 4, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(151, 151, 4, 0x0020, 0x10, 18, 3),
+	PIN_FIELD_BASE(152, 152, 4, 0x0020, 0x10, 15, 3),
+	PIN_FIELD_BASE(153, 153, 4, 0x0020, 0x10, 12, 3),
+	PIN_FIELD_BASE(154, 154, 4, 0x0020, 0x10, 6, 3),
+	PIN_FIELD_BASE(155, 155, 4, 0x0020, 0x10, 9, 3),
+	PIN_FIELD_BASE(156, 156, 4, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(157, 157, 4, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(158, 158, 4, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(159, 159, 4, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(160, 160, 4, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(161, 161, 4, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(162, 162, 4, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(163, 163, 4, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(164, 164, 5, 0x0010, 0x10, 6, 3),
+	PIN_FIELD_BASE(165, 165, 5, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(166, 166, 5, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(167, 167, 5, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(168, 168, 5, 0x0010, 0x10, 9, 3),
+	PIN_FIELD_BASE(169, 169, 5, 0x0010, 0x10, 12, 3),
+	PIN_FIELD_BASE(170, 170, 5, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(171, 171, 6, 0x0000, 0x10, 0, 3),
+	PIN_FIELD_BASE(172, 172, 6, 0x0000, 0x10, 3, 3),
+	PIN_FIELD_BASE(173, 173, 6, 0x0000, 0x10, 6, 3),
+	PIN_FIELD_BASE(174, 174, 6, 0x0000, 0x10, 9, 3),
+	PIN_FIELD_BASE(175, 175, 6, 0x0000, 0x10, 12, 3),
+	PIN_FIELD_BASE(176, 176, 6, 0x0000, 0x10, 15, 3),
+	PIN_FIELD_BASE(177, 177, 6, 0x0000, 0x10, 18, 3),
+	PIN_FIELD_BASE(178, 178, 6, 0x0000, 0x10, 21, 3),
+	PIN_FIELD_BASE(179, 179, 6, 0x0000, 0x10, 24, 3),
+	PIN_FIELD_BASE(180, 180, 6, 0x0000, 0x10, 27, 3),
+	PIN_FIELD_BASE(181, 181, 10, 0x0000, 0x10, 0, 3),
+};
+
+static const struct mtk_pin_field_calc mt8901_pin_drv_adv_range[] = {
+	PIN_FIELD_BASE(8, 8, 2, 0x0030, 0x10, 6, 3),
+	PIN_FIELD_BASE(9, 9, 2, 0x0030, 0x10, 9, 3),
+	PIN_FIELD_BASE(10, 10, 2, 0x0030, 0x10, 12, 3),
+	PIN_FIELD_BASE(11, 11, 2, 0x0030, 0x10, 15, 3),
+	PIN_FIELD_BASE(12, 12, 1, 0x0040, 0x10, 0, 3),
+	PIN_FIELD_BASE(13, 13, 1, 0x0040, 0x10, 3, 3),
+	PIN_FIELD_BASE(17, 17, 1, 0x0040, 0x10, 6, 3),
+	PIN_FIELD_BASE(18, 18, 1, 0x0040, 0x10, 9, 3),
+	PIN_FIELD_BASE(52, 52, 2, 0x0030, 0x10, 0, 3),
+	PIN_FIELD_BASE(53, 53, 2, 0x0030, 0x10, 3, 3),
+	PIN_FIELD_BASE(54, 54, 5, 0x0030, 0x10, 24, 3),
+	PIN_FIELD_BASE(55, 55, 5, 0x0030, 0x10, 27, 3),
+	PIN_FIELD_BASE(56, 56, 1, 0x0040, 0x10, 12, 3),
+	PIN_FIELD_BASE(57, 57, 1, 0x0040, 0x10, 15, 3),
+	PIN_FIELD_BASE(60, 60, 9, 0x0020, 0x10, 0, 3),
+	PIN_FIELD_BASE(61, 61, 9, 0x0020, 0x10, 3, 3),
+	PIN_FIELD_BASE(66, 66, 5, 0x0030, 0x10, 0, 3),
+	PIN_FIELD_BASE(67, 67, 5, 0x0030, 0x10, 3, 3),
+	PIN_FIELD_BASE(70, 70, 7, 0x0030, 0x10, 0, 3),
+	PIN_FIELD_BASE(71, 71, 7, 0x0030, 0x10, 3, 3),
+	PIN_FIELD_BASE(72, 72, 7, 0x0030, 0x10, 6, 3),
+	PIN_FIELD_BASE(73, 73, 7, 0x0030, 0x10, 9, 3),
+	PIN_FIELD_BASE(88, 88, 7, 0x0030, 0x10, 12, 3),
+	PIN_FIELD_BASE(89, 89, 7, 0x0030, 0x10, 15, 3),
+	PIN_FIELD_BASE(92, 92, 3, 0x0040, 0x10, 12, 3),
+	PIN_FIELD_BASE(93, 93, 3, 0x0040, 0x10, 15, 3),
+	PIN_FIELD_BASE(117, 117, 4, 0x0030, 0x10, 0, 3),
+	PIN_FIELD_BASE(118, 118, 4, 0x0030, 0x10, 3, 3),
+	PIN_FIELD_BASE(119, 119, 4, 0x0030, 0x10, 6, 3),
+	PIN_FIELD_BASE(120, 120, 4, 0x0030, 0x10, 9, 3),
+	PIN_FIELD_BASE(121, 121, 4, 0x0030, 0x10, 12, 3),
+	PIN_FIELD_BASE(122, 122, 4, 0x0030, 0x10, 15, 3),
+	PIN_FIELD_BASE(123, 123, 4, 0x0030, 0x10, 18, 3),
+	PIN_FIELD_BASE(124, 124, 4, 0x0030, 0x10, 21, 3),
+	PIN_FIELD_BASE(126, 126, 5, 0x0030, 0x10, 12, 3),
+	PIN_FIELD_BASE(127, 127, 5, 0x0030, 0x10, 15, 3),
+	PIN_FIELD_BASE(128, 128, 5, 0x0030, 0x10, 18, 3),
+	PIN_FIELD_BASE(129, 129, 5, 0x0030, 0x10, 21, 3),
+	PIN_FIELD_BASE(134, 134, 3, 0x0040, 0x10, 0, 3),
+	PIN_FIELD_BASE(135, 135, 3, 0x0040, 0x10, 3, 3),
+	PIN_FIELD_BASE(136, 136, 3, 0x0040, 0x10, 6, 3),
+	PIN_FIELD_BASE(137, 137, 3, 0x0040, 0x10, 9, 3),
+	PIN_FIELD_BASE(165, 165, 5, 0x0030, 0x10, 6, 3),
+	PIN_FIELD_BASE(166, 166, 5, 0x0030, 0x10, 9, 3),
+};
+
+static const struct mtk_pin_field_calc mt8901_pin_rsel_range[] = {
+	PIN_FIELD_BASE(8, 8, 2, 0x0110, 0x10, 6, 3),
+	PIN_FIELD_BASE(9, 9, 2, 0x0110, 0x10, 9, 3),
+	PIN_FIELD_BASE(10, 10, 2, 0x0110, 0x10, 12, 3),
+	PIN_FIELD_BASE(11, 11, 2, 0x0110, 0x10, 15, 3),
+	PIN_FIELD_BASE(12, 12, 1, 0x0130, 0x10, 0, 1),
+	PIN_FIELD_BASE(13, 13, 1, 0x0130, 0x10, 1, 1),
+	PIN_FIELD_BASE(17, 17, 1, 0x0130, 0x10, 2, 1),
+	PIN_FIELD_BASE(18, 18, 1, 0x0130, 0x10, 3, 1),
+	PIN_FIELD_BASE(52, 52, 2, 0x0110, 0x10, 0, 3),
+	PIN_FIELD_BASE(53, 53, 2, 0x0110, 0x10, 3, 3),
+	PIN_FIELD_BASE(54, 54, 5, 0x0110, 0x10, 12, 3),
+	PIN_FIELD_BASE(55, 55, 5, 0x0110, 0x10, 15, 3),
+	PIN_FIELD_BASE(56, 56, 1, 0x0130, 0x10, 4, 1),
+	PIN_FIELD_BASE(57, 57, 1, 0x0130, 0x10, 5, 1),
+	PIN_FIELD_BASE(60, 60, 9, 0x00f0, 0x10, 0, 3),
+	PIN_FIELD_BASE(61, 61, 9, 0x00f0, 0x10, 3, 3),
+	PIN_FIELD_BASE(66, 66, 5, 0x0110, 0x10, 0, 1),
+	PIN_FIELD_BASE(67, 67, 5, 0x0110, 0x10, 1, 1),
+	PIN_FIELD_BASE(70, 70, 7, 0x0100, 0x10, 0, 3),
+	PIN_FIELD_BASE(71, 71, 7, 0x0100, 0x10, 3, 3),
+	PIN_FIELD_BASE(72, 72, 7, 0x0100, 0x10, 6, 3),
+	PIN_FIELD_BASE(73, 73, 7, 0x0100, 0x10, 9, 3),
+	PIN_FIELD_BASE(88, 88, 7, 0x0100, 0x10, 12, 3),
+	PIN_FIELD_BASE(89, 89, 7, 0x0100, 0x10, 15, 3),
+	PIN_FIELD_BASE(92, 92, 3, 0x0120, 0x10, 12, 3),
+	PIN_FIELD_BASE(93, 93, 3, 0x0120, 0x10, 15, 3),
+	PIN_FIELD_BASE(117, 117, 4, 0x0100, 0x10, 0, 3),
+	PIN_FIELD_BASE(118, 118, 4, 0x0100, 0x10, 3, 3),
+	PIN_FIELD_BASE(119, 119, 4, 0x0100, 0x10, 6, 3),
+	PIN_FIELD_BASE(120, 120, 4, 0x0100, 0x10, 9, 3),
+	PIN_FIELD_BASE(121, 121, 4, 0x0100, 0x10, 12, 3),
+	PIN_FIELD_BASE(122, 122, 4, 0x0100, 0x10, 15, 3),
+	PIN_FIELD_BASE(123, 123, 4, 0x0100, 0x10, 18, 3),
+	PIN_FIELD_BASE(124, 124, 4, 0x0100, 0x10, 21, 3),
+	PIN_FIELD_BASE(126, 126, 5, 0x0110, 0x10, 8, 1),
+	PIN_FIELD_BASE(127, 127, 5, 0x0110, 0x10, 9, 1),
+	PIN_FIELD_BASE(128, 128, 5, 0x0110, 0x10, 10, 1),
+	PIN_FIELD_BASE(129, 129, 5, 0x0110, 0x10, 11, 1),
+	PIN_FIELD_BASE(134, 134, 3, 0x0120, 0x10, 0, 3),
+	PIN_FIELD_BASE(135, 135, 3, 0x0120, 0x10, 3, 3),
+	PIN_FIELD_BASE(136, 136, 3, 0x0120, 0x10, 6, 3),
+	PIN_FIELD_BASE(137, 137, 3, 0x0120, 0x10, 9, 3),
+	PIN_FIELD_BASE(165, 165, 5, 0x0110, 0x10, 2, 3),
+	PIN_FIELD_BASE(166, 166, 5, 0x0110, 0x10, 5, 3),
+};
+
+static const struct mtk_pin_rsel mt8901_pin_rsel_val_range[] = {
+	0
+};
+
+static const unsigned int mt8901_pull_type[] = {
+	MTK_PULL_PUPD_R1R0_TYPE, /*0*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*1*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*2*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*3*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*4*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*5*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*6*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*7*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*8*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*9*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*10*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*11*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*12*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*13*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*14*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*15*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*16*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*17*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*18*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*19*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*20*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*21*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*22*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*23*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*24*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*25*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*26*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*27*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*28*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*29*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*30*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*31*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*32*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*33*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*34*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*35*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*36*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*37*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*38*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*39*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*40*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*41*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*42*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*43*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*44*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*45*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*46*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*47*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*48*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*49*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*50*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*51*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*52*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*53*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*54*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*55*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*56*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*57*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*58*/
+	MTK_PULL_PU_PD_TYPE, /*59*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*60*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*61*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*62*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*63*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*64*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*65*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*66*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*67*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*68*/
+	MTK_PULL_PU_PD_TYPE, /*69*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*70*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*71*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*72*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*73*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*74*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*75*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*76*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*77*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*78*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*79*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*80*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*81*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*82*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*83*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*84*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*85*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*86*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*87*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*88*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*89*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*90*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*91*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*92*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*93*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*94*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*95*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*96*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*97*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*98*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*99*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*100*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*101*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*102*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*103*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*104*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*105*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*106*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*107*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*108*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*109*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*110*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*111*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*112*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*113*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*114*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*115*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*116*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*117*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*118*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*119*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*120*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*121*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*122*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*123*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*124*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*125*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*126*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*127*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*128*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*129*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*130*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*131*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*132*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*133*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*134*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*135*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*136*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*137*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*138*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*139*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*140*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*141*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*142*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*143*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*144*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*145*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*146*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*147*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*148*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*149*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*150*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*151*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*152*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*153*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*154*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*155*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*156*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*157*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*158*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*159*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*160*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*161*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*162*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*163*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*164*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*165*/
+	MTK_PULL_PU_PD_RSEL_TYPE, /*166*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*167*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*168*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*169*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*170*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*171*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*172*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*173*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*174*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*175*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*176*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*177*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*178*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*179*/
+	MTK_PULL_PUPD_R1R0_TYPE, /*180*/
+	MTK_PULL_PU_PD_TYPE, /*181*/
+};
+
+static const struct mtk_pin_reg_calc mt8901_reg_cals[PINCTRL_PIN_REG_MAX] = {
+	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8901_pin_mode_range),
+	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8901_pin_dir_range),
+	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8901_pin_di_range),
+	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8901_pin_do_range),
+	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8901_pin_smt_range),
+	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8901_pin_ies_range),
+	[PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8901_pin_pupd_range),
+	[PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8901_pin_r0_range),
+	[PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8901_pin_r1_range),
+	[PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8901_pin_pu_range),
+	[PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8901_pin_pd_range),
+	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8901_pin_drv_range),
+	[PINCTRL_PIN_REG_DRV_ADV] = MTK_RANGE(mt8901_pin_drv_adv_range),
+	[PINCTRL_PIN_REG_RSEL] = MTK_RANGE(mt8901_pin_rsel_range),
+};
+
+static const char * const mt8901_pinctrl_register_base_name[] = {
+	"iocfg0", "iocfg_lt2", "iocfg_lt3", "iocfg_rt1", "iocfg_rt2", "iocfg_rt3",
+	"iocfg_tr", "iocfg_rt0", "iocfg_lt1", "iocfg_lb", "iocfg_rb",
+};
+
+static const struct mtk_eint_hw mt8901_eint_hw = {
+	.port_mask = 0xf,
+	.ports     = 7,
+	.ap_num    = 209,
+	.db_cnt    = 32,
+	.db_time   = debounce_time_mt8901,
+};
+
+static const struct mtk_pin_soc mt8901_data = {
+	.reg_cal = mt8901_reg_cals,
+	.pins = mtk_pins_mt8901,
+	.npins = ARRAY_SIZE(mtk_pins_mt8901),
+	.ngrps = ARRAY_SIZE(mtk_pins_mt8901),
+	.eint_hw = &mt8901_eint_hw,
+	.eint_pin = eint_pins_mt8901,
+	.nfuncs = 8,
+	.gpio_m = 0,
+	.base_names = mt8901_pinctrl_register_base_name,
+	.nbase_names = ARRAY_SIZE(mt8901_pinctrl_register_base_name),
+	.pull_type = mt8901_pull_type,
+	.pin_rsel = mt8901_pin_rsel_val_range,
+	.npin_rsel = ARRAY_SIZE(mt8901_pin_rsel_val_range), /*numsel*/
+	.bias_set_combo = mtk_pinconf_bias_set_combo,
+	.bias_get_combo = mtk_pinconf_bias_get_combo,
+	.drive_set = mtk_pinconf_drive_set_rev1,
+	.drive_get = mtk_pinconf_drive_get_rev1,
+	.adv_drive_set = mtk_pinconf_adv_drive_set_raw,
+	.adv_drive_get = mtk_pinconf_adv_drive_get_raw,
+};
+
+static const struct acpi_device_id mt8901_pinctrl_acpi_match[] = {
+	{"NVDA9221", (kernel_ulong_t)&mt8901_data },
+	{ }
+};
+MODULE_DEVICE_TABLE(acpi, mt8901_pinctrl_acpi_match);
+
+static struct platform_driver mt8901_pinctrl_driver = {
+	.driver = {
+		.name = "mt8901-pinctrl",
+		.acpi_match_table = ACPI_PTR(mt8901_pinctrl_acpi_match),
+		.pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops)
+	},
+	.probe = mtk_paris_pinctrl_probe,
+};
+
+static int __init mt8901_pinctrl_init(void)
+{
+	return platform_driver_register(&mt8901_pinctrl_driver);
+}
+
+arch_initcall(mt8901_pinctrl_init);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("MediaTek MT8901 Pinctrl Driver");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8901.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8901.h
new file mode 100644
index 000000000000..fc64fc6ff5f9
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8901.h
@@ -0,0 +1,2130 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2025 MediaTek Inc.
+ *
+ */
+
+#ifndef __PINCTRL_MTK_MT8901_H
+#define __PINCTRL_MTK_MT8901_H
+
+#include "pinctrl-paris.h"
+
+#define INVALID_BASE	0xFF
+
+static const struct mtk_pin_desc mtk_pins_mt8901[] = {
+	MTK_PIN(
+		0, "GPIO0",
+		MTK_EINT_FUNCTION(0, 0),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B:GPIO0"),
+		MTK_FUNCTION(1, "O:ESPI_SCK")
+	),
+	MTK_PIN(
+		1, "GPIO1",
+		MTK_EINT_FUNCTION(0, 1),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO1"),
+		MTK_FUNCTION(1, "B1_ESPI_IO0")
+	),
+	MTK_PIN(
+		2, "GPIO2",
+		MTK_EINT_FUNCTION(0, 2),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO2"),
+		MTK_FUNCTION(1, "B1_ESPI_IO1")
+	),
+	MTK_PIN(
+		3, "GPIO3",
+		MTK_EINT_FUNCTION(0, 3),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO3"),
+		MTK_FUNCTION(1, "B1_ESPI_IO2")
+	),
+	MTK_PIN(
+		4, "GPIO4",
+		MTK_EINT_FUNCTION(0, 4),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO4"),
+		MTK_FUNCTION(1, "B1_ESPI_IO3")
+	),
+	MTK_PIN(
+		5, "GPIO5",
+		MTK_EINT_FUNCTION(0, 5),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO5"),
+		MTK_FUNCTION(1, "O_ESPI_CSN")
+	),
+	MTK_PIN(
+		6, "GPIO6",
+		MTK_EINT_FUNCTION(0, 6),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO6"),
+		MTK_FUNCTION(1, "O_ESPI_RESET_O"),
+		MTK_FUNCTION(2, "I1_ESPI_RESET_I")
+	),
+	MTK_PIN(
+		7, "GPIO7",
+		MTK_EINT_FUNCTION(0, 7),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO7"),
+		MTK_FUNCTION(1, "I1_ESPI_ALERT")
+	),
+	MTK_PIN(
+		8, "GPIO8",
+		MTK_EINT_FUNCTION(0, 8),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO8"),
+		MTK_FUNCTION(1, "B1_I2C_SCL3"),
+		MTK_FUNCTION(2, "B1_DISP_SCL2"),
+		MTK_FUNCTION(4, "O_PMSR_SMAP"),
+		MTK_FUNCTION(6, "O_MD32_0_TXD"),
+		MTK_FUNCTION(7, "O_MD32_1_TXD")
+	),
+	MTK_PIN(
+		9, "GPIO9",
+		MTK_EINT_FUNCTION(0, 9),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO9"),
+		MTK_FUNCTION(1, "B1_I2C_SDA3"),
+		MTK_FUNCTION(2, "B1_DISP_SDA2"),
+		MTK_FUNCTION(4, "O_PMSR_SMAP_MAX"),
+		MTK_FUNCTION(6, "I1_MD32_0_RXD"),
+		MTK_FUNCTION(7, "I1_MD32_1_RXD")
+	),
+	MTK_PIN(
+		10, "GPIO10",
+		MTK_EINT_FUNCTION(0, 10),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO10"),
+		MTK_FUNCTION(1, "B1_I2C_SCL4"),
+		MTK_FUNCTION(2, "B1_DISP_SCL2"),
+		MTK_FUNCTION(4, "O_PMSR_SMAP_MAX_W"),
+		MTK_FUNCTION(6, "O_MD32_0_GPIO0"),
+		MTK_FUNCTION(7, "O_MD32_1_GPIO0")
+	),
+	MTK_PIN(
+		11, "GPIO11",
+		MTK_EINT_FUNCTION(0, 11),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO11"),
+		MTK_FUNCTION(1, "B1_I2C_SDA4"),
+		MTK_FUNCTION(2, "B1_DISP_SDA2")
+	),
+	MTK_PIN(
+		12, "GPIO12",
+		MTK_EINT_FUNCTION(0, 12),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO12"),
+		MTK_FUNCTION(1, "B0_SPMI_M_SCL"),
+		MTK_FUNCTION(2, "B0_TP_GPIO31_AO")
+	),
+	MTK_PIN(
+		13, "GPIO13",
+		MTK_EINT_FUNCTION(0, 13),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO13"),
+		MTK_FUNCTION(1, "B0_SPMI_M_SDA"),
+		MTK_FUNCTION(2, "B0_TP_GPIO6_AO")
+	),
+	MTK_PIN(
+		14, "GPIO14",
+		MTK_EINT_FUNCTION(0, 14),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO14"),
+		MTK_FUNCTION(1, "I0_DPAUX_HPD_IN_2"),
+		MTK_FUNCTION(7, "O_DBG_MON_A0")
+	),
+	MTK_PIN(
+		15, "GPIO15",
+		MTK_EINT_FUNCTION(0, 15),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO15"),
+		MTK_FUNCTION(1, "I0_DPAUX_HPD_IN_3"),
+		MTK_FUNCTION(2, "B0_TP_GPIO25_AO"),
+		MTK_FUNCTION(7, "O_DBG_MON_A1")
+	),
+	MTK_PIN(
+		16, "GPIO16",
+		MTK_EINT_FUNCTION(0, 16),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO16"),
+		MTK_FUNCTION(1, "O_USB4_L_TCPC_RESET"),
+		MTK_FUNCTION(7, "O_DBG_MON_A18")
+	),
+	MTK_PIN(
+		17, "GPIO17",
+		MTK_EINT_FUNCTION(0, 17),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO17"),
+		MTK_FUNCTION(1, "B0_SPMI_P_SCL")
+	),
+	MTK_PIN(
+		18, "GPIO18",
+		MTK_EINT_FUNCTION(0, 18),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO18"),
+		MTK_FUNCTION(1, "B0_SPMI_P_SDA")
+	),
+	MTK_PIN(
+		19, "GPIO19",
+		MTK_EINT_FUNCTION(0, 19),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO19"),
+		MTK_FUNCTION(1, "B0_TP_GPIO29_AO")
+	),
+	MTK_PIN(
+		20, "GPIO20",
+		MTK_EINT_FUNCTION(0, 20),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO20"),
+		MTK_FUNCTION(1, "B0_TP_GPIO30_AO")
+	),
+	MTK_PIN(
+		21, "GPIO21",
+		MTK_EINT_FUNCTION(0, 21),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO21"),
+		MTK_FUNCTION(1, "B1_PROCHOT")
+	),
+	MTK_PIN(
+		22, "GPIO22",
+		MTK_EINT_FUNCTION(0, 22),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO22"),
+		MTK_FUNCTION(1, "I0_RTC32K_CK")
+	),
+	MTK_PIN(
+		23, "GPIO23",
+		MTK_EINT_FUNCTION(0, 23),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO23"),
+		MTK_FUNCTION(1, "B0_TP_GPIO0_AO")
+	),
+	MTK_PIN(
+		24, "GPIO24",
+		MTK_EINT_FUNCTION(0, 24),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO24"),
+		MTK_FUNCTION(2, "B0_TP_GPIO1_AO"),
+		MTK_FUNCTION(3, "O_CMMCLK1"),
+		MTK_FUNCTION(4, "O_SROOT_GPIO_O"),
+		MTK_FUNCTION(5, "O_MD32_10_TXD"),
+		MTK_FUNCTION(6, "O_MD32_11_TXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_A3")
+	),
+	MTK_PIN(
+		25, "GPIO25",
+		MTK_EINT_FUNCTION(0, 25),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO25"),
+		MTK_FUNCTION(1, "B0_TP_GPIO2_AO"),
+		MTK_FUNCTION(2, "I0_VBUSVALID_0P"),
+		MTK_FUNCTION(4, "I0_SROOT_GPIO_I"),
+		MTK_FUNCTION(5, "I1_MD32_10_RXD"),
+		MTK_FUNCTION(6, "I1_MD32_11_RXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_A4")
+	),
+	MTK_PIN(
+		26, "GPIO26",
+		MTK_EINT_FUNCTION(0, 26),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO26"),
+		MTK_FUNCTION(1, "B0_TP_GPIO3_AO"),
+		MTK_FUNCTION(5, "O_MD32_12_TXD"),
+		MTK_FUNCTION(6, "O_MD32_13_TXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_A5")
+	),
+	MTK_PIN(
+		27, "GPIO27",
+		MTK_EINT_FUNCTION(0, 27),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO27"),
+		MTK_FUNCTION(1, "B0_TP_GPIO4_AO"),
+		MTK_FUNCTION(5, "I1_MD32_12_RXD"),
+		MTK_FUNCTION(6, "I1_MD32_13_RXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_A6")
+	),
+	MTK_PIN(
+		28, "GPIO28",
+		MTK_EINT_FUNCTION(0, 28),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO28"),
+		MTK_FUNCTION(1, "B0_TP_GPIO5_AO"),
+		MTK_FUNCTION(5, "O_MD32_12_GPIO0"),
+		MTK_FUNCTION(6, "O_MD32_13_GPIO0"),
+		MTK_FUNCTION(7, "O_DBG_MON_A7")
+	),
+	MTK_PIN(
+		29, "GPIO29",
+		MTK_EINT_FUNCTION(0, 29),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO29"),
+		MTK_FUNCTION(1, "B1_THERMTRIP")
+	),
+	MTK_PIN(
+		30, "GPIO30",
+		MTK_EINT_FUNCTION(0, 30),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO30"),
+		MTK_FUNCTION(1, "B0_TP_GPIO7_AO"),
+		MTK_FUNCTION(2, "O_CMMCLK0"),
+		MTK_FUNCTION(4, "I0_CLUSTER0_SLV_CPUEB_JTAG_TRSTN"),
+		MTK_FUNCTION(5, "I0_CLUSTER1_SLV_CPUEB_JTAG_TRSTN"),
+		MTK_FUNCTION(6, "I0_OSROOT_GPIO_I"),
+		MTK_FUNCTION(7, "O_DBG_MON_A8")
+	),
+	MTK_PIN(
+		31, "GPIO31",
+		MTK_EINT_FUNCTION(0, 31),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO31"),
+		MTK_FUNCTION(1, "B0_TP_GPIO8_AO"),
+		MTK_FUNCTION(2, "O_CMMCLK1"),
+		MTK_FUNCTION(4, "I1_CLUSTER0_SLV_CPUEB_JTAG_TMS"),
+		MTK_FUNCTION(5, "I1_CLUSTER1_SLV_CPUEB_JTAG_TMS"),
+		MTK_FUNCTION(6, "O_OSROOT_GPIO_O"),
+		MTK_FUNCTION(7, "O_DBG_MON_A9")
+	),
+	MTK_PIN(
+		32, "GPIO32",
+		MTK_EINT_FUNCTION(0, 32),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO32"),
+		MTK_FUNCTION(1, "B0_TP_GPIO9_AO"),
+		MTK_FUNCTION(5, "O_SROOT_UTX"),
+		MTK_FUNCTION(6, "I1_TP_UCTS1_VLP"),
+		MTK_FUNCTION(7, "O_DBG_MON_A10")
+	),
+	MTK_PIN(
+		33, "GPIO33",
+		MTK_EINT_FUNCTION(0, 33),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO33"),
+		MTK_FUNCTION(1, "B0_TP_GPIO10_AO"),
+		MTK_FUNCTION(2, "O_CMMCLK2"),
+		MTK_FUNCTION(3, "I0_VBUSVALID_1P"),
+		MTK_FUNCTION(4, "I1_CLUSTER0_SLV_CPUEB_JTAG_TCK"),
+		MTK_FUNCTION(5, "I1_CLUSTER1_SLV_CPUEB_JTAG_TCK"),
+		MTK_FUNCTION(6, "I0_SROOT_TCK"),
+		MTK_FUNCTION(7, "I0_OSROOT_TCK")
+	),
+	MTK_PIN(
+		34, "GPIO34",
+		MTK_EINT_FUNCTION(0, 34),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO34"),
+		MTK_FUNCTION(1, "B0_TP_GPIO11_AO"),
+		MTK_FUNCTION(2, "O_CMMCLK4"),
+		MTK_FUNCTION(3, "I0_VBUSVALID_3P"),
+		MTK_FUNCTION(4, "I1_CLUSTER0_SLV_CPUEB_JTAG_TDI"),
+		MTK_FUNCTION(5, "I1_CLUSTER1_SLV_CPUEB_JTAG_TDI"),
+		MTK_FUNCTION(6, "I0_SROOT_TDI"),
+		MTK_FUNCTION(7, "I0_OSROOT_TDI")
+	),
+	MTK_PIN(
+		35, "GPIO35",
+		MTK_EINT_FUNCTION(0, 35),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO35"),
+		MTK_FUNCTION(1, "B0_TP_GPIO12_AO"),
+		MTK_FUNCTION(2, "O_SCP_PWM_1_VLP"),
+		MTK_FUNCTION(4, "O_CLUSTER0_SLV_CPUEB_JTAG_TDO"),
+		MTK_FUNCTION(5, "O_CLUSTER1_SLV_CPUEB_JTAG_TDO"),
+		MTK_FUNCTION(6, "O_SROOT_TDO"),
+		MTK_FUNCTION(7, "O_OSROOT_TDO")
+	),
+	MTK_PIN(
+		36, "GPIO36",
+		MTK_EINT_FUNCTION(0, 36),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO36"),
+		MTK_FUNCTION(1, "B0_TP_GPIO22_AO"),
+		MTK_FUNCTION(5, "I1_SROOT_URX"),
+		MTK_FUNCTION(6, "O_TP_URTS1_VLP"),
+		MTK_FUNCTION(7, "O_DBG_MON_A31")
+	),
+	MTK_PIN(
+		37, "GPIO37",
+		MTK_EINT_FUNCTION(0, 37),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO37"),
+		MTK_FUNCTION(1, "B0_TP_GPIO23_AO"),
+		MTK_FUNCTION(2, "O_CMMCLK3"),
+		MTK_FUNCTION(4, "O_SCP_PWM_2_VLP"),
+		MTK_FUNCTION(6, "O_MD32_5_GPIO0"),
+		MTK_FUNCTION(7, "O_DBG_MON_A11")
+	),
+	MTK_PIN(
+		38, "GPIO38",
+		MTK_EINT_FUNCTION(0, 38),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO38"),
+		MTK_FUNCTION(1, "B0_TP_GPIO24_AO"),
+		MTK_FUNCTION(2, "O_SCP_VREQ_VAO")
+	),
+	MTK_PIN(
+		39, "GPIO39",
+		MTK_EINT_FUNCTION(0, 39),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO39"),
+		MTK_FUNCTION(1, "B0_TP_GPIO13_AO"),
+		MTK_FUNCTION(2, "O_SCP_PWM_2_VLP"),
+		MTK_FUNCTION(3, "O_CMMCLK0"),
+		MTK_FUNCTION(4, "I0_VBUSVALID_2P"),
+		MTK_FUNCTION(5, "O_MD32_10_GPIO0"),
+		MTK_FUNCTION(6, "I0_SROOT_TMS"),
+		MTK_FUNCTION(7, "I0_OSROOT_TMS")
+	),
+	MTK_PIN(
+		40, "GPIO40",
+		MTK_EINT_FUNCTION(0, 40),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO40"),
+		MTK_FUNCTION(1, "B0_TP_GPIO14_AO"),
+		MTK_FUNCTION(2, "I0_VBUSVALID_1P"),
+		MTK_FUNCTION(3, "O_URTS2"),
+		MTK_FUNCTION(4, "O_TP_URTS2_VLP"),
+		MTK_FUNCTION(5, "O_SPMI_P_TRIG_FLAG"),
+		MTK_FUNCTION(6, "I1_MD32_5_RXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_A13")
+	),
+	MTK_PIN(
+		41, "GPIO41",
+		MTK_EINT_FUNCTION(0, 41),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO41"),
+		MTK_FUNCTION(1, "B0_TP_GPIO15_AO"),
+		MTK_FUNCTION(2, "I0_VBUSVALID_0P"),
+		MTK_FUNCTION(3, "I1_UCTS2"),
+		MTK_FUNCTION(4, "I1_TP_UCTS2_VLP"),
+		MTK_FUNCTION(5, "O_SPMI_S_TRIG_FLAG"),
+		MTK_FUNCTION(6, "O_MD32_5_TXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_A12")
+	),
+	MTK_PIN(
+		42, "GPIO42",
+		MTK_EINT_FUNCTION(0, 42),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO42"),
+		MTK_FUNCTION(1, "B0_TP_GPIO16_AO"),
+		MTK_FUNCTION(2, "O_CMMCLK3"),
+		MTK_FUNCTION(3, "O_UTXD2"),
+		MTK_FUNCTION(4, "O_TP_UTXD2_VLP"),
+		MTK_FUNCTION(5, "O_SPMI_M_TRIG_FLAG"),
+		MTK_FUNCTION(6, "I0_SROOT_NTRST"),
+		MTK_FUNCTION(7, "I0_OSROOT_NTRST")
+	),
+	MTK_PIN(
+		43, "GPIO43",
+		MTK_EINT_FUNCTION(0, 43),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO43"),
+		MTK_FUNCTION(1, "B0_TP_GPIO17_AO"),
+		MTK_FUNCTION(2, "O_CMMCLK4"),
+		MTK_FUNCTION(3, "I1_URXD2"),
+		MTK_FUNCTION(4, "I1_TP_URXD2_VLP"),
+		MTK_FUNCTION(5, "O_MD32_4_TXD"),
+		MTK_FUNCTION(6, "O_MD32PCM_UTXD_AO_VLP")
+	),
+	MTK_PIN(
+		44, "GPIO44",
+		MTK_EINT_FUNCTION(0, 44),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO44"),
+		MTK_FUNCTION(1, "B0_TP_GPIO18_AO"),
+		MTK_FUNCTION(2, "I1_TP_UCTS2_VLP"),
+		MTK_FUNCTION(3, "I1_UCTS2"),
+		MTK_FUNCTION(5, "I1_MD32_4_RXD"),
+		MTK_FUNCTION(6, "I1_MD32PCM_URXD_AO_VLP")
+	),
+	MTK_PIN(
+		45, "GPIO45",
+		MTK_EINT_FUNCTION(0, 45),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO45"),
+		MTK_FUNCTION(1, "B0_TP_GPIO19_AO"),
+		MTK_FUNCTION(2, "O_TP_URTS2_VLP"),
+		MTK_FUNCTION(3, "O_URTS2"),
+		MTK_FUNCTION(5, "O_MD32_4_GPIO0"),
+		MTK_FUNCTION(6, "O_MD32_11_GPIO0")
+	),
+	MTK_PIN(
+		46, "GPIO46",
+		MTK_EINT_FUNCTION(0, 46),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO46"),
+		MTK_FUNCTION(1, "B0_TP_GPIO20_AO"),
+		MTK_FUNCTION(2, "I0_VBUSVALID_2P"),
+		MTK_FUNCTION(3, "O_SCP_VREQ_VAO"),
+		MTK_FUNCTION(4, "O_SCP_PWM_1_VLP"),
+		MTK_FUNCTION(5, "O_SROOT_GPIO_O"),
+		MTK_FUNCTION(6, "O_OSROOT_GPIO_O")
+	),
+	MTK_PIN(
+		47, "GPIO47",
+		MTK_EINT_FUNCTION(0, 47),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO47"),
+		MTK_FUNCTION(1, "B0_TP_GPIO21_AO"),
+		MTK_FUNCTION(2, "I0_VBUSVALID_3P"),
+		MTK_FUNCTION(3, "O_CMMCLK2"),
+		MTK_FUNCTION(5, "I0_SROOT_GPIO_I"),
+		MTK_FUNCTION(6, "I0_OSROOT_GPIO_I"),
+		MTK_FUNCTION(7, "O_DBG_MON_A2")
+	),
+	MTK_PIN(
+		48, "GPIO48",
+		MTK_EINT_FUNCTION(0, 48),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO48"),
+		MTK_FUNCTION(1, "O_UTXD0"),
+		MTK_FUNCTION(2, "O_TP_UTXD1_VLP"),
+		MTK_FUNCTION(6, "O_ADSP_UTXD0"),
+		MTK_FUNCTION(7, "O_DBG_MON_A19")
+	),
+	MTK_PIN(
+		49, "GPIO49",
+		MTK_EINT_FUNCTION(0, 49),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO49"),
+		MTK_FUNCTION(1, "I1_URXD0"),
+		MTK_FUNCTION(2, "I1_TP_URXD1_VLP"),
+		MTK_FUNCTION(6, "I1_ADSP_URXD0"),
+		MTK_FUNCTION(7, "O_DBG_MON_A20")
+	),
+	MTK_PIN(
+		50, "GPIO50",
+		MTK_EINT_FUNCTION(0, 50),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO50"),
+		MTK_FUNCTION(1, "O_TP_UTXD2_VLP"),
+		MTK_FUNCTION(2, "O_UTXD2"),
+		MTK_FUNCTION(4, "B0_TP_GPIO26_AO"),
+		MTK_FUNCTION(5, "O_TP_UTXD1_VLP"),
+		MTK_FUNCTION(7, "O_SROOT_UTX")
+	),
+	MTK_PIN(
+		51, "GPIO51",
+		MTK_EINT_FUNCTION(0, 51),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO51"),
+		MTK_FUNCTION(1, "I1_TP_URXD2_VLP"),
+		MTK_FUNCTION(2, "I1_URXD2"),
+		MTK_FUNCTION(4, "B0_TP_GPIO27_AO"),
+		MTK_FUNCTION(5, "I1_TP_URXD1_VLP"),
+		MTK_FUNCTION(7, "I1_SROOT_URX")
+	),
+	MTK_PIN(
+		52, "GPIO52",
+		MTK_EINT_FUNCTION(0, 52),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO52"),
+		MTK_FUNCTION(1, "B1_USB4_L_PD_SCL"),
+		MTK_FUNCTION(7, "O_ADSP_UTXD0")
+	),
+	MTK_PIN(
+		53, "GPIO53",
+		MTK_EINT_FUNCTION(0, 53),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO53"),
+		MTK_FUNCTION(1, "B1_USB4_L_PD_SDA"),
+		MTK_FUNCTION(5, "O_MD32_7_TXD"),
+		MTK_FUNCTION(6, "O_MD32_6_TXD"),
+		MTK_FUNCTION(7, "I1_ADSP_URXD0")
+	),
+	MTK_PIN(
+		54, "GPIO54",
+		MTK_EINT_FUNCTION(0, 54),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO54"),
+		MTK_FUNCTION(1, "B1_USB4_R_PD_SCL"),
+		MTK_FUNCTION(4, "I1_CKM_SCL"),
+		MTK_FUNCTION(5, "I1_MD32_7_RXD"),
+		MTK_FUNCTION(6, "I1_USB4_L_PAR_SCL"),
+		MTK_FUNCTION(7, "O_PBUD_CTRL_UTXD_AO_VLP")
+	),
+	MTK_PIN(
+		55, "GPIO55",
+		MTK_EINT_FUNCTION(0, 55),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO55"),
+		MTK_FUNCTION(1, "B1_USB4_R_PD_SDA"),
+		MTK_FUNCTION(4, "B1_CKM_SDA"),
+		MTK_FUNCTION(5, "O_MD32_7_GPIO0"),
+		MTK_FUNCTION(6, "B1_USB4_L_PAR_SDA"),
+		MTK_FUNCTION(7, "I1_PBUD_CTRL_URXD_AO_VLP")
+	),
+	MTK_PIN(
+		56, "GPIO56",
+		MTK_EINT_FUNCTION(0, 56),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO56"),
+		MTK_FUNCTION(1, "B0_SPMI_S_SCL")
+	),
+	MTK_PIN(
+		57, "GPIO57",
+		MTK_EINT_FUNCTION(0, 57),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO57"),
+		MTK_FUNCTION(1, "B0_SPMI_S_SDA")
+	),
+	MTK_PIN(
+		58, "GPIO58",
+		MTK_EINT_FUNCTION(0, 58),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO58"),
+		MTK_FUNCTION(1, "O_WATCHDOG")
+	),
+	MTK_PIN(
+		59, "GPIO59",
+		MTK_EINT_FUNCTION(0, 59),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO59"),
+		MTK_FUNCTION(1, "B0_PAD_RESET_DRAM_0")
+	),
+	MTK_PIN(
+		60, "GPIO60",
+		MTK_EINT_FUNCTION(0, 60),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO60"),
+		MTK_FUNCTION(1, "B1_I2C_SCL0"),
+		MTK_FUNCTION(5, "O_MD32_2_TXD"),
+		MTK_FUNCTION(6, "O_MD32_3_TXD")
+	),
+	MTK_PIN(
+		61, "GPIO61",
+		MTK_EINT_FUNCTION(0, 61),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO61"),
+		MTK_FUNCTION(1, "B1_I2C_SDA0"),
+		MTK_FUNCTION(5, "I1_MD32_2_RXD"),
+		MTK_FUNCTION(6, "I1_MD32_3_RXD")
+	),
+	MTK_PIN(
+		62, "GPIO62",
+		MTK_EINT_FUNCTION(0, 62),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO62"),
+		MTK_FUNCTION(1, "I0_DMIC0_DAT"),
+		MTK_FUNCTION(6, "O_TP_UTXD1_VLP"),
+		MTK_FUNCTION(7, "O_DBG_MON_B0")
+	),
+	MTK_PIN(
+		63, "GPIO63",
+		MTK_EINT_FUNCTION(0, 63),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO63"),
+		MTK_FUNCTION(1, "O_DMIC0_CLK"),
+		MTK_FUNCTION(6, "I1_TP_URXD1_VLP"),
+		MTK_FUNCTION(7, "O_DBG_MON_B1")
+	),
+	MTK_PIN(
+		64, "GPIO64",
+		MTK_EINT_FUNCTION(0, 64),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO64"),
+		MTK_FUNCTION(1, "I0_DMIC1_DAT"),
+		MTK_FUNCTION(5, "O_MD32_2_GPIO0"),
+		MTK_FUNCTION(6, "O_MD32_3_GPIO0"),
+		MTK_FUNCTION(7, "O_DBG_MON_B2")
+	),
+	MTK_PIN(
+		65, "GPIO65",
+		MTK_EINT_FUNCTION(0, 65),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO65"),
+		MTK_FUNCTION(1, "O_DMIC1_CLK"),
+		MTK_FUNCTION(7, "O_DBG_MON_B3")
+	),
+	MTK_PIN(
+		66, "GPIO66",
+		MTK_EINT_FUNCTION(0, 66),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO66"),
+		MTK_FUNCTION(1, "O_SOUNDWIRE0_CK"),
+		MTK_FUNCTION(3, "I1_TP_UCTS0_VLP"),
+		MTK_FUNCTION(4, "O_SPI_HID_IRQ_S_MON0"),
+		MTK_FUNCTION(7, "O_VADSP_UTXD0")
+	),
+	MTK_PIN(
+		67, "GPIO67",
+		MTK_EINT_FUNCTION(0, 67),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO67"),
+		MTK_FUNCTION(1, "B0_SOUNDWIRE0_D0"),
+		MTK_FUNCTION(3, "O_TP_URTS0_VLP"),
+		MTK_FUNCTION(7, "I1_VADSP_URXD0")
+	),
+	MTK_PIN(
+		68, "GPIO68",
+		MTK_EINT_FUNCTION(0, 68),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO68"),
+		MTK_FUNCTION(1, "O_SCP_PWM_0_VLP"),
+		MTK_FUNCTION(2, "O_PWM_VLP"),
+		MTK_FUNCTION(3, "B0_TP_GPIO28_AO")
+	),
+	MTK_PIN(
+		69, "GPIO69",
+		MTK_EINT_FUNCTION(0, 69),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO69"),
+		MTK_FUNCTION(1, "B0_PAD_RESET_DRAM_8")
+	),
+	MTK_PIN(
+		70, "GPIO70",
+		MTK_EINT_FUNCTION(0, 70),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO70"),
+		MTK_FUNCTION(1, "B1_SCP_SCL0"),
+		MTK_FUNCTION(4, "I0_VADSP_JTAG0_TCK"),
+		MTK_FUNCTION(5, "I1_PCIE4_USB3_PAR_SCL"),
+		MTK_FUNCTION(6, "I1_SCP_JTAG0_TCK_VLP"),
+		MTK_FUNCTION(7, "B1_SROOT_SCL")
+	),
+	MTK_PIN(
+		71, "GPIO71",
+		MTK_EINT_FUNCTION(0, 71),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO71"),
+		MTK_FUNCTION(1, "B1_SCP_SDA0"),
+		MTK_FUNCTION(4, "I1_VADSP_JTAG0_TMS"),
+		MTK_FUNCTION(5, "B1_PCIE4_USB3_PAR_SDA"),
+		MTK_FUNCTION(6, "B1_SCP_JTAG0_TMS_VLP"),
+		MTK_FUNCTION(7, "B1_SROOT_SDA")
+	),
+	MTK_PIN(
+		72, "GPIO72",
+		MTK_EINT_FUNCTION(0, 72),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO72"),
+		MTK_FUNCTION(1, "B1_SCP_SCL2"),
+		MTK_FUNCTION(2, "B1_I3C_HCI_AO_SCL"),
+		MTK_FUNCTION(4, "I1_VADSP_JTAG0_TDI"),
+		MTK_FUNCTION(5, "I1_PCIE5_PAR_SCL"),
+		MTK_FUNCTION(6, "I1_SCP_JTAG0_TDI_VLP"),
+		MTK_FUNCTION(7, "O_OSROOT_UTX")
+	),
+	MTK_PIN(
+		73, "GPIO73",
+		MTK_EINT_FUNCTION(0, 73),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO73"),
+		MTK_FUNCTION(1, "B1_SCP_SDA2"),
+		MTK_FUNCTION(2, "B1_I3C_HCI_AO_SDA"),
+		MTK_FUNCTION(4, "O_VADSP_JTAG0_TDO"),
+		MTK_FUNCTION(5, "B1_PCIE5_PAR_SDA"),
+		MTK_FUNCTION(6, "O_SCP_JTAG0_TDO_VLP"),
+		MTK_FUNCTION(7, "I1_OSROOT_URX")
+	),
+	MTK_PIN(
+		74, "GPIO74",
+		MTK_EINT_FUNCTION(0, 74),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO74"),
+		MTK_FUNCTION(1, "I0_SCP_SPIS0_SCL"),
+		MTK_FUNCTION(2, "O_SPI2_CLK"),
+		MTK_FUNCTION(3, "O_SCP_SPIM0_CK"),
+		MTK_FUNCTION(4, "I1_SPM_JTAG_TCK_VLP"),
+		MTK_FUNCTION(5, "I1_SSPM_JTAG_TCK_VLP"),
+		MTK_FUNCTION(6, "I1_PBUD_CTRL_JTAG_TCK_VLP"),
+		MTK_FUNCTION(7, "I0_OSROOT_TCK")
+	),
+	MTK_PIN(
+		75, "GPIO75",
+		MTK_EINT_FUNCTION(0, 75),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO75"),
+		MTK_FUNCTION(1, "B0_SCP_SPIS0_SIO0"),
+		MTK_FUNCTION(2, "B0_SPI2_MI"),
+		MTK_FUNCTION(3, "B0_SCP_SPIM0_SIO0"),
+		MTK_FUNCTION(4, "I1_SPM_JTAG_TDI_VLP"),
+		MTK_FUNCTION(5, "I1_SSPM_JTAG_TDI_VLP"),
+		MTK_FUNCTION(6, "I1_PBUD_CTRL_JTAG_TDI_VLP"),
+		MTK_FUNCTION(7, "I0_OSROOT_TDI")
+	),
+	MTK_PIN(
+		76, "GPIO76",
+		MTK_EINT_FUNCTION(0, 76),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO76"),
+		MTK_FUNCTION(1, "B0_SCP_SPIS0_SIO1"),
+		MTK_FUNCTION(2, "B0_SPI2_MO"),
+		MTK_FUNCTION(3, "B0_SCP_SPIM0_SIO1"),
+		MTK_FUNCTION(4, "B1_SPM_JTAG_TDO_VLP"),
+		MTK_FUNCTION(5, "O_SSPM_JTAG_TDO_VLP"),
+		MTK_FUNCTION(6, "O_PBUD_CTRL_JTAG_TDO_VLP"),
+		MTK_FUNCTION(7, "O_OSROOT_TDO")
+	),
+	MTK_PIN(
+		77, "GPIO77",
+		MTK_EINT_FUNCTION(0, 77),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO77"),
+		MTK_FUNCTION(1, "B0_SCP_SPIS0_SIO2"),
+		MTK_FUNCTION(2, "B0_SPI2_WP"),
+		MTK_FUNCTION(3, "B0_SCP_SPIM0_SIO2"),
+		MTK_FUNCTION(4, "I1_SPM_JTAG_TMS_VLP"),
+		MTK_FUNCTION(5, "I1_SSPM_JTAG_TMS_VLP"),
+		MTK_FUNCTION(6, "I1_PBUD_CTRL_JTAG_TMS_VLP"),
+		MTK_FUNCTION(7, "I0_OSROOT_TMS")
+	),
+	MTK_PIN(
+		78, "GPIO78",
+		MTK_EINT_FUNCTION(0, 78),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO78"),
+		MTK_FUNCTION(1, "B0_SCP_SPIS0_SIO3"),
+		MTK_FUNCTION(2, "B0_SPI2_HOLD"),
+		MTK_FUNCTION(3, "B0_SCP_SPIM0_SIO3"),
+		MTK_FUNCTION(4, "I0_SPM_JTAG_TRSTN_VLP"),
+		MTK_FUNCTION(5, "I0_SSPM_JTAG_TRSTN_VLP"),
+		MTK_FUNCTION(6, "I0_PBUD_CTRL_JTAG_TRSTN_VLP"),
+		MTK_FUNCTION(7, "I0_OSROOT_NTRST")
+	),
+	MTK_PIN(
+		79, "GPIO79",
+		MTK_EINT_FUNCTION(0, 79),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO79"),
+		MTK_FUNCTION(1, "I1_SCP_SPIS0_CS"),
+		MTK_FUNCTION(2, "O_SPI2_CSB"),
+		MTK_FUNCTION(3, "O_SCP_SPIM0_CS"),
+		MTK_FUNCTION(4, "I1_VADSP_JTAG0_TRSTN"),
+		MTK_FUNCTION(6, "I0_SCP_JTAG0_TRSTN_VLP")
+	),
+	MTK_PIN(
+		80, "GPIO80",
+		MTK_EINT_FUNCTION(0, 80),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO80"),
+		MTK_FUNCTION(1, "O_SPI0_CLK"),
+		MTK_FUNCTION(2, "B0_SPI0_OSROOT_CLK"),
+		MTK_FUNCTION(4, "I1_SSPM_JTAG_TCK_VLP"),
+		MTK_FUNCTION(5, "I0_VADSP_JTAG0_TCK"),
+		MTK_FUNCTION(6, "I1_SPM_JTAG_TCK_VLP"),
+		MTK_FUNCTION(7, "I1_SCP_JTAG0_TCK_VLP")
+	),
+	MTK_PIN(
+		81, "GPIO81",
+		MTK_EINT_FUNCTION(0, 81),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO81"),
+		MTK_FUNCTION(1, "B0_SPI0_MI"),
+		MTK_FUNCTION(2, "I0_SPI0_OSROOT_MI"),
+		MTK_FUNCTION(4, "I1_SSPM_JTAG_TDI_VLP"),
+		MTK_FUNCTION(5, "I1_VADSP_JTAG0_TDI"),
+		MTK_FUNCTION(6, "I1_SPM_JTAG_TDI_VLP"),
+		MTK_FUNCTION(7, "I1_SCP_JTAG0_TDI_VLP")
+	),
+	MTK_PIN(
+		82, "GPIO82",
+		MTK_EINT_FUNCTION(0, 82),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO82"),
+		MTK_FUNCTION(1, "B0_SPI0_MO"),
+		MTK_FUNCTION(2, "O_SPI0_OSROOT_MO"),
+		MTK_FUNCTION(4, "O_SSPM_JTAG_TDO_VLP"),
+		MTK_FUNCTION(5, "O_VADSP_JTAG0_TDO"),
+		MTK_FUNCTION(6, "B1_SPM_JTAG_TDO_VLP"),
+		MTK_FUNCTION(7, "O_SCP_JTAG0_TDO_VLP")
+	),
+	MTK_PIN(
+		83, "GPIO83",
+		MTK_EINT_FUNCTION(0, 83),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO83"),
+		MTK_FUNCTION(1, "O_SPI0_CSB0"),
+		MTK_FUNCTION(2, "O_SPI0_OSROOT_CSB"),
+		MTK_FUNCTION(4, "I1_SSPM_JTAG_TMS_VLP"),
+		MTK_FUNCTION(5, "I1_VADSP_JTAG0_TMS"),
+		MTK_FUNCTION(6, "I1_SPM_JTAG_TMS_VLP"),
+		MTK_FUNCTION(7, "B1_SCP_JTAG0_TMS_VLP")
+	),
+	MTK_PIN(
+		84, "GPIO84",
+		MTK_EINT_FUNCTION(0, 84),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO84"),
+		MTK_FUNCTION(1, "O_SPI0_CSB1"),
+		MTK_FUNCTION(4, "I0_SSPM_JTAG_TRSTN_VLP"),
+		MTK_FUNCTION(5, "I1_VADSP_JTAG0_TRSTN"),
+		MTK_FUNCTION(6, "I0_SPM_JTAG_TRSTN_VLP"),
+		MTK_FUNCTION(7, "I0_SCP_JTAG0_TRSTN_VLP")
+	),
+	MTK_PIN(
+		85, "GPIO85",
+		MTK_EINT_FUNCTION(0, 85),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO85"),
+		MTK_FUNCTION(1, "O_DISP_PWM"),
+		MTK_FUNCTION(4, "B1_U4CP_JTAG_TMS"),
+		MTK_FUNCTION(5, "I0_CLUSTER0_UDI_TDI_1"),
+		MTK_FUNCTION(6, "I0_CLUSTER1_UDI_TDI_1"),
+		MTK_FUNCTION(7, "O_DBG_MON_A21")
+	),
+	MTK_PIN(
+		86, "GPIO86",
+		MTK_EINT_FUNCTION(0, 86),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO86"),
+		MTK_FUNCTION(1, "O_DISP_BL_EN"),
+		MTK_FUNCTION(4, "I1_U4CP_JTAG_TDI"),
+		MTK_FUNCTION(5, "O_CLUSTER0_UDI_TDO_1"),
+		MTK_FUNCTION(6, "O_CLUSTER1_UDI_TDO_1"),
+		MTK_FUNCTION(7, "O_DBG_MON_A22")
+	),
+	MTK_PIN(
+		87, "GPIO87",
+		MTK_EINT_FUNCTION(0, 87),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO87"),
+		MTK_FUNCTION(1, "B0_DISP_GPIO_N_1"),
+		MTK_FUNCTION(4, "O_U4CP_JTAG_TDO"),
+		MTK_FUNCTION(5, "I0_CLUSTER0_UDI_TDI_2"),
+		MTK_FUNCTION(6, "I0_CLUSTER1_UDI_TDI_2"),
+		MTK_FUNCTION(7, "O_DBG_MON_A23")
+	),
+	MTK_PIN(
+		88, "GPIO88",
+		MTK_EINT_FUNCTION(0, 88),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO88"),
+		MTK_FUNCTION(1, "B1_DISP_SCL1"),
+		MTK_FUNCTION(4, "I1_U4CP_JTAG_TCK"),
+		MTK_FUNCTION(5, "I1_EDP0_SCL"),
+		MTK_FUNCTION(6, "I1_HDMITX_DBG_I2C_SCL")
+	),
+	MTK_PIN(
+		89, "GPIO89",
+		MTK_EINT_FUNCTION(0, 89),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO89"),
+		MTK_FUNCTION(1, "B1_DISP_SDA1"),
+		MTK_FUNCTION(4, "I0_U4CP_JTAG_TRSTN"),
+		MTK_FUNCTION(5, "B1_EDP0_SDA"),
+		MTK_FUNCTION(6, "B1_HDMITX_DBG_I2C_SDA")
+	),
+	MTK_PIN(
+		90, "GPIO90",
+		MTK_EINT_FUNCTION(0, 90),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO90"),
+		MTK_FUNCTION(1, "B0_DISP_GPIO_N2"),
+		MTK_FUNCTION(4, "O_CLKM0_C"),
+		MTK_FUNCTION(5, "O_CLUSTER0_UDI_TDO_2"),
+		MTK_FUNCTION(6, "O_CLUSTER1_UDI_TDO_2"),
+		MTK_FUNCTION(7, "O_DBG_MON_A24")
+	),
+	MTK_PIN(
+		91, "GPIO91",
+		MTK_EINT_FUNCTION(0, 91),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO91"),
+		MTK_FUNCTION(1, "I0_DPAUX_HPD_IN_4"),
+		MTK_FUNCTION(4, "O_CLKM1_C"),
+		MTK_FUNCTION(5, "I0_CLUSTER0_UDI_TDI_3"),
+		MTK_FUNCTION(6, "I0_CLUSTER1_UDI_TDI_3"),
+		MTK_FUNCTION(7, "O_DBG_MON_A25")
+	),
+	MTK_PIN(
+		92, "GPIO92",
+		MTK_EINT_FUNCTION(0, 92),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO92"),
+		MTK_FUNCTION(1, "B1_I2C_SCL5"),
+		MTK_FUNCTION(2, "O_TP_UTXD0_VLP"),
+		MTK_FUNCTION(3, "O_SSPM_UTXD_AO_VLP"),
+		MTK_FUNCTION(4, "O_TSFDC_FOUT"),
+		MTK_FUNCTION(5, "O_CLUSTER0_UDI_TDO_3"),
+		MTK_FUNCTION(6, "O_CLUSTER1_UDI_TDO_3"),
+		MTK_FUNCTION(7, "O_DBG_MON_A26")
+	),
+	MTK_PIN(
+		93, "GPIO93",
+		MTK_EINT_FUNCTION(0, 93),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO93"),
+		MTK_FUNCTION(1, "B1_I2C_SDA5"),
+		MTK_FUNCTION(2, "I1_TP_URXD0_VLP"),
+		MTK_FUNCTION(3, "I1_SSPM_URXD_AO_VLP"),
+		MTK_FUNCTION(4, "O_TSFDC_SDO"),
+		MTK_FUNCTION(5, "I0_CLUSTER0_UDI_TDI_4"),
+		MTK_FUNCTION(6, "I0_CLUSTER1_UDI_TDI_4"),
+		MTK_FUNCTION(7, "O_DBG_MON_A27")
+	),
+	MTK_PIN(
+		94, "GPIO94",
+		MTK_EINT_FUNCTION(0, 94),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO94"),
+		MTK_FUNCTION(1, "O_CMFLASH0"),
+		MTK_FUNCTION(4, "I0_TSFDC_26M"),
+		MTK_FUNCTION(5, "O_CLUSTER0_UDI_TDO_4"),
+		MTK_FUNCTION(6, "O_CLUSTER1_UDI_TDO_4"),
+		MTK_FUNCTION(7, "O_DBG_MON_A28")
+	),
+	MTK_PIN(
+		95, "GPIO95",
+		MTK_EINT_FUNCTION(0, 95),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO95"),
+		MTK_FUNCTION(1, "O_CMFLASH1"),
+		MTK_FUNCTION(4, "I0_TSFDC_SCF"),
+		MTK_FUNCTION(5, "I0_CLUSTER0_UDI_TDI_5"),
+		MTK_FUNCTION(6, "I0_CLUSTER1_UDI_TDI_5"),
+		MTK_FUNCTION(7, "O_DBG_MON_A29")
+	),
+	MTK_PIN(
+		96, "GPIO96",
+		MTK_EINT_FUNCTION(0, 96),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO96"),
+		MTK_FUNCTION(1, "O_CMVREF0"),
+		MTK_FUNCTION(2, "O_CMFLASH1"),
+		MTK_FUNCTION(4, "I0_TSFDC_SCK"),
+		MTK_FUNCTION(5, "O_CLUSTER0_UDI_TDO_5"),
+		MTK_FUNCTION(6, "O_CLUSTER1_UDI_TDO_5"),
+		MTK_FUNCTION(7, "O_DBG_MON_A30")
+	),
+	MTK_PIN(
+		97, "GPIO97",
+		MTK_EINT_FUNCTION(0, 97),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO97"),
+		MTK_FUNCTION(1, "O_CMVREF1"),
+		MTK_FUNCTION(2, "O_CMFLASH0"),
+		MTK_FUNCTION(4, "I0_TSFDC_SDI"),
+		MTK_FUNCTION(5, "I0_CLUSTER0_UDI_TDI_6"),
+		MTK_FUNCTION(6, "I0_CLUSTER1_UDI_TDI_6"),
+		MTK_FUNCTION(7, "O_U4CP_UTXD")
+	),
+	MTK_PIN(
+		98, "GPIO98",
+		MTK_EINT_FUNCTION(0, 98),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO98"),
+		MTK_FUNCTION(2, "O_CMFLASH2"),
+		MTK_FUNCTION(4, "I0_RG_TSFDC_LDO_EN"),
+		MTK_FUNCTION(5, "O_CLUSTER0_UDI_TDO_6"),
+		MTK_FUNCTION(6, "O_CLUSTER1_UDI_TDO_6"),
+		MTK_FUNCTION(7, "I1_U4CP_URXD")
+	),
+	MTK_PIN(
+		99, "GPIO99",
+		MTK_EINT_FUNCTION(0, 99),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO99"),
+		MTK_FUNCTION(1, "I0_MCU_M_PMIC_POC_I"),
+		MTK_FUNCTION(4, "I0_DA_TSFDC_LDO_MODE"),
+		MTK_FUNCTION(5, "I0_CLUSTER0_UDI_TDI_7"),
+		MTK_FUNCTION(6, "I0_CLUSTER1_UDI_TDI_7"),
+		MTK_FUNCTION(7, "O_U4CP_URTS")
+	),
+	MTK_PIN(
+		100, "GPIO100",
+		MTK_EINT_FUNCTION(0, 100),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO100"),
+		MTK_FUNCTION(1, "I0_MCU_B_PMIC_POC_I"),
+		MTK_FUNCTION(4, "I0_RG_TSFDC_LDO_REFSEL1"),
+		MTK_FUNCTION(5, "O_CLUSTER0_UDI_TDO_7"),
+		MTK_FUNCTION(6, "O_CLUSTER1_UDI_TDO_7"),
+		MTK_FUNCTION(7, "I1_U4CP_UCTS")
+	),
+	MTK_PIN(
+		101, "GPIO101",
+		MTK_EINT_FUNCTION(0, 101),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO101"),
+		MTK_FUNCTION(1, "O_CMFLASH2"),
+		MTK_FUNCTION(2, "O_CMVREF1"),
+		MTK_FUNCTION(3, "I1_UCTS0"),
+		MTK_FUNCTION(4, "I0_RG_TSFDC_LDO_REFSEL0"),
+		MTK_FUNCTION(5, "I1_U4CP_JTAG_TCK"),
+		MTK_FUNCTION(6, "I1_PBUD_CTRL_JTAG_TCK_VCORE"),
+		MTK_FUNCTION(7, "O_CLKM0_A")
+	),
+	MTK_PIN(
+		102, "GPIO102",
+		MTK_EINT_FUNCTION(0, 102),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO102"),
+		MTK_FUNCTION(1, "O_CMFLASH3"),
+		MTK_FUNCTION(2, "O_CMVREF0"),
+		MTK_FUNCTION(3, "O_URTS0"),
+		MTK_FUNCTION(4, "O_TSFDC_BG_COMP"),
+		MTK_FUNCTION(5, "B1_U4CP_JTAG_TMS"),
+		MTK_FUNCTION(6, "I1_PBUD_CTRL_JTAG_TMS_VCORE"),
+		MTK_FUNCTION(7, "O_CLKM1_A")
+	),
+	MTK_PIN(
+		103, "GPIO103",
+		MTK_EINT_FUNCTION(0, 103),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO103"),
+		MTK_FUNCTION(1, "O_CMVREF2"),
+		MTK_FUNCTION(2, "O_UTXD0"),
+		MTK_FUNCTION(4, "O_CLKM2_B"),
+		MTK_FUNCTION(5, "I1_U4CP_JTAG_TDI"),
+		MTK_FUNCTION(6, "I1_PBUD_CTRL_JTAG_TDI_VCORE"),
+		MTK_FUNCTION(7, "O_CLKM2_A")
+	),
+	MTK_PIN(
+		104, "GPIO104",
+		MTK_EINT_FUNCTION(0, 104),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO104"),
+		MTK_FUNCTION(1, "O_CMVREF3"),
+		MTK_FUNCTION(2, "I1_URXD0"),
+		MTK_FUNCTION(4, "O_CLKM3_B"),
+		MTK_FUNCTION(5, "O_U4CP_JTAG_TDO"),
+		MTK_FUNCTION(6, "O_PBUD_CTRL_JTAG_TDO_VCORE"),
+		MTK_FUNCTION(7, "O_CLKM3_A")
+	),
+	MTK_PIN(
+		105, "GPIO105",
+		MTK_EINT_FUNCTION(0, 105),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO105"),
+		MTK_FUNCTION(2, "O_CMFLASH3"),
+		MTK_FUNCTION(4, "O_CLKM0_B"),
+		MTK_FUNCTION(5, "I0_U4CP_JTAG_TRSTN"),
+		MTK_FUNCTION(6, "I0_PBUD_CTRL_JTAG_TRSTN_VCORE"),
+		MTK_FUNCTION(7, "O_PMSR_SMAP")
+	),
+	MTK_PIN(
+		106, "GPIO106",
+		MTK_EINT_FUNCTION(0, 106),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO106"),
+		MTK_FUNCTION(1, "B0_SPINOR_CK")
+	),
+	MTK_PIN(
+		107, "GPIO107",
+		MTK_EINT_FUNCTION(0, 107),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO107"),
+		MTK_FUNCTION(1, "B0_SPINOR_IO0")
+	),
+	MTK_PIN(
+		108, "GPIO108",
+		MTK_EINT_FUNCTION(0, 108),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO108"),
+		MTK_FUNCTION(1, "B0_SPINOR_IO1")
+	),
+	MTK_PIN(
+		109, "GPIO109",
+		MTK_EINT_FUNCTION(0, 109),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO109"),
+		MTK_FUNCTION(1, "B0_SPINOR_IO2")
+	),
+	MTK_PIN(
+		110, "GPIO110",
+		MTK_EINT_FUNCTION(0, 110),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO110"),
+		MTK_FUNCTION(1, "B0_SPINOR_IO3")
+	),
+	MTK_PIN(
+		111, "GPIO111",
+		MTK_EINT_FUNCTION(0, 111),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO111"),
+		MTK_FUNCTION(1, "B1_SPINOR_CS")
+	),
+	MTK_PIN(
+		112, "GPIO112",
+		MTK_EINT_FUNCTION(0, 112),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO112"),
+		MTK_FUNCTION(1, "O_SPI1_CLK"),
+		MTK_FUNCTION(5, "I1_HFRP_JTAG1_TCK")
+	),
+	MTK_PIN(
+		113, "GPIO113",
+		MTK_EINT_FUNCTION(0, 113),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO113"),
+		MTK_FUNCTION(1, "B0_SPI1_MI"),
+		MTK_FUNCTION(5, "I1_HFRP_JTAG1_TMS")
+	),
+	MTK_PIN(
+		114, "GPIO114",
+		MTK_EINT_FUNCTION(0, 114),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO114"),
+		MTK_FUNCTION(1, "B0_SPI1_MO"),
+		MTK_FUNCTION(5, "I1_HFRP_JTAG1_TDI")
+	),
+	MTK_PIN(
+		115, "GPIO115",
+		MTK_EINT_FUNCTION(0, 115),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO115"),
+		MTK_FUNCTION(1, "O_SPI1_CSB0"),
+		MTK_FUNCTION(5, "O_HFRP_JTAG1_TDO")
+	),
+	MTK_PIN(
+		116, "GPIO116",
+		MTK_EINT_FUNCTION(0, 116),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO116"),
+		MTK_FUNCTION(1, "O_SPI1_CSB1"),
+		MTK_FUNCTION(5, "I0_HFRP_JTAG1_TRSTN")
+	),
+	MTK_PIN(
+		117, "GPIO117",
+		MTK_EINT_FUNCTION(0, 117),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO117"),
+		MTK_FUNCTION(1, "B1_I2C_SCL1"),
+		MTK_FUNCTION(2, "B1_OSROOT_SCL"),
+		MTK_FUNCTION(4, "O_SPI_CS_S_MON0"),
+		MTK_FUNCTION(5, "I1_USB4_L_PAR_SCL"),
+		MTK_FUNCTION(6, "I1_CKM_SCL"),
+		MTK_FUNCTION(7, "I1_USB4_R_PAR_SCL")
+	),
+	MTK_PIN(
+		118, "GPIO118",
+		MTK_EINT_FUNCTION(0, 118),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO118"),
+		MTK_FUNCTION(1, "B1_I2C_SDA1"),
+		MTK_FUNCTION(2, "B1_OSROOT_SDA"),
+		MTK_FUNCTION(4, "O_SPI_SCL_S_MON0"),
+		MTK_FUNCTION(5, "B1_USB4_L_PAR_SDA"),
+		MTK_FUNCTION(6, "B1_CKM_SDA"),
+		MTK_FUNCTION(7, "B1_USB4_R_PAR_SDA")
+	),
+	MTK_PIN(
+		119, "GPIO119",
+		MTK_EINT_FUNCTION(0, 119),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO119"),
+		MTK_FUNCTION(1, "B1_I2C_SCL2"),
+		MTK_FUNCTION(4, "I1_HDMITX_DBG_I2C_SCL"),
+		MTK_FUNCTION(5, "O_CLUSTER0_MBISTREADEN_TRIGGER"),
+		MTK_FUNCTION(6, "O_CLUSTER1_MBISTREADEN_TRIGGER"),
+		MTK_FUNCTION(7, "O_PMSR_SMAP_MAX")
+	),
+	MTK_PIN(
+		120, "GPIO120",
+		MTK_EINT_FUNCTION(0, 120),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO120"),
+		MTK_FUNCTION(1, "B1_I2C_SDA2+J130_S133"),
+		MTK_FUNCTION(4, "B1_HDMITX_DBG_I2C_SDA"),
+		MTK_FUNCTION(5, "O_CLUSTER0_MBISTWRITEEN_TRIGGER"),
+		MTK_FUNCTION(6, "O_CLUSTER1_MBISTWRITEEN_TRIGGER"),
+		MTK_FUNCTION(7, "O_PMSR_SMAP_MAX_W")
+	),
+	MTK_PIN(
+		121, "GPIO121",
+		MTK_EINT_FUNCTION(0, 121),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO121"),
+		MTK_FUNCTION(1, "B1_I3C_SCL0"),
+		MTK_FUNCTION(2, "B1_I3C_HCI_0_AO_SCL"),
+		MTK_FUNCTION(4, "I1_PCIE5_PAR_SCL"),
+		MTK_FUNCTION(5, "O_CLUSTER0_AD_ILDO_DTEST0"),
+		MTK_FUNCTION(6, "O_CLUSTER1_AD_ILDO_DTEST0"),
+		MTK_FUNCTION(7, "I1_USB4_R_PAR_SCL")
+	),
+	MTK_PIN(
+		122, "GPIO122",
+		MTK_EINT_FUNCTION(0, 122),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO122"),
+		MTK_FUNCTION(1, "B1_I3C_SDA0"),
+		MTK_FUNCTION(2, "B1_I3C_HCI_0_AO_SDA"),
+		MTK_FUNCTION(4, "B1_PCIE5_PAR_SDA"),
+		MTK_FUNCTION(5, "O_CLUSTER0_AD_ILDO_DTEST1"),
+		MTK_FUNCTION(6, "O_CLUSTER1_AD_ILDO_DTEST1"),
+		MTK_FUNCTION(7, "B1_USB4_R_PAR_SDA")
+	),
+	MTK_PIN(
+		123, "GPIO123",
+		MTK_EINT_FUNCTION(0, 123),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO123"),
+		MTK_FUNCTION(1, "B1_I3C_SCL1"),
+		MTK_FUNCTION(2, "B1_I3C_HCI_1_AO_SCL"),
+		MTK_FUNCTION(4, "I1_PCIE4_USB3_PAR_SCL"),
+		MTK_FUNCTION(5, "O_CLUSTER0_AD_ILDO_DTEST2"),
+		MTK_FUNCTION(6, "O_CLUSTER1_AD_ILDO_DTEST2"),
+		MTK_FUNCTION(7, "O_VADSP_UTXD0")
+	),
+	MTK_PIN(
+		124, "GPIO124",
+		MTK_EINT_FUNCTION(0, 124),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO124"),
+		MTK_FUNCTION(1, "B1_I3C_SDA1"),
+		MTK_FUNCTION(2, "B1_I3C_HCI_1_AO_SDA"),
+		MTK_FUNCTION(4, "B1_PCIE4_USB3_PAR_SDA"),
+		MTK_FUNCTION(5, "O_CLUSTER0_AD_ILDO_DTEST3"),
+		MTK_FUNCTION(6, "O_CLUSTER1_AD_ILDO_DTEST3"),
+		MTK_FUNCTION(7, "I1_VADSP_URXD0")
+	),
+	MTK_PIN(
+		125, "GPIO125",
+		MTK_EINT_FUNCTION(0, 125),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO125"),
+		MTK_FUNCTION(1, "O_I2SIN_1_MCK"),
+		MTK_FUNCTION(4, "I0_TSFDC_SCK"),
+		MTK_FUNCTION(6, "O_CLKM2_C")
+	),
+	MTK_PIN(
+		126, "GPIO126",
+		MTK_EINT_FUNCTION(0, 126),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO126"),
+		MTK_FUNCTION(1, "O_SOUNDWIRE1_CK"),
+		MTK_FUNCTION(2, "O_I2SIN_1_BCK"),
+		MTK_FUNCTION(4, "O_CLUSTER0_AD_ILDO_DTEST4"),
+		MTK_FUNCTION(5, "O_CLUSTER1_AD_ILDO_DTEST4"),
+		MTK_FUNCTION(6, "I0_ADSP_JTAG0_TCK"),
+		MTK_FUNCTION(7, "I1_HFRP_JTAG0_TCK")
+	),
+	MTK_PIN(
+		127, "GPIO127",
+		MTK_EINT_FUNCTION(0, 127),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO127"),
+		MTK_FUNCTION(1, "B0_SOUNDWIRE1_D0"),
+		MTK_FUNCTION(2, "O_I2SOUT1_DO"),
+		MTK_FUNCTION(4, "O_CLUSTER0_AD_ILDO_DTEST5"),
+		MTK_FUNCTION(5, "O_CLUSTER1_AD_ILDO_DTEST5"),
+		MTK_FUNCTION(6, "I1_ADSP_JTAG0_TMS"),
+		MTK_FUNCTION(7, "B1_HFRP_JTAG0_TMS")
+	),
+	MTK_PIN(
+		128, "GPIO128",
+		MTK_EINT_FUNCTION(0, 128),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO128"),
+		MTK_FUNCTION(1, "B0_SOUNDWIRE1_D1"),
+		MTK_FUNCTION(2, "I0_I2SIN_1_DI"),
+		MTK_FUNCTION(4, "O_CLUSTER0_AD_ILDO_DTEST6"),
+		MTK_FUNCTION(5, "O_CLUSTER1_AD_ILDO_DTEST6"),
+		MTK_FUNCTION(6, "I1_ADSP_JTAG0_TDI"),
+		MTK_FUNCTION(7, "I1_HFRP_JTAG0_TDI")
+	),
+	MTK_PIN(
+		129, "GPIO129",
+		MTK_EINT_FUNCTION(0, 129),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO129"),
+		MTK_FUNCTION(1, "B0_SOUNDWIRE1_D2"),
+		MTK_FUNCTION(2, "O_I2SIN_1_LRCK"),
+		MTK_FUNCTION(4, "O_CLUSTER0_AD_ILDO_DTEST7"),
+		MTK_FUNCTION(5, "O_CLUSTER1_AD_ILDO_DTEST7"),
+		MTK_FUNCTION(6, "O_ADSP_JTAG0_TDO"),
+		MTK_FUNCTION(7, "O_HFRP_JTAG0_TDO")
+	),
+	MTK_PIN(
+		130, "GPIO130",
+		MTK_EINT_FUNCTION(0, 130),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO130"),
+		MTK_FUNCTION(1, "B0_I2SIN0_BCK"),
+		MTK_FUNCTION(3, "O_DISP_CLKM0"),
+		MTK_FUNCTION(4, "I0_TSFDC_26M"),
+		MTK_FUNCTION(5, "I0_RG_TSFDC_LDO_EN"),
+		MTK_FUNCTION(6, "O_CCU0_URTS"),
+		MTK_FUNCTION(7, "O_DBG_MON_B4")
+	),
+	MTK_PIN(
+		131, "GPIO131",
+		MTK_EINT_FUNCTION(0, 131),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO131"),
+		MTK_FUNCTION(1, "I0_I2SIN0_DI"),
+		MTK_FUNCTION(3, "O_DISP_CLKM1"),
+		MTK_FUNCTION(4, "O_TSFDC_FOUT"),
+		MTK_FUNCTION(5, "I0_DA_TSFDC_LDO_MODE"),
+		MTK_FUNCTION(6, "I1_CCU0_UCTS"),
+		MTK_FUNCTION(7, "O_DBG_MON_B5")
+	),
+	MTK_PIN(
+		132, "GPIO132",
+		MTK_EINT_FUNCTION(0, 132),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO132"),
+		MTK_FUNCTION(1, "O_I2SOUT0_DO"),
+		MTK_FUNCTION(3, "O_DISP_CLKM2"),
+		MTK_FUNCTION(4, "O_TSFDC_SDO"),
+		MTK_FUNCTION(5, "I0_RG_TSFDC_LDO_REFSEL1"),
+		MTK_FUNCTION(6, "O_CCU1_URTS"),
+		MTK_FUNCTION(7, "O_DBG_MON_B6")
+	),
+	MTK_PIN(
+		133, "GPIO133",
+		MTK_EINT_FUNCTION(0, 133),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO133"),
+		MTK_FUNCTION(1, "B0_I2SIN0_LRCK"),
+		MTK_FUNCTION(3, "O_DISP_CLKM3"),
+		MTK_FUNCTION(4, "I0_TSFDC_SCF"),
+		MTK_FUNCTION(5, "I0_RG_TSFDC_LDO_REFSEL0"),
+		MTK_FUNCTION(6, "I1_CCU1_UCTS"),
+		MTK_FUNCTION(7, "O_DBG_MON_B7")
+	),
+	MTK_PIN(
+		134, "GPIO134",
+		MTK_EINT_FUNCTION(0, 134),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO134"),
+		MTK_FUNCTION(1, "B1_SCP_SCL1"),
+		MTK_FUNCTION(2, "B1_VADSP_SCL0"),
+		MTK_FUNCTION(3, "B1_SROOT_SCL"),
+		MTK_FUNCTION(4, "O_SSPM_UTXD_AO_VLP"),
+		MTK_FUNCTION(5, "O_SPI_HID_IRQ_S_MON0"),
+		MTK_FUNCTION(6, "I1_ADSP_JTAG0_TRSTN"),
+		MTK_FUNCTION(7, "O_DBG_MON_B8")
+	),
+	MTK_PIN(
+		135, "GPIO135",
+		MTK_EINT_FUNCTION(0, 135),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO135"),
+		MTK_FUNCTION(1, "B1_SCP_SDA1"),
+		MTK_FUNCTION(2, "B1_VADSP_SDA0"),
+		MTK_FUNCTION(3, "B1_SROOT_SDA"),
+		MTK_FUNCTION(4, "I1_SSPM_URXD_AO_VLP"),
+		MTK_FUNCTION(7, "O_DBG_MON_B9")
+	),
+	MTK_PIN(
+		136, "GPIO136",
+		MTK_EINT_FUNCTION(0, 136),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO136"),
+		MTK_FUNCTION(1, "O_CMVREF2"),
+		MTK_FUNCTION(2, "B1_SCP_SCL3"),
+		MTK_FUNCTION(3, "B1_VADSP_SCL0"),
+		MTK_FUNCTION(4, "B1_SCP_SCL1"),
+		MTK_FUNCTION(5, "I1_MD32_8_RXD"),
+		MTK_FUNCTION(6, "I1_MD32_9_RXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_B10")
+	),
+	MTK_PIN(
+		137, "GPIO137",
+		MTK_EINT_FUNCTION(0, 137),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO137"),
+		MTK_FUNCTION(1, "O_CMVREF3"),
+		MTK_FUNCTION(2, "B1_SCP_SDA3"),
+		MTK_FUNCTION(3, "B1_VADSP_SDA0"),
+		MTK_FUNCTION(4, "B1_SCP_SDA1"),
+		MTK_FUNCTION(5, "O_MD32_8_GPIO0"),
+		MTK_FUNCTION(6, "O_MD32_9_GPIO0"),
+		MTK_FUNCTION(7, "O_DBG_MON_B11")
+	),
+	MTK_PIN(
+		138, "GPIO138",
+		MTK_EINT_FUNCTION(0, 138),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO138"),
+		MTK_FUNCTION(1, "B0_DISP_GPIO_N3"),
+		MTK_FUNCTION(2, "I0_DISP_LSPII"),
+		MTK_FUNCTION(4, "O_CLKM1_B"),
+		MTK_FUNCTION(5, "O_MD32_8_TXD"),
+		MTK_FUNCTION(6, "O_MD32_9_TXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_B12")
+	),
+	MTK_PIN(
+		139, "GPIO139",
+		MTK_EINT_FUNCTION(0, 139),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO139"),
+		MTK_FUNCTION(1, "B0_DISP_GPIO_N4"),
+		MTK_FUNCTION(2, "O_DISP_HSYNC0"),
+		MTK_FUNCTION(3, "O_DISP_HSYNC1"),
+		MTK_FUNCTION(4, "O_CLKM0_A"),
+		MTK_FUNCTION(5, "O_CLKM0_B"),
+		MTK_FUNCTION(6, "O_CLKM0_C"),
+		MTK_FUNCTION(7, "O_DBG_MON_B13")
+	),
+	MTK_PIN(
+		140, "GPIO140",
+		MTK_EINT_FUNCTION(0, 140),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO140"),
+		MTK_FUNCTION(1, "B0_DISP_GPIO_N5"),
+		MTK_FUNCTION(2, "O_DISP_VSYNC0"),
+		MTK_FUNCTION(3, "O_DISP_VSYNC1"),
+		MTK_FUNCTION(4, "O_CLKM1_A"),
+		MTK_FUNCTION(5, "O_CLKM1_B"),
+		MTK_FUNCTION(6, "O_CLKM1_C"),
+		MTK_FUNCTION(7, "O_DBG_MON_A14")
+	),
+	MTK_PIN(
+		141, "GPIO141",
+		MTK_EINT_FUNCTION(0, 141),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO141"),
+		MTK_FUNCTION(1, "B0_DISP_GPIO_N6"),
+		MTK_FUNCTION(2, "O_DISP_HSYNC2"),
+		MTK_FUNCTION(3, "O_DISP_HSYNC3"),
+		MTK_FUNCTION(4, "O_CLKM2_A"),
+		MTK_FUNCTION(5, "O_CLKM2_B"),
+		MTK_FUNCTION(6, "O_CLKM2_C"),
+		MTK_FUNCTION(7, "O_DBG_MON_A15")
+	),
+	MTK_PIN(
+		142, "GPIO142",
+		MTK_EINT_FUNCTION(0, 142),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO142"),
+		MTK_FUNCTION(1, "B0_DISP_GPIO_N7"),
+		MTK_FUNCTION(2, "O_DISP_VSYNC2"),
+		MTK_FUNCTION(3, "O_DISP_VSYNC3"),
+		MTK_FUNCTION(4, "O_CLKM3_A"),
+		MTK_FUNCTION(5, "O_CLKM3_B"),
+		MTK_FUNCTION(6, "O_CLKM3_C"),
+		MTK_FUNCTION(7, "O_DBG_MON_A16")
+	),
+	MTK_PIN(
+		143, "GPIO143",
+		MTK_EINT_FUNCTION(0, 143),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO143"),
+		MTK_FUNCTION(1, "I0_MCU_M_PMIC_POC_I"),
+		MTK_FUNCTION(2, "I0_JTCK_SEL1"),
+		MTK_FUNCTION(3, "O_JTAGAP_JTCK"),
+		MTK_FUNCTION(4, "I0_ADSP_JTAG1_TCK"),
+		MTK_FUNCTION(5, "I0_ADSP_JTAG0_TCK"),
+		MTK_FUNCTION(6, "I0_CLUSTER0_UDI_TCK"),
+		MTK_FUNCTION(7, "I0_CLUSTER1_UDI_TCK")
+	),
+	MTK_PIN(
+		144, "GPIO144",
+		MTK_EINT_FUNCTION(0, 144),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO144"),
+		MTK_FUNCTION(1, "I0_MCU_B_PMIC_POC_I"),
+		MTK_FUNCTION(2, "B1_JTMS_SEL1"),
+		MTK_FUNCTION(3, "O_JTAGAP_JTMS"),
+		MTK_FUNCTION(4, "I1_ADSP_JTAG1_TMS"),
+		MTK_FUNCTION(5, "I1_ADSP_JTAG0_TMS"),
+		MTK_FUNCTION(6, "I0_CLUSTER0_UDI_TMS"),
+		MTK_FUNCTION(7, "I0_CLUSTER1_UDI_TMS")
+	),
+	MTK_PIN(
+		145, "GPIO145",
+		MTK_EINT_FUNCTION(0, 145),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO145"),
+		MTK_FUNCTION(1, "I1_UCTS0"),
+		MTK_FUNCTION(2, "I1_JTDI_SEL1"),
+		MTK_FUNCTION(3, "O_JTAGAP_JTDI"),
+		MTK_FUNCTION(4, "I1_ADSP_JTAG1_TDI"),
+		MTK_FUNCTION(5, "I1_ADSP_JTAG0_TDI"),
+		MTK_FUNCTION(6, "I0_CLUSTER0_UDI_TDI_0"),
+		MTK_FUNCTION(7, "I0_CLUSTER1_UDI_TDI_0")
+	),
+	MTK_PIN(
+		146, "GPIO146",
+		MTK_EINT_FUNCTION(0, 146),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO146"),
+		MTK_FUNCTION(1, "O_URTS0"),
+		MTK_FUNCTION(2, "O_JTDO_SEL1"),
+		MTK_FUNCTION(3, "I0_JTAGAP_JTDO"),
+		MTK_FUNCTION(4, "O_ADSP_JTAG1_TDO"),
+		MTK_FUNCTION(5, "O_ADSP_JTAG0_TDO"),
+		MTK_FUNCTION(6, "O_CLUSTER0_UDI_TDO_0"),
+		MTK_FUNCTION(7, "O_CLUSTER1_UDI_TDO_0")
+	),
+	MTK_PIN(
+		147, "GPIO147",
+		MTK_EINT_FUNCTION(0, 147),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO147"),
+		MTK_FUNCTION(2, "I1_JTRSTn_SEL1"),
+		MTK_FUNCTION(3, "O_JTAGAP_JTRSTn"),
+		MTK_FUNCTION(4, "I1_ADSP_JTAG1_TRSTN"),
+		MTK_FUNCTION(5, "I1_ADSP_JTAG0_TRSTN"),
+		MTK_FUNCTION(6, "I0_CLUSTER0_UDI_NTRST"),
+		MTK_FUNCTION(7, "I0_CLUSTER1_UDI_NTRST")
+	),
+	MTK_PIN(
+		148, "GPIO148",
+		MTK_EINT_FUNCTION(0, 148),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO148"),
+		MTK_FUNCTION(1, "O_SRCLKENA0")
+	),
+	MTK_PIN(
+		149, "GPIO149",
+		MTK_EINT_FUNCTION(0, 149),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO149"),
+		MTK_FUNCTION(1, "O_SRCLKENA1")
+	),
+	MTK_PIN(
+		150, "GPIO150",
+		MTK_EINT_FUNCTION(0, 150),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO150"),
+		MTK_FUNCTION(2, "O_NVJTAG_SEL"),
+		MTK_FUNCTION(4, "I0_TSFDC_SDI"),
+		MTK_FUNCTION(5, "O_TSFDC_BG_COMP"),
+		MTK_FUNCTION(6, "O_CLKM3_C"),
+		MTK_FUNCTION(7, "I0_HFRP_JTAG0_TRSTN")
+	),
+	MTK_PIN(
+		151, "GPIO151",
+		MTK_EINT_FUNCTION(0, 151),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO151"),
+		MTK_FUNCTION(1, "I1_JTRSTn_SEL1"),
+		MTK_FUNCTION(2, "O_JTAGAP_JTRSTn"),
+		MTK_FUNCTION(6, "I0_HFRP_JTAG1_TRSTN"),
+		MTK_FUNCTION(7, "I1_ADSP_JTAG1_TRSTN")
+	),
+	MTK_PIN(
+		152, "GPIO152",
+		MTK_EINT_FUNCTION(0, 152),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO152"),
+		MTK_FUNCTION(1, "B1_JTMS_SEL1"),
+		MTK_FUNCTION(2, "O_JTAGAP_JTMS"),
+		MTK_FUNCTION(6, "I1_HFRP_JTAG1_TMS"),
+		MTK_FUNCTION(7, "I1_ADSP_JTAG1_TMS")
+	),
+	MTK_PIN(
+		153, "GPIO153",
+		MTK_EINT_FUNCTION(0, 153),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO153"),
+		MTK_FUNCTION(1, "O_JTDO_SEL1"),
+		MTK_FUNCTION(2, "I0_JTAGAP_JTDO"),
+		MTK_FUNCTION(6, "O_HFRP_JTAG1_TDO"),
+		MTK_FUNCTION(7, "O_ADSP_JTAG1_TDO")
+	),
+	MTK_PIN(
+		154, "GPIO154",
+		MTK_EINT_FUNCTION(0, 154),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO154"),
+		MTK_FUNCTION(1, "I0_JTCK_SEL1"),
+		MTK_FUNCTION(2, "O_JTAGAP_JTCK"),
+		MTK_FUNCTION(6, "I1_HFRP_JTAG1_TCK"),
+		MTK_FUNCTION(7, "I0_ADSP_JTAG1_TCK")
+	),
+	MTK_PIN(
+		155, "GPIO155",
+		MTK_EINT_FUNCTION(0, 155),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO155"),
+		MTK_FUNCTION(1, "I1_JTDI_SEL1"),
+		MTK_FUNCTION(2, "O_JTAGAP_JTDI"),
+		MTK_FUNCTION(6, "I1_HFRP_JTAG1_TDI"),
+		MTK_FUNCTION(7, "I1_ADSP_JTAG1_TDI")
+	),
+	MTK_PIN(
+		156, "GPIO156",
+		MTK_EINT_FUNCTION(0, 156),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO156"),
+		MTK_FUNCTION(1, "O_TP_UTXD0_VLP"),
+		MTK_FUNCTION(2, "O_UTXD3"),
+		MTK_FUNCTION(3, "O_VADSP_UTXD1"),
+		MTK_FUNCTION(4, "O_SPI_SIO0_S_MON0"),
+		MTK_FUNCTION(5, "O_ADSP_UTXD1"),
+		MTK_FUNCTION(6, "I0_SROOT_TCK"),
+		MTK_FUNCTION(7, "O_OSROOT_UTX")
+	),
+	MTK_PIN(
+		157, "GPIO157",
+		MTK_EINT_FUNCTION(0, 157),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO157"),
+		MTK_FUNCTION(1, "I1_TP_URXD0_VLP"),
+		MTK_FUNCTION(2, "I1_URXD3"),
+		MTK_FUNCTION(3, "I1_VADSP_URXD1"),
+		MTK_FUNCTION(4, "O_SPI_SIO1_S_MON0"),
+		MTK_FUNCTION(5, "I1_ADSP_URXD1"),
+		MTK_FUNCTION(6, "I0_SROOT_TDI"),
+		MTK_FUNCTION(7, "I1_OSROOT_URX")
+	),
+	MTK_PIN(
+		158, "GPIO158",
+		MTK_EINT_FUNCTION(0, 158),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO158"),
+		MTK_FUNCTION(1, "O_TP_URTS0_VLP"),
+		MTK_FUNCTION(2, "O_URTS3"),
+		MTK_FUNCTION(3, "O_VADSP_URTS1"),
+		MTK_FUNCTION(4, "O_SPI_SIO2_S_MON0"),
+		MTK_FUNCTION(5, "O_ADSP_URTX1"),
+		MTK_FUNCTION(6, "O_SROOT_TDO"),
+		MTK_FUNCTION(7, "O_PBUD_CTRL_UTXD_AO_VLP")
+	),
+	MTK_PIN(
+		159, "GPIO159",
+		MTK_EINT_FUNCTION(0, 159),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO159"),
+		MTK_FUNCTION(1, "I1_TP_UCTS0_VLP"),
+		MTK_FUNCTION(2, "I1_UCTS3"),
+		MTK_FUNCTION(3, "I1_VADSP_UCTS1"),
+		MTK_FUNCTION(4, "O_SPI_SIO3_S_MON0"),
+		MTK_FUNCTION(5, "I1_ADSP_UCTS1"),
+		MTK_FUNCTION(6, "I0_SROOT_TMS"),
+		MTK_FUNCTION(7, "I1_PBUD_CTRL_URXD_AO_VLP")
+	),
+	MTK_PIN(
+		160, "GPIO160",
+		MTK_EINT_FUNCTION(0, 160),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO160"),
+		MTK_FUNCTION(1, "O_UTXD1"),
+		MTK_FUNCTION(2, "O_ADSP_UTXD1"),
+		MTK_FUNCTION(3, "O_HFRP_UTXD1"),
+		MTK_FUNCTION(4, "O_CCU1_UTXD"),
+		MTK_FUNCTION(5, "O_PBUD_CTRL_UTXD_AO_VCORE"),
+		MTK_FUNCTION(6, "O_U4CP_UTXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_B14")
+	),
+	MTK_PIN(
+		161, "GPIO161",
+		MTK_EINT_FUNCTION(0, 161),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO161"),
+		MTK_FUNCTION(1, "I1_URXD1"),
+		MTK_FUNCTION(2, "I1_ADSP_URXD1"),
+		MTK_FUNCTION(3, "I1_HFRP_URXD1"),
+		MTK_FUNCTION(4, "I1_CCU1_URXD"),
+		MTK_FUNCTION(5, "I1_PBUD_CTRL_URXD_AO_VCORE"),
+		MTK_FUNCTION(6, "I1_U4CP_URXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_B15")
+	),
+	MTK_PIN(
+		162, "GPIO162",
+		MTK_EINT_FUNCTION(0, 162),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO162"),
+		MTK_FUNCTION(1, "O_URTS1"),
+		MTK_FUNCTION(2, "O_ADSP_URTX1"),
+		MTK_FUNCTION(3, "O_HFRP_URTS1"),
+		MTK_FUNCTION(4, "O_CCU0_UTXD"),
+		MTK_FUNCTION(5, "O_PBUD_CTRL_UTXD_AO_VCORE"),
+		MTK_FUNCTION(6, "O_U4CP_URTS"),
+		MTK_FUNCTION(7, "O_DBG_MON_B16")
+	),
+	MTK_PIN(
+		163, "GPIO163",
+		MTK_EINT_FUNCTION(0, 163),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO163"),
+		MTK_FUNCTION(1, "I1_UCTS1"),
+		MTK_FUNCTION(2, "I1_ADSP_UCTS1"),
+		MTK_FUNCTION(3, "I1_HFRP_UCTS1"),
+		MTK_FUNCTION(4, "I1_CCU0_URXD"),
+		MTK_FUNCTION(5, "I1_PBUD_CTRL_URXD_AO_VCORE"),
+		MTK_FUNCTION(6, "I1_U4CP_UCTS"),
+		MTK_FUNCTION(7, "O_DBG_MON_B17")
+	),
+	MTK_PIN(
+		164, "GPIO164",
+		MTK_EINT_FUNCTION(0, 164),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO164"),
+		MTK_FUNCTION(1, "O_HDMITX_DC_CTRL"),
+		MTK_FUNCTION(6, "I0_SROOT_NTRST"),
+		MTK_FUNCTION(7, "O_DBG_MON_B18")
+	),
+	MTK_PIN(
+		165, "GPIO165",
+		MTK_EINT_FUNCTION(0, 165),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO165"),
+		MTK_FUNCTION(1, "B1_DISP_SCL0"),
+		MTK_FUNCTION(4, "I1_EDP0_SCL"),
+		MTK_FUNCTION(5, "O_CCU0_URTS"),
+		MTK_FUNCTION(6, "O_CCU1_URTS"),
+		MTK_FUNCTION(7, "I1_MD32_6_RXD")
+	),
+	MTK_PIN(
+		166, "GPIO166",
+		MTK_EINT_FUNCTION(0, 166),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO166"),
+		MTK_FUNCTION(1, "B1_DISP_SDA0"),
+		MTK_FUNCTION(4, "B1_EDP0_SDA"),
+		MTK_FUNCTION(5, "I1_CCU0_UCTS"),
+		MTK_FUNCTION(6, "I1_CCU1_UCTS"),
+		MTK_FUNCTION(7, "O_MD32_6_GPIO0")
+	),
+	MTK_PIN(
+		167, "GPIO167",
+		MTK_EINT_FUNCTION(0, 167),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO167"),
+		MTK_FUNCTION(1, "B0_DISP_GPIO_N0"),
+		MTK_FUNCTION(5, "O_CLUSTER0_AD_ILDO_DTEST0"),
+		MTK_FUNCTION(6, "O_CLUSTER1_AD_ILDO_DTEST0"),
+		MTK_FUNCTION(7, "O_DBG_MON_B19")
+	),
+	MTK_PIN(
+		168, "GPIO168",
+		MTK_EINT_FUNCTION(0, 168),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO168"),
+		MTK_FUNCTION(1, "I0_DPAUX_HPD_IN_0"),
+		MTK_FUNCTION(5, "O_CLUSTER0_AD_ILDO_DTEST1"),
+		MTK_FUNCTION(6, "O_CLUSTER1_AD_ILDO_DTEST1"),
+		MTK_FUNCTION(7, "O_DBG_MON_B20")
+	),
+	MTK_PIN(
+		169, "GPIO169",
+		MTK_EINT_FUNCTION(0, 169),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO169"),
+		MTK_FUNCTION(1, "I0_DPAUX_HPD_IN_1"),
+		MTK_FUNCTION(5, "O_CLUSTER0_AD_ILDO_DTEST3"),
+		MTK_FUNCTION(6, "O_CLUSTER1_AD_ILDO_DTEST3"),
+		MTK_FUNCTION(7, "O_DBG_MON_B21")
+	),
+	MTK_PIN(
+		170, "GPIO170",
+		MTK_EINT_FUNCTION(0, 170),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO170"),
+		MTK_FUNCTION(1, "O_USB4_R_TCPC_RESET"),
+		MTK_FUNCTION(5, "O_CLUSTER0_AD_ILDO_DTEST2"),
+		MTK_FUNCTION(6, "O_CLUSTER1_AD_ILDO_DTEST2"),
+		MTK_FUNCTION(7, "O_DBG_MON_A17")
+	),
+	MTK_PIN(
+		171, "GPIO171",
+		MTK_EINT_FUNCTION(0, 171),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO171"),
+		MTK_FUNCTION(1, "O_PCIE_PERSTN"),
+		MTK_FUNCTION(4, "O_MD32_14_GPIO0"),
+		MTK_FUNCTION(7, "O_DBG_MON_B22")
+	),
+	MTK_PIN(
+		172, "GPIO172",
+		MTK_EINT_FUNCTION(0, 172),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO172"),
+		MTK_FUNCTION(1, "B1_PCIE_CLKREQN_0P"),
+		MTK_FUNCTION(2, "I1_PCIE_PRSNT_0P"),
+		MTK_FUNCTION(5, "O_HFRP_UTXD1"),
+		MTK_FUNCTION(6, "O_CCU0_UTXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_B23")
+	),
+	MTK_PIN(
+		173, "GPIO173",
+		MTK_EINT_FUNCTION(0, 173),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO173"),
+		MTK_FUNCTION(1, "B1_PCIE_CLKREQN_1P"),
+		MTK_FUNCTION(2, "I1_PCIE_PRSNT_1P"),
+		MTK_FUNCTION(5, "I1_HFRP_URXD1"),
+		MTK_FUNCTION(6, "I1_CCU0_URXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_B24")
+	),
+	MTK_PIN(
+		174, "GPIO174",
+		MTK_EINT_FUNCTION(0, 174),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO174"),
+		MTK_FUNCTION(1, "B1_PCIE_CLKREQN_2P"),
+		MTK_FUNCTION(2, "I1_PCIE_PRSNT_2P"),
+		MTK_FUNCTION(4, "O_MD32PCM_UTXD_AO_VLP"),
+		MTK_FUNCTION(5, "O_HFRP_URTS1"),
+		MTK_FUNCTION(6, "O_CCU1_UTXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_B25")
+	),
+	MTK_PIN(
+		175, "GPIO175",
+		MTK_EINT_FUNCTION(0, 175),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO175"),
+		MTK_FUNCTION(1, "B1_PCIE_CLKREQN_3P"),
+		MTK_FUNCTION(2, "I1_PCIE_PRSNT_3P"),
+		MTK_FUNCTION(4, "I1_MD32PCM_URXD_AO_VLP"),
+		MTK_FUNCTION(5, "I1_HFRP_UCTS1"),
+		MTK_FUNCTION(6, "I1_CCU1_URXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_B26")
+	),
+	MTK_PIN(
+		176, "GPIO176",
+		MTK_EINT_FUNCTION(0, 176),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO176"),
+		MTK_FUNCTION(1, "B1_PCIE_CLKREQN_4P"),
+		MTK_FUNCTION(2, "I1_PCIE_PRSNT_4P"),
+		MTK_FUNCTION(4, "O_MD32_14_TXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_B27")
+	),
+	MTK_PIN(
+		177, "GPIO177",
+		MTK_EINT_FUNCTION(0, 177),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO177"),
+		MTK_FUNCTION(1, "B1_PCIE_CLKREQN_5P"),
+		MTK_FUNCTION(2, "I1_PCIE_PRSNT_5P"),
+		MTK_FUNCTION(4, "I1_MD32_14_RXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_B28")
+	),
+	MTK_PIN(
+		178, "GPIO178",
+		MTK_EINT_FUNCTION(0, 178),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO178"),
+		MTK_FUNCTION(1, "B1_PCIE_CLKREQN_6P"),
+		MTK_FUNCTION(2, "I1_PCIE_PRSNT_6P"),
+		MTK_FUNCTION(4, "O_MD32_15_TXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_B29")
+	),
+	MTK_PIN(
+		179, "GPIO179",
+		MTK_EINT_FUNCTION(0, 179),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO179"),
+		MTK_FUNCTION(1, "B1_PCIE_CLKREQN_7P"),
+		MTK_FUNCTION(2, "I1_PCIE_PRSNT_7P"),
+		MTK_FUNCTION(4, "I1_MD32_15_RXD"),
+		MTK_FUNCTION(7, "O_DBG_MON_B30")
+	),
+	MTK_PIN(
+		180, "GPIO180",
+		MTK_EINT_FUNCTION(0, 180),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO180"),
+		MTK_FUNCTION(1, "I1_PCIE_WAKEN"),
+		MTK_FUNCTION(4, "O_MD32_15_GPIO0"),
+		MTK_FUNCTION(7, "O_DBG_MON_B31")
+	),
+	MTK_PIN(
+		181, "GPIO181",
+		MTK_EINT_FUNCTION(0, 181),
+		DRV_GRP4,
+		MTK_FUNCTION(0, "B_GPIO181"),
+		MTK_FUNCTION(1, "O_GPU_PWRGOOD")
+	),
+};
+
+static struct mtk_eint_pin eint_pins_mt8901[] = {
+	MTK_EINT_PIN(0, 0, 16, 0),
+	MTK_EINT_PIN(1, 0, 17, 0),
+	MTK_EINT_PIN(2, 0, 18, 0),
+	MTK_EINT_PIN(3, 0, 19, 0),
+	MTK_EINT_PIN(4, 0, 20, 0),
+	MTK_EINT_PIN(5, 0, 21, 0),
+	MTK_EINT_PIN(6, 0, 22, 0),
+	MTK_EINT_PIN(7, 0, 23, 0),
+	MTK_EINT_PIN(8, 0, 24, 0),
+	MTK_EINT_PIN(9, 0, 25, 0),
+	MTK_EINT_PIN(10, 0, 26, 0),
+	MTK_EINT_PIN(11, 0, 27, 0),
+	MTK_EINT_PIN(12, INVALID_BASE, 0, 0),
+	MTK_EINT_PIN(13, INVALID_BASE, 0, 0),
+	MTK_EINT_PIN(14, 0, 28, 0),
+	MTK_EINT_PIN(15, 0, 29, 0),
+	MTK_EINT_PIN(16, 0, 30, 0),
+	MTK_EINT_PIN(17, INVALID_BASE, 0, 0),
+	MTK_EINT_PIN(18, INVALID_BASE, 0, 0),
+	MTK_EINT_PIN(19, 0, 31, 0),
+	MTK_EINT_PIN(20, 0, 0, 1),
+	MTK_EINT_PIN(21, 0, 1, 1),
+	MTK_EINT_PIN(22, INVALID_BASE, 0, 0),
+	MTK_EINT_PIN(23, 0, 2, 1),
+	MTK_EINT_PIN(24, 0, 3, 1),
+	MTK_EINT_PIN(25, 0, 4, 1),
+	MTK_EINT_PIN(26, 0, 5, 1),
+	MTK_EINT_PIN(27, 0, 6, 1),
+	MTK_EINT_PIN(28, 0, 7, 1),
+	MTK_EINT_PIN(29, 0, 8, 1),
+	MTK_EINT_PIN(30, 0, 9, 1),
+	MTK_EINT_PIN(31, 0, 10, 1),
+	MTK_EINT_PIN(32, 1, 0, 1),
+	MTK_EINT_PIN(33, 0, 32, 0),
+	MTK_EINT_PIN(34, 0, 33, 0),
+	MTK_EINT_PIN(35, 0, 34, 0),
+	MTK_EINT_PIN(36, 1, 1, 1),
+	MTK_EINT_PIN(37, 0, 11, 1),
+	MTK_EINT_PIN(38, 0, 12, 1),
+	MTK_EINT_PIN(39, 0, 35, 0),
+	MTK_EINT_PIN(40, 0, 36, 0),
+	MTK_EINT_PIN(41, 0, 37, 0),
+	MTK_EINT_PIN(42, 0, 13, 1),
+	MTK_EINT_PIN(43, 0, 14, 1),
+	MTK_EINT_PIN(44, 0, 38, 0),
+	MTK_EINT_PIN(45, 0, 39, 0),
+	MTK_EINT_PIN(46, 0, 40, 0),
+	MTK_EINT_PIN(47, 0, 15, 1),
+	MTK_EINT_PIN(48, 0, 41, 0),
+	MTK_EINT_PIN(49, 0, 42, 0),
+	MTK_EINT_PIN(50, 0, 43, 0),
+	MTK_EINT_PIN(51, 0, 44, 0),
+	MTK_EINT_PIN(52, 0, 45, 0),
+	MTK_EINT_PIN(53, 0, 46, 0),
+	MTK_EINT_PIN(54, 2, 13, 0),
+	MTK_EINT_PIN(55, 2, 14, 0),
+	MTK_EINT_PIN(56, INVALID_BASE, 0, 0),
+	MTK_EINT_PIN(57, INVALID_BASE, 0, 0),
+	MTK_EINT_PIN(58, INVALID_BASE, 0, 0),
+	MTK_EINT_PIN(59, INVALID_BASE, 0, 0),
+	MTK_EINT_PIN(60, 1, 3, 0),
+	MTK_EINT_PIN(61, 1, 4, 0),
+	MTK_EINT_PIN(62, 1, 5, 0),
+	MTK_EINT_PIN(63, 1, 6, 0),
+	MTK_EINT_PIN(64, 1, 7, 0),
+	MTK_EINT_PIN(65, 1, 8, 0),
+	MTK_EINT_PIN(66, 2, 15, 0),
+	MTK_EINT_PIN(67, 2, 16, 0),
+	MTK_EINT_PIN(68, 1, 2, 1),
+	MTK_EINT_PIN(69, INVALID_BASE, 0, 0),
+	MTK_EINT_PIN(70, 2, 17, 0),
+	MTK_EINT_PIN(71, 2, 18, 0),
+	MTK_EINT_PIN(72, 2, 19, 0),
+	MTK_EINT_PIN(73, 2, 20, 0),
+	MTK_EINT_PIN(74, 2, 21, 0),
+	MTK_EINT_PIN(75, 2, 22, 0),
+	MTK_EINT_PIN(76, 2, 23, 0),
+	MTK_EINT_PIN(77, 2, 24, 0),
+	MTK_EINT_PIN(78, 2, 25, 0),
+	MTK_EINT_PIN(79, 2, 26, 0),
+	MTK_EINT_PIN(80, 2, 27, 0),
+	MTK_EINT_PIN(81, 2, 28, 0),
+	MTK_EINT_PIN(82, 2, 29, 1),
+	MTK_EINT_PIN(83, 2, 30, 1),
+	MTK_EINT_PIN(84, 2, 31, 1),
+	MTK_EINT_PIN(85, 2, 32, 1),
+	MTK_EINT_PIN(86, 2, 33, 0),
+	MTK_EINT_PIN(87, 2, 34, 0),
+	MTK_EINT_PIN(88, 2, 35, 0),
+	MTK_EINT_PIN(89, 2, 36, 0),
+	MTK_EINT_PIN(90, 2, 37, 0),
+	MTK_EINT_PIN(91, 2, 38, 0),
+	MTK_EINT_PIN(92, 2, 39, 0),
+	MTK_EINT_PIN(93, 2, 40, 0),
+	MTK_EINT_PIN(94, 2, 0, 1),
+	MTK_EINT_PIN(95, 2, 1, 1),
+	MTK_EINT_PIN(96, 2, 2, 1),
+	MTK_EINT_PIN(97, 2, 3, 1),
+	MTK_EINT_PIN(98, 2, 41, 0),
+	MTK_EINT_PIN(99, 2, 4, 1),
+	MTK_EINT_PIN(100, 2, 5, 1),
+	MTK_EINT_PIN(101, 2, 6, 1),
+	MTK_EINT_PIN(102, 2, 7, 1),
+	MTK_EINT_PIN(103, 2, 8, 1),
+	MTK_EINT_PIN(104, 2, 9, 1),
+	MTK_EINT_PIN(105, 2, 10, 1),
+	MTK_EINT_PIN(106, 0, 47, 0),
+	MTK_EINT_PIN(107, 0, 48, 0),
+	MTK_EINT_PIN(108, 0, 49, 0),
+	MTK_EINT_PIN(109, 0, 50, 0),
+	MTK_EINT_PIN(110, 0, 51, 0),
+	MTK_EINT_PIN(111, 0, 52, 0),
+	MTK_EINT_PIN(112, 2, 42, 0),
+	MTK_EINT_PIN(113, 2, 43, 0),
+	MTK_EINT_PIN(114, 2, 44, 0),
+	MTK_EINT_PIN(115, 2, 45, 0),
+	MTK_EINT_PIN(116, 2, 46, 0),
+	MTK_EINT_PIN(117, 2, 47, 0),
+	MTK_EINT_PIN(118, 2, 48, 0),
+	MTK_EINT_PIN(119, 2, 49, 0),
+	MTK_EINT_PIN(120, 2, 50, 0),
+	MTK_EINT_PIN(121, 2, 51, 0),
+	MTK_EINT_PIN(122, 2, 52, 0),
+	MTK_EINT_PIN(123, 2, 53, 0),
+	MTK_EINT_PIN(124, 2, 54, 0),
+	MTK_EINT_PIN(125, 2, 55, 0),
+	MTK_EINT_PIN(126, 2, 56, 0),
+	MTK_EINT_PIN(127, 2, 57, 0),
+	MTK_EINT_PIN(128, 2, 58, 0),
+	MTK_EINT_PIN(129, 2, 59, 0),
+	MTK_EINT_PIN(130, 2, 60, 0),
+	MTK_EINT_PIN(131, 2, 61, 0),
+	MTK_EINT_PIN(132, 2, 62, 0),
+	MTK_EINT_PIN(133, 2, 63, 0),
+	MTK_EINT_PIN(134, 2, 64, 0),
+	MTK_EINT_PIN(135, 2, 65, 0),
+	MTK_EINT_PIN(136, 2, 66, 0),
+	MTK_EINT_PIN(137, 2, 67, 0),
+	MTK_EINT_PIN(138, 2, 11, 1),
+	MTK_EINT_PIN(139, 2, 12, 1),
+	MTK_EINT_PIN(140, 2, 68, 0),
+	MTK_EINT_PIN(141, 2, 69, 0),
+	MTK_EINT_PIN(142, 2, 70, 0),
+	MTK_EINT_PIN(143, 2, 71, 0),
+	MTK_EINT_PIN(144, 2, 72, 0),
+	MTK_EINT_PIN(145, 2, 73, 0),
+	MTK_EINT_PIN(146, 2, 74, 0),
+	MTK_EINT_PIN(147, 2, 75, 0),
+	MTK_EINT_PIN(148, INVALID_BASE, 0, 0),
+	MTK_EINT_PIN(149, INVALID_BASE, 0, 0),
+	MTK_EINT_PIN(150, 2, 76, 0),
+	MTK_EINT_PIN(151, 2, 77, 0),
+	MTK_EINT_PIN(152, 2, 78, 0),
+	MTK_EINT_PIN(153, 2, 79, 0),
+	MTK_EINT_PIN(154, 2, 80, 0),
+	MTK_EINT_PIN(155, 2, 81, 0),
+	MTK_EINT_PIN(156, 2, 82, 0),
+	MTK_EINT_PIN(157, 2, 83, 0),
+	MTK_EINT_PIN(158, 2, 84, 0),
+	MTK_EINT_PIN(159, 2, 85, 0),
+	MTK_EINT_PIN(160, 2, 86, 0),
+	MTK_EINT_PIN(161, 2, 87, 0),
+	MTK_EINT_PIN(162, 2, 88, 0),
+	MTK_EINT_PIN(163, 2, 89, 0),
+	MTK_EINT_PIN(164, 2, 90, 0),
+	MTK_EINT_PIN(165, 2, 91, 0),
+	MTK_EINT_PIN(166, 2, 92, 0),
+	MTK_EINT_PIN(167, 2, 93, 0),
+	MTK_EINT_PIN(168, 2, 94, 0),
+	MTK_EINT_PIN(169, 2, 95, 0),
+	MTK_EINT_PIN(170, 2, 96, 0),
+	MTK_EINT_PIN(171, 2, 97, 0),
+	MTK_EINT_PIN(172, 2, 98, 0),
+	MTK_EINT_PIN(173, 2, 99, 0),
+	MTK_EINT_PIN(174, 2, 100, 0),
+	MTK_EINT_PIN(175, 2, 101, 0),
+	MTK_EINT_PIN(176, 2, 102, 0),
+	MTK_EINT_PIN(177, 2, 103, 0),
+	MTK_EINT_PIN(178, 2, 104, 0),
+	MTK_EINT_PIN(179, 2, 105, 0),
+	MTK_EINT_PIN(180, 2, 106, 0),
+	MTK_EINT_PIN(181, 3, 0, 0),
+	MTK_EINT_PIN(182, 3, 1, 0),
+	MTK_EINT_PIN(183, 3, 2, 0),
+	MTK_EINT_PIN(184, 3, 3, 0),
+	MTK_EINT_PIN(185, 3, 4, 0),
+	MTK_EINT_PIN(186, 3, 5, 0),
+	MTK_EINT_PIN(187, 3, 6, 0),
+	MTK_EINT_PIN(188, 3, 7, 0),
+	MTK_EINT_PIN(189, 3, 8, 0),
+	MTK_EINT_PIN(190, 3, 9, 0),
+	MTK_EINT_PIN(191, 3, 10, 0),
+	MTK_EINT_PIN(192, 3, 11, 0),
+	MTK_EINT_PIN(193, 3, 12, 0),
+	MTK_EINT_PIN(194, 3, 13, 0),
+	MTK_EINT_PIN(195, 3, 14, 0),
+	MTK_EINT_PIN(196, 3, 15, 0),
+	MTK_EINT_PIN(197, 3, 16, 0),
+	MTK_EINT_PIN(198, 3, 17, 0),
+	MTK_EINT_PIN(199, 3, 18, 0),
+	MTK_EINT_PIN(200, 3, 19, 0),
+	MTK_EINT_PIN(201, 3, 20, 0),
+	MTK_EINT_PIN(202, 3, 21, 0),
+	MTK_EINT_PIN(203, 3, 22, 0),
+	MTK_EINT_PIN(204, 3, 23, 0),
+	MTK_EINT_PIN(205, 3, 24, 0),
+	MTK_EINT_PIN(206, 3, 25, 0),
+	MTK_EINT_PIN(207, 3, 26, 0),
+	MTK_EINT_PIN(208, 3, 27, 0),
+};
+
+#endif /* __PINCTRL__MTK_MT8901_H */
-- 
2.45.2

Re: [PATCH 3/3] pinctrl: mediatek: mt8901: Add pinctrl driver for MT8901

[AngeloGioacchino Del Regno]

Il 25/11/25 03:36, Lei Xue ha scritto:
> Add mt8901 pinctrl, gpio and eint driver implementation.
> 
> Signed-off-by: Lei Xue <lei.xue@mediatek.com>
> ---
>   drivers/pinctrl/mediatek/Kconfig              |   12 +
>   drivers/pinctrl/mediatek/Makefile             |    1 +
>   drivers/pinctrl/mediatek/mtk-eint.c           |    4 +
>   drivers/pinctrl/mediatek/mtk-eint.h           |    1 +
>   drivers/pinctrl/mediatek/pinctrl-mt8901.c     | 1460 +++++++++++
>   drivers/pinctrl/mediatek/pinctrl-mtk-mt8901.h | 2130 +++++++++++++++++
>   6 files changed, 3608 insertions(+)
>   create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8901.c
>   create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8901.h
> 
> diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
> index 4819617d9368..4820ae5197a0 100644
> --- a/drivers/pinctrl/mediatek/Kconfig
> +++ b/drivers/pinctrl/mediatek/Kconfig
> @@ -321,6 +321,18 @@ config PINCTRL_MT8516
>   	default ARM64 && ARCH_MEDIATEK
>   	select PINCTRL_MTK
>   
> +config PINCTRL_MT8901
> +	bool "MediaTek MT8901 pin control"
> +	depends on ACPI
> +	depends on ARM64 || COMPILE_TEST
> +	default ARM64 && ARCH_MEDIATEK
> +	select PINCTRL_MTK_PARIS
> +	help
> +	  Say yes here to support pin controller and gpio driver
> +	  on MediaTek MT8901 SoC.
> +	  In MTK platform, we support virtual gpio and use it to
> +	  map specific eint which doesn't have real gpio pin.
> +
>   # For PMIC
>   config PINCTRL_MT6397
>   	bool "MediaTek MT6397 pin control"
> diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
> index ae765bd99965..57c69b1e5c2d 100644
> --- a/drivers/pinctrl/mediatek/Makefile
> +++ b/drivers/pinctrl/mediatek/Makefile
> @@ -43,3 +43,4 @@ obj-$(CONFIG_PINCTRL_MT8196)		+= pinctrl-mt8196.o
>   obj-$(CONFIG_PINCTRL_MT8365)		+= pinctrl-mt8365.o
>   obj-$(CONFIG_PINCTRL_MT8516)		+= pinctrl-mt8516.o
>   obj-$(CONFIG_PINCTRL_MT6397)		+= pinctrl-mt6397.o
> +obj-$(CONFIG_PINCTRL_MT8901)		+= pinctrl-mt8901.o
> diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c
> index c8c5097c11c4..b5a5beebf9cd 100644
> --- a/drivers/pinctrl/mediatek/mtk-eint.c
> +++ b/drivers/pinctrl/mediatek/mtk-eint.c
> @@ -71,6 +71,10 @@ const unsigned int debounce_time_mt6878[] = {
>   };
>   EXPORT_SYMBOL_GPL(debounce_time_mt6878);
>   
> +const unsigned int debounce_time_mt8901[] = {
> +	156, 313, 625, 1250, 20000, 40000, 80000, 160000, 320000, 640000, 0};
> +EXPORT_SYMBOL_GPL(debounce_time_mt8901);
> +
>   static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
>   					 unsigned int eint_num,
>   					 unsigned int offset)
> diff --git a/drivers/pinctrl/mediatek/mtk-eint.h b/drivers/pinctrl/mediatek/mtk-eint.h
> index 3cdd6f6310cd..1b185f660aff 100644
> --- a/drivers/pinctrl/mediatek/mtk-eint.h
> +++ b/drivers/pinctrl/mediatek/mtk-eint.h
> @@ -53,6 +53,7 @@ extern const unsigned int debounce_time_mt2701[];
>   extern const unsigned int debounce_time_mt6765[];
>   extern const unsigned int debounce_time_mt6795[];
>   extern const unsigned int debounce_time_mt6878[];
> +extern const unsigned int debounce_time_mt8901[];
>   
>   struct mtk_eint;
>   
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8901.c b/drivers/pinctrl/mediatek/pinctrl-mt8901.c
> new file mode 100644
> index 000000000000..77dec85fe29b
> --- /dev/null
> +++ b/drivers/pinctrl/mediatek/pinctrl-mt8901.c
> @@ -0,0 +1,1460 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2025 MediaTek Inc.
> + *
> + */
> +
> +#include <linux/acpi.h>
> +#include <linux/module.h>
> +#include "pinctrl-mtk-mt8901.h"
> +#include "pinctrl-paris.h"
> +

..snip..

> +static const char * const mt8901_pinctrl_register_base_name[] = {
> +	"iocfg0", "iocfg_lt2", "iocfg_lt3", "iocfg_rt1", "iocfg_rt2", "iocfg_rt3",
> +	"iocfg_tr", "iocfg_rt0", "iocfg_lt1", "iocfg_lb", "iocfg_rb",
> +};
> +
> +static const struct mtk_eint_hw mt8901_eint_hw = {
> +	.port_mask = 0xf,
> +	.ports     = 7,
> +	.ap_num    = 209,
> +	.db_cnt    = 32,
> +	.db_time   = debounce_time_mt8901,
> +};
> +
> +static const struct mtk_pin_soc mt8901_data = {
> +	.reg_cal = mt8901_reg_cals,
> +	.pins = mtk_pins_mt8901,
> +	.npins = ARRAY_SIZE(mtk_pins_mt8901),
> +	.ngrps = ARRAY_SIZE(mtk_pins_mt8901),
> +	.eint_hw = &mt8901_eint_hw,
> +	.eint_pin = eint_pins_mt8901,
> +	.nfuncs = 8,
> +	.gpio_m = 0,
> +	.base_names = mt8901_pinctrl_register_base_name,
> +	.nbase_names = ARRAY_SIZE(mt8901_pinctrl_register_base_name),
> +	.pull_type = mt8901_pull_type,
> +	.pin_rsel = mt8901_pin_rsel_val_range,
> +	.npin_rsel = ARRAY_SIZE(mt8901_pin_rsel_val_range), /*numsel*/
> +	.bias_set_combo = mtk_pinconf_bias_set_combo,
> +	.bias_get_combo = mtk_pinconf_bias_get_combo,
> +	.drive_set = mtk_pinconf_drive_set_rev1,
> +	.drive_get = mtk_pinconf_drive_get_rev1,
> +	.adv_drive_set = mtk_pinconf_adv_drive_set_raw,
> +	.adv_drive_get = mtk_pinconf_adv_drive_get_raw,
> +};
> +
> +static const struct acpi_device_id mt8901_pinctrl_acpi_match[] = {
> +	{"NVDA9221", (kernel_ulong_t)&mt8901_data },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(acpi, mt8901_pinctrl_acpi_match);
> +
> +static struct platform_driver mt8901_pinctrl_driver = {
> +	.driver = {
> +		.name = "mt8901-pinctrl",
> +		.acpi_match_table = ACPI_PTR(mt8901_pinctrl_acpi_match),

Please also add support for devicetree - I have a hunch (and I'm sure that I am
not the only one) that ACPI may give some issues at the end of the day, on ARM64.

Of course, I'd hope that ACPI is all good on this platform, but still.... :-)

static const struct of_device_id mt8901_pinctrl_of_match[] = {
	{ .compatible = "mediatek,mt8901-pinctrl", .data = &mt8901_data },
	{ /* sentinel */ }
};

	.of_match_table = mt8901_pinctrl_of_match,

> +		.pm = pm_sleep_ptr(&mtk_paris_pinctrl_pm_ops)
> +	},
> +	.probe = mtk_paris_pinctrl_probe,
> +};

Cheers,
Angelo

> +
> +static int __init mt8901_pinctrl_init(void)
> +{
> +	return platform_driver_register(&mt8901_pinctrl_driver);
> +}
> +
> +arch_initcall(mt8901_pinctrl_init);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("MediaTek MT8901 Pinctrl Driver");

Re: [PATCH 2/3] pinctrl: mediatek: Add acpi support

[Linus Walleij]

On Tue, Nov 25, 2025 at 3:36 AM Lei Xue <lei.xue@mediatek.com> wrote:

> Add acpi support in the common part of pinctrl driver. Parsing
> hardware base addresses and irq number to initialize eint
> accroding to the acpi table data.
>
> Signed-off-by: Lei Xue <lei.xue@mediatek.com>

I'd ideally like Andy and the ARM64 ACPI maintainers look on
this. (Added to To:) and CC linux-acpi@vger.kernel.org.

I'm not aware of the best way to deal with ACPI in combined drivers
but things like this:

> -               hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
> -                                       hw->soc->base_names[i]);
> +               hw->base[i] = is_of_node(fwnode)
> +                       ? devm_platform_ioremap_resource_byname(pdev, hw->soc->base_names[i])
> +                       : devm_platform_get_and_ioremap_resource(pdev, i, NULL);

Just look really quirky, I think there are better ways to go about
this and sometimes the ACPI maintainers give some good
pushback about the firmware as well.

Yours,
Linus Walleij

Re: [PATCH 2/3] pinctrl: mediatek: Add acpi support

[Lorenzo Pieralisi]

[+cc: RobH for his information]

On Wed, Nov 26, 2025 at 10:10:15AM +0100, Linus Walleij wrote:
> On Tue, Nov 25, 2025 at 3:36 AM Lei Xue <lei.xue@mediatek.com> wrote:
> 
> > Add acpi support in the common part of pinctrl driver. Parsing
> > hardware base addresses and irq number to initialize eint
> > accroding to the acpi table data.
> >
> > Signed-off-by: Lei Xue <lei.xue@mediatek.com>
> 
> I'd ideally like Andy and the ARM64 ACPI maintainers look on
> this. (Added to To:) and CC linux-acpi@vger.kernel.org.
> 
> I'm not aware of the best way to deal with ACPI in combined drivers
> but things like this:
> 
> > -               hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
> > -                                       hw->soc->base_names[i]);
> > +               hw->base[i] = is_of_node(fwnode)
> > +                       ? devm_platform_ioremap_resource_byname(pdev, hw->soc->base_names[i])
> > +                       : devm_platform_get_and_ioremap_resource(pdev, i, NULL);
> 
> Just look really quirky, I think there are better ways to go about
> this and sometimes the ACPI maintainers give some good
> pushback about the firmware as well.

How are pdev->resource initialized ? For OF I suppose the names come from
"reg-names" (that don't exist in ACPI, yet), for ACPI I assume they come
from a _CRS (and you can't tag them by name for the reason above) ?

I assume that in ACPI the _CRS resource order is foolproof against the
variaty of SOCs this code has to deal with.

I also assume/hope that we don't want to add a "reg-names" _DSD property either
in ACPI to deal with this seamlessly in DT/ACPI (that was done for
"interrupt-names"):

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/firmware-guide/acpi/enumeration.rst?h=v6.18-rc7#n188

I am sorry I have got more questions than answers here - it would be good
to understand where the line is drawn when it comes to OF/ACPI and fwnode
heuristics compatibility.

Thanks,
Lorenzo

Re: [PATCH 1/3] pinctrl: mediatek: Add gpio-range record in pinctrl driver

[Andy Shevchenko]

On Tue, Nov 25, 2025 at 10:36:34AM +0800, Lei Xue wrote:
> Kernel GPIO subsystem mapping hardware pin number to a different
> range of gpio number. Add gpio-range structure to hold
> the mapped gpio range in pinctrl driver. That enables the kernel
> to search a range of mapped gpio range against a pinctrl device.

...

>  static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
>  {
>  	struct gpio_chip *chip = &hw->chip;

>  	if (ret < 0)
>  		return ret;
>  
> +	mtk_pinctrl_gpio_range_init(hw, chip);
> +
>  	return 0;

We have a callback for that in struct gpio_chip. Any reason not to use it?

>  }

...

> +	pinctrl_add_gpio_range(hw->pctrl, &hw->range);

Not sure if this is needed.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 2/3] pinctrl: mediatek: Add acpi support

[Andy Shevchenko]

On Wed, Nov 26, 2025 at 05:52:59PM +0100, Lorenzo Pieralisi wrote:
> On Wed, Nov 26, 2025 at 10:10:15AM +0100, Linus Walleij wrote:
> > On Tue, Nov 25, 2025 at 3:36 AM Lei Xue <lei.xue@mediatek.com> wrote:
> > 
> > > Add acpi support in the common part of pinctrl driver. Parsing

ACPI

> > > hardware base addresses and irq number to initialize eint

IRQ

> > > accroding to the acpi table data.

ACPI

> > > Signed-off-by: Lei Xue <lei.xue@mediatek.com>
> > 
> > I'd ideally like Andy and the ARM64 ACPI maintainers look on
> > this. (Added to To:) and CC linux-acpi@vger.kernel.org.
> > 
> > I'm not aware of the best way to deal with ACPI in combined drivers
> > but things like this:
> > 
> > > -               hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
> > > -                                       hw->soc->base_names[i]);
> > > +               hw->base[i] = is_of_node(fwnode)
> > > +                       ? devm_platform_ioremap_resource_byname(pdev, hw->soc->base_names[i])
> > > +                       : devm_platform_get_and_ioremap_resource(pdev, i, NULL);
> > 
> > Just look really quirky, I think there are better ways to go about
> > this and sometimes the ACPI maintainers give some good
> > pushback about the firmware as well.

Agree. It looks fragile.
I believe the best approach is to have fwnode_iomap_byname() and if required
add a quirk to have a software node with names.

> How are pdev->resource initialized ? For OF I suppose the names come from
> "reg-names" (that don't exist in ACPI, yet), for ACPI I assume they come
> from a _CRS (and you can't tag them by name for the reason above) ?

We always can hardcode the names if required in quirks via software nodes.
GPIO has even special data types for that (struct acpi_gpio_mapping).

> I assume that in ACPI the _CRS resource order is foolproof against the
> variaty of SOCs this code has to deal with.

Yeah, that's what we have with GPIOs in a few drivers, the hardcoded quirks.

> I also assume/hope that we don't want to add a "reg-names" _DSD property either
> in ACPI to deal with this seamlessly in DT/ACPI (that was done for
> "interrupt-names"):
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/firmware-guide/acpi/enumeration.rst?h=v6.18-rc7#n188

Hmm... Why not?

> I am sorry I have got more questions than answers here - it would be good
> to understand where the line is drawn when it comes to OF/ACPI and fwnode
> heuristics compatibility.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 2/3] pinctrl: mediatek: Add acpi support

[Lorenzo Pieralisi]

On Wed, Nov 26, 2025 at 08:06:51PM +0200, Andy Shevchenko wrote:

[...]

> > I also assume/hope that we don't want to add a "reg-names" _DSD property either
> > in ACPI to deal with this seamlessly in DT/ACPI (that was done for
> > "interrupt-names"):
> > 
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/firmware-guide/acpi/enumeration.rst?h=v6.18-rc7#n188
> 
> Hmm... Why not?

What's the policy there ? Half of the ACPI bindings for an interrupt
descriptor are defined in the ACPI specs (ie _CRS) and the other half
(ie "interrupt-names") is documented in the Linux kernel (or are we
documenting this elsewhere ?) ?

Or we are saying that "interrupt-names" properties are added by kernel
code _only_ (through software nodes, to make parsing seamless between DT
and ACPI) based on hardcoded name values in drivers ?

I don't think I can grok any example of the latter in the mainline.

I am asking because I'd need to add something similar shortly to make parsing
of platform devices created out of ACPI static tables easier (I guess we
can postpone discussion till I post the code but I thought I'd ask).

Are we going to do the same for "reg-names" ?

Most importantly, what is DT maintainers stance on the matter ?

Thanks,
Lorenzo

> > I am sorry I have got more questions than answers here - it would be good
> > to understand where the line is drawn when it comes to OF/ACPI and fwnode
> > heuristics compatibility.
> 
> -- 
> With Best Regards,
> Andy Shevchenko
> 
> 

Re: [PATCH 2/3] pinctrl: mediatek: Add acpi support

[Andy Shevchenko]

On Thu, Nov 27, 2025 at 11:06:29AM +0100, Lorenzo Pieralisi wrote:
> On Wed, Nov 26, 2025 at 08:06:51PM +0200, Andy Shevchenko wrote:

[...]

> > > I also assume/hope that we don't want to add a "reg-names" _DSD property either
> > > in ACPI to deal with this seamlessly in DT/ACPI (that was done for
> > > "interrupt-names"):
> > > 
> > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/firmware-guide/acpi/enumeration.rst?h=v6.18-rc7#n188
> > 
> > Hmm... Why not?
> 
> What's the policy there ?

> Half of the ACPI bindings for an interrupt
> descriptor are defined in the ACPI specs (ie _CRS) and the other half
> (ie "interrupt-names") is documented in the Linux kernel (or are we
> documenting this elsewhere ?) ?

Yeah, nobody pursued ACPI specification updates / addendum to make it fully
official. _De facto_ we have established practice for GPIOs enumeration
(as most used resources in the OSes), Linux official for PWM, I²C muxes,
multi-functional HW (such as Diolan DLN-2, LJCA), Microsoft defined for
so called "USB hardwired" devices, Linux defined for LEDs and GPIO keys,
sensor mount matrix as per "most used" cases + DT analogue works just
because we have agnostic APIs in IIO to retrieve that. There are maybe
more, but don't remember

So, I think the practical "policies" are that:
- if it's defined in ACPI spec, we use the spec
- if there is Microsoft addendum, we rely on what Windows does
- WMI, EFI, and other "windoze"-like vendor defined cases
- if it makes sense, we establish practice from Linux perspective
- the rest, every vendor does what it does

That said, for the first two we expect OEMs to follow, for the third one
depends, but there are established WMI calls and other more or less "standard"
interfaces, so like the first two.

For the fourth one (Linux) we do, but living in the expectation that some or
more vendors fall to the fifth category and we might need to support that if
we want their HW work in Linux.

> Or we are saying that "interrupt-names" properties are added by kernel
> code _only_ (through software nodes, to make parsing seamless between DT
> and ACPI) based on hardcoded name values in drivers ?

No, the idea behind software nodes is to "fix" the FW nodes in case the FW
description can not be modified (and that might well happen to even DT in some
cases AFAIH). So, if some driver hard codes "interrupt-names" we expect that
new versions of the FW that support the HW that needs the property will be
amended accordingly.

"interrupt-names" has been established for ACPI to support a separate SMB alert
interrupt. However, I haven't heard any development of that IRL (for real
devices in ACPI environment).

> I don't think I can grok any example of the latter in the mainline.
> 
> I am asking because I'd need to add something similar shortly to make parsing
> of platform devices created out of ACPI static tables easier (I guess we
> can postpone discussion till I post the code but I thought I'd ask).

Oh, I can go ahead and tell you, try to avoid that. Why?! Whatever,
indeed, please Cc me to that, I will be glad to study the case and
try to be helpful.

(Have you considered DT overlays instead? There is a big pending support for
 that for _ACPI_ platforms.)

> Are we going to do the same for "reg-names" ?

If it makes sense and we expect some vendor to follow that _in ACPI_,
why not?

> Most importantly, what is DT maintainers stance on the matter ?

AFAIK They don't care as long as there is a schema provided, accepted and
used in DT, if it's ACPI-only thing, then it most likely should be done
in ACPI-like way (see above the first two / three items: spec, MS, WMI/EFI).

> > > I am sorry I have got more questions than answers here - it would be good
> > > to understand where the line is drawn when it comes to OF/ACPI and fwnode
> > > heuristics compatibility.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 2/3] pinctrl: mediatek: Add acpi support

[Lorenzo Pieralisi]

On Thu, Nov 27, 2025 at 04:29:54PM +0200, Andy Shevchenko wrote:
> On Thu, Nov 27, 2025 at 11:06:29AM +0100, Lorenzo Pieralisi wrote:
> > On Wed, Nov 26, 2025 at 08:06:51PM +0200, Andy Shevchenko wrote:
> 
> [...]
> 
> > > > I also assume/hope that we don't want to add a "reg-names" _DSD property either
> > > > in ACPI to deal with this seamlessly in DT/ACPI (that was done for
> > > > "interrupt-names"):
> > > > 
> > > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/firmware-guide/acpi/enumeration.rst?h=v6.18-rc7#n188
> > > 
> > > Hmm... Why not?
> > 
> > What's the policy there ?
> 
> > Half of the ACPI bindings for an interrupt
> > descriptor are defined in the ACPI specs (ie _CRS) and the other half
> > (ie "interrupt-names") is documented in the Linux kernel (or are we
> > documenting this elsewhere ?) ?
> 
> Yeah, nobody pursued ACPI specification updates / addendum to make it fully
> official. _De facto_ we have established practice for GPIOs enumeration
> (as most used resources in the OSes), Linux official for PWM, I²C muxes,
> multi-functional HW (such as Diolan DLN-2, LJCA), Microsoft defined for
> so called "USB hardwired" devices, Linux defined for LEDs and GPIO keys,
> sensor mount matrix as per "most used" cases + DT analogue works just
> because we have agnostic APIs in IIO to retrieve that. There are maybe
> more, but don't remember
> 
> So, I think the practical "policies" are that:
> - if it's defined in ACPI spec, we use the spec
> - if there is Microsoft addendum, we rely on what Windows does
> - WMI, EFI, and other "windoze"-like vendor defined cases
> - if it makes sense, we establish practice from Linux perspective
> - the rest, every vendor does what it does
> 
> That said, for the first two we expect OEMs to follow, for the third one
> depends, but there are established WMI calls and other more or less "standard"
> interfaces, so like the first two.
> 
> For the fourth one (Linux) we do, but living in the expectation that some or
> more vendors fall to the fifth category and we might need to support that if
> we want their HW work in Linux.
> 
> > Or we are saying that "interrupt-names" properties are added by kernel
> > code _only_ (through software nodes, to make parsing seamless between DT
> > and ACPI) based on hardcoded name values in drivers ?
> 
> No, the idea behind software nodes is to "fix" the FW nodes in case the FW
> description can not be modified (and that might well happen to even DT in some
> cases AFAIH). So, if some driver hard codes "interrupt-names" we expect that
> new versions of the FW that support the HW that needs the property will be
> amended accordingly.
> 
> "interrupt-names" has been established for ACPI to support a separate SMB alert
> interrupt. However, I haven't heard any development of that IRL (for real
> devices in ACPI environment).
> 
> > I don't think I can grok any example of the latter in the mainline.
> > 
> > I am asking because I'd need to add something similar shortly to make parsing
> > of platform devices created out of ACPI static tables easier (I guess we
> > can postpone discussion till I post the code but I thought I'd ask).
> 
> Oh, I can go ahead and tell you, try to avoid that. Why?! Whatever,
> indeed, please Cc me to that, I will be glad to study the case and
> try to be helpful.
> 
> (Have you considered DT overlays instead? There is a big pending support for
>  that for _ACPI_ platforms.)

Long story short: we do need to create platform devices out of static
table (eg ARM64 IORT) entries. Current code parses the table entries and
try to map the devices IRQs (ie acpi_register_gsi()) when the platform
device is created. Now, the interrupt controller that device IRQ's is
routed to might not have probed yet. We have to defer probing and later,
when the platform driver probes, map the IRQ.

Issue is: for OF nodes and ACPI devices, behind the platform device
firmware node there is a standard firmware object, so implementing
fwnode_irq_get() is trivial. For the devices I am talking about,
the data providing GSI info (hwirq, trigger/polarity) is static
table specific, so the idea was to stash that data and embed it in
fwnode_static along with a irq_get() fwnode_operations function
specific to that piece of data so that device drivers can actually do:

fwnode_irq_get()

on the fwnode _seamlessly_ (if you still do wonder: those platform
devices created out of static table entries in ACPI in OF are
of_node(s)).

There is a less convoluted solution (that is what some platform
drivers in ACPI do today), that is, we pass the static table
data in pdev->dev.platform_data and each platform_driver parses it differently.

That works but that also means the in the respective device drivers
OF and ACPI IRQ (and MMIO) parsing differ (which is not necessarily
a problem I just have to rewrite them all).

Now - when it comes to "interrupt-names". Some of the device drivers
I mention do:

eg platform_get_irq_byname_optional()

that expects the IRQ to be mapped and stored in a named platform device resource.

That's easy in DT - for two reasons:

(1) "interrupt-names"
(2) standard properties behind the of_node

how to do that for fwnodes that aren't backed by either OF nodes or ACPI
devices (that do use "interrupt-names" _DSD property) is a question.

Mind, the "interrupt-names" thing is a detail in the whole mechanism.

DT overlays to represent in ACPI those static table entries ?

I vividly remember the days ACPI for ARM64 was being merged - that's what
our crystal ball predicted :)

This delayed IRQ mapping notwithstanding, I read what you wrote and took
note. The worry is, this fwnode_*() (on ACPI nodes) interface trickling
into subsystems where it should not (ie PCI, clocks, regulators) - hopefully
the respective maintainers are keeping an eye on it.

Thanks,
Lorenzo

> > Are we going to do the same for "reg-names" ?
> 
> If it makes sense and we expect some vendor to follow that _in ACPI_,
> why not?
> 
> > Most importantly, what is DT maintainers stance on the matter ?
> 
> AFAIK They don't care as long as there is a schema provided, accepted and
> used in DT, if it's ACPI-only thing, then it most likely should be done
> in ACPI-like way (see above the first two / three items: spec, MS, WMI/EFI).
> 
> > > > I am sorry I have got more questions than answers here - it would be good
> > > > to understand where the line is drawn when it comes to OF/ACPI and fwnode
> > > > heuristics compatibility.
> 
> -- 
> With Best Regards,
> Andy Shevchenko
> 
>