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Thu, 27 Feb 2025 13:18:38 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 45CEC40045; Thu, 27 Feb 2025 13:17:31 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 73A2540E4F0; Thu, 27 Feb 2025 13:16:43 +0100 (CET) Received: from [10.48.86.79] (10.48.86.79) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 27 Feb 2025 13:16:42 +0100 Message-ID: Date: Thu, 27 Feb 2025 13:16:42 +0100 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 7/9] ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp25 To: Krzysztof Kozlowski , Clement LE GOFFIC , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Bartosz Golaszewski CC: , , , , References: <20250225-hdp-upstream-v1-0-9d049c65330a@foss.st.com> <20250225-hdp-upstream-v1-7-9d049c65330a@foss.st.com> <418a80a9-8c08-4dd1-bf49-1bd7378321aa@kernel.org> <988667a4-4bc0-4594-8dfd-a7b652b149b2@foss.st.com> <55beb3e7-65ac-4145-adae-fb064378c78d@kernel.org> <8cdc7e52-f9e2-4fc9-be68-0dd72a25ee1b@foss.st.com> <48cc626a-d632-444f-8563-07a9ea0ecc71@kernel.org> <17450f7d-d398-4a75-8b53-6c9c396661ab@kernel.org> Content-Language: en-US From: Alexandre TORGUE In-Reply-To: <17450f7d-d398-4a75-8b53-6c9c396661ab@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-27_05,2025-02-27_01,2024-11-22_01 On 2/26/25 22:31, Krzysztof Kozlowski wrote: > On 26/02/2025 22:26, Krzysztof Kozlowski wrote: >> On 26/02/2025 16:30, Alexandre TORGUE wrote: >>> >>> >>> On 2/26/25 16:08, Krzysztof Kozlowski wrote: >>>> On 26/02/2025 10:33, Alexandre TORGUE wrote: >>>>>>>>> + hdp: pinctrl@44090000 { >>>>>>>>> + compatible = "st,stm32mp-hdp"; >>>>>>>> >>>>>>>> So here again - you have stm32mp251 SoC, but use entirely different >>>>>>>> compatible. >>>>>>> >>>>>>> Ok so I will use "st,stm32mp15-hdp" >>>>>> >>>>>> >>>>>> This means this is stm32mp15 SoC. I do not see such SoC on list of your >>>>>> SoCs in bindings. What's more, there are no bindings for other SoC >>>>>> components for stm32mp15! >>>>> >>>>> Yes stm32mp15 is not a "real SoC". I agree that at the beginning of the >>>>> STM32 story we didn't have a clear rule/view to correctly naming our >>>>> compatible. We tried to improve the situation to avoid compatible like >>>>> "st,stm32", "st,stm32mp" or "st,stm32mp1". So we introduced >>>>> "st,stm32mp13", "st,stm32mp15" or "st,stm32mp25" for new drivers. So yes >>>>> it represents a SoC family and not a real SoC. We haven't had much >>>>> negative feedback it. >>>>> >>>>> But, if it's not clean to do it in this way, lets define SoC compatible >>>>> for any new driver. >>>> >>>> Compatibles are for hardware. >>>> >>>>> For the HDP case it is: "st,stm32mp157" and used for STM32MP13, >>>>> STM32MP15 end STM32MP25 SoC families (if driver is the same for all >>>>> those SoCs). >>>> >>>> No, it's three compatibles, because you have three SoCs. BTW, writing >>>> bindings (and online resources and previous reviews and my talks) are >>>> saying that, so we do not ask for anything new here, anything different. >>>> At least not new when looking at last 5 years, because 10 years ago many >>>> rules were relaxed... >>> >>> So adding 3 times the same IP in 3 different SoCs implies to have 3 >> >> Yes. Always, as requested by writing bindings. >> >>> different compatibles. So each time we use this same IP in a new SoC, we >>> have to add a new compatible. My (wrong) understanding was: as we have >> >> Yes, as requested by writing bindings and followed up by all recent >> platforms having decent/active upstream support. See qcom, nxp, renesas >> for example. >> >>> the same IP (same hardware) in each SoC we have the same compatible (and >> >> You do not have same hardware. You have same IP, or almost same because >> they are almost never same, implemented in different hardware. >> >>> IP integration differences (clocks, interrupts) are handled by DT >>> properties. >> >> Which binding doc/guide suggested such way? Countless reviews from DT >> maintainers were saying opposite. > I was not precise: IP integration differences are of course handles as > DT properties, but I wanted to say that it does not solve the problem > that IP integration means you might have differences in this device and > you should have different quirks. Yes I agree. We'll take care of it for future development. Maybe, It would be nice to apply this rule in our current drivers/DT already upstream ? > > And the example in this patchset: entirely different pin functions is a > proof. This device behaves/operates/integrates differently, thus > different compatible. Yes, discussing with Clement, it is clear that we need 3 different compatibles. > Best regards, > Krzysztof