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([2600:8803:e7e4:500:e504:a034:1152:a664]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7d76aeccd73sm12749664a34.27.2026.03.16.08.51.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Mar 2026 08:51:29 -0700 (PDT) Message-ID: Date: Mon, 16 Mar 2026 10:51:28 -0500 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/4] iio: adc: ad4691: add initial driver for AD4691 family To: "Sabau, Radu bogdan" , Andy Shevchenko Cc: Lars-Peter Clausen , "Hennerich, Michael" , Jonathan Cameron , "Sa, Nuno" , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , Liam Girdwood , Mark Brown , Linus Walleij , Bartosz Golaszewski , Philipp Zabel , "linux-iio@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pwm@vger.kernel.org" , "linux-gpio@vger.kernel.org" References: <20260313-ad4692-multichannel-sar-adc-driver-v3-0-b4d14d81a181@analog.com> <20260313-ad4692-multichannel-sar-adc-driver-v3-2-b4d14d81a181@analog.com> Content-Language: en-US From: David Lechner In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 3/16/26 10:29 AM, Sabau, Radu bogdan wrote: > > >> -----Original Message----- >> From: Andy Shevchenko >> Sent: Friday, March 13, 2026 12:58 PM >> To: Sabau, Radu bogdan >> >>> + u32 acc_mask[2] = { mask & 0xFF, mask >> 8 }; >> >> This looks quite wrong. Is it for sure like two 32-bit stances per each mask >> byte? If not, this should be __le16 acc_mask = cpu_to_le16(~BIT(...)); >> > > Hi Andy, > > Each acc_mask has its own register, therefore the u32 acc_mask[2] is > intentional - since the regmap is configured with val_bits=32 - the 4-byte > stride matches what regmap reads. However, I understand how this > can be confusing for anyone reading the code, therefore I propose > two ways for this : > > 1. Keep regmap_bulk_write and add a comment above acc_mask explaining > why u32 is used, although these register values are 8 bits. > 2. Switch to regmap_multi_reg_write, which takes explicit (reg, value) pairs > and sidesteps the ambiguity entirely. > > Do you have a preference? Since we already have a custom read/write functions to handle different register sizes and the chip can read more than one consecutive register at once, can we just call this a single register and add a special case to ad4691_reg_read/write() to handle it? Then we can just do a regular regmap_read/write() functions to access it as a single 16-bit value.