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AJvYcCXwaznzgUkPYnDhA+ylU0C9rzZjdRIN2UsqLHaRHWLKDiTFw7qsDfsuemfLO680GzLQFLUSPAKljNjgzhOoljfCh4Kj+HHvbmgXgg== X-Gm-Message-State: AOJu0YxVmc3Zt2aY6sMdPc331Ds2OISJ3rtUXLtJeIirrDrcapbft9Uy MOnhWSP35MyVvRX167rVTF93OAtgV+ZMZOJebl51byAOIfEO03y0kxx0P+GO47Y= X-Google-Smtp-Source: AGHT+IH29Wte+fcyhuRsKCPqSiaTew5pLfA8h8FdKKj6z0S4WRk8AFcfmziFTtXwiLY7lgiU/PX/XQ== X-Received: by 2002:a50:d504:0:b0:57c:749f:f5ef with SMTP id 4fb4d7f45d1cf-57d4a020170mr2321012a12.34.1719205045172; Sun, 23 Jun 2024 21:57:25 -0700 (PDT) Received: from [192.168.50.4] ([82.78.167.70]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d303d7aecsm4209761a12.20.2024.06.23.21.57.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 23 Jun 2024 21:57:24 -0700 (PDT) Message-ID: Date: Mon, 24 Jun 2024 07:57:23 +0300 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the file Content-Language: en-US To: Prabhakar , Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Fabrizio Castro , Lad Prabhakar References: <20240618174831.415583-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240618174831.415583-4-prabhakar.mahadev-lad.rj@bp.renesas.com> From: claudiu beznea In-Reply-To: <20240618174831.415583-4-prabhakar.mahadev-lad.rj@bp.renesas.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 18.06.2024 20:48, Prabhakar wrote: > From: Lad Prabhakar > > Define `RZG2L_SINGLE_PIN` at the top of the file to clarify its use for > dedicated pins for improved readability. > > While at it update the comment for `RZG2L_SINGLE_PIN_PACK` macro and place > it just above the macro for clarity. > > Signed-off-by: Lad Prabhakar Tested-by: Claudiu Beznea > --- > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > index b79dd1ea2616..37a99d33400d 100644 > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -64,6 +64,8 @@ > #define PIN_CFG_ELC BIT(20) > #define PIN_CFG_IOLH_RZV2H BIT(21) > > +#define RZG2L_SINGLE_PIN BIT_ULL(63) /* Dedicated pin */ > + > #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ > (PIN_CFG_IOLH_##group | \ > PIN_CFG_PUPD | \ > @@ -105,15 +107,13 @@ > */ > #define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f)) > > -/* > - * BIT(63) indicates dedicated pin, p is the register index while > - * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits > - * (b * 8) and f is the pin configuration capabilities supported. > - */ > -#define RZG2L_SINGLE_PIN BIT_ULL(63) > #define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK_ULL(62, 56) > #define RZG2L_SINGLE_PIN_BITS_MASK GENMASK_ULL(55, 53) > - > +/* > + * p is the register index while referencing to SR/IEN/IOLH/FILxx > + * registers, b is the register bits (b * 8) and f is the pin > + * configuration capabilities supported. > + */ > #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ > FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \ > FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \