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[84.106.84.65]) by smtp.gmail.com with ESMTPSA id z11sm8286936wrg.0.2019.11.14.02.00.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Nov 2019 02:00:37 -0800 (PST) Subject: Re: [PATCH v3 3/3] pinctrl: cherryview: Pass irqchip when adding gpiochip To: Andy Shevchenko Cc: Mika Westerberg , Bartosz Golaszewski , Linus Walleij , linux-gpio@vger.kernel.org, linux-acpi@vger.kernel.org References: <20191113190520.305410-1-hdegoede@redhat.com> <20191113190520.305410-3-hdegoede@redhat.com> <20191113192722.GK32742@smile.fi.intel.com> From: Hans de Goede Message-ID: Date: Thu, 14 Nov 2019 11:00:36 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0 MIME-Version: 1.0 In-Reply-To: <20191113192722.GK32742@smile.fi.intel.com> Content-Language: en-US X-MC-Unique: j59FNaTBPzSQajCWcqhStQ-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=WINDOWS-1252; format=flowed Content-Transfer-Encoding: quoted-printable Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hi, On 13-11-2019 20:27, Andy Shevchenko wrote: > On Wed, Nov 13, 2019 at 08:05:20PM +0100, Hans de Goede wrote: >> We need to convert all old gpio irqchips to pass the irqchip >> setup along when adding the gpio_chip. For more info see >> drivers/gpio/TODO. >> >> For chained irqchips this is a pretty straight-forward conversion. >> >> Acked-by: Mika Westerberg >> Signed-off-by: Hans de Goede >=20 >> =09struct irq_chip irqchip; >> =09void __iomem *regs; >> +=09unsigned int irq; >> =09unsigned intr_lines[16]; >=20 > This will conflict with our for-next. Ah, I did cherry-pick intel-pinctrl for-next into my tree a couple of days back, but I see there is a new "pinctrl: cherryview: Missed type change to = unsigned int" commit there which causes this conflict. I have cherry picked this new commit into my tree and I will send out a v4 which should not conflict. >=20 >> +=09if (need_valid_mask) >> +=09=09chip->irq.init_valid_mask =3D chv_init_irq_valid_mask; >> +=09chip->irq.init_hw =3D chv_gpio_irq_init_hw; >> +=09chip->irq.parent_handler =3D chv_gpio_irq_handler; >> +=09chip->irq.num_parents =3D 1; >> +=09chip->irq.parents =3D &pctrl->irq; >> +=09chip->irq.default_type =3D IRQ_TYPE_NONE; >> +=09chip->irq.handler =3D handle_bad_irq; >> =20 >> =09if (!need_valid_mask) { >> =09=09irq_base =3D devm_irq_alloc_descs(pctrl->dev, -1, 0, >=20 >=20 > Perhaps now it makes sense to >=20 > =09if (need_valid_mask) { > =09=09chip->irq.init_valid_mask =3D chv_init_irq_valid_mask; > =09} else { > =09=09irq_base =3D devm_irq_alloc_descs(pctrl->dev, -1, 0, > =09=09... > =09} > > ? Ack good one, will also change this for v4. Regards, Hans p.s. About upstreaming this, I know this has a pre-requisite on the new add_rang= es callback stuff, but how about Linus Walleij creating an immutable branch of his tree with the first series which adds the add_ranges callback in there and then you merge that branch into pinctrl-intel/for-next and then we just upstream all of this for 5.5 ? That seems easier then spreading it out over 2 cycles. Just my 2 cents.