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Wed, 28 May 2025 14:17:57 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id C0EEB4004A; Wed, 28 May 2025 14:16:49 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 68E786D6652; Wed, 28 May 2025 14:16:00 +0200 (CEST) Received: from [10.48.86.185] (10.48.86.185) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 28 May 2025 14:15:59 +0200 Message-ID: Date: Wed, 28 May 2025 14:15:58 +0200 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 6/9] ARM: dts: stm32: add Hardware debug port (HDP) on stm32mp15 To: Krzysztof Kozlowski , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski CC: , , , , References: <20250523-hdp-upstream-v3-0-bd6ca199466a@foss.st.com> <20250523-hdp-upstream-v3-6-bd6ca199466a@foss.st.com> <1c21f915-e067-4801-925a-3d4882f358f2@kernel.org> Content-Language: en-US From: Clement LE GOFFIC In-Reply-To: <1c21f915-e067-4801-925a-3d4882f358f2@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-28_06,2025-05-27_01,2025-03-28_01 On 5/28/25 11:00, Krzysztof Kozlowski wrote: > On 23/05/2025 14:38, Clément Le Goffic wrote: >> Add the hdp devicetree node for stm32mp15 SoC family >> >> Signed-off-by: Clément Le Goffic >> --- >> arch/arm/boot/dts/st/stm32mp151.dtsi | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi >> index 0daa8ffe2ff5..b1b568dfd126 100644 >> --- a/arch/arm/boot/dts/st/stm32mp151.dtsi >> +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi >> @@ -270,6 +270,13 @@ dts: thermal@50028000 { >> status = "disabled"; >> }; >> >> + hdp: pinctrl@5002a000 { >> + compatible = "st,stm32mp151-hdp"; >> + reg = <0x5002a000 0x400>; >> + clocks = <&rcc HDP>; >> + status = "disabled"; > > Same questions here and in further patches. Same, disabled by default and enable in board's dts file > > Best regards, > Krzysztof Clément