From: "Tanwar, Rahul" <rahul.tanwar@linux.intel.com>
To: Rob Herring <robh@kernel.org>
Cc: linus.walleij@linaro.org, mark.rutland@arm.com,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, andriy.shevchenko@intel.com,
qi-ming.wu@intel.com, yixin.zhu@linux.intel.com,
cheol.yong.kim@intel.com
Subject: Re: [PATCH v3 2/2] dt-bindings: pinctrl: intel: Add for new SoC
Date: Wed, 6 Nov 2019 18:29:19 +0800 [thread overview]
Message-ID: <f58ee4e0-1ffc-b5c4-f9eb-f14b01beb696@linux.intel.com> (raw)
In-Reply-To: <e7d1d72e-54d7-63ae-0eae-685a207d36ef@linux.intel.com>
On 6/11/2019 6:24 PM, Tanwar, Rahul wrote:
> Hi Rob,
>
> Thanks for the feedback.
>
> On 6/11/2019 5:29 AM, Rob Herring wrote:
>>> + bias-pull-up:
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>> + description: Specifies pull-up configuration.
>> Isn't this boolean?
>>
>>> +
>>> + bias-pull-down:
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>> + description: Specifies pull-down configuration.
>> And this?
>>
>> Though looks like sometimes it has a value? Pull strength I guess.
>>
>>> +
>>> + drive-strength:
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>> + description: Enables driver-current.
>>> +
>>> + slew-rate:
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>> + description: Enables slew-rate.
>>> +
>>> + drive-open-drain:
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>> + description: Specifies open-drain configuration.
>> boolean?
>>
>>> +
>>> + output-enable:
>>> + $ref: /schemas/types.yaml#/definitions/uint32
>>> + description: Specifies if the pin is to be configured as output.
>> boolean?
>>
>> But really, all of these should have a common schema defining the types
>> and only put any additional constraints here.
> Yes, you are right. These are all boolean types.
> All these are standard properties & we are using them with no
> additional constraintsi.e conforming to how they are already
> documented in pinctrl-bindings.txt. Shall ijust omit documenting
> these properties here in driver bindings ?
>
>>> +
>>> +examples:
>>> + # Pinmux controller node
>>> + - |
>>> + pinctrl: pinctrl@e2880000 {
>>> + compatible = "intel,lgm-pinctrl";
>>> + reg = <0xe2880000 0x100000>;
>>> +
>>> + # Client device subnode
>>> + uart0:uart0 {
>> space ^
> Just to be sure, you mean space misalignment at below
> line <65>; /* UART_TX0 */ ?Or is it something else ?
Please ignore this query of mine. I now realize that you meant space
between alias name & node name i.e. uart0: uart0 {. I will fix it in
nextpatch version. Thanks.
>>> + pins = <64>, /* UART_RX0 */
>>> + <65>; /* UART_TX0 */
>>> + function = "CONSOLE_UART0";
>>> + pinmux = <1>,
>>> + <1>;
>>> + groups = "CONSOLE_UART0";
>>> + };
>>> + };
>>> +
>>> +...
>>> --
>>> 2.11.0
>>>
> Regards,
> Rahul
next prev parent reply other threads:[~2019-11-06 10:29 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-05 6:49 [PATCH v3 0/2] pinctrl: Add new pinctrl/GPIO driver Rahul Tanwar
2019-11-05 6:49 ` [PATCH v3 1/2] pinctrl: Add pinmux & GPIO controller driver for a new SoC Rahul Tanwar
2019-11-05 9:49 ` Andy Shevchenko
2019-11-05 10:52 ` Tanwar, Rahul
2019-11-05 12:05 ` Andy Shevchenko
2019-11-05 6:49 ` [PATCH v3 2/2] dt-bindings: pinctrl: intel: Add for " Rahul Tanwar
2019-11-05 21:29 ` Rob Herring
2019-11-06 10:24 ` Tanwar, Rahul
2019-11-06 10:29 ` Tanwar, Rahul [this message]
2019-11-05 9:46 ` [PATCH v3 0/2] pinctrl: Add new pinctrl/GPIO driver Linus Walleij
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