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Tue, 08 Oct 2024 09:25:10 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4989P9dC017414 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 8 Oct 2024 09:25:09 GMT Received: from [10.50.47.90] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 8 Oct 2024 02:25:02 -0700 Message-ID: Date: Tue, 8 Oct 2024 14:54:59 +0530 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V3 2/7] dt-bindings: clock: Add Qualcomm IPQ5424 GCC binding To: Rob Herring CC: , , , , , , , , , , , , , , , , , , , , References: <20241004102342.2414317-1-quic_srichara@quicinc.com> <20241004102342.2414317-3-quic_srichara@quicinc.com> <20241005182345.GA482031-robh@kernel.org> Content-Language: en-US From: Sricharan Ramabadhran In-Reply-To: <20241005182345.GA482031-robh@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: T44Fz8J2z-M1GA5_5nVayamXjaRQ99da X-Proofpoint-ORIG-GUID: T44Fz8J2z-M1GA5_5nVayamXjaRQ99da X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=0 phishscore=0 mlxlogscore=999 spamscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410080061 On 10/5/2024 11:53 PM, Rob Herring wrote: > On Fri, Oct 04, 2024 at 03:53:37PM +0530, Sricharan R wrote: >> From: Sricharan Ramabadhran >> >> Add binding for the Qualcomm IPQ5424 Global Clock Controller >> >> Signed-off-by: Sricharan Ramabadhran >> --- >> [V3] Added only new clocks for IPQ5424 and ordered for both >> IPQ5332 and IPQ5424 based on min/max items >> >> .../bindings/clock/qcom,ipq5332-gcc.yaml | 40 ++- >> include/dt-bindings/clock/qcom,ipq5424-gcc.h | 156 +++++++++ >> include/dt-bindings/reset/qcom,ipq5424-gcc.h | 310 ++++++++++++++++++ >> 3 files changed, 499 insertions(+), 7 deletions(-) >> create mode 100644 include/dt-bindings/clock/qcom,ipq5424-gcc.h >> create mode 100644 include/dt-bindings/reset/qcom,ipq5424-gcc.h >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml >> index 9193de681de2..1b6d64385116 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml >> @@ -4,30 +4,34 @@ >> $id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml# >> $schema: http://devicetree.org/meta-schemas/core.yaml# >> >> -title: Qualcomm Global Clock & Reset Controller on IPQ5332 >> +title: Qualcomm Global Clock & Reset Controller on IPQ5332 and IPQ5424 >> >> maintainers: >> - Bjorn Andersson >> >> description: | >> Qualcomm global clock control module provides the clocks, resets and power >> - domains on IPQ5332. >> + domains on IPQ5332 and IPQ5424. >> >> - See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h >> - >> -allOf: >> - - $ref: qcom,gcc.yaml# >> + See also:: >> + include/dt-bindings/clock/qcom,gcc-ipq5332.h >> + include/dt-bindings/clock/qcom,gcc-ipq5424.h >> >> properties: >> compatible: >> - const: qcom,ipq5332-gcc >> + enum: >> + - qcom,ipq5332-gcc >> + - qcom,ipq5424-gcc >> >> clocks: >> + minItems: 5 >> items: >> - description: Board XO clock source >> - description: Sleep clock source >> - description: PCIE 2lane PHY pipe clock source >> - description: PCIE 2lane x1 PHY pipe clock source (For second lane) >> + - description: PCIE 2-lane PHY2 pipe clock source >> + - description: PCIE 2-lane PHY3 pipe clock source >> - description: USB PCIE wrapper pipe clock source > > New clocks go on the end of the list. Otherwise, it is an ABI break (or > the descriptions are wrong in one case). ok got it. Had a similar comment from Krzysztof for this. Will fix in V4. Regards, Sricharan