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Tue, 24 Mar 2026 05:03:55 -0700 (PDT) X-Received: by 2002:a17:903:3ba5:b0:2b0:5aab:c40a with SMTP id d9443c01a7336-2b08277aecamr143662045ad.31.1774353830506; Tue, 24 Mar 2026 05:03:50 -0700 (PDT) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b083656f65sm208995095ad.45.2026.03.24.05.03.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Mar 2026 05:03:50 -0700 (PDT) Message-ID: Date: Tue, 24 Mar 2026 17:33:42 +0530 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 3/3] PCI: Add support for PCIe WAKE# interrupt To: Manivannan Sadhasivam Cc: "Rafael J. Wysocki" , Len Brown , Pavel Machek , Greg Kroah-Hartman , Danilo Krummrich , Bjorn Helgaas , Bartosz Golaszewski , Linus Walleij , Bartosz Golaszewski , Rob Herring , Saravana Kannan , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org, quic_vbadigan@quicinc.com, sherry.sun@nxp.com, driver-core@lists.linux.dev, devicetree@vger.kernel.org References: <20260313-wakeirq_support-v8-0-48a0a702518a@oss.qualcomm.com> <20260313-wakeirq_support-v8-3-48a0a702518a@oss.qualcomm.com> <4n5heks4oymfz75wiajyc5zuzzulmwyfj2couudbi7gi67h2rk@smpnmyhdjkns> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <4n5heks4oymfz75wiajyc5zuzzulmwyfj2couudbi7gi67h2rk@smpnmyhdjkns> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI0MDA5NiBTYWx0ZWRfX8EgmLEE4HsoX AiPhZEXaMwwkizY3KbbtqbBAbRRRRR3VyT1ItNraXM/W/SXVuVHZ44XMxzK7jIUZlEVsQzMe4hu L+s2hA1uTpyn9aPv74UJaZKqQGwxiJbqczc8MKN3MPSwTRLT+77usJKF3M5u+0izRCkHVrRWenN PJ4Radms13RsE1k44vuIOno0eLr0Z7a7QhkcFo8TkgWAnMLD1Qz6pn5cplNB8fjjU5aNxsca25J AENr2gHLBIZk5nWlb+b4EnrBEQsLsbJ6c9bmRjPoV1UCMZtBYRQZ5kXMpk/T5vr8NywsqfRoXXU kxn67OOquveU+Un0Dx58/2jqsYlm9Z0wixQ4NZjIw5fOVdXRW506NtwAo9u9F9fXOw82hDnB6BH QxX7x1aICvN3OtDeRxJwQ4E3D7isKxSpk81hVbowCqVJPgkMGrP28+u5yFFrU2f25ZATo8T2t0L wjl/MnIHKx8J/RI00dw== X-Proofpoint-GUID: pebWK6XXUEoV0V2kC5v5p2y9EHMX34F2 X-Proofpoint-ORIG-GUID: pebWK6XXUEoV0V2kC5v5p2y9EHMX34F2 X-Authority-Analysis: v=2.4 cv=Bd/VE7t2 c=1 sm=1 tr=0 ts=69c27ded cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=NEAV23lmAAAA:8 a=KKAkSRfTAAAA:8 a=rFA5VEQNUbPbIC_WhckA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-24_02,2026-03-23_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 clxscore=1015 malwarescore=0 bulkscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603240096 On 3/17/2026 12:56 PM, Manivannan Sadhasivam wrote: > On Fri, Mar 13, 2026 at 12:38:42PM +0530, Krishna Chaitanya Chundru wrote: >> According to the PCI Express specification (PCIe r7.0, Section 5.3.3.2), >> two link wakeup mechanisms are defined: Beacon and WAKE#. Beacon is a >> hardware-only mechanism and is invisible to software (PCIe r7.0, >> Section 4.2.7.8.1). This change adds support for the WAKE# mechanism in >> the PCI core. >> >> According to the PCIe specification, multiple WAKE# signals can exist in >> a system or each component in the hierarchy could share a single WAKE# >> signal. In configurations involving a PCIe switch, each downstream port >> (DSP) of the switch may be connected to a separate WAKE# line, allowing >> each endpoint to signal WAKE# independently. From figure 5.4 in sec >> 5.3.3.2, WAKE# can also be terminated at the switch itself. To support >> this, the WAKE# should be described in the device tree node of the >> endpoint/bridge. If all endpoints share a single WAKE# line, then each >> endpoint node should describe the same WAKE# signal or a single WAKE# in >> the Root Port node. >> >> In pci_device_add(), PCI framework will search for the WAKE# in device >> node, If not found, it searches in its upstream port only if upstream port >> is Root Port. Once found, register for the wake IRQ in shared mode, as the >> WAKE# may be shared among multiple endpoints. >> >> dev_pm_set_dedicated_shared_wake_irq() associates a wakeup IRQ with a >> device and requests it, but the PM core keeps the IRQ disabled by default. >> The IRQ is enabled only when the device is permitted to wake the system, >> i.e. during system suspend and after runtime suspend, and only when device >> wakeup is enabled. >> >> When the wake IRQ fires, the wakeirq handler invokes pm_runtime_resume() to >> bring the device back to an active power state, such as transitioning from >> D3cold to D0. Once the device is active and the link is usable, the >> endpoint may generate a PME, which is then handled by the PCI core through >> PME polling or the PCIe PME service driver to complete the wakeup of the >> endpoint. >> >> WAKE# is added in dts schema and merged based on below links. >> >> Link: https://lore.kernel.org/all/20250515090517.3506772-1-krishna.chundru@oss.qualcomm.com/ >> Link: https://github.com/devicetree-org/dt-schema/pull/170 >> Reviewed-by: Linus Walleij >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> drivers/pci/of.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++ >> drivers/pci/pci.c | 10 +++++++ >> drivers/pci/pci.h | 2 ++ >> drivers/pci/probe.c | 2 ++ >> drivers/pci/remove.c | 1 + >> include/linux/of_pci.h | 4 +++ >> include/linux/pci.h | 2 ++ >> 7 files changed, 95 insertions(+) >> >> diff --git a/drivers/pci/of.c b/drivers/pci/of.c >> index 9f8eb5df279ed28db7a3b2fd29c65da9975c2efa..b7199d3598b31b62245716c178a5a73565efc89e 100644 >> --- a/drivers/pci/of.c >> +++ b/drivers/pci/of.c >> @@ -7,6 +7,7 @@ >> #define pr_fmt(fmt) "PCI: OF: " fmt >> >> #include >> +#include >> #include >> #include >> #include >> @@ -15,6 +16,7 @@ >> #include >> #include >> #include >> +#include >> #include "pci.h" >> >> #ifdef CONFIG_PCI >> @@ -586,6 +588,78 @@ int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin) >> return irq_create_of_mapping(&oirq); >> } >> EXPORT_SYMBOL_GPL(of_irq_parse_and_map_pci); >> + >> +static void pci_configure_wake_irq(struct pci_dev *pdev, struct gpio_desc *wake) >> +{ >> + int ret, wake_irq; >> + >> + wake_irq = gpiod_to_irq(wake); >> + if (wake_irq < 0) { >> + pci_err(pdev, "Failed to get wake irq: %d\n", wake_irq); >> + return; >> + } >> + >> + device_init_wakeup(&pdev->dev, true); > Just set wakeup only if dev_pm_set_dedicated_shared_wake_irq() succeeds. ack. >> + >> + /* >> + * dev_pm_set_dedicated_shared_wake_irq() associates a wakeup IRQ with the >> + * device and requests it, but the PM core keeps it disabled by default. >> + * The IRQ is enabled only when the device is allowed to wake the system >> + * (during system suspend and after runtime suspend), and only if device >> + * wakeup is enabled. >> + * >> + * When the wake IRQ fires, the wakeirq handler invokes pm_runtime_resume() >> + * to bring the device back to an active power state (e.g. from D3cold to D0). >> + * Once the device is active and the link is usable, the endpoint may signal >> + * a PME, which is then handled by the PCI core (either via PME polling or the >> + * PCIe PME service driver) to wakeup particular endpoint. >> + */ >> + ret = dev_pm_set_dedicated_shared_wake_irq(&pdev->dev, wake_irq, >> + IRQ_TYPE_EDGE_FALLING); > Isn't WAKE# a level triggered signal? Ack. I will change IRQ_TYPE_EDGE_FALLING to IRQ_TYPE_LEVEL_LOW. >> + if (ret < 0) { >> + pci_err(pdev, "Failed to set wake IRQ: %d\n", ret); > s/wake/WAKE# ack. - Krishna Chaitanya. > - Mani >