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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d806fed4e1sm15216164a12.70.2024.12.30.05.58.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Dec 2024 05:58:18 -0800 (PST) Message-ID: Date: Mon, 30 Dec 2024 14:58:17 +0100 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 0/6] Add SPI4 support for IPQ5424 To: Konrad Dybcio , Kathiravan Thirumoorthy , Manikanta Mylavarapu , andersson@kernel.org, linus.walleij@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Cc: quic_varada@quicinc.com, quic_srichara@quicinc.com References: <20241227072446.2545148-1-quic_mmanikan@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: NclqQnFVjS6DYnt4ebCcvAjS-EFRGTre X-Proofpoint-ORIG-GUID: NclqQnFVjS6DYnt4ebCcvAjS-EFRGTre X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 spamscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 impostorscore=0 mlxlogscore=875 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412300121 On 30.12.2024 2:54 PM, Konrad Dybcio wrote: > On 30.12.2024 7:51 AM, Kathiravan Thirumoorthy wrote: >> >> >> On 12/27/2024 12:54 PM, Manikanta Mylavarapu wrote: >>> Add SPI4 node to the IPQ5424 device tree and update the relevant >>> bindings, GPIO pin mappings accordingly. >>> >>> Changes in V3: >>>     - Rename SPI0 to SPI4 because SPI protocol runs on serial engine 4 >> >> Do we really need to do this? If so, it will not align with the HW documentation and will lead to the confusion down the line. IMHO, we should stick with the convention followed in the HW documentation. > > +1, the clocks are called SPI0/SPI1 internally Ok, I looked at a bit more documentation and it looks like somebody just had fun naming things.. SPI0 is on SE4 and SPI1 is on something else, with no more clock provisions for that protocol.. Which is not usually the case. Let's just go with what you guys use internally, as this is mighty spaghetti Konrad