* Re: [PATCH v1] pinctrl: msm8998: Squash TSIF pins together
From: Marc Gonzalez @ 2019-06-26 14:46 UTC (permalink / raw)
To: Jeffrey Hugo; +Cc: Bjorn Andersson, Linus Walleij, MSM, gpio
In-Reply-To: <CAOCk7Nqi6j07TzH0tp8x8NzwqX1CAG8wj55Yvxw2tVC8cXhxmQ@mail.gmail.com>
On 26/06/2019 16:42, Jeffrey Hugo wrote:
> On Wed, Jun 26, 2019 at 8:40 AM Marc Gonzalez <marc.w.gonzalez@free.fr> wrote:
>
>> Preamble: Rename tsif1 to tsif0, tsif2 to tsif1.
>> Squash tsif0 pins into a single function. Same for tsif1.
>>
>> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
>> ---
>> .../bindings/pinctrl/qcom,msm8998-pinctrl.txt | 19 ++---
>> drivers/pinctrl/qcom/pinctrl-msm8998.c | 76 +++++--------------
>> 2 files changed, 24 insertions(+), 71 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
>> index 00174f08ba1d..47b0f30a39e9 100644
>> --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
>> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
>> @@ -124,9 +124,8 @@ to specify in a pin configuration subnode:
>> qlink_request, qua_mi2s, sd_card, sd_write, sdc40, sdc41,
>> sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu,
>> spkr_i2s, ssbi1, ssc_irq, ter_mi2s, tgu_ch0, tgu_ch1,
>> - tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
>> - tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
>> - tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
>> + tsense_pwm1, tsense_pwm2, tsif0, tsif1,
>> + uim1_clk, uim1_data, uim1_present,
>> uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
>> uim_batt, usb_phy, vfr_1, vsense_clkout, vsense_data0,
>> vsense_data1, vsense_mode, wlan1_adc0, wlan1_adc1,
>> @@ -179,15 +178,9 @@ Example:
>> #interrupt-cells = <2>;
>>
>> uart_console_active: uart_console_active {
>> - mux {
>> - pins = "gpio4", "gpio5";
>> - function = "blsp_uart8_a";
>> - };
>> -
>> - config {
>> - pins = "gpio4", "gpio5";
>> - drive-strength = <2>;
>> - bias-disable;
>> - };
>> + pins = "gpio4", "gpio5";
>> + function = "blsp_uart8_a";
>> + drive-strength = <2>;
>> + bias-disable;
>> };
>
> Whats with these "uart" changes? Modernizing the example? Doesn't
> seem related to the commit text...
Good point. I squashed one commit too many. I'll drop that hunk
in v2. (Yes, I meant to document the syntax recommended by Bjorn.)
Regards.
^ permalink raw reply
* Re: [PATCH v1] pinctrl: msm8998: Squash TSIF pins together
From: Jeffrey Hugo @ 2019-06-26 14:42 UTC (permalink / raw)
To: Marc Gonzalez; +Cc: Bjorn Andersson, Linus Walleij, MSM, gpio
In-Reply-To: <57d0644d-164f-58e7-6c07-9608da4233a3@free.fr>
On Wed, Jun 26, 2019 at 8:40 AM Marc Gonzalez <marc.w.gonzalez@free.fr> wrote:
>
> Preamble: Rename tsif1 to tsif0, tsif2 to tsif1.
> Squash tsif0 pins into a single function. Same for tsif1.
>
> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
> ---
> .../bindings/pinctrl/qcom,msm8998-pinctrl.txt | 19 ++---
> drivers/pinctrl/qcom/pinctrl-msm8998.c | 76 +++++--------------
> 2 files changed, 24 insertions(+), 71 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
> index 00174f08ba1d..47b0f30a39e9 100644
> --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
> @@ -124,9 +124,8 @@ to specify in a pin configuration subnode:
> qlink_request, qua_mi2s, sd_card, sd_write, sdc40, sdc41,
> sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu,
> spkr_i2s, ssbi1, ssc_irq, ter_mi2s, tgu_ch0, tgu_ch1,
> - tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
> - tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
> - tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
> + tsense_pwm1, tsense_pwm2, tsif0, tsif1,
> + uim1_clk, uim1_data, uim1_present,
> uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
> uim_batt, usb_phy, vfr_1, vsense_clkout, vsense_data0,
> vsense_data1, vsense_mode, wlan1_adc0, wlan1_adc1,
> @@ -179,15 +178,9 @@ Example:
> #interrupt-cells = <2>;
>
> uart_console_active: uart_console_active {
> - mux {
> - pins = "gpio4", "gpio5";
> - function = "blsp_uart8_a";
> - };
> -
> - config {
> - pins = "gpio4", "gpio5";
> - drive-strength = <2>;
> - bias-disable;
> - };
> + pins = "gpio4", "gpio5";
> + function = "blsp_uart8_a";
> + drive-strength = <2>;
> + bias-disable;
> };
Whats with these "uart" changes? Modernizing the example? Doesn't
seem related to the commit text...
^ permalink raw reply
* [PATCH v1] pinctrl: msm8998: Squash TSIF pins together
From: Marc Gonzalez @ 2019-06-26 14:38 UTC (permalink / raw)
To: Bjorn Andersson, Linus Walleij; +Cc: MSM, gpio, Jeffrey Hugo
In-Reply-To: <20190620184124.GB24205@tuxbook-pro>
Preamble: Rename tsif1 to tsif0, tsif2 to tsif1.
Squash tsif0 pins into a single function. Same for tsif1.
Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
---
.../bindings/pinctrl/qcom,msm8998-pinctrl.txt | 19 ++---
drivers/pinctrl/qcom/pinctrl-msm8998.c | 76 +++++--------------
2 files changed, 24 insertions(+), 71 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
index 00174f08ba1d..47b0f30a39e9 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
@@ -124,9 +124,8 @@ to specify in a pin configuration subnode:
qlink_request, qua_mi2s, sd_card, sd_write, sdc40, sdc41,
sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu,
spkr_i2s, ssbi1, ssc_irq, ter_mi2s, tgu_ch0, tgu_ch1,
- tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
- tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
- tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
+ tsense_pwm1, tsense_pwm2, tsif0, tsif1,
+ uim1_clk, uim1_data, uim1_present,
uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
uim_batt, usb_phy, vfr_1, vsense_clkout, vsense_data0,
vsense_data1, vsense_mode, wlan1_adc0, wlan1_adc1,
@@ -179,15 +178,9 @@ Example:
#interrupt-cells = <2>;
uart_console_active: uart_console_active {
- mux {
- pins = "gpio4", "gpio5";
- function = "blsp_uart8_a";
- };
-
- config {
- pins = "gpio4", "gpio5";
- drive-strength = <2>;
- bias-disable;
- };
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart8_a";
+ drive-strength = <2>;
+ bias-disable;
};
};
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8998.c b/drivers/pinctrl/qcom/pinctrl-msm8998.c
index 00d7b94bc3f1..a05f41fe2706 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8998.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8998.c
@@ -581,16 +581,8 @@ enum msm8998_functions {
msm_mux_tgu_ch1,
msm_mux_tsense_pwm1,
msm_mux_tsense_pwm2,
- msm_mux_tsif1_clk,
- msm_mux_tsif1_data,
- msm_mux_tsif1_en,
- msm_mux_tsif1_error,
- msm_mux_tsif1_sync,
- msm_mux_tsif2_clk,
- msm_mux_tsif2_data,
- msm_mux_tsif2_en,
- msm_mux_tsif2_error,
- msm_mux_tsif2_sync,
+ msm_mux_tsif0,
+ msm_mux_tsif1,
msm_mux_uim1_clk,
msm_mux_uim1_data,
msm_mux_uim1_present,
@@ -692,9 +684,6 @@ static const char * const atest_usb13_groups[] = {
static const char * const bimc_dte1_groups[] = {
"gpio8", "gpio10",
};
-static const char * const tsif1_sync_groups[] = {
- "gpio9",
-};
static const char * const wlan1_adc0_groups[] = {
"gpio9",
};
@@ -863,9 +852,6 @@ static const char * const lpass_slimbus_groups[] = {
static const char * const sd_write_groups[] = {
"gpio40",
};
-static const char * const tsif1_error_groups[] = {
- "gpio40",
-};
static const char * const blsp_spi6_groups[] = {
"gpio41", "gpio42", "gpio43", "gpio44",
};
@@ -1048,11 +1034,8 @@ static const char * const blsp_uim2_b_groups[] = {
static const char * const blsp_i2c5_groups[] = {
"gpio87", "gpio88",
};
-static const char * const tsif1_clk_groups[] = {
- "gpio89",
-};
-static const char * const tsif1_en_groups[] = {
- "gpio90",
+static const char * const tsif0_groups[] = {
+ "gpio9", "gpio40", "gpio89", "gpio90", "gpio91",
};
static const char * const mdp_vsync0_groups[] = {
"gpio90",
@@ -1075,17 +1058,14 @@ static const char * const tgu_ch0_groups[] = {
static const char * const qdss_cti1_b_groups[] = {
"gpio90", "gpio91",
};
-static const char * const tsif1_data_groups[] = {
- "gpio91",
-};
static const char * const sdc4_cmd_groups[] = {
"gpio91",
};
static const char * const tgu_ch1_groups[] = {
"gpio91",
};
-static const char * const tsif2_error_groups[] = {
- "gpio92",
+static const char * const tsif1_groups[] = {
+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96",
};
static const char * const sdc43_groups[] = {
"gpio92",
@@ -1093,30 +1073,18 @@ static const char * const sdc43_groups[] = {
static const char * const vfr_1_groups[] = {
"gpio92",
};
-static const char * const tsif2_clk_groups[] = {
- "gpio93",
-};
static const char * const sdc4_clk_groups[] = {
"gpio93",
};
-static const char * const tsif2_en_groups[] = {
- "gpio94",
-};
static const char * const sdc42_groups[] = {
"gpio94",
};
static const char * const sd_card_groups[] = {
"gpio95",
};
-static const char * const tsif2_data_groups[] = {
- "gpio95",
-};
static const char * const sdc41_groups[] = {
"gpio95",
};
-static const char * const tsif2_sync_groups[] = {
- "gpio96",
-};
static const char * const sdc40_groups[] = {
"gpio96",
};
@@ -1355,16 +1323,8 @@ static const struct msm_function msm8998_functions[] = {
FUNCTION(tgu_ch1),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
- FUNCTION(tsif1_clk),
- FUNCTION(tsif1_data),
- FUNCTION(tsif1_en),
- FUNCTION(tsif1_error),
- FUNCTION(tsif1_sync),
- FUNCTION(tsif2_clk),
- FUNCTION(tsif2_data),
- FUNCTION(tsif2_en),
- FUNCTION(tsif2_error),
- FUNCTION(tsif2_sync),
+ FUNCTION(tsif0),
+ FUNCTION(tsif1),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
@@ -1396,7 +1356,7 @@ static const struct msm_pingroup msm8998_groups[] = {
PINGROUP(6, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, _, _, _, _, _, _),
PINGROUP(7, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, ddr_bist, _, atest_tsens2, atest_usb1, _, _),
PINGROUP(8, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, _, ddr_bist, _, wlan1_adc1, atest_usb13, bimc_dte1),
- PINGROUP(9, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, tsif1_sync, ddr_bist, _, wlan1_adc0, atest_usb12, bimc_dte0),
+ PINGROUP(9, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, tsif0, ddr_bist, _, wlan1_adc0, atest_usb12, bimc_dte0),
PINGROUP(10, EAST, mdp_vsync_a, blsp_spi4, blsp_uart1_b, blsp_i2c4, ddr_bist, atest_gpsadc1, wlan2_adc1, atest_usb11, bimc_dte1),
PINGROUP(11, EAST, mdp_vsync_a, edp_lcd, blsp_spi4, blsp_uart1_b, blsp_i2c4, dbg_out, atest_gpsadc0, wlan2_adc0, atest_usb10),
PINGROUP(12, EAST, mdp_vsync, m_voc, _, _, _, _, _, _, _),
@@ -1427,7 +1387,7 @@ static const struct msm_pingroup msm8998_groups[] = {
PINGROUP(37, NORTH, agera_pll, _, _, _, _, _, _, _, _),
PINGROUP(38, WEST, usb_phy, _, _, _, _, _, _, _, _),
PINGROUP(39, WEST, lpass_slimbus, _, _, _, _, _, _, _, _),
- PINGROUP(40, EAST, sd_write, tsif1_error, _, _, _, _, _, _, _),
+ PINGROUP(40, EAST, sd_write, tsif0, _, _, _, _, _, _, _),
PINGROUP(41, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _),
PINGROUP(42, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _),
PINGROUP(43, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, _, qdss, _, _, _, _),
@@ -1476,14 +1436,14 @@ static const struct msm_pingroup msm8998_groups[] = {
PINGROUP(86, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, _, _, _, _, _, _),
PINGROUP(87, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _),
PINGROUP(88, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _),
- PINGROUP(89, EAST, tsif1_clk, phase_flag, _, _, _, _, _, _, _),
- PINGROUP(90, EAST, tsif1_en, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, _),
- PINGROUP(91, EAST, tsif1_data, sdc4_cmd, tgu_ch1, phase_flag, qdss_cti1_b, _, _, _, _),
- PINGROUP(92, EAST, tsif2_error, sdc43, vfr_1, phase_flag, _, _, _, _, _),
- PINGROUP(93, EAST, tsif2_clk, sdc4_clk, _, qdss, _, _, _, _, _),
- PINGROUP(94, EAST, tsif2_en, sdc42, _, _, _, _, _, _, _),
- PINGROUP(95, EAST, tsif2_data, sdc41, _, _, _, _, _, _, _),
- PINGROUP(96, EAST, tsif2_sync, sdc40, phase_flag, _, _, _, _, _, _),
+ PINGROUP(89, EAST, tsif0, phase_flag, _, _, _, _, _, _, _),
+ PINGROUP(90, EAST, tsif0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, _),
+ PINGROUP(91, EAST, tsif0, sdc4_cmd, tgu_ch1, phase_flag, qdss_cti1_b, _, _, _, _),
+ PINGROUP(92, EAST, tsif1, sdc43, vfr_1, phase_flag, _, _, _, _, _),
+ PINGROUP(93, EAST, tsif1, sdc4_clk, _, qdss, _, _, _, _, _),
+ PINGROUP(94, EAST, tsif1, sdc42, _, _, _, _, _, _, _),
+ PINGROUP(95, EAST, tsif1, sdc41, _, _, _, _, _, _, _),
+ PINGROUP(96, EAST, tsif1, sdc40, phase_flag, _, _, _, _, _, _),
PINGROUP(97, WEST, _, mdp_vsync_b, ldo_en, _, _, _, _, _, _),
PINGROUP(98, WEST, _, mdp_vsync_b, ldo_update, _, _, _, _, _, _),
PINGROUP(99, WEST, _, _, _, _, _, _, _, _, _),
--
2.17.1
^ permalink raw reply related
* Re: [PATCH 2/8] dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema
From: Rob Herring @ 2019-06-26 13:47 UTC (permalink / raw)
To: Andrew Jeffery
Cc: open list:GPIO SUBSYSTEM, Ryan Chen, Linus Walleij, Mark Rutland,
Joel Stanley, linux-aspeed, OpenBMC Maillist, devicetree,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel@vger.kernel.org
In-Reply-To: <20190626071430.28556-3-andrew@aj.id.au>
On Wed, Jun 26, 2019 at 1:21 AM Andrew Jeffery <andrew@aj.id.au> wrote:
>
> Convert ASPEED pinctrl bindings to DT schema format using json-schema
BTW, ASPEED is one of the remaining platforms needing the top-level
board bindings converted.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> .../pinctrl/aspeed,ast2400-pinctrl.txt | 80 -------------------
> .../pinctrl/aspeed,ast2400-pinctrl.yaml | 73 +++++++++++++++++
> 2 files changed, 73 insertions(+), 80 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
> diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
> new file mode 100644
> index 000000000000..3b8cf3e51506
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml
> @@ -0,0 +1,73 @@
> +# SPDX-License-Identifier: GPL-2.0+
Do you have rights to change the license? If so, the preference is to
dual license with (GPL-2.0 OR BSD-2-Clause).
BTW, '-or-later' is the preferred form over '+'.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2400-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ASPEED AST2400 Pin Controller
> +
> +maintainers:
> + - Andrew Jeffery <andrew@aj.id.au>
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - aspeed,ast2400-pinctrl
> + - items:
> + - enum:
> + - aspeed,g4-pinctrl
This can be simplified to:
compatible:
enum:
- aspeed,ast2400-pinctrl
- aspeed,g4-pinctrl
> +
> +required:
> + - compatible
> +
> +description: |+
description goes before properties.
> + The pin controller node should be the child of a syscon node with the
> + required property:
> +
> + - compatible: Should be one of the following:
> + "aspeed,ast2400-scu", "syscon", "simple-mfd"
> + "aspeed,g4-scu", "syscon", "simple-mfd"
> +
> + Refer to the the bindings described in
> + Documentation/devicetree/bindings/mfd/syscon.txt
> +
> + For the AST2400 pinmux, each mux function has only one associated pin group.
> + Each group is named by its function. The following values for the function
> + and groups properties are supported:
> +
> + ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6
> + ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT EXTRST FLACK FLBUSY FLWP GPID GPID0 GPID2
> + GPID4 GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4
> + I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCRST LPCSMI MAC1LINK MAC2LINK MDIO1
> + MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1 NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4
> + NDTR1 NDTR2 NDTR3 NDTR4 NDTS4 NRI1 NRI2 NRI3 NRI4 NRTS1 NRTS2 NRTS3 OSCCLK
> + PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8
> + ROMCS1 ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1
> + SD2 SGPMCK SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI
> + SIOPBO SIOPWREQ SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU
> + SPICS1 TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6
> + USB11D1 USB11H2 USB2D1 USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24
> + VPI30 VPO12 VPO24 WDTRST1 WDTRST2
This should be a schema. You need to define child nodes and list these
as values for 'function' and 'group'. Ideally, the child nodes would
have some sort of pattern, but if not, you can just match on '^.*$'
under patternProperties.
BTW, You can put the names under a 'definitions' key and then use
'$ref' to reference them from function and group to avoid duplicating
the names. Or use patternProperties with '^(function|group)$'.
Similar comments apply to AST2500 binding.
Rob
^ permalink raw reply
* [PATCH] gpio: tegra: Clean-up debugfs initialisation
From: Jon Hunter @ 2019-06-26 13:42 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Thierry Reding
Cc: linux-gpio, linux-tegra, gregkh, Jon Hunter
The function tegra_gpio_debuginit() just calls debugfs_create_file()
and given that there is already a stub function implemented for
debugfs_create_file() when CONFIG_DEBUG_FS is not enabled, there is
no need for the function tegra_gpio_debuginit() and so remove it.
Finally, use a space and not a tab between the #ifdef and
CONFIG_DEBUG_FS.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
drivers/gpio/gpio-tegra.c | 18 +++---------------
1 file changed, 3 insertions(+), 15 deletions(-)
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 0f59161a4701..59b99d8c3647 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -508,7 +508,7 @@ static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
}
#endif
-#ifdef CONFIG_DEBUG_FS
+#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#include <linux/seq_file.h>
@@ -538,19 +538,6 @@ static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
}
DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio);
-
-static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
-{
- debugfs_create_file("tegra_gpio", 0444, NULL, tgi,
- &tegra_dbg_gpio_fops);
-}
-
-#else
-
-static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
-{
-}
-
#endif
static const struct dev_pm_ops tegra_gpio_pm_ops = {
@@ -675,7 +662,8 @@ static int tegra_gpio_probe(struct platform_device *pdev)
}
}
- tegra_gpio_debuginit(tgi);
+ debugfs_create_file("tegra_gpio", 0444, NULL, tgi,
+ &tegra_dbg_gpio_fops);
return 0;
}
--
2.17.1
^ permalink raw reply related
* Re: [PATCH v3] gpio: mockup: no need to check return value of debugfs_create functions
From: Greg Kroah-Hartman @ 2019-06-26 12:22 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Linus Walleij, linux-gpio, linux-kernel, Bamvor Jian Zhang,
Bartosz Golaszewski
In-Reply-To: <20190626084557.11847-1-brgl@bgdev.pl>
On Wed, Jun 26, 2019 at 10:45:57AM +0200, Bartosz Golaszewski wrote:
> From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>
> When calling debugfs functions, there is no need to ever check the
> return value. The function can work or not, but the code logic should
> never do something different based on this.
>
> Cc: Bamvor Jian Zhang <bamv2005@gmail.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> Cc: linux-gpio@vger.kernel.org
> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> [Bartosz: removed one more check for debugfs return value]
THank you for making this change. I'm on the road all this week and
have had very limited time for email and doing any work like this.
Your change looks good to me!
greg k-h
^ permalink raw reply
* Re: [PATCH v3] gpio: mockup: no need to check return value of debugfs_create functions
From: Bartosz Golaszewski @ 2019-06-26 11:55 UTC (permalink / raw)
To: Linus Walleij
Cc: Greg Kroah-Hartman, open list:GPIO SUBSYSTEM,
linux-kernel@vger.kernel.org, Bamvor Jian Zhang,
Bartosz Golaszewski
In-Reply-To: <CACRpkdZXtFUimMATgKA6Qdo4-mTLW5xV3XvdcBShpO9c32_gbQ@mail.gmail.com>
śr., 26 cze 2019 o 13:54 Linus Walleij <linus.walleij@linaro.org> napisał(a):
>
> On Wed, Jun 26, 2019 at 10:46 AM Bartosz Golaszewski <brgl@bgdev.pl> wrote:
>
> > From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> >
> > When calling debugfs functions, there is no need to ever check the
> > return value. The function can work or not, but the code logic should
> > never do something different based on this.
> >
> > Cc: Bamvor Jian Zhang <bamv2005@gmail.com>
> > Cc: Linus Walleij <linus.walleij@linaro.org>
> > Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> > Cc: linux-gpio@vger.kernel.org
> > Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> > [Bartosz: removed one more check for debugfs return value]
> > Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> > ---
> > v1 -> v2:
> > - fix build warning found by kbuild
> > - fix build error found by kbuild
> >
> > v2 -> v3:
> > - remove one more unnecessary ifdef
>
> Looks good
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
>
> Will you send me this in a pull request with the rest of
> the stuff you have queued?
>
> Yours,
> Linus Walleij
Yes, I'll do it shortly.
Bart
^ permalink raw reply
* Re: [PATCH v3] gpio: mockup: no need to check return value of debugfs_create functions
From: Linus Walleij @ 2019-06-26 11:54 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Greg Kroah-Hartman, open list:GPIO SUBSYSTEM,
linux-kernel@vger.kernel.org, Bamvor Jian Zhang,
Bartosz Golaszewski
In-Reply-To: <20190626084557.11847-1-brgl@bgdev.pl>
On Wed, Jun 26, 2019 at 10:46 AM Bartosz Golaszewski <brgl@bgdev.pl> wrote:
> From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>
> When calling debugfs functions, there is no need to ever check the
> return value. The function can work or not, but the code logic should
> never do something different based on this.
>
> Cc: Bamvor Jian Zhang <bamv2005@gmail.com>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> Cc: linux-gpio@vger.kernel.org
> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> [Bartosz: removed one more check for debugfs return value]
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
> v1 -> v2:
> - fix build warning found by kbuild
> - fix build error found by kbuild
>
> v2 -> v3:
> - remove one more unnecessary ifdef
Looks good
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Will you send me this in a pull request with the rest of
the stuff you have queued?
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 1/5] gpio: siox: Do not call gpiochip_remove() on errorpath
From: Linus Walleij @ 2019-06-26 11:49 UTC (permalink / raw)
To: Uwe Kleine-König; +Cc: open list:GPIO SUBSYSTEM, Bartosz Golaszewski
In-Reply-To: <20190626091220.zemlwyf4ubaawvds@pengutronix.de>
On Wed, Jun 26, 2019 at 11:12 AM Uwe Kleine-König
<u.kleine-koenig@pengutronix.de> wrote:
> On Wed, Jun 26, 2019 at 10:44:03AM +0200, Linus Walleij wrote:
> > gpiochip_remove() was called on the errorpath if
> > gpiochip_add() failed: this is wrong, if the chip failed
> > to add it is not there so it should not be removed.
> >
> > Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> > Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
>
> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
>
> Does this warrant a
>
> Fixes: be8c8facc707 ("gpio: new driver to work with a 8x12 siox")
Thanks yeah I put the fixes in as a lowprio fix that goes
in with the rest of the v5.3 patches.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH] gpio: pl061: Pass irqchip when adding gpiochip
From: Sudeep Holla @ 2019-06-26 11:11 UTC (permalink / raw)
To: Linus Walleij
Cc: linux-gpio, Bartosz Golaszewski, Manivannan Sadhasivam,
Sudeep Holla
In-Reply-To: <20190625111824.28482-1-linus.walleij@linaro.org>
On Tue, Jun 25, 2019 at 01:18:24PM +0200, Linus Walleij wrote:
> We need to convert all old gpio irqchips to pass the irqchip
> setup along when adding the gpio_chip.
>
> For chained irqchips this is a pretty straight-forward
> conversion.
>
FWIW, looks good to me and breaks nothing :), so
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Tested-by: Sudeep Holla <sudeep.holla@arm.com>
--
Regards,
Sudeep
^ permalink raw reply
* Re: [PATCH V4 18/18] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings
From: Thierry Reding @ 2019-06-26 10:28 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: jonathanh, tglx, jason, marc.zyngier, linus.walleij, stefan,
mark.rutland, pdeschrijver, pgaikwad, sboyd, linux-clk,
linux-gpio, jckuo, josephl, talho, linux-tegra, linux-kernel,
mperttunen, spatra, robh+dt, digetx, devicetree
In-Reply-To: <1561345379-2429-19-git-send-email-skomatineni@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 1172 bytes --]
On Sun, Jun 23, 2019 at 08:02:59PM -0700, Sowjanya Komatineni wrote:
> This patch has Jetson TX1 platform specific SC7 timing configuration
> in device tree.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
Can you provide a similar patch for Jetson Nano (p3450-0000)? It'd be
great if we can make new features like this available across all boards.
Thierry
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
> index 27723829d033..cb58f79deb48 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi
> @@ -279,6 +279,13 @@
>
> pmc@7000e400 {
> nvidia,invert-interrupt;
> + nvidia,suspend-mode = <0>;
> + nvidia,cpu-pwr-good-time = <0>;
> + nvidia,cpu-pwr-off-time = <0>;
> + nvidia,core-pwr-good-time = <4587 3876>;
> + nvidia,core-pwr-off-time = <39065>;
> + nvidia,core-power-req-active-high;
> + nvidia,sys-clock-req-active-high;
> };
>
> /* eMMC */
> --
> 2.7.4
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH V4 14/18] soc/tegra: pmc: add pmc wake support for tegra210
From: Thierry Reding @ 2019-06-26 10:26 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: jonathanh, tglx, jason, marc.zyngier, linus.walleij, stefan,
mark.rutland, pdeschrijver, pgaikwad, sboyd, linux-clk,
linux-gpio, jckuo, josephl, talho, linux-tegra, linux-kernel,
mperttunen, spatra, robh+dt, digetx, devicetree
In-Reply-To: <1561345379-2429-15-git-send-email-skomatineni@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 5715 bytes --]
On Sun, Jun 23, 2019 at 08:02:55PM -0700, Sowjanya Komatineni wrote:
> This patch implements PMC wakeup sequence for Tegra210 and defines
> common used RTC alarm wake event.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/soc/tegra/pmc.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 111 insertions(+)
One general note, and it's a really pedantic one, which means that this
patch is plenty good already: sstart the commit subject with a capital
letter after the prefix, and watch the capitalization of the rest of the
line:
soc/tegra: pmc: Add PMC wake support for Tegra210
I will usually fix up these trivialities when applying, but you can save
me a couple of seconds per patch by doing this right to begin with. =)
Thanks again for the great work on this series!
Thierry
>
> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
> index e87f29a35fcf..603fc3bd73f5 100644
> --- a/drivers/soc/tegra/pmc.c
> +++ b/drivers/soc/tegra/pmc.c
> @@ -57,6 +57,12 @@
> #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
> #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
> #define PMC_CNTRL_MAIN_RST BIT(4)
> +#define PMC_CNTRL_LATCH_WAKEUPS BIT(5)
> +
> +#define PMC_WAKE_MASK 0x0c
> +#define PMC_WAKE_LEVEL 0x10
> +#define PMC_WAKE_STATUS 0x14
> +#define PMC_SW_WAKE_STATUS 0x18
>
> #define DPD_SAMPLE 0x020
> #define DPD_SAMPLE_ENABLE BIT(0)
> @@ -87,6 +93,11 @@
>
> #define PMC_SCRATCH41 0x140
>
> +#define PMC_WAKE2_MASK 0x160
> +#define PMC_WAKE2_LEVEL 0x164
> +#define PMC_WAKE2_STATUS 0x168
> +#define PMC_SW_WAKE2_STATUS 0x16c
> +
> #define PMC_SENSOR_CTRL 0x1b0
> #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
> #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
> @@ -1921,6 +1932,55 @@ static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
> .alloc = tegra_pmc_irq_alloc,
> };
>
> +static int tegra210_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
> +{
> + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
> + unsigned int offset, bit;
> + u32 value;
> +
> + if (data->hwirq == ULONG_MAX)
> + return 0;
> +
> + offset = data->hwirq / 32;
> + bit = data->hwirq % 32;
> +
> + /*
> + * latch wakeups to SW_WAKE_STATUS register to capture events
> + * that would not make it into wakeup event register during LP0 exit.
> + */
> + value = tegra_pmc_readl(pmc, PMC_CNTRL);
> + value |= PMC_CNTRL_LATCH_WAKEUPS;
> + tegra_pmc_writel(pmc, value, PMC_CNTRL);
> + udelay(120);
> +
> + value &= ~PMC_CNTRL_LATCH_WAKEUPS;
> + tegra_pmc_writel(pmc, value, PMC_CNTRL);
> + udelay(120);
> +
> + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
> + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
> +
> + tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
> + tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
> +
> + /* enable PMC wake */
> + if (data->hwirq >= 32)
> + offset = PMC_WAKE2_MASK;
> + else
> + offset = PMC_WAKE_MASK;
> +
> + value = tegra_pmc_readl(pmc, offset);
> +
> + if (on)
> + value |= 1 << bit;
> + else
> + value &= ~(1 << bit);
> +
> + tegra_pmc_writel(pmc, value, offset);
> +
> + return 0;
> +}
> +
> static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
> {
> struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
> @@ -1953,6 +2013,49 @@ static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
> return 0;
> }
>
> +static int tegra210_pmc_irq_set_type(struct irq_data *data, unsigned int type)
> +{
> + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
> + unsigned int offset, bit;
> + u32 value;
> +
> + if (data->hwirq == ULONG_MAX)
> + return 0;
> +
> + offset = data->hwirq / 32;
> + bit = data->hwirq % 32;
> +
> + if (data->hwirq >= 32)
> + offset = PMC_WAKE2_LEVEL;
> + else
> + offset = PMC_WAKE_LEVEL;
> +
> + value = tegra_pmc_readl(pmc, offset);
> +
> + switch (type) {
> + case IRQ_TYPE_EDGE_RISING:
> + case IRQ_TYPE_LEVEL_HIGH:
> + value |= 1 << bit;
> + break;
> +
> + case IRQ_TYPE_EDGE_FALLING:
> + case IRQ_TYPE_LEVEL_LOW:
> + value &= ~(1 << bit);
> + break;
> +
> + case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
> + value ^= 1 << bit;
> + break;
> +
> + default:
> + return -EINVAL;
> + }
> +
> + tegra_pmc_writel(pmc, value, offset);
> +
> + return 0;
> +}
> +
> static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)
> {
> struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
> @@ -2541,6 +2644,10 @@ static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
> TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
> };
>
> +static const struct tegra_wake_event tegra210_wake_events[] = {
> + TEGRA_WAKE_IRQ("rtc", 16, 2),
> +};
> +
> static const struct tegra_pmc_soc tegra210_pmc_soc = {
> .num_powergates = ARRAY_SIZE(tegra210_powergates),
> .powergates = tegra210_powergates,
> @@ -2558,10 +2665,14 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {
> .regs = &tegra20_pmc_regs,
> .init = tegra20_pmc_init,
> .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
> + .irq_set_wake = tegra210_pmc_irq_set_wake,
> + .irq_set_type = tegra210_pmc_irq_set_type,
> .reset_sources = tegra210_reset_sources,
> .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
> .reset_levels = NULL,
> .num_reset_levels = 0,
> + .num_wake_events = ARRAY_SIZE(tegra210_wake_events),
> + .wake_events = tegra210_wake_events,
> };
>
> #define TEGRA186_IO_PAD_TABLE(_pad) \
> --
> 2.7.4
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH V4 12/18] clk: tegra210: support for Tegra210 clocks suspend and resume
From: Thierry Reding @ 2019-06-26 10:16 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: jonathanh, tglx, jason, marc.zyngier, linus.walleij, stefan,
mark.rutland, pdeschrijver, pgaikwad, sboyd, linux-clk,
linux-gpio, jckuo, josephl, talho, linux-tegra, linux-kernel,
mperttunen, spatra, robh+dt, digetx, devicetree
In-Reply-To: <1561345379-2429-13-git-send-email-skomatineni@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 8279 bytes --]
On Sun, Jun 23, 2019 at 08:02:53PM -0700, Sowjanya Komatineni wrote:
> This patch adds system suspend and resume support for Tegra210
> clocks.
>
> All the CAR controller settings are lost on suspend when core power
> goes off.
>
> This patch has implementation for saving and restoring all the PLLs
> and clocks context during system suspend and resume to have the
> clocks back to same state for normal operation.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra210.c | 115 ++++++++++++++++++++++++++++++++++++++-
> drivers/clk/tegra/clk.c | 14 +++++
> drivers/clk/tegra/clk.h | 1 +
> 3 files changed, 127 insertions(+), 3 deletions(-)
Can you give a brief overview of how you've been testing this? Is this
just about confirming that "things work fine" after resume? Could we be
more methodical and perhaps check the state of the clock tree before
suspend (perhaps by inspecting debugfs) and comparing it to the state
after resume?
One minor nit below...
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index c414cd72d045..4fb3509fe9f6 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -9,10 +9,12 @@
> #include <linux/clkdev.h>
> #include <linux/of.h>
> #include <linux/of_address.h>
> +#include <linux/of_platform.h>
> #include <linux/delay.h>
> #include <linux/export.h>
> #include <linux/mutex.h>
> #include <linux/clk/tegra.h>
> +#include <linux/syscore_ops.h>
> #include <dt-bindings/clock/tegra210-car.h>
> #include <dt-bindings/reset/tegra210-car.h>
> #include <linux/iopoll.h>
> @@ -20,6 +22,7 @@
> #include <soc/tegra/pmc.h>
>
> #include "clk.h"
> +#include "clk-dfll.h"
> #include "clk-id.h"
>
> /*
> @@ -225,6 +228,7 @@
>
> #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
> #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
> +#define CPU_SOFTRST_CTRL 0x380
>
> #define LVL2_CLK_GATE_OVRA 0xf8
> #define LVL2_CLK_GATE_OVRC 0x3a0
> @@ -2820,6 +2824,7 @@ static int tegra210_enable_pllu(void)
> struct tegra_clk_pll_freq_table *fentry;
> struct tegra_clk_pll pllu;
> u32 reg;
> + int ret;
>
> for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {
> if (fentry->input_rate == pll_ref_freq)
> @@ -2847,10 +2852,10 @@ static int tegra210_enable_pllu(void)
> fence_udelay(1, clk_base);
> reg |= PLL_ENABLE;
> writel(reg, clk_base + PLLU_BASE);
> + fence_udelay(1, clk_base);
>
> - readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg,
> - reg & PLL_BASE_LOCK, 2, 1000);
> - if (!(reg & PLL_BASE_LOCK)) {
> + ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK);
> + if (ret) {
> pr_err("Timed out waiting for PLL_U to lock\n");
> return -ETIMEDOUT;
> }
> @@ -3282,6 +3287,103 @@ static void tegra210_disable_cpu_clock(u32 cpu)
> }
>
> #ifdef CONFIG_PM_SLEEP
> +static u32 cpu_softrst_ctx[3];
> +static struct platform_device *dfll_pdev;
> +#define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4))
> +#define car_writel(_val, _base, _off) \
> + writel_relaxed(_val, clk_base + (_base) + ((_off) * 4))
> +
> +static int tegra210_clk_suspend(void)
> +{
> + int i;
This can be unsigned int.
> + struct device_node *node;
> +
> + tegra_cclkg_burst_policy_save_context();
> +
> + if (!dfll_pdev) {
> + node = of_find_compatible_node(NULL, NULL,
> + "nvidia,tegra210-dfll");
> + if (node)
> + dfll_pdev = of_find_device_by_node(node);
> +
> + of_node_put(node);
> + if (!dfll_pdev)
> + pr_err("dfll node not found. no suspend for dfll\n");
> + }
> +
> + if (dfll_pdev)
> + tegra_dfll_suspend(dfll_pdev);
> +
> + /* Enable PLLP_OUT_CPU after dfll suspend */
> + tegra_clk_set_pllp_out_cpu(true);
> +
> + tegra_sclk_cclklp_burst_policy_save_context();
> +
> + clk_save_context();
> +
> + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
> + cpu_softrst_ctx[i] = car_readl(CPU_SOFTRST_CTRL, i);
> +
> + return 0;
> +}
> +
> +static void tegra210_clk_resume(void)
> +{
> + int i;
And here too.
With that:
Acked-by: Thierry Reding <treding@nvidia.com>
> + struct clk_hw *parent;
> + struct clk *clk;
> +
> + /*
> + * clk_restore_context restores clocks as per the clock tree.
> + *
> + * dfllCPU_out is first in the clock tree to get restored and it
> + * involves programming DFLL controller along with restoring CPUG
> + * clock burst policy.
> + *
> + * DFLL programming needs dfll_ref and dfll_soc peripheral clocks
> + * to be restores which are part ofthe peripheral clocks.
> + * So, peripheral clocks restore should happen prior to dfll clock
> + * restore.
> + */
> +
> + tegra_clk_osc_resume(clk_base);
> + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
> + car_writel(cpu_softrst_ctx[i], CPU_SOFTRST_CTRL, i);
> +
> + /* restore all plls and peripheral clocks */
> + tegra210_init_pllu();
> + clk_restore_context();
> +
> + fence_udelay(5, clk_base);
> +
> + /* resume SCLK and CPULP clocks */
> + tegra_sclk_cpulp_burst_policy_restore_context();
> +
> + /*
> + * restore CPUG clocks:
> + * - enable DFLL in open loop mode
> + * - switch CPUG to DFLL clock source
> + * - close DFLL loop
> + * - sync PLLX state
> + */
> + if (dfll_pdev)
> + tegra_dfll_resume(dfll_pdev, false);
> +
> + tegra_cclkg_burst_policy_restore_context();
> + fence_udelay(2, clk_base);
> +
> + if (dfll_pdev)
> + tegra_dfll_resume(dfll_pdev, true);
> +
> + parent = clk_hw_get_parent(__clk_get_hw(clks[TEGRA210_CLK_CCLK_G]));
> + clk = clks[TEGRA210_CLK_PLL_X];
> + if (parent != __clk_get_hw(clk))
> + tegra_clk_sync_state_pll(__clk_get_hw(clk));
> +
> + /* Disable PLL_OUT_CPU after DFLL resume */
> + tegra_clk_set_pllp_out_cpu(false);
> +}
> +
> static void tegra210_cpu_clock_suspend(void)
> {
> /* switch coresite to clk_m, save off original source */
> @@ -3297,6 +3399,11 @@ static void tegra210_cpu_clock_resume(void)
> }
> #endif
>
> +static struct syscore_ops tegra_clk_syscore_ops = {
> + .suspend = tegra210_clk_suspend,
> + .resume = tegra210_clk_resume,
> +};
> +
> static struct tegra_cpu_car_ops tegra210_cpu_car_ops = {
> .wait_for_reset = tegra210_wait_cpu_in_reset,
> .disable_clock = tegra210_disable_cpu_clock,
> @@ -3582,5 +3689,7 @@ static void __init tegra210_clock_init(struct device_node *np)
> tegra210_mbist_clk_init();
>
> tegra_cpu_car_ops = &tegra210_cpu_car_ops;
> +
> + register_syscore_ops(&tegra_clk_syscore_ops);
> }
> CLK_OF_DECLARE(tegra210, "nvidia,tegra210-car", tegra210_clock_init);
> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
> index 9e863362d2bf..96cc9937ea37 100644
> --- a/drivers/clk/tegra/clk.c
> +++ b/drivers/clk/tegra/clk.c
> @@ -23,6 +23,7 @@
> #define CLK_OUT_ENB_W 0x364
> #define CLK_OUT_ENB_X 0x280
> #define CLK_OUT_ENB_Y 0x298
> +#define CLK_ENB_PLLP_OUT_CPU BIT(31)
> #define CLK_OUT_ENB_SET_L 0x320
> #define CLK_OUT_ENB_CLR_L 0x324
> #define CLK_OUT_ENB_SET_H 0x328
> @@ -205,6 +206,19 @@ const struct tegra_clk_periph_regs *get_reg_bank(int clkid)
> }
> }
>
> +void tegra_clk_set_pllp_out_cpu(bool enable)
> +{
> + u32 val;
> +
> + val = readl_relaxed(clk_base + CLK_OUT_ENB_Y);
> + if (enable)
> + val |= CLK_ENB_PLLP_OUT_CPU;
> + else
> + val &= ~CLK_ENB_PLLP_OUT_CPU;
> +
> + writel_relaxed(val, clk_base + CLK_OUT_ENB_Y);
> +}
> +
> void tegra_cclkg_burst_policy_save_context(void)
> {
> unsigned int i;
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 7b99496fefb9..b994dfaa9602 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -862,6 +862,7 @@ void tegra_cclkg_burst_policy_restore_context(void);
> void tegra_sclk_cclklp_burst_policy_save_context(void);
> void tegra_sclk_cpulp_burst_policy_restore_context(void);
> void tegra_clk_osc_resume(void __iomem *clk_base);
> +void tegra_clk_set_pllp_out_cpu(bool enable);
>
> /* Combined read fence with delay */
> #define fence_udelay(delay, reg) \
> --
> 2.7.4
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH V4 11/18] clk: tegra210: use fence_udelay during PLLU init
From: Thierry Reding @ 2019-06-26 10:12 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: jonathanh, tglx, jason, marc.zyngier, linus.walleij, stefan,
mark.rutland, pdeschrijver, pgaikwad, sboyd, linux-clk,
linux-gpio, jckuo, josephl, talho, linux-tegra, linux-kernel,
mperttunen, spatra, robh+dt, digetx, devicetree
In-Reply-To: <1561345379-2429-12-git-send-email-skomatineni@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 459 bytes --]
On Sun, Jun 23, 2019 at 08:02:52PM -0700, Sowjanya Komatineni wrote:
> This patch uses fence_udelay rather than udelay during PLLU
> initialization to ensure writes to clock registers happens before
> waiting for specified delay.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra210.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
Acked-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH V4 10/18] clk: tegra: add save and restore context support for peripheral clocks
From: Thierry Reding @ 2019-06-26 10:12 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: jonathanh, tglx, jason, marc.zyngier, linus.walleij, stefan,
mark.rutland, pdeschrijver, pgaikwad, sboyd, linux-clk,
linux-gpio, jckuo, josephl, talho, linux-tegra, linux-kernel,
mperttunen, spatra, robh+dt, digetx, devicetree
In-Reply-To: <1561345379-2429-11-git-send-email-skomatineni@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 1044 bytes --]
On Sun, Jun 23, 2019 at 08:02:51PM -0700, Sowjanya Komatineni wrote:
> This patch implements save and restore context for peripheral fixed
> clock ops, peripheral gate clock ops, sdmmc mux clock ops, and
> peripheral clock ops.
>
> During system suspend, core power goes off and looses the settings
> of the Tegra CAR controller registers.
>
> So during suspend entry clock and reset state of peripherals is saved
> and on resume they are restored to have clocks back to same rate and
> state as before suspend.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/clk/tegra/clk-periph-fixed.c | 31 ++++++++++++++++++++++++++
> drivers/clk/tegra/clk-periph-gate.c | 34 ++++++++++++++++++++++++++++
> drivers/clk/tegra/clk-periph.c | 43 ++++++++++++++++++++++++++++++++++++
> drivers/clk/tegra/clk-sdmmc-mux.c | 30 +++++++++++++++++++++++++
> drivers/clk/tegra/clk.h | 8 +++++++
> 5 files changed, 146 insertions(+)
Acked-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH V4 02/18] pinctrl: tegra: add suspend and resume support
From: Thierry Reding @ 2019-06-26 10:08 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: jonathanh, tglx, jason, marc.zyngier, linus.walleij, stefan,
mark.rutland, pdeschrijver, pgaikwad, sboyd, linux-clk,
linux-gpio, jckuo, josephl, talho, linux-tegra, linux-kernel,
mperttunen, spatra, robh+dt, digetx, devicetree
In-Reply-To: <1561345379-2429-3-git-send-email-skomatineni@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 717 bytes --]
On Sun, Jun 23, 2019 at 08:02:43PM -0700, Sowjanya Komatineni wrote:
> This patch adds support for Tegra pinctrl driver suspend and resume.
>
> During suspend, context of all pinctrl registers are stored and
> on resume they are all restored to have all the pinmux and pad
> configuration for normal operation.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/pinctrl/tegra/pinctrl-tegra.c | 47 ++++++++++++++++++++++++++++++++
> drivers/pinctrl/tegra/pinctrl-tegra.h | 4 +++
> drivers/pinctrl/tegra/pinctrl-tegra210.c | 6 ++++
> 3 files changed, 57 insertions(+)
With Dmitry's comments addressed, this is:
Acked-by: Thierry Reding <treding@nvidia.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* [PATCH] unicore: Drop pointless include
From: Linus Walleij @ 2019-06-26 9:34 UTC (permalink / raw)
To: linux-gpio; +Cc: Bartosz Golaszewski, Linus Walleij, Guan Xuetao
I can't see why this file includes <linux/gpio.h>, it is not
using any of the interfaces. Lots of things are named "gpio"
in the file but it is an irqchip driver and has nothing to
do with the GPIO interfaces.
Cc: Guan Xuetao <gxt@pku.edu.cn>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/unicore32/kernel/irq.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/unicore32/kernel/irq.c b/arch/unicore32/kernel/irq.c
index eb1fd0030359..8385e4fc0ff6 100644
--- a/arch/unicore32/kernel/irq.c
+++ b/arch/unicore32/kernel/irq.c
@@ -24,7 +24,6 @@
#include <linux/kallsyms.h>
#include <linux/proc_fs.h>
#include <linux/syscore_ops.h>
-#include <linux/gpio.h>
#include <mach/hardware.h>
--
2.20.1
^ permalink raw reply related
* [PATCH] x86: platform/geode: Drop <linux/gpio.h> includes
From: Linus Walleij @ 2019-06-26 9:21 UTC (permalink / raw)
To: x86
Cc: linux-gpio, Linus Walleij, Andres Salomon, linux-geode,
Andy Shevchenko, Darren Hart, platform-driver-x86
These board files only use gpio_keys not gpio in general.
This include is just surplus, delete it.
Cc: Andres Salomon <dilinger@queued.net>
Cc: linux-geode@lists.infradead.org
Cc: Andy Shevchenko <andy@infradead.org>
Cc: Darren Hart <dvhart@infradead.org>
Cc: platform-driver-x86@vger.kernel.org
Cc: x86@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/x86/platform/geode/alix.c | 1 -
arch/x86/platform/geode/geos.c | 1 -
arch/x86/platform/geode/net5501.c | 1 -
3 files changed, 3 deletions(-)
diff --git a/arch/x86/platform/geode/alix.c b/arch/x86/platform/geode/alix.c
index 1865c196f136..abcf27077bac 100644
--- a/arch/x86/platform/geode/alix.c
+++ b/arch/x86/platform/geode/alix.c
@@ -24,7 +24,6 @@
#include <linux/moduleparam.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
-#include <linux/gpio.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/dmi.h>
diff --git a/arch/x86/platform/geode/geos.c b/arch/x86/platform/geode/geos.c
index 4fcdb91318a0..529ad847d496 100644
--- a/arch/x86/platform/geode/geos.c
+++ b/arch/x86/platform/geode/geos.c
@@ -21,7 +21,6 @@
#include <linux/string.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
-#include <linux/gpio.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/dmi.h>
diff --git a/arch/x86/platform/geode/net5501.c b/arch/x86/platform/geode/net5501.c
index a2f6b982a729..30cb3377ecc7 100644
--- a/arch/x86/platform/geode/net5501.c
+++ b/arch/x86/platform/geode/net5501.c
@@ -22,7 +22,6 @@
#include <linux/string.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
-#include <linux/gpio.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
--
2.20.1
^ permalink raw reply related
* Re: [PATCH 3/5] gpio: siox: Pass irqchip when adding gpiochip
From: Uwe Kleine-König @ 2019-06-26 9:16 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, Bartosz Golaszewski, Thierry Reding
In-Reply-To: <20190626084407.27976-3-linus.walleij@linaro.org>
On Wed, Jun 26, 2019 at 10:44:05AM +0200, Linus Walleij wrote:
> We need to convert all old gpio irqchips to pass the irqchip
> setup along when adding the gpio_chip.
>
> For chained irqchips this is a pretty straight-forward
> conversion.
>
> Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> Cc: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> ChangeLog v1->v2:
> - Split out bugfixes to separate patches.
> ---
> drivers/gpio/gpio-siox.c | 14 +++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpio/gpio-siox.c b/drivers/gpio/gpio-siox.c
> index 40067e1535d3..31749c058e33 100644
> --- a/drivers/gpio/gpio-siox.c
> +++ b/drivers/gpio/gpio-siox.c
> @@ -211,6 +211,7 @@ static int gpio_siox_get_direction(struct gpio_chip *chip, unsigned int offset)
> static int gpio_siox_probe(struct siox_device *sdevice)
> {
> struct gpio_siox_ddata *ddata;
> + struct gpio_irq_chip *girq;
> int ret;
>
> ddata = devm_kzalloc(&sdevice->dev, sizeof(*ddata), GFP_KERNEL);
> @@ -239,6 +240,11 @@ static int gpio_siox_probe(struct siox_device *sdevice)
> ddata->ichip.irq_unmask = gpio_siox_irq_unmask;
> ddata->ichip.irq_set_type = gpio_siox_irq_set_type;
>
> + girq = &ddata->gchip.irq;
> + girq->chip = &ddata->ichip;
> + girq->default_type = IRQ_TYPE_NONE;
> + girq->handler = handle_level_irq;
> +
> ret = gpiochip_add(&ddata->gchip);
> if (ret) {
> dev_err(&sdevice->dev,
> @@ -246,13 +252,7 @@ static int gpio_siox_probe(struct siox_device *sdevice)
> return ret;
> }
>
> - ret = gpiochip_irqchip_add(&ddata->gchip, &ddata->ichip,
> - 0, handle_level_irq, IRQ_TYPE_NONE);
> - if (ret)
> - dev_err(&sdevice->dev,
> - "Failed to register irq chip (%d)\n", ret);
> -
> - return ret;
> + return 0;
> }
You can simplify this a bit further from:
if (ret) {
...
return ret;
}
return 0;
to
if (ret) {
...
}
return ret;
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* Re: [PATCH 5/5] gpio: siox: Use devm_ managed gpiochip
From: Uwe Kleine-König @ 2019-06-26 9:14 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, Bartosz Golaszewski
In-Reply-To: <20190626084407.27976-5-linus.walleij@linaro.org>
Hello,
On Wed, Jun 26, 2019 at 10:44:07AM +0200, Linus Walleij wrote:
> By using devm_gpiochip_add_data() we can get rid of the
> remove() callback. As this driver doesn't use the
> gpiochip data pointer we simply pass in NULL.
>
> Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Thanks,
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* Re: [PATCH 4/5] gpio: siox: Add struct device *dev helper variable
From: Uwe Kleine-König @ 2019-06-26 9:13 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, Bartosz Golaszewski
In-Reply-To: <20190626084407.27976-4-linus.walleij@linaro.org>
On Wed, Jun 26, 2019 at 10:44:06AM +0200, Linus Walleij wrote:
> This makes the code easier to read.
>
> Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
fine,
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Thanks
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* Re: [PATCH 2/5] gpio: siox: Switch to IRQ_TYPE_NONE
From: Uwe Kleine-König @ 2019-06-26 9:12 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, Bartosz Golaszewski
In-Reply-To: <20190626084407.27976-2-linus.walleij@linaro.org>
On Wed, Jun 26, 2019 at 10:44:04AM +0200, Linus Walleij wrote:
> The siox driver is hardcoding a default type of
> IRQ_TYPE_EDGE_RISING to the irq helper, but this should only
> be applicable to old boardfiles and odd device tree irqchips
> with just onecell irq (no flags). I doubt this is the case
> with the siox, I think all consumers specify the flags they
> use in the device tree.
>
> Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Thanks
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* Re: [PATCH 1/5] gpio: siox: Do not call gpiochip_remove() on errorpath
From: Uwe Kleine-König @ 2019-06-26 9:12 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-gpio, Bartosz Golaszewski
In-Reply-To: <20190626084407.27976-1-linus.walleij@linaro.org>
On Wed, Jun 26, 2019 at 10:44:03AM +0200, Linus Walleij wrote:
> gpiochip_remove() was called on the errorpath if
> gpiochip_add() failed: this is wrong, if the chip failed
> to add it is not there so it should not be removed.
>
> Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Does this warrant a
Fixes: be8c8facc707 ("gpio: new driver to work with a 8x12 siox")
?
Thanks
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [RFC/RFT v2 03/14] clk: meson: regmap: export regmap_div ops functions
From: Neil Armstrong @ 2019-06-26 9:06 UTC (permalink / raw)
To: jbrunet, khilman
Cc: linux-arm-kernel, linux-amlogic, linux-kernel, linux-clk,
martin.blumenstingl, linux-gpio, Neil Armstrong
In-Reply-To: <20190626090632.7540-1-narmstrong@baylibre.com>
The G12A CPU Clock Postmux divider needs a custom div_set_rate() call.
Export the clk_regmap_div_round_rate() and clk_regmap_div_recalc_rate()
to be able to override the default clk_regmap_div_set_rate() callback.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/clk/meson/clk-regmap.c | 10 ++++++----
drivers/clk/meson/clk-regmap.h | 5 +++++
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/meson/clk-regmap.c b/drivers/clk/meson/clk-regmap.c
index dcd1757cc5df..26c8c74a8cf0 100644
--- a/drivers/clk/meson/clk-regmap.c
+++ b/drivers/clk/meson/clk-regmap.c
@@ -56,8 +56,8 @@ const struct clk_ops clk_regmap_gate_ro_ops = {
};
EXPORT_SYMBOL_GPL(clk_regmap_gate_ro_ops);
-static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw,
- unsigned long prate)
+unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw,
+ unsigned long prate)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
@@ -74,9 +74,10 @@ static unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw,
return divider_recalc_rate(hw, prate, val, div->table, div->flags,
div->width);
}
+EXPORT_SYMBOL_GPL(clk_regmap_div_recalc_rate);
-static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk);
@@ -100,6 +101,7 @@ static long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate,
return divider_round_rate(hw, rate, prate, div->table, div->width,
div->flags);
}
+EXPORT_SYMBOL_GPL(clk_regmap_div_round_rate);
static int clk_regmap_div_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h
index 1dd0abe3ba91..d22b83fb9bad 100644
--- a/drivers/clk/meson/clk-regmap.h
+++ b/drivers/clk/meson/clk-regmap.h
@@ -78,6 +78,11 @@ clk_get_regmap_div_data(struct clk_regmap *clk)
return (struct clk_regmap_div_data *)clk->data;
}
+unsigned long clk_regmap_div_recalc_rate(struct clk_hw *hw,
+ unsigned long prate);
+long clk_regmap_div_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate);
+
extern const struct clk_ops clk_regmap_divider_ops;
extern const struct clk_ops clk_regmap_divider_ro_ops;
--
2.21.0
^ permalink raw reply related
* [RFC/RFT v2 02/14] clk: core: introduce clk_hw_set_parent()
From: Neil Armstrong @ 2019-06-26 9:06 UTC (permalink / raw)
To: jbrunet, khilman
Cc: linux-arm-kernel, linux-amlogic, linux-kernel, linux-clk,
martin.blumenstingl, linux-gpio, Neil Armstrong
In-Reply-To: <20190626090632.7540-1-narmstrong@baylibre.com>
Introduce the clk_hw_set_parent() provider call to change parent of
a clock by using the clk_hw pointers.
This eases the clock reparenting from clock rate notifiers and
implementing DVFS with simpler code avoiding the boilerplates
functions as __clk_lookup(clk_hw_get_name()) then clk_set_parent().
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/clk/clk.c | 6 ++++++
include/linux/clk-provider.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index aa51756fd4d6..06e1abe3391c 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -2490,6 +2490,12 @@ static int clk_core_set_parent_nolock(struct clk_core *core,
return ret;
}
+int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *parent)
+{
+ return clk_core_set_parent_nolock(hw->core, parent->core);
+}
+EXPORT_SYMBOL_GPL(clk_hw_set_parent);
+
/**
* clk_set_parent - switch the parent of a mux clk
* @clk: the mux clk whose input we are switching
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index bb6118f79784..8a453380f9a4 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -812,6 +812,7 @@ unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
unsigned int index);
+int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
unsigned int __clk_get_enable_count(struct clk *clk);
unsigned long clk_hw_get_rate(const struct clk_hw *hw);
unsigned long __clk_get_flags(struct clk *clk);
--
2.21.0
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox