* Re: [PATCH v1] pinctrl: intel: Drop double check for data in intel_pinctrl_probe_by_uid()
From: Mika Westerberg @ 2019-07-04 13:13 UTC (permalink / raw)
To: Andy Shevchenko; +Cc: linux-gpio, Linus Walleij
In-Reply-To: <20190704130239.24111-1-andriy.shevchenko@linux.intel.com>
On Thu, Jul 04, 2019 at 04:02:39PM +0300, Andy Shevchenko wrote:
> There is no need to duplicate the check which is done in the common
> intel_pinctrl_probe().
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
^ permalink raw reply
* [PATCH v1] pinctrl: intel: Drop double check for data in intel_pinctrl_probe_by_uid()
From: Andy Shevchenko @ 2019-07-04 13:02 UTC (permalink / raw)
To: Mika Westerberg, linux-gpio, Linus Walleij; +Cc: Andy Shevchenko
There is no need to duplicate the check which is done in the common
intel_pinctrl_probe().
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/intel/pinctrl-intel.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index a18d6eefe672..8014c95c649f 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -1421,8 +1421,6 @@ int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
table = (const struct intel_pinctrl_soc_data **)id->driver_data;
data = table[pdev->id];
}
- if (!data)
- return -ENODEV;
return intel_pinctrl_probe(pdev, data);
}
--
2.20.1
^ permalink raw reply related
* [pinctrl:devel 72/79] drivers/pinctrl/aspeed/pinctrl-aspeed.h:547:28: error: field 'pinmux' has incomplete type
From: kbuild test robot @ 2019-07-04 12:10 UTC (permalink / raw)
To: Andrew Jeffery; +Cc: kbuild-all, linux-gpio, Linus Walleij
[-- Attachment #1: Type: text/plain, Size: 5112 bytes --]
tree: https://kernel.googlesource.com/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
head: eb0a2daa45b83d67b69a620243ed844e9dfa671b
commit: efa5623981b72f6b5f95933d1c36ed2518c2ee4e [72/79] pinctrl: aspeed: Split out pinmux from general pinctrl
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout efa5623981b72f6b5f95933d1c36ed2518c2ee4e
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>):
vim +/pinmux +547 drivers/pinctrl/aspeed/pinctrl-aspeed.h
439
440 #define MS_PIN_DECL_(pin, ...) \
441 static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \
442 { __VA_ARGS__, NULL }; \
443 static const struct aspeed_pin_desc PIN_SYM(pin) = \
444 { #pin, PIN_EXPRS_PTR(pin) }
445
446 /**
447 * Declare a multi-signal pin
448 *
449 * @pin: The pin number
450 * @other: Macro name for "other" functionality (subjected to stringification)
451 * @high: Macro name for the highest priority signal functions
452 * @low: Macro name for the low signal functions
453 *
454 * For example:
455 *
456 * #define A8 56
457 * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
458 * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
459 * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
460 * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
461 * SIG_EXPR_PTR(ROMD8, ROM16S));
462 * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
463 * MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6);
464 */
465 #define MS_PIN_DECL(pin, other, high, low) \
466 SIG_EXPR_LIST_DECL_SINGLE(other, other); \
467 MS_PIN_DECL_(pin, \
468 SIG_EXPR_LIST_PTR(high), \
469 SIG_EXPR_LIST_PTR(low), \
470 SIG_EXPR_LIST_PTR(other))
471
472 #define PIN_GROUP_SYM(func) pins_ ## func
> 473 #define FUNC_GROUP_SYM(func) groups_ ## func
474 #define FUNC_GROUP_DECL(func, ...) \
475 static const int PIN_GROUP_SYM(func)[] = { __VA_ARGS__ }; \
> 476 static const char *FUNC_GROUP_SYM(func)[] = { #func }
477
478 /**
479 * Declare a single signal pin
480 *
481 * @pin: The pin number
482 * @other: Macro name for "other" functionality (subjected to stringification)
483 * @sig: Macro name for the signal (subjected to stringification)
484 *
485 * For example:
486 *
487 * #define E3 80
488 * SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
489 * SS_PIN_DECL(E3, GPIOK0, SCL5);
490 */
491 #define SS_PIN_DECL(pin, other, sig) \
492 SIG_EXPR_LIST_DECL_SINGLE(other, other); \
493 MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other))
494
495 /**
496 * Single signal, single function pin declaration
497 *
498 * @pin: The pin number
499 * @other: Macro name for "other" functionality (subjected to stringification)
500 * @sig: Macro name for the signal (subjected to stringification)
501 * @...: Signal descriptors that define the function expression
502 *
503 * For example:
504 *
505 * SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
506 */
507 #define SSSF_PIN_DECL(pin, other, sig, ...) \
508 SIG_EXPR_LIST_DECL_SINGLE(sig, sig, __VA_ARGS__); \
509 SIG_EXPR_LIST_DECL_SINGLE(other, other); \
510 MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)); \
> 511 FUNC_GROUP_DECL(sig, pin)
512
513 #define GPIO_PIN_DECL(pin, gpio) \
514 SIG_EXPR_LIST_DECL_SINGLE(gpio, gpio); \
515 MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio))
516
517 /**
518 * @param The pinconf parameter type
519 * @pins The pin range this config struct covers, [low, high]
520 * @reg The register housing the configuration bits
521 * @mask The mask to select the bits of interest in @reg
522 */
523 struct aspeed_pin_config {
524 enum pin_config_param param;
525 unsigned int pins[2];
526 unsigned int reg;
527 u8 bit;
528 u8 value;
529 };
530
531 #define ASPEED_PINCTRL_PIN(name_) \
532 [name_] = { \
533 .number = name_, \
534 .name = #name_, \
535 .drv_data = (void *) &(PIN_SYM(name_)) \
536 }
537
538 struct aspeed_pinctrl_data {
539 struct regmap *scu;
540
541 const struct pinctrl_pin_desc *pins;
542 const unsigned int npins;
543
544 const struct aspeed_pin_config *configs;
545 const unsigned int nconfigs;
546
> 547 struct aspeed_pinmux_data pinmux;
548 };
549
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 71063 bytes --]
^ permalink raw reply
* Re: [PATCH] Revert "spi: gpio: Don't request CS GPIO in DT use-case"
From: Mark Brown @ 2019-07-04 11:49 UTC (permalink / raw)
To: Linus Walleij; +Cc: linux-spi, open list:GPIO SUBSYSTEM, Andrey Smirnov
In-Reply-To: <CACRpkdaUTvMJ3tbuA7moyLjn_+6QbfJwm3UhLxA1-nh+A5y_KA@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 188 bytes --]
On Thu, Jul 04, 2019 at 09:00:17AM +0200, Linus Walleij wrote:
> Hi Mark,
>
> the proper fix is now upstream in Torvald's tree so you can drop/revert
> this patch.
Great, thanks.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH V5 02/18] pinctrl: tegra: Add suspend and resume support
From: Dmitry Osipenko @ 2019-07-04 10:40 UTC (permalink / raw)
To: Linus Walleij
Cc: Sowjanya Komatineni, thierry.reding@gmail.com, Jon Hunter,
Thomas Gleixner, Jason Cooper, Marc Zyngier, Stefan Agner,
Mark Rutland, Peter De Schrijver, Prashant Gaikwad, Stephen Boyd,
linux-clk, open list:GPIO SUBSYSTEM, jckuo, Joseph Lo, talho,
linux-tegra, linux-kernel@vger.kernel.org, Mikko Perttunen,
spatra, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <CACRpkdYdCmT0ErTuewYbv7bPkjoFLrK9KSVuKVMkAXNQYAGV7g@mail.gmail.com>
04.07.2019 10:31, Linus Walleij пишет:
> On Sat, Jun 29, 2019 at 5:58 PM Dmitry Osipenko <digetx@gmail.com> wrote:
>
>> Oh, also what about GPIO-pinctrl suspend resume ordering .. is it okay that pinctrl
>> will be resumed after GPIO? Shouldn't a proper pin-muxing be selected at first?
>
> Thierry sent some initial patches about this I think. We need to use
> device links for this to work properly so he adds support for
> linking the pinctrl and GPIO devices through the ranges.
>
> For links between pin control handles and their consumers, see also:
> 036f394dd77f pinctrl: Enable device link creation for pin control
> c6045b4e3cad pinctrl: stmfx: enable links creations
> 489b64d66325 pinctrl: stm32: Add links to consumers
>
> I am using STM32 as guinea pig for this, consider adding links also
> from the Tegra pinctrl. I might simply make these pinctrl consumer
> to producer links default because I think it makes a lot sense.
IIUC, currently the plan is to resume pinctrl *after* GPIO for Tegra210 [1]. But this
contradicts to what was traditionally done for older Tegras where pinctrl was always
resumed first and apparently it won't work well for the GPIO ranges as well. I think this
and the other patchsets related to suspend-resume still need some more thought.
[1] https://patchwork.kernel.org/patch/11012077/
^ permalink raw reply
* [PATCH v2] pinctrl: msm8998: Squash TSIF pins together
From: Marc Gonzalez @ 2019-07-04 8:57 UTC (permalink / raw)
To: Bjorn Andersson, Jonathan Neuschäfer, Jeffrey Hugo,
Linus Walleij
Cc: MSM, Linux ARM, gpio, DT, Rob Herring
TSIF is the Transport Stream Interface.
First, rename tsif1 to tsif0, and tsif2 to tsif1.
Then squash all 5 tsif0 pins into a single function.
Same for tsif1.
Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
---
Changes from v1:
- Reword commit message for clarity (hopefully)
- Drop unrelated change in qcom,msm8998-pinctrl.txt
- CC DT
---
.../bindings/pinctrl/qcom,msm8998-pinctrl.txt | 5 +-
drivers/pinctrl/qcom/pinctrl-msm8998.c | 76 +++++--------------
2 files changed, 20 insertions(+), 61 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
index 00174f08ba1d..18e3f3d3e3c5 100644
--- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
@@ -124,9 +124,8 @@ to specify in a pin configuration subnode:
qlink_request, qua_mi2s, sd_card, sd_write, sdc40, sdc41,
sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu,
spkr_i2s, ssbi1, ssc_irq, ter_mi2s, tgu_ch0, tgu_ch1,
- tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en,
- tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en,
- tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present,
+ tsense_pwm1, tsense_pwm2, tsif0, tsif1,
+ uim1_clk, uim1_data, uim1_present,
uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset,
uim_batt, usb_phy, vfr_1, vsense_clkout, vsense_data0,
vsense_data1, vsense_mode, wlan1_adc0, wlan1_adc1,
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8998.c b/drivers/pinctrl/qcom/pinctrl-msm8998.c
index 00d7b94bc3f1..a05f41fe2706 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8998.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8998.c
@@ -581,16 +581,8 @@ enum msm8998_functions {
msm_mux_tgu_ch1,
msm_mux_tsense_pwm1,
msm_mux_tsense_pwm2,
- msm_mux_tsif1_clk,
- msm_mux_tsif1_data,
- msm_mux_tsif1_en,
- msm_mux_tsif1_error,
- msm_mux_tsif1_sync,
- msm_mux_tsif2_clk,
- msm_mux_tsif2_data,
- msm_mux_tsif2_en,
- msm_mux_tsif2_error,
- msm_mux_tsif2_sync,
+ msm_mux_tsif0,
+ msm_mux_tsif1,
msm_mux_uim1_clk,
msm_mux_uim1_data,
msm_mux_uim1_present,
@@ -692,9 +684,6 @@ static const char * const atest_usb13_groups[] = {
static const char * const bimc_dte1_groups[] = {
"gpio8", "gpio10",
};
-static const char * const tsif1_sync_groups[] = {
- "gpio9",
-};
static const char * const wlan1_adc0_groups[] = {
"gpio9",
};
@@ -863,9 +852,6 @@ static const char * const lpass_slimbus_groups[] = {
static const char * const sd_write_groups[] = {
"gpio40",
};
-static const char * const tsif1_error_groups[] = {
- "gpio40",
-};
static const char * const blsp_spi6_groups[] = {
"gpio41", "gpio42", "gpio43", "gpio44",
};
@@ -1048,11 +1034,8 @@ static const char * const blsp_uim2_b_groups[] = {
static const char * const blsp_i2c5_groups[] = {
"gpio87", "gpio88",
};
-static const char * const tsif1_clk_groups[] = {
- "gpio89",
-};
-static const char * const tsif1_en_groups[] = {
- "gpio90",
+static const char * const tsif0_groups[] = {
+ "gpio9", "gpio40", "gpio89", "gpio90", "gpio91",
};
static const char * const mdp_vsync0_groups[] = {
"gpio90",
@@ -1075,17 +1058,14 @@ static const char * const tgu_ch0_groups[] = {
static const char * const qdss_cti1_b_groups[] = {
"gpio90", "gpio91",
};
-static const char * const tsif1_data_groups[] = {
- "gpio91",
-};
static const char * const sdc4_cmd_groups[] = {
"gpio91",
};
static const char * const tgu_ch1_groups[] = {
"gpio91",
};
-static const char * const tsif2_error_groups[] = {
- "gpio92",
+static const char * const tsif1_groups[] = {
+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96",
};
static const char * const sdc43_groups[] = {
"gpio92",
@@ -1093,30 +1073,18 @@ static const char * const sdc43_groups[] = {
static const char * const vfr_1_groups[] = {
"gpio92",
};
-static const char * const tsif2_clk_groups[] = {
- "gpio93",
-};
static const char * const sdc4_clk_groups[] = {
"gpio93",
};
-static const char * const tsif2_en_groups[] = {
- "gpio94",
-};
static const char * const sdc42_groups[] = {
"gpio94",
};
static const char * const sd_card_groups[] = {
"gpio95",
};
-static const char * const tsif2_data_groups[] = {
- "gpio95",
-};
static const char * const sdc41_groups[] = {
"gpio95",
};
-static const char * const tsif2_sync_groups[] = {
- "gpio96",
-};
static const char * const sdc40_groups[] = {
"gpio96",
};
@@ -1355,16 +1323,8 @@ static const struct msm_function msm8998_functions[] = {
FUNCTION(tgu_ch1),
FUNCTION(tsense_pwm1),
FUNCTION(tsense_pwm2),
- FUNCTION(tsif1_clk),
- FUNCTION(tsif1_data),
- FUNCTION(tsif1_en),
- FUNCTION(tsif1_error),
- FUNCTION(tsif1_sync),
- FUNCTION(tsif2_clk),
- FUNCTION(tsif2_data),
- FUNCTION(tsif2_en),
- FUNCTION(tsif2_error),
- FUNCTION(tsif2_sync),
+ FUNCTION(tsif0),
+ FUNCTION(tsif1),
FUNCTION(uim1_clk),
FUNCTION(uim1_data),
FUNCTION(uim1_present),
@@ -1396,7 +1356,7 @@ static const struct msm_pingroup msm8998_groups[] = {
PINGROUP(6, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, _, _, _, _, _, _),
PINGROUP(7, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, ddr_bist, _, atest_tsens2, atest_usb1, _, _),
PINGROUP(8, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, _, ddr_bist, _, wlan1_adc1, atest_usb13, bimc_dte1),
- PINGROUP(9, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, tsif1_sync, ddr_bist, _, wlan1_adc0, atest_usb12, bimc_dte0),
+ PINGROUP(9, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, tsif0, ddr_bist, _, wlan1_adc0, atest_usb12, bimc_dte0),
PINGROUP(10, EAST, mdp_vsync_a, blsp_spi4, blsp_uart1_b, blsp_i2c4, ddr_bist, atest_gpsadc1, wlan2_adc1, atest_usb11, bimc_dte1),
PINGROUP(11, EAST, mdp_vsync_a, edp_lcd, blsp_spi4, blsp_uart1_b, blsp_i2c4, dbg_out, atest_gpsadc0, wlan2_adc0, atest_usb10),
PINGROUP(12, EAST, mdp_vsync, m_voc, _, _, _, _, _, _, _),
@@ -1427,7 +1387,7 @@ static const struct msm_pingroup msm8998_groups[] = {
PINGROUP(37, NORTH, agera_pll, _, _, _, _, _, _, _, _),
PINGROUP(38, WEST, usb_phy, _, _, _, _, _, _, _, _),
PINGROUP(39, WEST, lpass_slimbus, _, _, _, _, _, _, _, _),
- PINGROUP(40, EAST, sd_write, tsif1_error, _, _, _, _, _, _, _),
+ PINGROUP(40, EAST, sd_write, tsif0, _, _, _, _, _, _, _),
PINGROUP(41, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _),
PINGROUP(42, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _),
PINGROUP(43, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, _, qdss, _, _, _, _),
@@ -1476,14 +1436,14 @@ static const struct msm_pingroup msm8998_groups[] = {
PINGROUP(86, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, _, _, _, _, _, _),
PINGROUP(87, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _),
PINGROUP(88, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _),
- PINGROUP(89, EAST, tsif1_clk, phase_flag, _, _, _, _, _, _, _),
- PINGROUP(90, EAST, tsif1_en, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, _),
- PINGROUP(91, EAST, tsif1_data, sdc4_cmd, tgu_ch1, phase_flag, qdss_cti1_b, _, _, _, _),
- PINGROUP(92, EAST, tsif2_error, sdc43, vfr_1, phase_flag, _, _, _, _, _),
- PINGROUP(93, EAST, tsif2_clk, sdc4_clk, _, qdss, _, _, _, _, _),
- PINGROUP(94, EAST, tsif2_en, sdc42, _, _, _, _, _, _, _),
- PINGROUP(95, EAST, tsif2_data, sdc41, _, _, _, _, _, _, _),
- PINGROUP(96, EAST, tsif2_sync, sdc40, phase_flag, _, _, _, _, _, _),
+ PINGROUP(89, EAST, tsif0, phase_flag, _, _, _, _, _, _, _),
+ PINGROUP(90, EAST, tsif0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, _),
+ PINGROUP(91, EAST, tsif0, sdc4_cmd, tgu_ch1, phase_flag, qdss_cti1_b, _, _, _, _),
+ PINGROUP(92, EAST, tsif1, sdc43, vfr_1, phase_flag, _, _, _, _, _),
+ PINGROUP(93, EAST, tsif1, sdc4_clk, _, qdss, _, _, _, _, _),
+ PINGROUP(94, EAST, tsif1, sdc42, _, _, _, _, _, _, _),
+ PINGROUP(95, EAST, tsif1, sdc41, _, _, _, _, _, _, _),
+ PINGROUP(96, EAST, tsif1, sdc40, phase_flag, _, _, _, _, _, _),
PINGROUP(97, WEST, _, mdp_vsync_b, ldo_en, _, _, _, _, _, _),
PINGROUP(98, WEST, _, mdp_vsync_b, ldo_update, _, _, _, _, _, _),
PINGROUP(99, WEST, _, _, _, _, _, _, _, _, _),
--
2.17.1
^ permalink raw reply related
* Re: [PATCH v1] pinctrl: baytrail: Use GENMASK() consistently
From: Linus Walleij @ 2019-07-04 7:58 UTC (permalink / raw)
To: Andy Shevchenko; +Cc: Mika Westerberg, open list:GPIO SUBSYSTEM
In-Reply-To: <20190703151554.30454-1-andriy.shevchenko@linux.intel.com>
On Wed, Jul 3, 2019 at 5:15 PM Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
> Use GENMASK() macro for all definitions where it's appropriate.
> No functional change intended.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Patch applied with Mika's ACK.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v1 2/2] pinctrl: baytrail: Re-use data structures from pinctrl-intel.h
From: Linus Walleij @ 2019-07-04 7:51 UTC (permalink / raw)
To: Andy Shevchenko; +Cc: Mika Westerberg, open list:GPIO SUBSYSTEM, Hans de Goede
In-Reply-To: <20190703003018.75186-2-andriy.shevchenko@linux.intel.com>
On Wed, Jul 3, 2019 at 2:30 AM Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
> We have some data structures duplicated across the drivers.
> Let's deduplicate them by using ones that being provided by
> pinctrl-intel.h.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Patch applied with Mika's ACK.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v1 1/2] pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux()
From: Linus Walleij @ 2019-07-04 7:50 UTC (permalink / raw)
To: Andy Shevchenko; +Cc: Mika Westerberg, open list:GPIO SUBSYSTEM, Hans de Goede
In-Reply-To: <20190703003018.75186-1-andriy.shevchenko@linux.intel.com>
On Wed, Jul 3, 2019 at 2:30 AM Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
> By the fact byt_get_gpio_mux() returns a value of mux settings as
> it is represented in hardware. Use defined macro instead of magic numbers
> to clarify this.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Patch applied directly with the ACKs.
A bit late for administrating pull requests now, so I just
apply this stuff.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v2 2/3] dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding
From: Linus Walleij @ 2019-07-04 7:46 UTC (permalink / raw)
To: Vinod Koul
Cc: MSM, Bjorn Andersson, Prasad Sodagudi, Andy Gross, Rob Herring,
Mark Rutland, open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org, Isaac J . Manjarres
In-Reply-To: <20190702105045.27646-3-vkoul@kernel.org>
On Tue, Jul 2, 2019 at 12:54 PM Vinod Koul <vkoul@kernel.org> wrote:
> From: Prasad Sodagudi <psodagud@codeaurora.org>
>
> Add the binding for the TLMM pinctrl block found in the SM8150 platform.
>
> Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
> Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
> [vkoul: add missing nodes of gpio range and reserved
> rewrote function names and order them]
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Patch applied with Bjorn's ACK.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v2 1/3] dt-bindings: pinctrl: qcom: Document missing gpio nodes
From: Linus Walleij @ 2019-07-04 7:45 UTC (permalink / raw)
To: Vinod Koul
Cc: MSM, Bjorn Andersson, Andy Gross, Rob Herring, Mark Rutland,
open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org
In-Reply-To: <20190702105045.27646-2-vkoul@kernel.org>
On Tue, Jul 2, 2019 at 12:54 PM Vinod Koul <vkoul@kernel.org> wrote:
> The bindings for msm8998-pinctrl was missing gpio-ranges and
> gpio-reserved-ranges, so document them as well
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Patch applied with Bjorn's ACK.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 4/4] gpio: stp-xway: allow compile-testing
From: Linus Walleij @ 2019-07-04 7:44 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: John Crispin, Bartosz Golaszewski, open list:GPIO SUBSYSTEM, dev,
linux-kernel@vger.kernel.org
In-Reply-To: <20190702223248.31934-5-martin.blumenstingl@googlemail.com>
On Wed, Jul 3, 2019 at 12:33 AM Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
> Enable compile-testing of the stp-xway GPIO driver now that it does not
> depend on any architecture specific includes anymore.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 3/4] gpio: stp-xway: get rid of the #include <lantiq_soc.h> dependency
From: Linus Walleij @ 2019-07-04 7:41 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: John Crispin, Bartosz Golaszewski, open list:GPIO SUBSYSTEM, dev,
linux-kernel@vger.kernel.org
In-Reply-To: <20190702223248.31934-4-martin.blumenstingl@googlemail.com>
On Wed, Jul 3, 2019 at 12:33 AM Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
> Use the xway_stp_{r,w}32 helpers in xway_stp_w32_mask instead of relying
> on ltq_{r,w}32 from the architecture specific <lantiq_soc.h>.
> This will allow the driver to be compile-tested on all architectures
> that support MMIO.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 2/4] gpio: stp-xway: improve module clock error handling
From: Linus Walleij @ 2019-07-04 7:40 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: John Crispin, Bartosz Golaszewski, open list:GPIO SUBSYSTEM, dev,
linux-kernel@vger.kernel.org
In-Reply-To: <20190702223248.31934-3-martin.blumenstingl@googlemail.com>
On Wed, Jul 3, 2019 at 12:33 AM Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
> Three module clock error handling improvements:
> - use devm_clk_get() so the clock instance can be freed if
> devm_gpiochip_add_data() fails later on
> - switch to clk_prepare_enable() so the driver is ready whenever the
> lantiq target switches to the common clock framework
> - disable the clock again (using clk_disable_unprepare()) if
> devm_gpiochip_add_data()
>
> All of these are virtually no-ops with the current lantiq target.
> However, these will be relevant if we switch to the common clock
> framework.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 1/4] gpio: stp-xway: simplify error handling in xway_stp_probe()
From: Linus Walleij @ 2019-07-04 7:39 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: John Crispin, Bartosz Golaszewski, open list:GPIO SUBSYSTEM, dev,
linux-kernel@vger.kernel.org
In-Reply-To: <20190702223248.31934-2-martin.blumenstingl@googlemail.com>
On Wed, Jul 3, 2019 at 12:33 AM Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
> Return early if devm_gpiochip_add_data() returns an error instead of
> having two consecutive "if (!ret) ..." statements.
>
> Also make xway_stp_hw_init() return void because it unconditionally
> returns 0. While here also update the kerneldoc comment for
> xway_stp_hw_init().
>
> These changes makes the error handling within the driver consistent.
> No functional changes intended.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH] gpiolib: Clarify use of non-sleeping functions
From: Linus Walleij @ 2019-07-04 7:36 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Bartosz Golaszewski, open list:GPIO SUBSYSTEM,
linux-kernel@vger.kernel.org
In-Reply-To: <20190701142809.25308-1-geert+renesas@glider.be>
On Mon, Jul 1, 2019 at 4:28 PM Geert Uytterhoeven
<geert+renesas@glider.be> wrote:
> Obviously functions that are safe to be called from atomic contexts, can
> be called from non-atomic contexts, too.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH] gpiolib: Fix references to gpiod_[gs]et_*value_cansleep() variants
From: Linus Walleij @ 2019-07-04 7:35 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Bartosz Golaszewski, open list:GPIO SUBSYSTEM,
linux-kernel@vger.kernel.org
In-Reply-To: <20190701142738.25219-1-geert+renesas@glider.be>
On Mon, Jul 1, 2019 at 4:27 PM Geert Uytterhoeven
<geert+renesas@glider.be> wrote:
> Commit 372e722ea4dd4ca1 ("gpiolib: use descriptors internally") renamed
> the functions to use a "gpiod" prefix, and commit 79a9becda8940deb
> ("gpiolib: export descriptor-based GPIO interface") introduced the "raw"
> variants, but both changes forgot to update the comments.
>
> Readd a similar reference to gpiod_set_value(), which was accidentally
> removed by commit 1e77fc82110ac36f ("gpio: Add missing open drain/source
> handling to gpiod_set_value_cansleep()").
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH] gpiolib: Document new gpio_chip.init_valid_mask field
From: Linus Walleij @ 2019-07-04 7:34 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Bartosz Golaszewski, Ricardo Ribalda Delgado,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org
In-Reply-To: <20190701142650.25122-1-geert+renesas@glider.be>
On Mon, Jul 1, 2019 at 4:26 PM Geert Uytterhoeven
<geert+renesas@glider.be> wrote:
> A new field init_valid_mask was added to struct gpio_chip, but it was
> not documented.
>
> Fixes: f8ec92a9f63b3b11 ("gpiolib: Add init_valid_mask exported function")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH] Documentation: gpio: Fix reference to gpiod_get_array()
From: Linus Walleij @ 2019-07-04 7:33 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Bartosz Golaszewski, Jonathan Corbet, Janusz Krzysztofik,
open list:GPIO SUBSYSTEM, Linux Doc Mailing List,
linux-kernel@vger.kernel.org
In-Reply-To: <20190701141005.24631-1-geert+renesas@glider.be>
On Mon, Jul 1, 2019 at 4:10 PM Geert Uytterhoeven
<geert+renesas@glider.be> wrote:
> The function is called gpiod_get_array(), not gpiod_array_get().
>
> Fixes: 77588c14ac868cae ("gpiolib: Pass array info to get/set array functions")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH V5 02/18] pinctrl: tegra: Add suspend and resume support
From: Linus Walleij @ 2019-07-04 7:31 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Sowjanya Komatineni, thierry.reding@gmail.com, Jon Hunter,
Thomas Gleixner, Jason Cooper, Marc Zyngier, Stefan Agner,
Mark Rutland, Peter De Schrijver, Prashant Gaikwad, Stephen Boyd,
linux-clk, open list:GPIO SUBSYSTEM, jckuo, Joseph Lo, talho,
linux-tegra, linux-kernel@vger.kernel.org, Mikko Perttunen,
spatra, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <822867d6-4a4d-5f68-9b21-84a20d73c589@gmail.com>
On Sat, Jun 29, 2019 at 5:58 PM Dmitry Osipenko <digetx@gmail.com> wrote:
> Oh, also what about GPIO-pinctrl suspend resume ordering .. is it okay that pinctrl
> will be resumed after GPIO? Shouldn't a proper pin-muxing be selected at first?
Thierry sent some initial patches about this I think. We need to use
device links for this to work properly so he adds support for
linking the pinctrl and GPIO devices through the ranges.
For links between pin control handles and their consumers, see also:
036f394dd77f pinctrl: Enable device link creation for pin control
c6045b4e3cad pinctrl: stmfx: enable links creations
489b64d66325 pinctrl: stm32: Add links to consumers
I am using STM32 as guinea pig for this, consider adding links also
from the Tegra pinctrl. I might simply make these pinctrl consumer
to producer links default because I think it makes a lot sense.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH V5 02/18] pinctrl: tegra: Add suspend and resume support
From: Linus Walleij @ 2019-07-04 7:26 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: thierry.reding@gmail.com, Jon Hunter, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Stefan Agner, Mark Rutland,
Peter De Schrijver, Prashant Gaikwad, Stephen Boyd, linux-clk,
open list:GPIO SUBSYSTEM, jckuo, Joseph Lo, talho, linux-tegra,
linux-kernel@vger.kernel.org, Mikko Perttunen, spatra,
Rob Herring, Dmitry Osipenko,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <1561687972-19319-3-git-send-email-skomatineni@nvidia.com>
On Fri, Jun 28, 2019 at 4:13 AM Sowjanya Komatineni
<skomatineni@nvidia.com> wrote:
> This patch adds support for Tegra pinctrl driver suspend and resume.
>
> During suspend, context of all pinctrl registers are stored and
> on resume they are all restored to have all the pinmux and pad
> configuration for normal operation.
>
> Acked-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Looks good.
Can I just apply this patch or does it need to go in with
the other (clk) changes?
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH] Revert "spi: gpio: Don't request CS GPIO in DT use-case"
From: Linus Walleij @ 2019-07-04 7:00 UTC (permalink / raw)
To: Mark Brown, linux-spi; +Cc: open list:GPIO SUBSYSTEM, Andrey Smirnov
In-Reply-To: <20190701172517.31641-1-linus.walleij@linaro.org>
Hi Mark,
the proper fix is now upstream in Torvald's tree so you can drop/revert
this patch.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] platform/x86: Fix PCENGINES_APU2 Kconfig warning
From: YueHaibing @ 2019-07-04 6:27 UTC (permalink / raw)
To: dvhart, andy, linus.walleij, rdunlap, info
Cc: linux-kernel, platform-driver-x86, linux-gpio, YueHaibing
Fix Kconfig warning for PCENGINES_APU2 symbol:
WARNING: unmet direct dependencies detected for GPIO_AMD_FCH
Depends on [n]: GPIOLIB [=n] && HAS_IOMEM [=y]
Selected by [y]:
- PCENGINES_APU2 [=y] && X86 [=y] && X86_PLATFORM_DEVICES [=y] && INPUT [=y] && INPUT_KEYBOARD [=y] && LEDS_CLASS [=y]
WARNING: unmet direct dependencies detected for KEYBOARD_GPIO_POLLED
Depends on [n]: !UML && INPUT [=y] && INPUT_KEYBOARD [=y] && GPIOLIB [=n]
Selected by [y]:
- PCENGINES_APU2 [=y] && X86 [=y] && X86_PLATFORM_DEVICES [=y] && INPUT [=y] && INPUT_KEYBOARD [=y] && LEDS_CLASS [=y]
Add GPIOLIB dependency to fix it.
Reported-by: Hulk Robot <hulkci@huawei.com>
Fixes: f8eb0235f659 ("x86: pcengines apuv2 gpio/leds/keys platform driver")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
---
drivers/platform/x86/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index 8c8bd45..2409d26 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -1322,7 +1322,7 @@ config HUAWEI_WMI
config PCENGINES_APU2
tristate "PC Engines APUv2/3 front button and LEDs driver"
- depends on INPUT && INPUT_KEYBOARD
+ depends on INPUT && INPUT_KEYBOARD && GPIOLIB
depends on LEDS_CLASS
select GPIO_AMD_FCH
select KEYBOARD_GPIO_POLLED
--
2.7.4
^ permalink raw reply related
* Re: [PATCH V4 2/2] gpio: inverter: document the inverter bindings
From: Harish Jenny K N @ 2019-07-04 5:01 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Rob Herring, Mark Rutland
Cc: devicetree, linux-gpio, Balasubramani Vivekanandan
In-Reply-To: <1561714250-19613-1-git-send-email-harish_kandiga@mentor.com>
Hi,
On 28/06/19 3:00 PM, Harish Jenny K N wrote:
> Document the device tree binding for the inverter gpio
> controller to configure the polarity of the gpio pins
> used by the consumers.
>
> Signed-off-by: Harish Jenny K N <harish_kandiga@mentor.com>
> ---
> .../devicetree/bindings/gpio/gpio-inverter.txt | 29 ++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/gpio/gpio-inverter.txt
>
> diff --git a/Documentation/devicetree/bindings/gpio/gpio-inverter.txt b/Documentation/devicetree/bindings/gpio/gpio-inverter.txt
> new file mode 100644
> index 0000000..8bb6b2e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/gpio/gpio-inverter.txt
> @@ -0,0 +1,29 @@
> +GPIO-INVERTER
> +======
> +This binding defines the gpio-inverter. The gpio-inverter is a driver that
> +allows to properly describe the gpio polarities on the hardware.
> +
> +Please refer to gpio.txt for generic information regarding GPIO bindings.
> +
> +Required properties:
> +- compatible : "gpio-inverter".
> +- gpio-controller: Marks the port as GPIO controller.
> +- #gpio-cells: One. This is the pin number.
> +- inverted-gpios: Array of GPIO pins required from consumers, whose polarity
> + has to be inverted in the driver.
> +Note: gpio flag should be set as GPIO_ACTIVE_HIGH. Using GPIO_ACTICE_LOW will
> +cause double inversion.
> +
> +Optional properties:
> +- gpio-line-names: Refer to gpio.txt for details regarding this property.
> +
> +Example:
> +
> +gpio_inv: gpio-inv {
> + compatible = "gpio-inverter";
> + gpio-controller;
> + #gpio-cells = <1>;
> + inverted-gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>,
> + <&gpio7 0 GPIO_ACTIVE_HIGH>, <&gpio7 1 GPIO_ACTIVE_HIGH>;
> + gpio-line-names = "JTAG_DNL_EN", "lvds-pwrdwn", "lcd-on";
> +};
> --
> 2.7.4
>
Can anyone of DT people please review this ?
Just to let you know that Linus Walleij has reviewed the gpio inverter driver and needs some review from the DT people before he applies it.
Thanks in advance.
Best Regards,
Harish Jenny K N
^ permalink raw reply
* [PATCH v2] gpiolib: Preserve desc->flags when setting state
From: Chris Packham @ 2019-07-04 4:20 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, ricardo.ribalda
Cc: linux-gpio, linux-kernel, Chris Packham
desc->flags may already have values set by of_gpiochip_add() so make
sure that this isn't undone when setting the initial direction.
Fixes: 3edfb7bd76bd1cba ("gpiolib: Show correct direction from the beginning")
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
---
Notes:
Changes in v2:
- add braces to avoid ambiguious else warning
drivers/gpio/gpiolib.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index e013d417a936..5ac57264171b 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1392,12 +1392,13 @@ int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data,
for (i = 0; i < chip->ngpio; i++) {
struct gpio_desc *desc = &gdev->descs[i];
- if (chip->get_direction && gpiochip_line_is_valid(chip, i))
- desc->flags = !chip->get_direction(chip, i) ?
- (1 << FLAG_IS_OUT) : 0;
- else
- desc->flags = !chip->direction_input ?
- (1 << FLAG_IS_OUT) : 0;
+ if (chip->get_direction && gpiochip_line_is_valid(chip, i)) {
+ if (!chip->get_direction(chip, i))
+ set_bit(FLAG_IS_OUT, &desc->flags);
+ } else {
+ if (!chip->direction_input)
+ set_bit(FLAG_IS_OUT, &desc->flags);
+ }
}
acpi_gpiochip_add(chip);
--
2.22.0
^ permalink raw reply related
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