* Re: [PATCH v4 5/8] clk: sunxi-ng: v3s: add Allwinner V3 support
From: Rob Herring @ 2019-07-22 17:07 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Maxime Ripard, Chen-Yu Tsai, Linus Walleij, devicetree,
linux-arm-kernel, linux-kernel, linux-clk, linux-gpio,
linux-sunxi, Icenowy Zheng
In-Reply-To: <20190713034634.44585-6-icenowy@aosc.io>
On Sat, 13 Jul 2019 11:46:31 +0800, Icenowy Zheng wrote:
> Allwinner V3 has the same main die with V3s, but with more pins wired.
> There's a I2S bus on V3 that is not available on V3s.
>
> Add the V3-only peripheral's clocks and reset to the V3s CCU driver,
> bound to a new V3 compatible string. The driver name is not changed
> because it's part of the device tree binding (the header file name).
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> Changes in v4:
> - Add the missing MMC2 clock slices.
>
> No changes in v3/v2.
>
> drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 228 +++++++++++++++++++++-
> drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 2 +-
> include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 +
> include/dt-bindings/reset/sun8i-v3s-ccu.h | 3 +
> 4 files changed, 234 insertions(+), 3 deletions(-)
>
Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.
If a tag was not added on purpose, please state why and what changed.
^ permalink raw reply
* Re: [PATCH V6 01/21] irqchip: tegra: Do not disable COP IRQ during suspend
From: Sowjanya Komatineni @ 2019-07-22 16:21 UTC (permalink / raw)
To: Dmitry Osipenko, Marc Zyngier, thierry.reding, jonathanh, tglx,
jason, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <0bee8775-756f-adad-4597-8cad53017718@gmail.com>
On 7/22/19 3:57 AM, Dmitry Osipenko wrote:
> 22.07.2019 13:13, Marc Zyngier пишет:
>> On 22/07/2019 10:54, Dmitry Osipenko wrote:
>>> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>>>> Tegra210 platforms use sc7 entry firmware to program Tegra LP0/SC7 entry
>>>> sequence and sc7 entry firmware is run from COP/BPMP-Lite.
>>>>
>>>> So, COP/BPMP-Lite still need IRQ function to finish SC7 suspend sequence
>>>> for Tegra210.
>>>>
>>>> This patch has fix for leaving the COP IRQ enabled for Tegra210 during
>>>> interrupt controller suspend operation.
>>>>
>>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>> ---
>>>> drivers/irqchip/irq-tegra.c | 20 ++++++++++++++++++--
>>>> 1 file changed, 18 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c
>>>> index e1f771c72fc4..851f88cef508 100644
>>>> --- a/drivers/irqchip/irq-tegra.c
>>>> +++ b/drivers/irqchip/irq-tegra.c
>>>> @@ -44,6 +44,7 @@ static unsigned int num_ictlrs;
>>>>
>>>> struct tegra_ictlr_soc {
>>>> unsigned int num_ictlrs;
>>>> + bool supports_sc7;
>>>> };
>>>>
>>>> static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
>>>> @@ -56,6 +57,7 @@ static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
>>>>
>>>> static const struct tegra_ictlr_soc tegra210_ictlr_soc = {
>>>> .num_ictlrs = 6,
>>>> + .supports_sc7 = true,
>>>> };
>>>>
>>>> static const struct of_device_id ictlr_matches[] = {
>>>> @@ -67,6 +69,7 @@ static const struct of_device_id ictlr_matches[] = {
>>>>
>>>> struct tegra_ictlr_info {
>>>> void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
>>>> + const struct tegra_ictlr_soc *soc;
>>>> #ifdef CONFIG_PM_SLEEP
>>>> u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
>>>> u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
>>>> @@ -147,8 +150,20 @@ static int tegra_ictlr_suspend(void)
>>>> lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
>>>> lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
>>>>
>>>> - /* Disable COP interrupts */
>>>> - writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
>>>> + /*
>>>> + * AVP/COP/BPMP-Lite is the Tegra boot processor.
>>>> + *
>>>> + * Tegra210 system suspend flow uses sc7entry firmware which
>>>> + * is executed by COP/BPMP and it includes disabling COP IRQ,
>>>> + * clamping CPU rail, turning off VDD_CPU, and preparing the
>>>> + * system to go to SC7/LP0.
>>>> + *
>>>> + * COP/BPMP wakes up when COP IRQ is triggered and runs
>>>> + * sc7entry-firmware. So need to keep COP interrupt enabled.
>>>> + */
>>>> + if (!lic->soc->supports_sc7)
>>>> + /* Disable COP interrupts if SC7 is not supported */
>>> All Tegra SoCs support SC7, hence the 'supports_sc7' and the comment
>>> doesn't sound correct to me. Something like 'firmware_sc7' should suit
>>> better here.
>> If what you're saying is true, then the whole patch is wrong, and the
>> SC7 property should come from DT.
> It should be safe to assume that all of existing Tegra210 devices use
> the firmware for SC7, hence I wouldn't say that the patch is entirely
> wrong. To me it's not entirely correct.
Yes, all existing Tegra210 platforms uses sc7 entry firmware for SC7 and
AVP/COP IRQ need to be kept enabled as during suspend ATF triggers IRQ
to COP for SC7 entry fw execution.
>>>> + writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
>>> Secondly, I'm also not sure why COP interrupts need to be disabled for
>>> pre-T210 at all, since COP is unused. This looks to me like it was
>>> cut-n-pasted from downstream kernel without a good reason and could be
>>> simply removed.
>> Please verify that this is actually the case. Tegra-2 definitely needed
>> some level of poking, and I'm not keen on changing anything there until
>> you (or someone else) has verified it on actual HW (see e307cc8941fc).
> Tested on Tegra20 and Tegra30, LP1 suspend-resume works perfectly fine
> with all COP bits removed from the driver.
>
> AFAIK, the reason why downstream needed that disabling is that it uses
> proprietary firmware which is running on the COP and that firmware is
> usually a BLOB audio/video DEC-ENC driver which doesn't cleanup
> interrupts after itself. That firmware is not applicable for the
> upstream kernel, hence there is no need to care about it.
>
>> Joseph, can you please shed some light here?
SC7 entry flow uses 3rd party ATF (arm-trusted FW) blob which is the one that actually loads SC7 entry firmware and triggers IRQ to AVP/COP which causes COP to wakeup and run SC7 entry FW.
So when SC7 support is enabled, IRQ need to be kept enabled and when SC7 FW starts execution, it will disable COP IRQ.
^ permalink raw reply
* Re: [PATCH v2] gpiolib: fix incorrect IRQ requesting of an active-low lineevent
From: Bartosz Golaszewski @ 2019-07-22 13:53 UTC (permalink / raw)
To: Michael Wu
Cc: Linus Walleij, linux-gpio, LKML, morgan.chang, Stable # 4 . 20+
In-Reply-To: <20190708052308.27802-1-michael.wu@vatics.com>
pon., 8 lip 2019 o 07:23 Michael Wu <michael.wu@vatics.com> napisał(a):
>
> When a pin is active-low, logical trigger edge should be inverted to match
> the same interrupt opportunity.
>
> For example, a button pushed triggers falling edge in ACTIVE_HIGH case; in
> ACTIVE_LOW case, the button pushed triggers rising edge. For user space the
> IRQ requesting doesn't need to do any modification except to configuring
> GPIOHANDLE_REQUEST_ACTIVE_LOW.
>
> For example, we want to catch the event when the button is pushed. The
> button on the original board drives level to be low when it is pushed, and
> drives level to be high when it is released.
>
> In user space we can do:
>
> req.handleflags = GPIOHANDLE_REQUEST_INPUT;
> req.eventflags = GPIOEVENT_REQUEST_FALLING_EDGE;
>
> while (1) {
> read(fd, &dat, sizeof(dat));
> if (dat.id == GPIOEVENT_EVENT_FALLING_EDGE)
> printf("button pushed\n");
> }
>
> Run the same logic on another board which the polarity of the button is
> inverted; it drives level to be high when pushed, and level to be low when
> released. For this inversion we add flag GPIOHANDLE_REQUEST_ACTIVE_LOW:
>
> req.handleflags = GPIOHANDLE_REQUEST_INPUT |
> GPIOHANDLE_REQUEST_ACTIVE_LOW;
> req.eventflags = GPIOEVENT_REQUEST_FALLING_EDGE;
>
> At the result, there are no any events caught when the button is pushed.
> By the way, button releasing will emit a "falling" event. The timing of
> "falling" catching is not expected.
>
> Cc: stable@vger.kernel.org
> Signed-off-by: Michael Wu <michael.wu@vatics.com>
> ---
> Changes from v1:
> - Correct undeclared 'IRQ_TRIGGER_RISING'
> - Add an example to descibe the issue
> ---
> drivers/gpio/gpiolib.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
> index e013d417a936..9c9597f929d7 100644
> --- a/drivers/gpio/gpiolib.c
> +++ b/drivers/gpio/gpiolib.c
> @@ -956,9 +956,11 @@ static int lineevent_create(struct gpio_device *gdev, void __user *ip)
> }
>
> if (eflags & GPIOEVENT_REQUEST_RISING_EDGE)
> - irqflags |= IRQF_TRIGGER_RISING;
> + irqflags |= test_bit(FLAG_ACTIVE_LOW, &desc->flags) ?
> + IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING;
> if (eflags & GPIOEVENT_REQUEST_FALLING_EDGE)
> - irqflags |= IRQF_TRIGGER_FALLING;
> + irqflags |= test_bit(FLAG_ACTIVE_LOW, &desc->flags) ?
> + IRQF_TRIGGER_RISING : IRQF_TRIGGER_FALLING;
> irqflags |= IRQF_ONESHOT;
>
> INIT_KFIFO(le->events);
> --
> 2.17.1
>
Applied to fixes.
Bart
^ permalink raw reply
* Re: [PATCH 00/18] ARM: Add minimal Raspberry Pi 4 support
From: Nicolas Saenz Julienne @ 2019-07-22 13:18 UTC (permalink / raw)
To: Stefan Wahren, Eric Anholt, Florian Fainelli, Ray Jui,
Scott Branden, Matthias Brugger, Rob Herring, Mark Rutland,
Linus Walleij, Michael Turquette, Stephen Boyd, Ulf Hansson,
Adrian Hunter
Cc: bcm-kernel-feedback-list, linux-arm-kernel, linux-rpi-kernel,
linux-gpio, linux-mmc
In-Reply-To: <1563774880-8061-1-git-send-email-wahrenst@gmx.net>
[-- Attachment #1: Type: text/plain, Size: 6945 bytes --]
On Mon, 2019-07-22 at 07:54 +0200, Stefan Wahren wrote:
> This series adds minimal support for the new Raspberry Pi 4, so we are able
> to login via debug UART.
>
> Patch 1-5: Prepare platform and DTS for the new SoC BMC2711
> Patch 6-10: Enable support for emmc2 on BCM2711
> Patch 11-12: Enable pinctrl for BCM2711
> Patch 13-17: Add Raspberry Pi 4 DTS support
> Patch 18: Update MAINTAINERS
>
> Unfortunately the Raspberry Pi Foundation didn't released a
> peripheral documentation for the new SoC yet. So we only have a preliminary
> datasheet [1] and reduced schematics [2].
>
> Changes since RFC:
> - change BCM2838 -> BCM2711 as discussed in RFC
> - update MAINTAINERS accordingly
> - drop "spi: bcm2835: enable shared interrupt support" from series
> - squash all pinctrl-bcm2835 changes into one patch
> - introduce SoC specific clock registration as suggested by Florian
> - fix watchdog probing for Raspberry Pi 4
> - convert brcm,bcm2835.txt to json-schema
> - move VC4 node to bcm2835-common.dtsi
> - fallback to legacy pull config for Raspberry Pi 4
> - revert unintended change of mailbox in bcm283x.dtsi
> - add reference for arm64
>
> [1] -
>
https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/rpi_DATA_2711_1p0_preliminary.pdf
> [2] -
>
https://www.raspberrypi.org/documentation/hardware/raspberrypi/schematics/rpi_SCH_4b_4p0_reduced.pdf
>
> Phil Elwell (1):
> ARM: bcm2835: DMA can only address 1GB
>
> Stefan Wahren (17):
> ARM: bcm283x: Reduce register ranges for UART, SPI and I2C
> ARM: dts: bcm283x: Move BCM2835/6/7 specific to bcm2835-common.dtsi
> ARM: dts: bcm283x: Define MMC interfaces at board level
> ARM: dts: bcm283x: Define memory at board level
> dt-bindings: bcm2835-cprman: Add bcm2711 support
> clk: bcm2835: Introduce SoC specific clock registration
> clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support
> dt-bindings: sdhci-iproc: Add brcm,bcm2711-emmc2
> mmc: sdhci-iproc: Add support for emmc2 of the BCM2711
> dt-bindings: pinctrl: bcm2835: Add brcm,bcm2711 compatible
> pinctrl: bcm2835: Add support for BCM2711 pull-up functionality
> dt-bindings: arm: Convert BCM2835 board/soc bindings to json-schema
> dt-bindings: arm: bcm2835: Add Raspberry Pi 4 to DT schema
> ARM: bcm2835: Add bcm2711 compatible string
> ARM: dts: Add minimal Raspberry Pi 4 support
> arm64: dts: broadcom: Add reference to RPi 4 B
> MAINTAINERS: Add BCM2711 to BCM2835 ARCH
Hi Stefan,
I rebased your bcm2711-initial branch on top of v5.3-rc1 and got this:
[ 2.307920] mmc1: new ultra high speed DDR50 SDHC card at address 59b4
[ 2.314972] mmcblk1: mmc1:59b4 USD 15.0 GiB
[ 2.320240] mmcblk1: p1 p2
[ 2.324366] mmc0: new high speed SDIO card at address 0001
[ 2.365315] EXT4-fs (mmcblk1p2): mounted filesystem with ordered data mode. Opts: (null)
[ 2.373579] VFS: Mounted root (ext4 filesystem) readonly on device 179:2.
[ 2.381220] devtmpfs: mounted
[ 2.386618] Freeing unused kernel memory: 2048K
[ 2.394373] Run /sbin/init as init process
[ 2.644330] 8<--- cut here ---
[ 2.647439] Unable to handle kernel paging request at virtual address bb000000
[ 2.654795] pgd = (ptrval)
[ 2.657540] [bb000000] *pgd=00000000
[ 2.661172] Internal error: Oops: 2805 [#1] SMP ARM
[ 2.666122] Modules linked in:
[ 2.669225] CPU: 0 PID: 86 Comm: kworker/0:1H Not tainted 5.3.0-rc1-00020-g496d90bc72a9 #374
[ 2.677792] Hardware name: BCM2835
[ 2.681254] Workqueue: mmc_complete mmc_blk_mq_complete_work
[ 2.687002] PC is at v7_dma_inv_range+0x3c/0x54
[ 2.691602] LR is at __dma_page_dev_to_cpu+0x84/0x104
[ 2.696728] pc : [<c031cfec>] lr : [<c0317468>] psr: 80000013
[ 2.703089] sp : e8081e60 ip : ea059000 fp : 00000000
[ 2.708390] r10: 00000002 r9 : 00000002 r8 : e9fb9000
[ 2.713692] r7 : c1708cc4 r6 : c18cde80 r5 : 00001000 r4 : 00000000
[ 2.720316] r3 : 0000003f r2 : 00000040 r1 : bb001000 r0 : bb000000
[ 2.726942] Flags: Nzcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none
[ 2.734185] Control: 10c5383d Table: 0020406a DAC: 00000051
[ 2.740017] Process kworker/0:1H (pid: 86, stack limit = 0x(ptrval))
[ 2.746466] Stack: (0xe8081e60 to 0xe8082000)
[ 2.750891] 1e60: c031d084 ea004480 e928f300 e8053014 00000002 c0319350 c0f015d0 e9196c10
[ 2.759197] 1e80: 00000002 c0317ac4 00000000 c124fc74 0000757d e97fb390 c0317a6c c1704c48
[ 2.767503] 1ea0: e92a60c4 00000000 e97fb2b0 e9782800 e9783800 c0cce770 00000000 ea004480
[ 2.775809] 1ec0: e928f300 e92a6008 e97fb200 c0cc8c68 e92a6008 e97fb200 c1704c48 e92a60c4
[ 2.784115] 1ee0: 00000000 c0cc9040 00000000 e4380000 00000000 ada3354f 28989000 e92a60d8
[ 2.792420] 1f00: e9286080 ea004280 ff7b0200 00000000 c1891c70 00000000 ea004280 c0360eb8
[ 2.800726] 1f20: ffffe000 ea004280 c1703d00 e9286080 ea004280 e9286094 c1703d00 ea004298
[ 2.809032] 1f40: ffffe000 00000008 ea004280 c0361bb4 ffffe000 c18915ac c124ea98 00000000
[ 2.817338] 1f60: ffffe000 e91fc380 e92d3b00 00000000 e8080000 e9286080 c0361b70 e90bfea4
[ 2.825643] 1f80: e91fc39c c0366dac 00000001 e92d3b00 c0366c64 00000000 00000000 00000000
[ 2.833948] 1fa0: 00000000 00000000 00000000 c03010e8 00000000 00000000 00000000 00000000
[ 2.842253] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 2.850559] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
[ 2.858872] [<c031cfec>] (v7_dma_inv_range) from [<c0317468>] (__dma_page_dev_to_cpu+0x84/0x104)
[ 2.867797] [<c0317468>] (__dma_page_dev_to_cpu) from [<c0317ac4>] (arm_dma_unmap_sg+0x58/0x74)
[ 2.876635] [<c0317ac4>] (arm_dma_unmap_sg) from [<c0cce770>] (sdhci_post_req+0x5c/0x8c)
[ 2.884857] [<c0cce770>] (sdhci_post_req) from [<c0cc8c68>] (mmc_blk_mq_post_req+0x30/0xb4)
[ 2.893340] [<c0cc8c68>] (mmc_blk_mq_post_req) from [<c0cc9040>] (mmc_blk_mq_complete_prev_req.part.4+0x174/0x238)
[ 2.903855] [<c0cc9040>] (mmc_blk_mq_complete_prev_req.part.4) from [<c0360eb8>] (process_one_work+0x218/0x510)
[ 2.914104] [<c0360eb8>] (process_one_work) from [<c0361bb4>] (worker_thread+0x44/0x5c0)
[ 2.922323] [<c0361bb4>] (worker_thread) from [<c0366dac>] (kthread+0x148/0x150)
[ 2.929836] [<c0366dac>] (kthread) from [<c03010e8>] (ret_from_fork+0x14/0x2c)
[ 2.937168] Exception stack(0xe8081fb0 to 0xe8081ff8)
[ 2.942296] 1fa0: 00000000 00000000 00000000 00000000
[ 2.950601] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 2.958906] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000
[ 2.965623] Code: e1110003 e1c11003 1e071f3e e1500001 (3e070f36)
[ 2.971830] ---[ end trace 918fd7aaa4c1e4cc ]---
I'm looking into it. Any ideas?
Regards,
Nicolas
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^ permalink raw reply
* Re: [PATCH v2 2/2] gpio: em: use a helper variable for &pdev->dev
From: Bartosz Golaszewski @ 2019-07-22 12:40 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Linus Walleij, Phil Reid, open list:GPIO SUBSYSTEM,
Linux Kernel Mailing List, Bartosz Golaszewski
In-Reply-To: <CAMuHMdUp3YMMzhYRBnHFDrf3w7GDK8HY5aAXdjVZ_oMd_n6xdQ@mail.gmail.com>
czw., 11 lip 2019 o 10:48 Geert Uytterhoeven <geert@linux-m68k.org> napisał(a):
>
> On Thu, Jul 11, 2019 at 10:29 AM Bartosz Golaszewski <brgl@bgdev.pl> wrote:
> > From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> >
> > Instead of always dereferencing &pdev->dev, just assign a helper local
> > variable of type struct device * and use it where applicable.
> >
> > Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
Applied for next.
^ permalink raw reply
* Re: [PATCH 00/18] ARM: Add minimal Raspberry Pi 4 support
From: Matthias Brugger @ 2019-07-22 11:26 UTC (permalink / raw)
To: Stefan Wahren, Eric Anholt, Florian Fainelli, Ray Jui,
Scott Branden, Nicolas Saenz Julienne, Matthias Brugger,
Rob Herring, Mark Rutland, Linus Walleij, Michael Turquette,
Stephen Boyd, Ulf Hansson, Adrian Hunter
Cc: linux-mmc, linux-gpio, bcm-kernel-feedback-list, linux-rpi-kernel,
linux-arm-kernel
In-Reply-To: <1563774880-8061-1-git-send-email-wahrenst@gmx.net>
On 22/07/2019 07:54, Stefan Wahren wrote:
> This series adds minimal support for the new Raspberry Pi 4, so we are able
> to login via debug UART.
>
> Patch 1-5: Prepare platform and DTS for the new SoC BMC2711
> Patch 6-10: Enable support for emmc2 on BCM2711
> Patch 11-12: Enable pinctrl for BCM2711
> Patch 13-17: Add Raspberry Pi 4 DTS support
> Patch 18: Update MAINTAINERS
It seems that you only send patch 1-12 and in two batches. Can you please resend
or send the rest of the patches.
Regards,
Matthias
>
> Unfortunately the Raspberry Pi Foundation didn't released a
> peripheral documentation for the new SoC yet. So we only have a preliminary
> datasheet [1] and reduced schematics [2].
>
> Changes since RFC:
> - change BCM2838 -> BCM2711 as discussed in RFC
> - update MAINTAINERS accordingly
> - drop "spi: bcm2835: enable shared interrupt support" from series
> - squash all pinctrl-bcm2835 changes into one patch
> - introduce SoC specific clock registration as suggested by Florian
> - fix watchdog probing for Raspberry Pi 4
> - convert brcm,bcm2835.txt to json-schema
> - move VC4 node to bcm2835-common.dtsi
> - fallback to legacy pull config for Raspberry Pi 4
> - revert unintended change of mailbox in bcm283x.dtsi
> - add reference for arm64
>
> [1] - https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/rpi_DATA_2711_1p0_preliminary.pdf
> [2] - https://www.raspberrypi.org/documentation/hardware/raspberrypi/schematics/rpi_SCH_4b_4p0_reduced.pdf
>
> Phil Elwell (1):
> ARM: bcm2835: DMA can only address 1GB
>
> Stefan Wahren (17):
> ARM: bcm283x: Reduce register ranges for UART, SPI and I2C
> ARM: dts: bcm283x: Move BCM2835/6/7 specific to bcm2835-common.dtsi
> ARM: dts: bcm283x: Define MMC interfaces at board level
> ARM: dts: bcm283x: Define memory at board level
> dt-bindings: bcm2835-cprman: Add bcm2711 support
> clk: bcm2835: Introduce SoC specific clock registration
> clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support
> dt-bindings: sdhci-iproc: Add brcm,bcm2711-emmc2
> mmc: sdhci-iproc: Add support for emmc2 of the BCM2711
> dt-bindings: pinctrl: bcm2835: Add brcm,bcm2711 compatible
> pinctrl: bcm2835: Add support for BCM2711 pull-up functionality
> dt-bindings: arm: Convert BCM2835 board/soc bindings to json-schema
> dt-bindings: arm: bcm2835: Add Raspberry Pi 4 to DT schema
> ARM: bcm2835: Add bcm2711 compatible string
> ARM: dts: Add minimal Raspberry Pi 4 support
> arm64: dts: broadcom: Add reference to RPi 4 B
> MAINTAINERS: Add BCM2711 to BCM2835 ARCH
>
> .../devicetree/bindings/arm/bcm/bcm2835.yaml | 51 ++
> .../devicetree/bindings/arm/bcm/brcm,bcm2835.txt | 67 ---
> .../bindings/clock/brcm,bcm2835-cprman.txt | 4 +-
> .../devicetree/bindings/mmc/brcm,sdhci-iproc.txt | 4 +-
> .../bindings/pinctrl/brcm,bcm2835-gpio.txt | 1 +
> MAINTAINERS | 3 +-
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 120 ++++
> arch/arm/boot/dts/bcm2711.dtsi | 667 +++++++++++++++++++++
> arch/arm/boot/dts/bcm2835-common.dtsi | 177 ++++++
> arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 12 +
> arch/arm/boot/dts/bcm2835-rpi-a.dts | 12 +
> arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 12 +
> arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 12 +
> arch/arm/boot/dts/bcm2835-rpi-b.dts | 12 +
> arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts | 7 +
> arch/arm/boot/dts/bcm2835-rpi-cm1.dtsi | 5 +
> arch/arm/boot/dts/bcm2835-rpi-zero-w.dts | 12 +
> arch/arm/boot/dts/bcm2835-rpi-zero.dts | 12 +
> arch/arm/boot/dts/bcm2835-rpi.dtsi | 18 -
> arch/arm/boot/dts/bcm2835.dtsi | 1 +
> arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 8 +
> arch/arm/boot/dts/bcm2836.dtsi | 1 +
> arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts | 1 +
> arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 1 +
> arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 1 +
> arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts | 7 +
> arch/arm/boot/dts/bcm2837-rpi-cm3.dtsi | 1 +
> arch/arm/boot/dts/bcm2837.dtsi | 1 +
> arch/arm/boot/dts/bcm283x.dtsi | 160 +----
> arch/arm/mach-bcm/board_bcm2835.c | 2 +
> arch/arm64/boot/dts/broadcom/Makefile | 3 +-
> arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts | 2 +
> drivers/clk/bcm/clk-bcm2835.c | 117 +++-
> drivers/mmc/host/sdhci-iproc.c | 9 +
> drivers/pinctrl/bcm/pinctrl-bcm2835.c | 105 +++-
> include/dt-bindings/clock/bcm2835.h | 2 +
> 37 files changed, 1365 insertions(+), 266 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml
> delete mode 100644 Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
> create mode 100644 arch/arm/boot/dts/bcm2711-rpi-4-b.dts
> create mode 100644 arch/arm/boot/dts/bcm2711.dtsi
> create mode 100644 arch/arm/boot/dts/bcm2835-common.dtsi
> create mode 100644 arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts
>
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply
* Re: [PATCH V6 01/21] irqchip: tegra: Do not disable COP IRQ during suspend
From: Dmitry Osipenko @ 2019-07-22 10:57 UTC (permalink / raw)
To: Marc Zyngier, Sowjanya Komatineni, thierry.reding, jonathanh,
tglx, jason, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <20c1d733-60f5-6375-c03c-639de5e41739@arm.com>
22.07.2019 13:13, Marc Zyngier пишет:
> On 22/07/2019 10:54, Dmitry Osipenko wrote:
>> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>>> Tegra210 platforms use sc7 entry firmware to program Tegra LP0/SC7 entry
>>> sequence and sc7 entry firmware is run from COP/BPMP-Lite.
>>>
>>> So, COP/BPMP-Lite still need IRQ function to finish SC7 suspend sequence
>>> for Tegra210.
>>>
>>> This patch has fix for leaving the COP IRQ enabled for Tegra210 during
>>> interrupt controller suspend operation.
>>>
>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>> ---
>>> drivers/irqchip/irq-tegra.c | 20 ++++++++++++++++++--
>>> 1 file changed, 18 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c
>>> index e1f771c72fc4..851f88cef508 100644
>>> --- a/drivers/irqchip/irq-tegra.c
>>> +++ b/drivers/irqchip/irq-tegra.c
>>> @@ -44,6 +44,7 @@ static unsigned int num_ictlrs;
>>>
>>> struct tegra_ictlr_soc {
>>> unsigned int num_ictlrs;
>>> + bool supports_sc7;
>>> };
>>>
>>> static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
>>> @@ -56,6 +57,7 @@ static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
>>>
>>> static const struct tegra_ictlr_soc tegra210_ictlr_soc = {
>>> .num_ictlrs = 6,
>>> + .supports_sc7 = true,
>>> };
>>>
>>> static const struct of_device_id ictlr_matches[] = {
>>> @@ -67,6 +69,7 @@ static const struct of_device_id ictlr_matches[] = {
>>>
>>> struct tegra_ictlr_info {
>>> void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
>>> + const struct tegra_ictlr_soc *soc;
>>> #ifdef CONFIG_PM_SLEEP
>>> u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
>>> u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
>>> @@ -147,8 +150,20 @@ static int tegra_ictlr_suspend(void)
>>> lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
>>> lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
>>>
>>> - /* Disable COP interrupts */
>>> - writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
>>> + /*
>>> + * AVP/COP/BPMP-Lite is the Tegra boot processor.
>>> + *
>>> + * Tegra210 system suspend flow uses sc7entry firmware which
>>> + * is executed by COP/BPMP and it includes disabling COP IRQ,
>>> + * clamping CPU rail, turning off VDD_CPU, and preparing the
>>> + * system to go to SC7/LP0.
>>> + *
>>> + * COP/BPMP wakes up when COP IRQ is triggered and runs
>>> + * sc7entry-firmware. So need to keep COP interrupt enabled.
>>> + */
>>> + if (!lic->soc->supports_sc7)
>>> + /* Disable COP interrupts if SC7 is not supported */
>>
>> All Tegra SoCs support SC7, hence the 'supports_sc7' and the comment
>> doesn't sound correct to me. Something like 'firmware_sc7' should suit
>> better here.
>
> If what you're saying is true, then the whole patch is wrong, and the
> SC7 property should come from DT.
It should be safe to assume that all of existing Tegra210 devices use
the firmware for SC7, hence I wouldn't say that the patch is entirely
wrong. To me it's not entirely correct.
>>
>>> + writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
>>
>> Secondly, I'm also not sure why COP interrupts need to be disabled for
>> pre-T210 at all, since COP is unused. This looks to me like it was
>> cut-n-pasted from downstream kernel without a good reason and could be
>> simply removed.
>
> Please verify that this is actually the case. Tegra-2 definitely needed
> some level of poking, and I'm not keen on changing anything there until
> you (or someone else) has verified it on actual HW (see e307cc8941fc).
Tested on Tegra20 and Tegra30, LP1 suspend-resume works perfectly fine
with all COP bits removed from the driver.
AFAIK, the reason why downstream needed that disabling is that it uses
proprietary firmware which is running on the COP and that firmware is
usually a BLOB audio/video DEC-ENC driver which doesn't cleanup
interrupts after itself. That firmware is not applicable for the
upstream kernel, hence there is no need to care about it.
> Joseph, can you please shed some light here?
^ permalink raw reply
* Re: [PATCH 08/18] clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support
From: Matthias Brugger @ 2019-07-22 10:30 UTC (permalink / raw)
To: Stefan Wahren, Eric Anholt, Mark Rutland, Michael Turquette,
Ray Jui, Scott Branden, Florian Fainelli, Adrian Hunter,
Rob Herring, Stephen Boyd, Linus Walleij, Ulf Hansson,
Nicolas Saenz Julienne
Cc: bcm-kernel-feedback-list@broadcom.com,
linux-arm-kernel@lists.infradead.org,
linux-rpi-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
linux-mmc@vger.kernel.org
In-Reply-To: <1563774880-8061-9-git-send-email-wahrenst@gmx.net>
On 22/07/2019 07:54, Stefan Wahren wrote:
> The new BCM2711 supports an additional clock for the emmc2 block.
> So add a new compatible and register this clock only for BCM2711.
>
> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> ---
> drivers/clk/bcm/clk-bcm2835.c | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
> index 3231b76..fbdc4e1 100644
> --- a/drivers/clk/bcm/clk-bcm2835.c
> +++ b/drivers/clk/bcm/clk-bcm2835.c
> @@ -114,6 +114,8 @@
> #define CM_AVEODIV 0x1bc
> #define CM_EMMCCTL 0x1c0
> #define CM_EMMCDIV 0x1c4
> +#define CM_EMMC2CTL 0x1d0
> +#define CM_EMMC2DIV 0x1d4
>
> /* General bits for the CM_*CTL regs */
> # define CM_ENABLE BIT(4)
> @@ -290,7 +292,8 @@
> #define BCM2835_MAX_FB_RATE 1750000000u
>
> #define SOC_BCM2835 BIT(0)
> -#define SOC_ALL (SOC_BCM2835)
> +#define SOC_BCM2711 BIT(1)
> +#define SOC_ALL (SOC_BCM2835 | SOC_BCM2711)
>
> /*
> * Names of clocks used within the driver that need to be replaced
> @@ -1999,6 +2002,16 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .frac_bits = 8,
> .tcnt_mux = 39),
>
> + /* EMMC2 clock (only available for BCM2711) */
> + [BCM2711_CLOCK_EMMC2] = REGISTER_PER_CLK(
> + SOC_BCM2711,
> + .name = "emmc2",
> + .ctl_reg = CM_EMMC2CTL,
> + .div_reg = CM_EMMC2DIV,
> + .int_bits = 4,
> + .frac_bits = 8,
> + .tcnt_mux = 42),
> +
> /* General purpose (GPIO) clocks */
> [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
> SOC_ALL,
> @@ -2230,6 +2243,7 @@ static int bcm2835_clk_probe(struct platform_device *pdev)
>
> static const struct of_device_id bcm2835_clk_of_match[] = {
> { .compatible = "brcm,bcm2835-cprman", .data = (void *)SOC_BCM2835 },
> + { .compatible = "brcm,bcm2711-cprman", .data = (void *)SOC_BCM2711 },
> {}
> };
> MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
> --
> 2.7.4
>
>
^ permalink raw reply
* Re: [PATCH 07/18] clk: bcm2835: Introduce SoC specific clock registration
From: Matthias Brugger @ 2019-07-22 10:30 UTC (permalink / raw)
To: Stefan Wahren, Eric Anholt, Mark Rutland, Michael Turquette,
Ray Jui, Scott Branden, Florian Fainelli, Adrian Hunter,
Rob Herring, Stephen Boyd, Linus Walleij, Ulf Hansson,
Nicolas Saenz Julienne
Cc: bcm-kernel-feedback-list@broadcom.com,
linux-arm-kernel@lists.infradead.org,
linux-rpi-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
linux-mmc@vger.kernel.org
In-Reply-To: <1563774880-8061-8-git-send-email-wahrenst@gmx.net>
On 22/07/2019 07:54, Stefan Wahren wrote:
> In order to support SoC specific clocks (e.g. emmc2 for BCM2711), we
> extend the description with a SoC support flag. This approach avoids long
> and mostly redundant lists of clock IDs.
>
> Suggested-by: Florian Fainelli <f.fainelli@gmail.com>
> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> ---
> drivers/clk/bcm/clk-bcm2835.c | 103 +++++++++++++++++++++++++++++++++++-------
> 1 file changed, 86 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
> index 867ae3c..3231b76 100644
> --- a/drivers/clk/bcm/clk-bcm2835.c
> +++ b/drivers/clk/bcm/clk-bcm2835.c
> @@ -31,7 +31,7 @@
> #include <linux/delay.h>
> #include <linux/io.h>
> #include <linux/module.h>
> -#include <linux/of.h>
> +#include <linux/of_device.h>
> #include <linux/platform_device.h>
> #include <linux/slab.h>
> #include <dt-bindings/clock/bcm2835.h>
> @@ -289,6 +289,9 @@
> #define LOCK_TIMEOUT_NS 100000000
> #define BCM2835_MAX_FB_RATE 1750000000u
>
> +#define SOC_BCM2835 BIT(0)
> +#define SOC_ALL (SOC_BCM2835)
> +
> /*
> * Names of clocks used within the driver that need to be replaced
> * with an external parent's name. This array is in the order that
> @@ -1451,22 +1454,28 @@ typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman,
> const void *data);
> struct bcm2835_clk_desc {
> bcm2835_clk_register clk_register;
> + unsigned int supported;
> const void *data;
> };
>
> /* assignment helper macros for different clock types */
> -#define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \
> - .data = __VA_ARGS__ }
> -#define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \
> +#define _REGISTER(f, s, ...) { .clk_register = (bcm2835_clk_register)f, \
> + .supported = s, \
> + .data = __VA_ARGS__ }
> +#define REGISTER_PLL(s, ...) _REGISTER(&bcm2835_register_pll, \
> + s, \
> &(struct bcm2835_pll_data) \
> {__VA_ARGS__})
> -#define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \
> - &(struct bcm2835_pll_divider_data) \
> - {__VA_ARGS__})
> -#define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \
> +#define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \
> + s, \
> + &(struct bcm2835_pll_divider_data) \
> + {__VA_ARGS__})
> +#define REGISTER_CLK(s, ...) _REGISTER(&bcm2835_register_clock, \
> + s, \
> &(struct bcm2835_clock_data) \
> {__VA_ARGS__})
> -#define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \
> +#define REGISTER_GATE(s, ...) _REGISTER(&bcm2835_register_gate, \
> + s, \
> &(struct bcm2835_gate_data) \
> {__VA_ARGS__})
>
> @@ -1480,7 +1489,8 @@ static const char *const bcm2835_clock_osc_parents[] = {
> "testdebug1"
> };
>
> -#define REGISTER_OSC_CLK(...) REGISTER_CLK( \
> +#define REGISTER_OSC_CLK(s, ...) REGISTER_CLK( \
> + s, \
> .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
> .parents = bcm2835_clock_osc_parents, \
> __VA_ARGS__)
> @@ -1497,7 +1507,8 @@ static const char *const bcm2835_clock_per_parents[] = {
> "pllh_aux",
> };
>
> -#define REGISTER_PER_CLK(...) REGISTER_CLK( \
> +#define REGISTER_PER_CLK(s, ...) REGISTER_CLK( \
> + s, \
> .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
> .parents = bcm2835_clock_per_parents, \
> __VA_ARGS__)
> @@ -1522,7 +1533,8 @@ static const char *const bcm2835_pcm_per_parents[] = {
> "-",
> };
>
> -#define REGISTER_PCM_CLK(...) REGISTER_CLK( \
> +#define REGISTER_PCM_CLK(s, ...) REGISTER_CLK( \
> + s, \
> .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \
> .parents = bcm2835_pcm_per_parents, \
> __VA_ARGS__)
> @@ -1541,7 +1553,8 @@ static const char *const bcm2835_clock_vpu_parents[] = {
> "pllc_core2",
> };
>
> -#define REGISTER_VPU_CLK(...) REGISTER_CLK( \
> +#define REGISTER_VPU_CLK(s, ...) REGISTER_CLK( \
> + s, \
> .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
> .parents = bcm2835_clock_vpu_parents, \
> __VA_ARGS__)
> @@ -1577,12 +1590,14 @@ static const char *const bcm2835_clock_dsi1_parents[] = {
> "dsi1_byte_inv",
> };
>
> -#define REGISTER_DSI0_CLK(...) REGISTER_CLK( \
> +#define REGISTER_DSI0_CLK(s, ...) REGISTER_CLK( \
> + s, \
> .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \
> .parents = bcm2835_clock_dsi0_parents, \
> __VA_ARGS__)
>
> -#define REGISTER_DSI1_CLK(...) REGISTER_CLK( \
> +#define REGISTER_DSI1_CLK(s, ...) REGISTER_CLK( \
> + s, \
> .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \
> .parents = bcm2835_clock_dsi1_parents, \
> __VA_ARGS__)
> @@ -1602,6 +1617,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> * AUDIO domain is on.
> */
> [BCM2835_PLLA] = REGISTER_PLL(
> + SOC_ALL,
> .name = "plla",
> .cm_ctrl_reg = CM_PLLA,
> .a2w_ctrl_reg = A2W_PLLA_CTRL,
> @@ -1616,6 +1632,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .max_rate = 2400000000u,
> .max_fb_rate = BCM2835_MAX_FB_RATE),
> [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(
> + SOC_ALL,
> .name = "plla_core",
> .source_pll = "plla",
> .cm_reg = CM_PLLA,
> @@ -1625,6 +1642,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .fixed_divider = 1,
> .flags = CLK_SET_RATE_PARENT),
> [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
> + SOC_ALL,
> .name = "plla_per",
> .source_pll = "plla",
> .cm_reg = CM_PLLA,
> @@ -1634,6 +1652,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .fixed_divider = 1,
> .flags = CLK_SET_RATE_PARENT),
> [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
> + SOC_ALL,
> .name = "plla_dsi0",
> .source_pll = "plla",
> .cm_reg = CM_PLLA,
> @@ -1642,6 +1661,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .hold_mask = CM_PLLA_HOLDDSI0,
> .fixed_divider = 1),
> [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
> + SOC_ALL,
> .name = "plla_ccp2",
> .source_pll = "plla",
> .cm_reg = CM_PLLA,
> @@ -1663,6 +1683,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> * AUDIO domain is on.
> */
> [BCM2835_PLLC] = REGISTER_PLL(
> + SOC_ALL,
> .name = "pllc",
> .cm_ctrl_reg = CM_PLLC,
> .a2w_ctrl_reg = A2W_PLLC_CTRL,
> @@ -1677,6 +1698,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .max_rate = 3000000000u,
> .max_fb_rate = BCM2835_MAX_FB_RATE),
> [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(
> + SOC_ALL,
> .name = "pllc_core0",
> .source_pll = "pllc",
> .cm_reg = CM_PLLC,
> @@ -1686,6 +1708,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .fixed_divider = 1,
> .flags = CLK_SET_RATE_PARENT),
> [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
> + SOC_ALL,
> .name = "pllc_core1",
> .source_pll = "pllc",
> .cm_reg = CM_PLLC,
> @@ -1695,6 +1718,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .fixed_divider = 1,
> .flags = CLK_SET_RATE_PARENT),
> [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
> + SOC_ALL,
> .name = "pllc_core2",
> .source_pll = "pllc",
> .cm_reg = CM_PLLC,
> @@ -1704,6 +1728,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .fixed_divider = 1,
> .flags = CLK_SET_RATE_PARENT),
> [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
> + SOC_ALL,
> .name = "pllc_per",
> .source_pll = "pllc",
> .cm_reg = CM_PLLC,
> @@ -1720,6 +1745,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> * AUDIO domain is on.
> */
> [BCM2835_PLLD] = REGISTER_PLL(
> + SOC_ALL,
> .name = "plld",
> .cm_ctrl_reg = CM_PLLD,
> .a2w_ctrl_reg = A2W_PLLD_CTRL,
> @@ -1734,6 +1760,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .max_rate = 2400000000u,
> .max_fb_rate = BCM2835_MAX_FB_RATE),
> [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(
> + SOC_ALL,
> .name = "plld_core",
> .source_pll = "plld",
> .cm_reg = CM_PLLD,
> @@ -1743,6 +1770,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .fixed_divider = 1,
> .flags = CLK_SET_RATE_PARENT),
> [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
> + SOC_ALL,
> .name = "plld_per",
> .source_pll = "plld",
> .cm_reg = CM_PLLD,
> @@ -1752,6 +1780,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .fixed_divider = 1,
> .flags = CLK_SET_RATE_PARENT),
> [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
> + SOC_ALL,
> .name = "plld_dsi0",
> .source_pll = "plld",
> .cm_reg = CM_PLLD,
> @@ -1760,6 +1789,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .hold_mask = CM_PLLD_HOLDDSI0,
> .fixed_divider = 1),
> [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
> + SOC_ALL,
> .name = "plld_dsi1",
> .source_pll = "plld",
> .cm_reg = CM_PLLD,
> @@ -1775,6 +1805,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> * It is in the HDMI power domain.
> */
> [BCM2835_PLLH] = REGISTER_PLL(
> + SOC_ALL,
> "pllh",
> .cm_ctrl_reg = CM_PLLH,
> .a2w_ctrl_reg = A2W_PLLH_CTRL,
> @@ -1789,6 +1820,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .max_rate = 3000000000u,
> .max_fb_rate = BCM2835_MAX_FB_RATE),
> [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(
> + SOC_ALL,
> .name = "pllh_rcal",
> .source_pll = "pllh",
> .cm_reg = CM_PLLH,
> @@ -1798,6 +1830,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .fixed_divider = 10,
> .flags = CLK_SET_RATE_PARENT),
> [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
> + SOC_ALL,
> .name = "pllh_aux",
> .source_pll = "pllh",
> .cm_reg = CM_PLLH,
> @@ -1807,6 +1840,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .fixed_divider = 1,
> .flags = CLK_SET_RATE_PARENT),
> [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
> + SOC_ALL,
> .name = "pllh_pix",
> .source_pll = "pllh",
> .cm_reg = CM_PLLH,
> @@ -1822,6 +1856,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
>
> /* One Time Programmable Memory clock. Maximum 10Mhz. */
> [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(
> + SOC_ALL,
> .name = "otp",
> .ctl_reg = CM_OTPCTL,
> .div_reg = CM_OTPDIV,
> @@ -1833,6 +1868,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> * bythe watchdog timer and the camera pulse generator.
> */
> [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK(
> + SOC_ALL,
> .name = "timer",
> .ctl_reg = CM_TIMERCTL,
> .div_reg = CM_TIMERDIV,
> @@ -1843,12 +1879,14 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> * Generally run at 2Mhz, max 5Mhz.
> */
> [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(
> + SOC_ALL,
> .name = "tsens",
> .ctl_reg = CM_TSENSCTL,
> .div_reg = CM_TSENSDIV,
> .int_bits = 5,
> .frac_bits = 0),
> [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
> + SOC_ALL,
> .name = "tec",
> .ctl_reg = CM_TECCTL,
> .div_reg = CM_TECDIV,
> @@ -1857,6 +1895,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
>
> /* clocks with vpu parent mux */
> [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
> + SOC_ALL,
> .name = "h264",
> .ctl_reg = CM_H264CTL,
> .div_reg = CM_H264DIV,
> @@ -1864,6 +1903,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .frac_bits = 8,
> .tcnt_mux = 1),
> [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
> + SOC_ALL,
> .name = "isp",
> .ctl_reg = CM_ISPCTL,
> .div_reg = CM_ISPDIV,
> @@ -1876,6 +1916,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> * in the SDRAM controller can't be used.
> */
> [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK(
> + SOC_ALL,
> .name = "sdram",
> .ctl_reg = CM_SDCCTL,
> .div_reg = CM_SDCDIV,
> @@ -1883,6 +1924,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .frac_bits = 0,
> .tcnt_mux = 3),
> [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
> + SOC_ALL,
> .name = "v3d",
> .ctl_reg = CM_V3DCTL,
> .div_reg = CM_V3DDIV,
> @@ -1896,6 +1938,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> * in various hardware documentation.
> */
> [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK(
> + SOC_ALL,
> .name = "vpu",
> .ctl_reg = CM_VPUCTL,
> .div_reg = CM_VPUDIV,
> @@ -1907,6 +1950,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
>
> /* clocks with per parent mux */
> [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "aveo",
> .ctl_reg = CM_AVEOCTL,
> .div_reg = CM_AVEODIV,
> @@ -1914,6 +1958,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .frac_bits = 0,
> .tcnt_mux = 38),
> [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "cam0",
> .ctl_reg = CM_CAM0CTL,
> .div_reg = CM_CAM0DIV,
> @@ -1921,6 +1966,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .frac_bits = 8,
> .tcnt_mux = 14),
> [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "cam1",
> .ctl_reg = CM_CAM1CTL,
> .div_reg = CM_CAM1DIV,
> @@ -1928,12 +1974,14 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .frac_bits = 8,
> .tcnt_mux = 15),
> [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "dft",
> .ctl_reg = CM_DFTCTL,
> .div_reg = CM_DFTDIV,
> .int_bits = 5,
> .frac_bits = 0),
> [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "dpi",
> .ctl_reg = CM_DPICTL,
> .div_reg = CM_DPIDIV,
> @@ -1943,6 +1991,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
>
> /* Arasan EMMC clock */
> [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "emmc",
> .ctl_reg = CM_EMMCCTL,
> .div_reg = CM_EMMCDIV,
> @@ -1952,6 +2001,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
>
> /* General purpose (GPIO) clocks */
> [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "gp0",
> .ctl_reg = CM_GP0CTL,
> .div_reg = CM_GP0DIV,
> @@ -1960,6 +2010,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .is_mash_clock = true,
> .tcnt_mux = 20),
> [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "gp1",
> .ctl_reg = CM_GP1CTL,
> .div_reg = CM_GP1DIV,
> @@ -1969,6 +2020,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .is_mash_clock = true,
> .tcnt_mux = 21),
> [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "gp2",
> .ctl_reg = CM_GP2CTL,
> .div_reg = CM_GP2DIV,
> @@ -1978,6 +2030,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
>
> /* HDMI state machine */
> [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "hsm",
> .ctl_reg = CM_HSMCTL,
> .div_reg = CM_HSMDIV,
> @@ -1985,6 +2038,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .frac_bits = 8,
> .tcnt_mux = 22),
> [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK(
> + SOC_ALL,
> .name = "pcm",
> .ctl_reg = CM_PCMCTL,
> .div_reg = CM_PCMDIV,
> @@ -1994,6 +2048,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .low_jitter = true,
> .tcnt_mux = 23),
> [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "pwm",
> .ctl_reg = CM_PWMCTL,
> .div_reg = CM_PWMDIV,
> @@ -2002,6 +2057,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .is_mash_clock = true,
> .tcnt_mux = 24),
> [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "slim",
> .ctl_reg = CM_SLIMCTL,
> .div_reg = CM_SLIMDIV,
> @@ -2010,6 +2066,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .is_mash_clock = true,
> .tcnt_mux = 25),
> [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "smi",
> .ctl_reg = CM_SMICTL,
> .div_reg = CM_SMIDIV,
> @@ -2017,6 +2074,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .frac_bits = 8,
> .tcnt_mux = 27),
> [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "uart",
> .ctl_reg = CM_UARTCTL,
> .div_reg = CM_UARTDIV,
> @@ -2026,6 +2084,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
>
> /* TV encoder clock. Only operating frequency is 108Mhz. */
> [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "vec",
> .ctl_reg = CM_VECCTL,
> .div_reg = CM_VECDIV,
> @@ -2040,6 +2099,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
>
> /* dsi clocks */
> [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "dsi0e",
> .ctl_reg = CM_DSI0ECTL,
> .div_reg = CM_DSI0EDIV,
> @@ -2047,6 +2107,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .frac_bits = 8,
> .tcnt_mux = 18),
> [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
> + SOC_ALL,
> .name = "dsi1e",
> .ctl_reg = CM_DSI1ECTL,
> .div_reg = CM_DSI1EDIV,
> @@ -2054,6 +2115,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .frac_bits = 8,
> .tcnt_mux = 19),
> [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK(
> + SOC_ALL,
> .name = "dsi0p",
> .ctl_reg = CM_DSI0PCTL,
> .div_reg = CM_DSI0PDIV,
> @@ -2061,6 +2123,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> .frac_bits = 0,
> .tcnt_mux = 12),
> [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(
> + SOC_ALL,
> .name = "dsi1p",
> .ctl_reg = CM_DSI1PCTL,
> .div_reg = CM_DSI1PDIV,
> @@ -2077,6 +2140,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
> * non-stop vpu clock.
> */
> [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
> + SOC_ALL,
> .name = "peri_image",
> .parent = "vpu",
> .ctl_reg = CM_PERIICTL),
> @@ -2109,9 +2173,14 @@ static int bcm2835_clk_probe(struct platform_device *pdev)
> struct resource *res;
> const struct bcm2835_clk_desc *desc;
> const size_t asize = ARRAY_SIZE(clk_desc_array);
> + unsigned int soc;
> size_t i;
> int ret;
>
> + soc = (unsigned int)of_device_get_match_data(&pdev->dev);
> + if (!soc)
> + return -ENODEV;
> +
> cprman = devm_kzalloc(dev,
> struct_size(cprman, onecell.hws, asize),
> GFP_KERNEL);
> @@ -2147,7 +2216,7 @@ static int bcm2835_clk_probe(struct platform_device *pdev)
>
> for (i = 0; i < asize; i++) {
> desc = &clk_desc_array[i];
> - if (desc->clk_register && desc->data)
> + if (desc->clk_register && desc->data && (desc->supported & soc))
> hws[i] = desc->clk_register(cprman, desc->data);
> }
>
> @@ -2160,7 +2229,7 @@ static int bcm2835_clk_probe(struct platform_device *pdev)
> }
>
> static const struct of_device_id bcm2835_clk_of_match[] = {
> - { .compatible = "brcm,bcm2835-cprman", },
> + { .compatible = "brcm,bcm2835-cprman", .data = (void *)SOC_BCM2835 },
> {}
> };
> MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
> --
> 2.7.4
>
>
^ permalink raw reply
* Re: [PATCH 09/18] dt-bindings: sdhci-iproc: Add brcm,bcm2711-emmc2
From: Matthias Brugger @ 2019-07-22 10:31 UTC (permalink / raw)
To: Stefan Wahren, Eric Anholt, Mark Rutland, Michael Turquette,
Ray Jui, Scott Branden, Florian Fainelli, Adrian Hunter,
Rob Herring, Stephen Boyd, Linus Walleij, Ulf Hansson,
Nicolas Saenz Julienne
Cc: bcm-kernel-feedback-list@broadcom.com,
linux-arm-kernel@lists.infradead.org,
linux-rpi-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
linux-mmc@vger.kernel.org
In-Reply-To: <1563774880-8061-10-git-send-email-wahrenst@gmx.net>
On 22/07/2019 07:54, Stefan Wahren wrote:
> Add a new compatible for the additional emmc2 controller
> on BCM2711 and clearify usage.
>
> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> ---
> Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt b/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
> index fa90d25..09d87cc 100644
> --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
> +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
> @@ -6,10 +6,12 @@ by mmc.txt and the properties that represent the IPROC SDHCI controller.
> Required properties:
> - compatible : Should be one of the following
> "brcm,bcm2835-sdhci"
> + "brcm,bcm2711-emmc2"
> "brcm,sdhci-iproc-cygnus"
> "brcm,sdhci-iproc"
>
> -Use brcm2835-sdhci for Rasperry PI.
> +Use brcm2835-sdhci for the eMMC controller on the BCM2835 (Raspberry Pi) and
> +bcm2711-emmc2 for the additional eMMC2 controller on BCM2711.
>
> Use sdhci-iproc-cygnus for Broadcom SDHCI Controllers
> restricted to 32bit host accesses to SDHCI registers.
> --
> 2.7.4
>
>
^ permalink raw reply
* Re: [PATCH V6 01/21] irqchip: tegra: Do not disable COP IRQ during suspend
From: Marc Zyngier @ 2019-07-22 10:13 UTC (permalink / raw)
To: Dmitry Osipenko, Sowjanya Komatineni, thierry.reding, jonathanh,
tglx, jason, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <f6582e43-168e-1b7e-9db8-3d263bc3ba0d@gmail.com>
On 22/07/2019 10:54, Dmitry Osipenko wrote:
> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>> Tegra210 platforms use sc7 entry firmware to program Tegra LP0/SC7 entry
>> sequence and sc7 entry firmware is run from COP/BPMP-Lite.
>>
>> So, COP/BPMP-Lite still need IRQ function to finish SC7 suspend sequence
>> for Tegra210.
>>
>> This patch has fix for leaving the COP IRQ enabled for Tegra210 during
>> interrupt controller suspend operation.
>>
>> Acked-by: Thierry Reding <treding@nvidia.com>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>> drivers/irqchip/irq-tegra.c | 20 ++++++++++++++++++--
>> 1 file changed, 18 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c
>> index e1f771c72fc4..851f88cef508 100644
>> --- a/drivers/irqchip/irq-tegra.c
>> +++ b/drivers/irqchip/irq-tegra.c
>> @@ -44,6 +44,7 @@ static unsigned int num_ictlrs;
>>
>> struct tegra_ictlr_soc {
>> unsigned int num_ictlrs;
>> + bool supports_sc7;
>> };
>>
>> static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
>> @@ -56,6 +57,7 @@ static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
>>
>> static const struct tegra_ictlr_soc tegra210_ictlr_soc = {
>> .num_ictlrs = 6,
>> + .supports_sc7 = true,
>> };
>>
>> static const struct of_device_id ictlr_matches[] = {
>> @@ -67,6 +69,7 @@ static const struct of_device_id ictlr_matches[] = {
>>
>> struct tegra_ictlr_info {
>> void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
>> + const struct tegra_ictlr_soc *soc;
>> #ifdef CONFIG_PM_SLEEP
>> u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
>> u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
>> @@ -147,8 +150,20 @@ static int tegra_ictlr_suspend(void)
>> lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
>> lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
>>
>> - /* Disable COP interrupts */
>> - writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
>> + /*
>> + * AVP/COP/BPMP-Lite is the Tegra boot processor.
>> + *
>> + * Tegra210 system suspend flow uses sc7entry firmware which
>> + * is executed by COP/BPMP and it includes disabling COP IRQ,
>> + * clamping CPU rail, turning off VDD_CPU, and preparing the
>> + * system to go to SC7/LP0.
>> + *
>> + * COP/BPMP wakes up when COP IRQ is triggered and runs
>> + * sc7entry-firmware. So need to keep COP interrupt enabled.
>> + */
>> + if (!lic->soc->supports_sc7)
>> + /* Disable COP interrupts if SC7 is not supported */
>
> All Tegra SoCs support SC7, hence the 'supports_sc7' and the comment
> doesn't sound correct to me. Something like 'firmware_sc7' should suit
> better here.
If what you're saying is true, then the whole patch is wrong, and the
SC7 property should come from DT.
>
>> + writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
>
> Secondly, I'm also not sure why COP interrupts need to be disabled for
> pre-T210 at all, since COP is unused. This looks to me like it was
> cut-n-pasted from downstream kernel without a good reason and could be
> simply removed.
Please verify that this is actually the case. Tegra-2 definitely needed
some level of poking, and I'm not keen on changing anything there until
you (or someone else) has verified it on actual HW (see e307cc8941fc).
Joseph, can you please shed some light here?
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* Re: [PATCH V6 07/21] clk: tegra: Support for OSC context save and restore
From: Dmitry Osipenko @ 2019-07-22 10:12 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <1563738060-30213-8-git-send-email-skomatineni@nvidia.com>
21.07.2019 22:40, Sowjanya Komatineni пишет:
> X-NVConfidentiality: public
What's that?
> This patch adds support for saving OSC clock frequency and the
> drive-strength during OSC clock init and creates an API to restore
> OSC control register value from the saved context.
>
> This API is invoked by Tegra210 clock driver during system resume
> to restore the OSC clock settings.
>
> Acked-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra-fixed.c | 15 +++++++++++++++
> drivers/clk/tegra/clk.h | 1 +
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c
> index 8d91b2b191cf..7c6c8abfcde6 100644
> --- a/drivers/clk/tegra/clk-tegra-fixed.c
> +++ b/drivers/clk/tegra/clk-tegra-fixed.c
> @@ -17,6 +17,10 @@
> #define OSC_CTRL 0x50
> #define OSC_CTRL_OSC_FREQ_SHIFT 28
> #define OSC_CTRL_PLL_REF_DIV_SHIFT 26
> +#define OSC_CTRL_MASK (0x3f2 | \
> + (0xf << OSC_CTRL_OSC_FREQ_SHIFT))
> +
> +static u32 osc_ctrl_ctx;
>
> int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
> unsigned long *input_freqs, unsigned int num,
> @@ -29,6 +33,7 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
> unsigned osc_idx;
>
> val = readl_relaxed(clk_base + OSC_CTRL);
> + osc_ctrl_ctx = val & OSC_CTRL_MASK;
> osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
>
> if (osc_idx < num)
> @@ -96,3 +101,13 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
> *dt_clk = clk;
> }
> }
> +
> +void tegra_clk_osc_resume(void __iomem *clk_base)
> +{
> + u32 val;
> +
> + val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK;
> + val |= osc_ctrl_ctx;
> + writel_relaxed(val, clk_base + OSC_CTRL);
> + fence_udelay(2, clk_base);
> +}
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 8532f5150091..3cd003b7512a 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -849,6 +849,7 @@ int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
> int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
> u8 frac_width, u8 flags);
> void tegra_clk_sync_state_pll(struct clk_hw *hw);
> +void tegra_clk_osc_resume(void __iomem *clk_base);
>
> /* Combined read fence with delay */
> #define fence_udelay(delay, reg) \
>
^ permalink raw reply
* Re: [PATCH V6 01/21] irqchip: tegra: Do not disable COP IRQ during suspend
From: Dmitry Osipenko @ 2019-07-22 9:54 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <1563738060-30213-2-git-send-email-skomatineni@nvidia.com>
21.07.2019 22:40, Sowjanya Komatineni пишет:
> Tegra210 platforms use sc7 entry firmware to program Tegra LP0/SC7 entry
> sequence and sc7 entry firmware is run from COP/BPMP-Lite.
>
> So, COP/BPMP-Lite still need IRQ function to finish SC7 suspend sequence
> for Tegra210.
>
> This patch has fix for leaving the COP IRQ enabled for Tegra210 during
> interrupt controller suspend operation.
>
> Acked-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/irqchip/irq-tegra.c | 20 ++++++++++++++++++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c
> index e1f771c72fc4..851f88cef508 100644
> --- a/drivers/irqchip/irq-tegra.c
> +++ b/drivers/irqchip/irq-tegra.c
> @@ -44,6 +44,7 @@ static unsigned int num_ictlrs;
>
> struct tegra_ictlr_soc {
> unsigned int num_ictlrs;
> + bool supports_sc7;
> };
>
> static const struct tegra_ictlr_soc tegra20_ictlr_soc = {
> @@ -56,6 +57,7 @@ static const struct tegra_ictlr_soc tegra30_ictlr_soc = {
>
> static const struct tegra_ictlr_soc tegra210_ictlr_soc = {
> .num_ictlrs = 6,
> + .supports_sc7 = true,
> };
>
> static const struct of_device_id ictlr_matches[] = {
> @@ -67,6 +69,7 @@ static const struct of_device_id ictlr_matches[] = {
>
> struct tegra_ictlr_info {
> void __iomem *base[TEGRA_MAX_NUM_ICTLRS];
> + const struct tegra_ictlr_soc *soc;
> #ifdef CONFIG_PM_SLEEP
> u32 cop_ier[TEGRA_MAX_NUM_ICTLRS];
> u32 cop_iep[TEGRA_MAX_NUM_ICTLRS];
> @@ -147,8 +150,20 @@ static int tegra_ictlr_suspend(void)
> lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);
> lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
>
> - /* Disable COP interrupts */
> - writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
> + /*
> + * AVP/COP/BPMP-Lite is the Tegra boot processor.
> + *
> + * Tegra210 system suspend flow uses sc7entry firmware which
> + * is executed by COP/BPMP and it includes disabling COP IRQ,
> + * clamping CPU rail, turning off VDD_CPU, and preparing the
> + * system to go to SC7/LP0.
> + *
> + * COP/BPMP wakes up when COP IRQ is triggered and runs
> + * sc7entry-firmware. So need to keep COP interrupt enabled.
> + */
> + if (!lic->soc->supports_sc7)
> + /* Disable COP interrupts if SC7 is not supported */
All Tegra SoCs support SC7, hence the 'supports_sc7' and the comment
doesn't sound correct to me. Something like 'firmware_sc7' should suit
better here.
> + writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
Secondly, I'm also not sure why COP interrupts need to be disabled for
pre-T210 at all, since COP is unused. This looks to me like it was
cut-n-pasted from downstream kernel without a good reason and could be
simply removed.
> /* Disable CPU interrupts */
> writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
> @@ -339,6 +354,7 @@ static int __init tegra_ictlr_init(struct device_node *node,
> goto out_unmap;
> }
>
> + lic->soc = soc;
> tegra_ictlr_syscore_init();
>
> pr_info("%pOF: %d interrupts forwarded to %pOF\n",
>
^ permalink raw reply
* [PATCH 2/3] pinctrl: madera: Add configuration for Cirrus Logic CS47L15
From: Charles Keepax @ 2019-07-22 9:10 UTC (permalink / raw)
To: linus.walleij; +Cc: linux-gpio, patches
In-Reply-To: <20190722091015.20884-1-ckeepax@opensource.cirrus.com>
From: Richard Fitzgerald <rf@opensource.cirrus.com>
This adds the pinctrl configuration for the CS47L15 codec to
the madera pinctrl driver.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
---
drivers/pinctrl/cirrus/Kconfig | 3 +++
drivers/pinctrl/cirrus/Makefile | 3 +++
drivers/pinctrl/cirrus/pinctrl-cs47l15.c | 40 ++++++++++++++++++++++++++++
drivers/pinctrl/cirrus/pinctrl-madera-core.c | 4 +++
drivers/pinctrl/cirrus/pinctrl-madera.h | 1 +
5 files changed, 51 insertions(+)
create mode 100644 drivers/pinctrl/cirrus/pinctrl-cs47l15.c
diff --git a/drivers/pinctrl/cirrus/Kconfig b/drivers/pinctrl/cirrus/Kconfig
index e546a6b75b4d7..ef01a0b062730 100644
--- a/drivers/pinctrl/cirrus/Kconfig
+++ b/drivers/pinctrl/cirrus/Kconfig
@@ -15,6 +15,9 @@ config PINCTRL_MADERA
select PINMUX
select GENERIC_PINCONF
+config PINCTRL_CS47L15
+ bool
+
config PINCTRL_CS47L35
bool
diff --git a/drivers/pinctrl/cirrus/Makefile b/drivers/pinctrl/cirrus/Makefile
index 0c5deb62153ef..491bcb658d8e1 100644
--- a/drivers/pinctrl/cirrus/Makefile
+++ b/drivers/pinctrl/cirrus/Makefile
@@ -3,6 +3,9 @@
obj-$(CONFIG_PINCTRL_LOCHNAGAR) += pinctrl-lochnagar.o
pinctrl-madera-objs := pinctrl-madera-core.o
+ifeq ($(CONFIG_PINCTRL_CS47L15),y)
+pinctrl-madera-objs += pinctrl-cs47l15.o
+endif
ifeq ($(CONFIG_PINCTRL_CS47L35),y)
pinctrl-madera-objs += pinctrl-cs47l35.o
endif
diff --git a/drivers/pinctrl/cirrus/pinctrl-cs47l15.c b/drivers/pinctrl/cirrus/pinctrl-cs47l15.c
new file mode 100644
index 0000000000000..a4bfec5281d07
--- /dev/null
+++ b/drivers/pinctrl/cirrus/pinctrl-cs47l15.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Pinctrl for Cirrus Logic CS47L15
+ *
+ * Copyright (C) 2018-2019 Cirrus Logic, Inc. and
+ * Cirrus Logic International Semiconductor Ltd.
+ */
+
+#include <linux/err.h>
+#include <linux/mfd/madera/core.h>
+
+#include "pinctrl-madera.h"
+
+/*
+ * The alt func groups are the most commonly used functions we place these at
+ * the lower function indexes for convenience, and the less commonly used gpio
+ * functions at higher indexes.
+ *
+ * To stay consistent with the datasheet the function names are the same as
+ * the group names for that function's pins
+ *
+ * Note - all 1 less than in datasheet because these are zero-indexed
+ */
+static const unsigned int cs47l15_aif1_pins[] = { 0, 1, 2, 3 };
+static const unsigned int cs47l15_aif2_pins[] = { 4, 5, 6, 7 };
+static const unsigned int cs47l15_aif3_pins[] = { 8, 9, 10, 11 };
+static const unsigned int cs47l15_spk1_pins[] = { 12, 13, 14 };
+
+static const struct madera_pin_groups cs47l15_pin_groups[] = {
+ { "aif1", cs47l15_aif1_pins, ARRAY_SIZE(cs47l15_aif1_pins) },
+ { "aif2", cs47l15_aif2_pins, ARRAY_SIZE(cs47l15_aif2_pins) },
+ { "aif3", cs47l15_aif3_pins, ARRAY_SIZE(cs47l15_aif3_pins) },
+ { "pdmspk1", cs47l15_spk1_pins, ARRAY_SIZE(cs47l15_spk1_pins) },
+};
+
+const struct madera_pin_chip cs47l15_pin_chip = {
+ .n_pins = CS47L15_NUM_GPIOS,
+ .pin_groups = cs47l15_pin_groups,
+ .n_pin_groups = ARRAY_SIZE(cs47l15_pin_groups),
+};
diff --git a/drivers/pinctrl/cirrus/pinctrl-madera-core.c b/drivers/pinctrl/cirrus/pinctrl-madera-core.c
index 0c7fa1febc802..64281ad5c1b9e 100644
--- a/drivers/pinctrl/cirrus/pinctrl-madera-core.c
+++ b/drivers/pinctrl/cirrus/pinctrl-madera-core.c
@@ -1004,6 +1004,10 @@ static int madera_pin_probe(struct platform_device *pdev)
pdev->dev.of_node = madera->dev->of_node;
switch (madera->type) {
+ case CS47L15:
+ if (IS_ENABLED(CONFIG_PINCTRL_CS47L15))
+ priv->chip = &cs47l15_pin_chip;
+ break;
case CS47L35:
if (IS_ENABLED(CONFIG_PINCTRL_CS47L35))
priv->chip = &cs47l35_pin_chip;
diff --git a/drivers/pinctrl/cirrus/pinctrl-madera.h b/drivers/pinctrl/cirrus/pinctrl-madera.h
index 4ae13918316fe..a10f0238dd928 100644
--- a/drivers/pinctrl/cirrus/pinctrl-madera.h
+++ b/drivers/pinctrl/cirrus/pinctrl-madera.h
@@ -30,6 +30,7 @@ struct madera_pin_private {
struct pinctrl_dev *pctl;
};
+extern const struct madera_pin_chip cs47l15_pin_chip;
extern const struct madera_pin_chip cs47l35_pin_chip;
extern const struct madera_pin_chip cs47l85_pin_chip;
extern const struct madera_pin_chip cs47l90_pin_chip;
--
2.11.0
^ permalink raw reply related
* [PATCH 1/3] pinctrl: madera: Use local copy of pdata
From: Charles Keepax @ 2019-07-22 9:10 UTC (permalink / raw)
To: linus.walleij; +Cc: linux-gpio, patches
A local copy of the pdata exists and it should be used rather than
pulling a fresh copy.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
---
drivers/pinctrl/cirrus/pinctrl-madera-core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/cirrus/pinctrl-madera-core.c b/drivers/pinctrl/cirrus/pinctrl-madera-core.c
index c6b9f65f23621..0c7fa1febc802 100644
--- a/drivers/pinctrl/cirrus/pinctrl-madera-core.c
+++ b/drivers/pinctrl/cirrus/pinctrl-madera-core.c
@@ -986,7 +986,7 @@ static struct pinctrl_desc madera_pin_desc = {
static int madera_pin_probe(struct platform_device *pdev)
{
struct madera *madera = dev_get_drvdata(pdev->dev.parent);
- const struct madera_pdata *pdata = dev_get_platdata(madera->dev);
+ const struct madera_pdata *pdata = &madera->pdata;
struct madera_pin_private *priv;
int ret;
@@ -1037,7 +1037,7 @@ static int madera_pin_probe(struct platform_device *pdev)
}
/* if the configuration is provided through pdata, apply it */
- if (pdata && pdata->gpio_configs) {
+ if (pdata->gpio_configs) {
ret = pinctrl_register_mappings(pdata->gpio_configs,
pdata->n_gpio_configs);
if (ret) {
--
2.11.0
^ permalink raw reply related
* [PATCH 3/3] pinctrl: madera: Add configuration for Cirrus Logic CS47L92
From: Charles Keepax @ 2019-07-22 9:10 UTC (permalink / raw)
To: linus.walleij; +Cc: linux-gpio, patches
In-Reply-To: <20190722091015.20884-1-ckeepax@opensource.cirrus.com>
This adds the pinctrl configuration for the CS47L92 codec to
the madera pinctrl driver.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
---
drivers/pinctrl/cirrus/Kconfig | 3 +++
drivers/pinctrl/cirrus/Makefile | 3 +++
drivers/pinctrl/cirrus/pinctrl-cs47l92.c | 40 ++++++++++++++++++++++++++++
drivers/pinctrl/cirrus/pinctrl-madera-core.c | 16 +++++++++++
drivers/pinctrl/cirrus/pinctrl-madera.h | 1 +
5 files changed, 63 insertions(+)
create mode 100644 drivers/pinctrl/cirrus/pinctrl-cs47l92.c
diff --git a/drivers/pinctrl/cirrus/Kconfig b/drivers/pinctrl/cirrus/Kconfig
index ef01a0b062730..f1806fd781a05 100644
--- a/drivers/pinctrl/cirrus/Kconfig
+++ b/drivers/pinctrl/cirrus/Kconfig
@@ -26,3 +26,6 @@ config PINCTRL_CS47L85
config PINCTRL_CS47L90
bool
+
+config PINCTRL_CS47L92
+ bool
diff --git a/drivers/pinctrl/cirrus/Makefile b/drivers/pinctrl/cirrus/Makefile
index 491bcb658d8e1..a484518c840e3 100644
--- a/drivers/pinctrl/cirrus/Makefile
+++ b/drivers/pinctrl/cirrus/Makefile
@@ -15,5 +15,8 @@ endif
ifeq ($(CONFIG_PINCTRL_CS47L90),y)
pinctrl-madera-objs += pinctrl-cs47l90.o
endif
+ifeq ($(CONFIG_PINCTRL_CS47L92),y)
+pinctrl-madera-objs += pinctrl-cs47l92.o
+endif
obj-$(CONFIG_PINCTRL_MADERA) += pinctrl-madera.o
diff --git a/drivers/pinctrl/cirrus/pinctrl-cs47l92.c b/drivers/pinctrl/cirrus/pinctrl-cs47l92.c
new file mode 100644
index 0000000000000..4e409734334e9
--- /dev/null
+++ b/drivers/pinctrl/cirrus/pinctrl-cs47l92.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Pinctrl for Cirrus Logic CS47L92
+ *
+ * Copyright (C) 2018-2019 Cirrus Logic, Inc. and
+ * Cirrus Logic International Semiconductor Ltd.
+ */
+
+#include <linux/err.h>
+#include <linux/mfd/madera/core.h>
+
+#include "pinctrl-madera.h"
+
+/*
+ * The alt func groups are the most commonly used functions we place these at
+ * the lower function indexes for convenience, and the less commonly used gpio
+ * functions at higher indexes.
+ *
+ * To stay consistent with the datasheet the function names are the same as
+ * the group names for that function's pins
+ *
+ * Note - all 1 less than in datasheet because these are zero-indexed
+ */
+static const unsigned int cs47l92_spk1_pins[] = { 2, 3 };
+static const unsigned int cs47l92_aif1_pins[] = { 4, 5, 6, 7 };
+static const unsigned int cs47l92_aif2_pins[] = { 8, 9, 10, 11 };
+static const unsigned int cs47l92_aif3_pins[] = { 12, 13, 14, 15 };
+
+static const struct madera_pin_groups cs47l92_pin_groups[] = {
+ { "aif1", cs47l92_aif1_pins, ARRAY_SIZE(cs47l92_aif1_pins) },
+ { "aif2", cs47l92_aif2_pins, ARRAY_SIZE(cs47l92_aif2_pins) },
+ { "aif3", cs47l92_aif3_pins, ARRAY_SIZE(cs47l92_aif3_pins) },
+ { "pdmspk1", cs47l92_spk1_pins, ARRAY_SIZE(cs47l92_spk1_pins) },
+};
+
+const struct madera_pin_chip cs47l92_pin_chip = {
+ .n_pins = CS47L92_NUM_GPIOS,
+ .pin_groups = cs47l92_pin_groups,
+ .n_pin_groups = ARRAY_SIZE(cs47l92_pin_groups),
+};
diff --git a/drivers/pinctrl/cirrus/pinctrl-madera-core.c b/drivers/pinctrl/cirrus/pinctrl-madera-core.c
index 64281ad5c1b9e..e2f72dcce4c9c 100644
--- a/drivers/pinctrl/cirrus/pinctrl-madera-core.c
+++ b/drivers/pinctrl/cirrus/pinctrl-madera-core.c
@@ -396,6 +396,16 @@ static const struct {
.group_names = madera_pin_single_group_names,
.func = 0x157
},
+ {
+ .name = "aux-pdm-clk",
+ .group_names = madera_pin_single_group_names,
+ .func = 0x280
+ },
+ {
+ .name = "aux-pdm-dat",
+ .group_names = madera_pin_single_group_names,
+ .func = 0x281
+ },
};
static u16 madera_pin_make_drv_str(struct madera_pin_private *priv,
@@ -1022,6 +1032,12 @@ static int madera_pin_probe(struct platform_device *pdev)
if (IS_ENABLED(CONFIG_PINCTRL_CS47L90))
priv->chip = &cs47l90_pin_chip;
break;
+ case CS42L92:
+ case CS47L92:
+ case CS47L93:
+ if (IS_ENABLED(CONFIG_PINCTRL_CS47L92))
+ priv->chip = &cs47l92_pin_chip;
+ break;
default:
break;
}
diff --git a/drivers/pinctrl/cirrus/pinctrl-madera.h b/drivers/pinctrl/cirrus/pinctrl-madera.h
index a10f0238dd928..c16a4dc19a2a0 100644
--- a/drivers/pinctrl/cirrus/pinctrl-madera.h
+++ b/drivers/pinctrl/cirrus/pinctrl-madera.h
@@ -34,5 +34,6 @@ extern const struct madera_pin_chip cs47l15_pin_chip;
extern const struct madera_pin_chip cs47l35_pin_chip;
extern const struct madera_pin_chip cs47l85_pin_chip;
extern const struct madera_pin_chip cs47l90_pin_chip;
+extern const struct madera_pin_chip cs47l92_pin_chip;
#endif
--
2.11.0
^ permalink raw reply related
* [PATCH 3/4] gpio: madera: Add support for Cirrus Logic CS47L15
From: Charles Keepax @ 2019-07-22 9:07 UTC (permalink / raw)
To: bgolaszewski; +Cc: linus.walleij, linux-gpio, patches
In-Reply-To: <20190722090748.20807-1-ckeepax@opensource.cirrus.com>
From: Richard Fitzgerald <rf@opensource.cirrus.com>
As the gpio is common to all madera codecs all that is needed
is to setup the correct number of GPIO pins for the CS47L15.
Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
---
drivers/gpio/gpio-madera.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpio/gpio-madera.c b/drivers/gpio/gpio-madera.c
index fa3441df0a5db..c403899ff4500 100644
--- a/drivers/gpio/gpio-madera.c
+++ b/drivers/gpio/gpio-madera.c
@@ -136,6 +136,9 @@ static int madera_gpio_probe(struct platform_device *pdev)
madera_gpio->gpio_chip.parent = pdev->dev.parent;
switch (madera->type) {
+ case CS47L15:
+ madera_gpio->gpio_chip.ngpio = CS47L15_NUM_GPIOS;
+ break;
case CS47L35:
madera_gpio->gpio_chip.ngpio = CS47L35_NUM_GPIOS;
break;
--
2.11.0
^ permalink raw reply related
* [PATCH 4/4] gpio: madera: Add support for Cirrus Logic CS47L92
From: Charles Keepax @ 2019-07-22 9:07 UTC (permalink / raw)
To: bgolaszewski; +Cc: linus.walleij, linux-gpio, patches
In-Reply-To: <20190722090748.20807-1-ckeepax@opensource.cirrus.com>
As the gpio is common to all madera codecs all that is needed
is to setup the correct number of GPIO pins for the CS47L92.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
---
drivers/gpio/gpio-madera.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpio/gpio-madera.c b/drivers/gpio/gpio-madera.c
index c403899ff4500..7086f8b5388fd 100644
--- a/drivers/gpio/gpio-madera.c
+++ b/drivers/gpio/gpio-madera.c
@@ -150,6 +150,11 @@ static int madera_gpio_probe(struct platform_device *pdev)
case CS47L91:
madera_gpio->gpio_chip.ngpio = CS47L90_NUM_GPIOS;
break;
+ case CS42L92:
+ case CS47L92:
+ case CS47L93:
+ madera_gpio->gpio_chip.ngpio = CS47L92_NUM_GPIOS;
+ break;
default:
dev_err(&pdev->dev, "Unknown chip variant %d\n", madera->type);
return -EINVAL;
--
2.11.0
^ permalink raw reply related
* [PATCH 1/4] gpio: arizona: Use local copy of pdata
From: Charles Keepax @ 2019-07-22 9:07 UTC (permalink / raw)
To: bgolaszewski; +Cc: linus.walleij, linux-gpio, patches
A local copy of the pdata exists and it should be used rather than
pulling a fresh copy.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
---
drivers/gpio/gpio-arizona.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/gpio-arizona.c b/drivers/gpio/gpio-arizona.c
index c07fad975049d..5640efe5e7504 100644
--- a/drivers/gpio/gpio-arizona.c
+++ b/drivers/gpio/gpio-arizona.c
@@ -142,7 +142,7 @@ static const struct gpio_chip template_chip = {
static int arizona_gpio_probe(struct platform_device *pdev)
{
struct arizona *arizona = dev_get_drvdata(pdev->dev.parent);
- struct arizona_pdata *pdata = dev_get_platdata(arizona->dev);
+ struct arizona_pdata *pdata = &arizona->pdata;
struct arizona_gpio *arizona_gpio;
int ret;
@@ -177,7 +177,7 @@ static int arizona_gpio_probe(struct platform_device *pdev)
return -EINVAL;
}
- if (pdata && pdata->gpio_base)
+ if (pdata->gpio_base)
arizona_gpio->gpio_chip.base = pdata->gpio_base;
else
arizona_gpio->gpio_chip.base = -1;
--
2.11.0
^ permalink raw reply related
* [PATCH 2/4] gpio: madera: Use local copy of pdata
From: Charles Keepax @ 2019-07-22 9:07 UTC (permalink / raw)
To: bgolaszewski; +Cc: linus.walleij, linux-gpio, patches
In-Reply-To: <20190722090748.20807-1-ckeepax@opensource.cirrus.com>
A local copy of the pdata exists and it should be used rather than
pulling a fresh copy.
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
---
drivers/gpio/gpio-madera.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/gpio-madera.c b/drivers/gpio/gpio-madera.c
index 4dbc837d12155..fa3441df0a5db 100644
--- a/drivers/gpio/gpio-madera.c
+++ b/drivers/gpio/gpio-madera.c
@@ -120,7 +120,7 @@ static const struct gpio_chip madera_gpio_chip = {
static int madera_gpio_probe(struct platform_device *pdev)
{
struct madera *madera = dev_get_drvdata(pdev->dev.parent);
- struct madera_pdata *pdata = dev_get_platdata(madera->dev);
+ struct madera_pdata *pdata = &madera->pdata;
struct madera_gpio *madera_gpio;
int ret;
@@ -153,7 +153,7 @@ static int madera_gpio_probe(struct platform_device *pdev)
}
/* We want to be usable on systems that don't use devicetree or acpi */
- if (pdata && pdata->gpio_base)
+ if (pdata->gpio_base)
madera_gpio->gpio_chip.base = pdata->gpio_base;
else
madera_gpio->gpio_chip.base = -1;
--
2.11.0
^ permalink raw reply related
* Re: [PATCH V6 09/21] clk: tegra: clk-super: Fix to enable PLLP branches to CPU
From: Sowjanya Komatineni @ 2019-07-22 7:36 UTC (permalink / raw)
To: Dmitry Osipenko, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <fc6403e6-0022-f505-8864-70bc047207c9@gmail.com>
On 7/22/19 12:30 AM, Dmitry Osipenko wrote:
> 22.07.2019 10:24, Sowjanya Komatineni пишет:
>> On 7/22/19 12:17 AM, Dmitry Osipenko wrote:
>>> 22.07.2019 10:12, Sowjanya Komatineni пишет:
>>>> On 7/21/19 11:32 PM, Dmitry Osipenko wrote:
>>>>> 22.07.2019 6:17, Sowjanya Komatineni пишет:
>>>>>> On 7/21/19 3:39 PM, Sowjanya Komatineni wrote:
>>>>>>> On 7/21/19 2:16 PM, Dmitry Osipenko wrote:
>>>>>>>> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>>>>>>>>> This patch has a fix to enable PLLP branches to CPU before changing
>>>>>>>>> the CPU clusters clock source to PLLP for Gen5 Super clock.
>>>>>>>>>
>>>>>>>>> During system suspend entry and exit, CPU source will be switched
>>>>>>>>> to PLLP and this needs PLLP branches to be enabled to CPU prior to
>>>>>>>>> the switch.
>>>>>>>>>
>>>>>>>>> On system resume, warmboot code enables PLLP branches to CPU and
>>>>>>>>> powers up the CPU with PLLP clock source.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>>> ---
>>>>>>>>> drivers/clk/tegra/clk-super.c | 11 +++++++++++
>>>>>>>>> drivers/clk/tegra/clk-tegra-super-gen4.c | 4 ++--
>>>>>>>>> drivers/clk/tegra/clk.h | 4 ++++
>>>>>>>>> 3 files changed, 17 insertions(+), 2 deletions(-)
>>>>>>>>>
>>>>>>>>> diff --git a/drivers/clk/tegra/clk-super.c
>>>>>>>>> b/drivers/clk/tegra/clk-super.c
>>>>>>>>> index 39ef31b46df5..d73c587e4853 100644
>>>>>>>>> --- a/drivers/clk/tegra/clk-super.c
>>>>>>>>> +++ b/drivers/clk/tegra/clk-super.c
>>>>>>>>> @@ -28,6 +28,9 @@
>>>>>>>>> #define super_state_to_src_shift(m, s) ((m->width * s))
>>>>>>>>> #define super_state_to_src_mask(m) (((1 << m->width) - 1))
>>>>>>>>> +#define CCLK_SRC_PLLP_OUT0 4
>>>>>>>>> +#define CCLK_SRC_PLLP_OUT4 5
>>>>>>>>> +
>>>>>>>>> static u8 clk_super_get_parent(struct clk_hw *hw)
>>>>>>>>> {
>>>>>>>>> struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
>>>>>>>>> @@ -97,6 +100,14 @@ static int clk_super_set_parent(struct clk_hw
>>>>>>>>> *hw, u8 index)
>>>>>>>>> if (index == mux->div2_index)
>>>>>>>>> index = mux->pllx_index;
>>>>>>>>> }
>>>>>>>>> +
>>>>>>>>> + /*
>>>>>>>>> + * Enable PLLP branches to CPU before selecting PLLP source
>>>>>>>>> + */
>>>>>>>>> + if ((mux->flags & TEGRA_CPU_CLK) &&
>>>>>>>>> + ((index == CCLK_SRC_PLLP_OUT0) || (index ==
>>>>>>>>> CCLK_SRC_PLLP_OUT4)))
>>>>>>>>> + tegra_clk_set_pllp_out_cpu(true);
>>>>>>>> Should somewhere here be tegra_clk_set_pllp_out_cpu(false) when
>>>>>>>> switching from PLLP?
>>>>>>> PLLP may be used for other CPU clusters.
>>>>>> Though to avoid flag and check needed to make sure other CPU is not
>>>>>> using before disabling PLLP branch to CPU.
>>>>>>
>>>>>> But leaving it enabled shouldn't impact much as clock source mux is
>>>>>> after this in design anyway.
>>>>>>
>>>>>> But can add as well if its clear that way.
>>>>> The TRM doc says "The CPU subsystem supports a switch-cluster mode
>>>>> meaning that only one of the clusters can be active at any given time".
>>>>>
>>>>> Given that cluster-switching isn't supported in upstream, I don't think
>>>>> that you need to care about the other cluster at all, at least for now.
>>>>>
>>>>> The cluster-switching implementation in upstream is very complicated
>>>>> because it requires a special "hotplugging" CPU governor, which
>>>>> apparently no other platform needs.
>>>>>
>>>>> [snip]
>>>> This patch enables PLLP branches to CPU for both CPUG & CPULP if they
>>>> use PLLP source.
>>>>
>>>> So, to disable PLLP out CPU when not in use, we still need check for
>>>> other cluster because during resume both LP CPU and G CPU gets restored.
>>>> CPUG runs from PLLP on resume and when it does super clk restore for LP
>>>> CPU which may not be using PLLP, but as both uses same super mux
>>>> clk_ops, without check (for PLLP branch to CPU in use) disabling PLLP
>>>> branch to CPU during LP CPU restore looses clock to CPU G as well which
>>>> is running from PLLP.
>>>>
>>>> Will add check and disable PLLP if not in use in next version... this
>>>> need extern flag as well to mark PLLP usage with either of CPU's.
>>> I still don't understand why do you need to care about LP cluster at
>>> all, given that it's always in a power-gated state.
>> cclk_lp is registered thru super clk mux which uses same clk_ops as cclk_g.
>>
>> during restore, cclk_lp also gets restored. So both cclk_lp & cclk_g
>> goes thru same clk_ops
>>
>> In this patch, I marked super flags with TEGRA_CPU_CLK for both cclk_lp
>> & cclk_g.
>>
>> So when cclk_lp restore happens, it goes thru same set_parent clk_ops
>> and as its source is not PLLP, it tries to disable PLLP_OUT_CPU if its
>> disabled without adding check for PLLP being in use by other cluster.
> Ah, okay.
>
>> So either I should not mark cclk_lp as TEGRA_CPU_CLK and mark cclk_g
>> only as TEGRA_CPU_CLK so PLLP out to CPU can be disabled without check
>> if its not the source.
>>
>> OR
>>
>> With TEGRA_CPU_CLK used for both cclk_lp & cclk_g, need to add check if
>> PLLP is in use so during cclk_lp restore it doesnt disable PLLP out to CPU.
>>
>>
>> To simplify without check, will just mark cclk_g super clock flag only
>> as TEGRA_CPU_CLK so PLLP_OUT_CPU enable or disable happens only for CPUG
> Sounds good. Then please add a brief comment to the CPULP, telling why
> it misses the flag, for the record.
Sure, will add comment.
^ permalink raw reply
* Re: [PATCH V6 09/21] clk: tegra: clk-super: Fix to enable PLLP branches to CPU
From: Dmitry Osipenko @ 2019-07-22 7:30 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <90e1a90b-1d33-a5db-9af8-dc5c5d45b65f@nvidia.com>
22.07.2019 10:24, Sowjanya Komatineni пишет:
>
> On 7/22/19 12:17 AM, Dmitry Osipenko wrote:
>> 22.07.2019 10:12, Sowjanya Komatineni пишет:
>>> On 7/21/19 11:32 PM, Dmitry Osipenko wrote:
>>>> 22.07.2019 6:17, Sowjanya Komatineni пишет:
>>>>> On 7/21/19 3:39 PM, Sowjanya Komatineni wrote:
>>>>>> On 7/21/19 2:16 PM, Dmitry Osipenko wrote:
>>>>>>> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>>>>>>>> This patch has a fix to enable PLLP branches to CPU before changing
>>>>>>>> the CPU clusters clock source to PLLP for Gen5 Super clock.
>>>>>>>>
>>>>>>>> During system suspend entry and exit, CPU source will be switched
>>>>>>>> to PLLP and this needs PLLP branches to be enabled to CPU prior to
>>>>>>>> the switch.
>>>>>>>>
>>>>>>>> On system resume, warmboot code enables PLLP branches to CPU and
>>>>>>>> powers up the CPU with PLLP clock source.
>>>>>>>>
>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>> ---
>>>>>>>> drivers/clk/tegra/clk-super.c | 11 +++++++++++
>>>>>>>> drivers/clk/tegra/clk-tegra-super-gen4.c | 4 ++--
>>>>>>>> drivers/clk/tegra/clk.h | 4 ++++
>>>>>>>> 3 files changed, 17 insertions(+), 2 deletions(-)
>>>>>>>>
>>>>>>>> diff --git a/drivers/clk/tegra/clk-super.c
>>>>>>>> b/drivers/clk/tegra/clk-super.c
>>>>>>>> index 39ef31b46df5..d73c587e4853 100644
>>>>>>>> --- a/drivers/clk/tegra/clk-super.c
>>>>>>>> +++ b/drivers/clk/tegra/clk-super.c
>>>>>>>> @@ -28,6 +28,9 @@
>>>>>>>> #define super_state_to_src_shift(m, s) ((m->width * s))
>>>>>>>> #define super_state_to_src_mask(m) (((1 << m->width) - 1))
>>>>>>>> +#define CCLK_SRC_PLLP_OUT0 4
>>>>>>>> +#define CCLK_SRC_PLLP_OUT4 5
>>>>>>>> +
>>>>>>>> static u8 clk_super_get_parent(struct clk_hw *hw)
>>>>>>>> {
>>>>>>>> struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
>>>>>>>> @@ -97,6 +100,14 @@ static int clk_super_set_parent(struct clk_hw
>>>>>>>> *hw, u8 index)
>>>>>>>> if (index == mux->div2_index)
>>>>>>>> index = mux->pllx_index;
>>>>>>>> }
>>>>>>>> +
>>>>>>>> + /*
>>>>>>>> + * Enable PLLP branches to CPU before selecting PLLP source
>>>>>>>> + */
>>>>>>>> + if ((mux->flags & TEGRA_CPU_CLK) &&
>>>>>>>> + ((index == CCLK_SRC_PLLP_OUT0) || (index ==
>>>>>>>> CCLK_SRC_PLLP_OUT4)))
>>>>>>>> + tegra_clk_set_pllp_out_cpu(true);
>>>>>>> Should somewhere here be tegra_clk_set_pllp_out_cpu(false) when
>>>>>>> switching from PLLP?
>>>>>> PLLP may be used for other CPU clusters.
>>>>> Though to avoid flag and check needed to make sure other CPU is not
>>>>> using before disabling PLLP branch to CPU.
>>>>>
>>>>> But leaving it enabled shouldn't impact much as clock source mux is
>>>>> after this in design anyway.
>>>>>
>>>>> But can add as well if its clear that way.
>>>> The TRM doc says "The CPU subsystem supports a switch-cluster mode
>>>> meaning that only one of the clusters can be active at any given time".
>>>>
>>>> Given that cluster-switching isn't supported in upstream, I don't think
>>>> that you need to care about the other cluster at all, at least for now.
>>>>
>>>> The cluster-switching implementation in upstream is very complicated
>>>> because it requires a special "hotplugging" CPU governor, which
>>>> apparently no other platform needs.
>>>>
>>>> [snip]
>>> This patch enables PLLP branches to CPU for both CPUG & CPULP if they
>>> use PLLP source.
>>>
>>> So, to disable PLLP out CPU when not in use, we still need check for
>>> other cluster because during resume both LP CPU and G CPU gets restored.
>>> CPUG runs from PLLP on resume and when it does super clk restore for LP
>>> CPU which may not be using PLLP, but as both uses same super mux
>>> clk_ops, without check (for PLLP branch to CPU in use) disabling PLLP
>>> branch to CPU during LP CPU restore looses clock to CPU G as well which
>>> is running from PLLP.
>>>
>>> Will add check and disable PLLP if not in use in next version... this
>>> need extern flag as well to mark PLLP usage with either of CPU's.
>> I still don't understand why do you need to care about LP cluster at
>> all, given that it's always in a power-gated state.
>
> cclk_lp is registered thru super clk mux which uses same clk_ops as cclk_g.
>
> during restore, cclk_lp also gets restored. So both cclk_lp & cclk_g
> goes thru same clk_ops
>
> In this patch, I marked super flags with TEGRA_CPU_CLK for both cclk_lp
> & cclk_g.
>
> So when cclk_lp restore happens, it goes thru same set_parent clk_ops
> and as its source is not PLLP, it tries to disable PLLP_OUT_CPU if its
> disabled without adding check for PLLP being in use by other cluster.
Ah, okay.
> So either I should not mark cclk_lp as TEGRA_CPU_CLK and mark cclk_g
> only as TEGRA_CPU_CLK so PLLP out to CPU can be disabled without check
> if its not the source.
>
> OR
>
> With TEGRA_CPU_CLK used for both cclk_lp & cclk_g, need to add check if
> PLLP is in use so during cclk_lp restore it doesnt disable PLLP out to CPU.
>
>
> To simplify without check, will just mark cclk_g super clock flag only
> as TEGRA_CPU_CLK so PLLP_OUT_CPU enable or disable happens only for CPUG
Sounds good. Then please add a brief comment to the CPULP, telling why
it misses the flag, for the record.
^ permalink raw reply
* Re: [PATCH V6 09/21] clk: tegra: clk-super: Fix to enable PLLP branches to CPU
From: Sowjanya Komatineni @ 2019-07-22 7:24 UTC (permalink / raw)
To: Dmitry Osipenko, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <07897688-2a02-b7a7-7048-72c4078d26a2@gmail.com>
On 7/22/19 12:17 AM, Dmitry Osipenko wrote:
> 22.07.2019 10:12, Sowjanya Komatineni пишет:
>> On 7/21/19 11:32 PM, Dmitry Osipenko wrote:
>>> 22.07.2019 6:17, Sowjanya Komatineni пишет:
>>>> On 7/21/19 3:39 PM, Sowjanya Komatineni wrote:
>>>>> On 7/21/19 2:16 PM, Dmitry Osipenko wrote:
>>>>>> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>>>>>>> This patch has a fix to enable PLLP branches to CPU before changing
>>>>>>> the CPU clusters clock source to PLLP for Gen5 Super clock.
>>>>>>>
>>>>>>> During system suspend entry and exit, CPU source will be switched
>>>>>>> to PLLP and this needs PLLP branches to be enabled to CPU prior to
>>>>>>> the switch.
>>>>>>>
>>>>>>> On system resume, warmboot code enables PLLP branches to CPU and
>>>>>>> powers up the CPU with PLLP clock source.
>>>>>>>
>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>> ---
>>>>>>> drivers/clk/tegra/clk-super.c | 11 +++++++++++
>>>>>>> drivers/clk/tegra/clk-tegra-super-gen4.c | 4 ++--
>>>>>>> drivers/clk/tegra/clk.h | 4 ++++
>>>>>>> 3 files changed, 17 insertions(+), 2 deletions(-)
>>>>>>>
>>>>>>> diff --git a/drivers/clk/tegra/clk-super.c
>>>>>>> b/drivers/clk/tegra/clk-super.c
>>>>>>> index 39ef31b46df5..d73c587e4853 100644
>>>>>>> --- a/drivers/clk/tegra/clk-super.c
>>>>>>> +++ b/drivers/clk/tegra/clk-super.c
>>>>>>> @@ -28,6 +28,9 @@
>>>>>>> #define super_state_to_src_shift(m, s) ((m->width * s))
>>>>>>> #define super_state_to_src_mask(m) (((1 << m->width) - 1))
>>>>>>> +#define CCLK_SRC_PLLP_OUT0 4
>>>>>>> +#define CCLK_SRC_PLLP_OUT4 5
>>>>>>> +
>>>>>>> static u8 clk_super_get_parent(struct clk_hw *hw)
>>>>>>> {
>>>>>>> struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
>>>>>>> @@ -97,6 +100,14 @@ static int clk_super_set_parent(struct clk_hw
>>>>>>> *hw, u8 index)
>>>>>>> if (index == mux->div2_index)
>>>>>>> index = mux->pllx_index;
>>>>>>> }
>>>>>>> +
>>>>>>> + /*
>>>>>>> + * Enable PLLP branches to CPU before selecting PLLP source
>>>>>>> + */
>>>>>>> + if ((mux->flags & TEGRA_CPU_CLK) &&
>>>>>>> + ((index == CCLK_SRC_PLLP_OUT0) || (index ==
>>>>>>> CCLK_SRC_PLLP_OUT4)))
>>>>>>> + tegra_clk_set_pllp_out_cpu(true);
>>>>>> Should somewhere here be tegra_clk_set_pllp_out_cpu(false) when
>>>>>> switching from PLLP?
>>>>> PLLP may be used for other CPU clusters.
>>>> Though to avoid flag and check needed to make sure other CPU is not
>>>> using before disabling PLLP branch to CPU.
>>>>
>>>> But leaving it enabled shouldn't impact much as clock source mux is
>>>> after this in design anyway.
>>>>
>>>> But can add as well if its clear that way.
>>> The TRM doc says "The CPU subsystem supports a switch-cluster mode
>>> meaning that only one of the clusters can be active at any given time".
>>>
>>> Given that cluster-switching isn't supported in upstream, I don't think
>>> that you need to care about the other cluster at all, at least for now.
>>>
>>> The cluster-switching implementation in upstream is very complicated
>>> because it requires a special "hotplugging" CPU governor, which
>>> apparently no other platform needs.
>>>
>>> [snip]
>> This patch enables PLLP branches to CPU for both CPUG & CPULP if they
>> use PLLP source.
>>
>> So, to disable PLLP out CPU when not in use, we still need check for
>> other cluster because during resume both LP CPU and G CPU gets restored.
>> CPUG runs from PLLP on resume and when it does super clk restore for LP
>> CPU which may not be using PLLP, but as both uses same super mux
>> clk_ops, without check (for PLLP branch to CPU in use) disabling PLLP
>> branch to CPU during LP CPU restore looses clock to CPU G as well which
>> is running from PLLP.
>>
>> Will add check and disable PLLP if not in use in next version... this
>> need extern flag as well to mark PLLP usage with either of CPU's.
> I still don't understand why do you need to care about LP cluster at
> all, given that it's always in a power-gated state.
cclk_lp is registered thru super clk mux which uses same clk_ops as cclk_g.
during restore, cclk_lp also gets restored. So both cclk_lp & cclk_g
goes thru same clk_ops
In this patch, I marked super flags with TEGRA_CPU_CLK for both cclk_lp
& cclk_g.
So when cclk_lp restore happens, it goes thru same set_parent clk_ops
and as its source is not PLLP, it tries to disable PLLP_OUT_CPU if its
disabled without adding check for PLLP being in use by other cluster.
So either I should not mark cclk_lp as TEGRA_CPU_CLK and mark cclk_g
only as TEGRA_CPU_CLK so PLLP out to CPU can be disabled without check
if its not the source.
OR
With TEGRA_CPU_CLK used for both cclk_lp & cclk_g, need to add check if
PLLP is in use so during cclk_lp restore it doesnt disable PLLP out to CPU.
To simplify without check, will just mark cclk_g super clock flag only
as TEGRA_CPU_CLK so PLLP_OUT_CPU enable or disable happens only for CPUG
^ permalink raw reply
* Re: [PATCH V6 09/21] clk: tegra: clk-super: Fix to enable PLLP branches to CPU
From: Dmitry Osipenko @ 2019-07-22 7:17 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <d9bbe208-6cd3-6a28-3e43-fdd566699b1d@nvidia.com>
22.07.2019 10:12, Sowjanya Komatineni пишет:
>
> On 7/21/19 11:32 PM, Dmitry Osipenko wrote:
>> 22.07.2019 6:17, Sowjanya Komatineni пишет:
>>> On 7/21/19 3:39 PM, Sowjanya Komatineni wrote:
>>>> On 7/21/19 2:16 PM, Dmitry Osipenko wrote:
>>>>> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>>>>>> This patch has a fix to enable PLLP branches to CPU before changing
>>>>>> the CPU clusters clock source to PLLP for Gen5 Super clock.
>>>>>>
>>>>>> During system suspend entry and exit, CPU source will be switched
>>>>>> to PLLP and this needs PLLP branches to be enabled to CPU prior to
>>>>>> the switch.
>>>>>>
>>>>>> On system resume, warmboot code enables PLLP branches to CPU and
>>>>>> powers up the CPU with PLLP clock source.
>>>>>>
>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>> ---
>>>>>> drivers/clk/tegra/clk-super.c | 11 +++++++++++
>>>>>> drivers/clk/tegra/clk-tegra-super-gen4.c | 4 ++--
>>>>>> drivers/clk/tegra/clk.h | 4 ++++
>>>>>> 3 files changed, 17 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/clk/tegra/clk-super.c
>>>>>> b/drivers/clk/tegra/clk-super.c
>>>>>> index 39ef31b46df5..d73c587e4853 100644
>>>>>> --- a/drivers/clk/tegra/clk-super.c
>>>>>> +++ b/drivers/clk/tegra/clk-super.c
>>>>>> @@ -28,6 +28,9 @@
>>>>>> #define super_state_to_src_shift(m, s) ((m->width * s))
>>>>>> #define super_state_to_src_mask(m) (((1 << m->width) - 1))
>>>>>> +#define CCLK_SRC_PLLP_OUT0 4
>>>>>> +#define CCLK_SRC_PLLP_OUT4 5
>>>>>> +
>>>>>> static u8 clk_super_get_parent(struct clk_hw *hw)
>>>>>> {
>>>>>> struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
>>>>>> @@ -97,6 +100,14 @@ static int clk_super_set_parent(struct clk_hw
>>>>>> *hw, u8 index)
>>>>>> if (index == mux->div2_index)
>>>>>> index = mux->pllx_index;
>>>>>> }
>>>>>> +
>>>>>> + /*
>>>>>> + * Enable PLLP branches to CPU before selecting PLLP source
>>>>>> + */
>>>>>> + if ((mux->flags & TEGRA_CPU_CLK) &&
>>>>>> + ((index == CCLK_SRC_PLLP_OUT0) || (index ==
>>>>>> CCLK_SRC_PLLP_OUT4)))
>>>>>> + tegra_clk_set_pllp_out_cpu(true);
>>>>> Should somewhere here be tegra_clk_set_pllp_out_cpu(false) when
>>>>> switching from PLLP?
>>>> PLLP may be used for other CPU clusters.
>>> Though to avoid flag and check needed to make sure other CPU is not
>>> using before disabling PLLP branch to CPU.
>>>
>>> But leaving it enabled shouldn't impact much as clock source mux is
>>> after this in design anyway.
>>>
>>> But can add as well if its clear that way.
>> The TRM doc says "The CPU subsystem supports a switch-cluster mode
>> meaning that only one of the clusters can be active at any given time".
>>
>> Given that cluster-switching isn't supported in upstream, I don't think
>> that you need to care about the other cluster at all, at least for now.
>>
>> The cluster-switching implementation in upstream is very complicated
>> because it requires a special "hotplugging" CPU governor, which
>> apparently no other platform needs.
>>
>> [snip]
>
> This patch enables PLLP branches to CPU for both CPUG & CPULP if they
> use PLLP source.
>
> So, to disable PLLP out CPU when not in use, we still need check for
> other cluster because during resume both LP CPU and G CPU gets restored.
> CPUG runs from PLLP on resume and when it does super clk restore for LP
> CPU which may not be using PLLP, but as both uses same super mux
> clk_ops, without check (for PLLP branch to CPU in use) disabling PLLP
> branch to CPU during LP CPU restore looses clock to CPU G as well which
> is running from PLLP.
>
> Will add check and disable PLLP if not in use in next version... this
> need extern flag as well to mark PLLP usage with either of CPU's.
I still don't understand why do you need to care about LP cluster at
all, given that it's always in a power-gated state.
^ permalink raw reply
* Re: [PATCH V6 14/21] clk: tegra210: Add suspend and resume support
From: Dmitry Osipenko @ 2019-07-22 7:12 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <5054f178-db27-9286-d123-3e2b2a885717@gmail.com>
22.07.2019 10:09, Dmitry Osipenko пишет:
> 22.07.2019 9:52, Sowjanya Komatineni пишет:
>>
>> On 7/21/19 11:10 PM, Dmitry Osipenko wrote:
>>> 22.07.2019 1:45, Sowjanya Komatineni пишет:
>>>> On 7/21/19 2:38 PM, Dmitry Osipenko wrote:
>>>>> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>>>>>> This patch adds support for clk: tegra210: suspend-resume.
>>>>>>
>>>>>> All the CAR controller settings are lost on suspend when core
>>>>>> power goes off.
>>>>>>
>>>>>> This patch has implementation for saving and restoring all PLLs
>>>>>> and clocks context during system suspend and resume to have the
>>>>>> clocks back to same state for normal operation.
>>>>>>
>>>>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>> ---
>>>>>> drivers/clk/tegra/clk-tegra210.c | 68
>>>>>> ++++++++++++++++++++++++++++++++++++++--
>>>>>> drivers/clk/tegra/clk.c | 14 +++++++++
>>>>>> drivers/clk/tegra/clk.h | 1 +
>>>>>> 3 files changed, 80 insertions(+), 3 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/clk/tegra/clk-tegra210.c
>>>>>> b/drivers/clk/tegra/clk-tegra210.c
>>>>>> index 55a88c0824a5..68271873acc1 100644
>>>>>> --- a/drivers/clk/tegra/clk-tegra210.c
>>>>>> +++ b/drivers/clk/tegra/clk-tegra210.c
>>>>>> @@ -9,6 +9,7 @@
>>>>>> #include <linux/clkdev.h>
>>>>>> #include <linux/of.h>
>>>>>> #include <linux/of_address.h>
>>>>>> +#include <linux/syscore_ops.h>
>>>>>> #include <linux/delay.h>
>>>>>> #include <linux/export.h>
>>>>>> #include <linux/mutex.h>
>>>>>> @@ -220,11 +221,15 @@
>>>>>> #define CLK_M_DIVISOR_SHIFT 2
>>>>>> #define CLK_M_DIVISOR_MASK 0x3
>>>>>> +#define CLK_MASK_ARM 0x44
>>>>>> +#define MISC_CLK_ENB 0x48
>>>>>> +
>>>>>> #define RST_DFLL_DVCO 0x2f4
>>>>>> #define DVFS_DFLL_RESET_SHIFT 0
>>>>>> #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
>>>>>> #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
>>>>>> +#define CPU_SOFTRST_CTRL 0x380
>>>>>> #define LVL2_CLK_GATE_OVRA 0xf8
>>>>>> #define LVL2_CLK_GATE_OVRC 0x3a0
>>>>>> @@ -2825,6 +2830,7 @@ static int tegra210_enable_pllu(void)
>>>>>> struct tegra_clk_pll_freq_table *fentry;
>>>>>> struct tegra_clk_pll pllu;
>>>>>> u32 reg;
>>>>>> + int ret;
>>>>>> for (fentry = pll_u_freq_table; fentry->input_rate;
>>>>>> fentry++) {
>>>>>> if (fentry->input_rate == pll_ref_freq)
>>>>>> @@ -2853,9 +2859,8 @@ static int tegra210_enable_pllu(void)
>>>>>> reg |= PLL_ENABLE;
>>>>>> writel(reg, clk_base + PLLU_BASE);
>>>>>> - readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg,
>>>>>> - reg & PLL_BASE_LOCK, 2, 1000);
>>>>>> - if (!(reg & PLL_BASE_LOCK)) {
>>>>>> + ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK);
>>>>>> + if (ret) {
>>>>> Why this is needed? Was there a bug?
>>>>>
>>>> during resume pllu init is needed and to use same terga210_init_pllu,
>>>> poll_timeout_atomic can't be used as its ony for atomic context.
>>>>
>>>> So changed to use wait_for_mask which should work in both cases.
>>> Atomic variant could be used from any context, not sure what do you
>>> mean. The 'atomic' part only means that function won't cause scheduling
>>> and that's it.
>>
>> Sorry, replied incorrect. readx_poll_timeout_atomic uses ktime_get() and
>> during resume timekeeping suspend/resume happens later than clock
>> suspend/resume. So using tegra210_wait_for_mask.
>>
>> both timekeeping and clk-tegra210 drivers are registered as syscore but
>> not ordered.
>
> Okay, thank you for the clarification.
>
> [snip]
>
You should remove the 'iopoll.h' then, since it's not used anymore.
^ permalink raw reply
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