* Re: [PATCH 10/14] ARM: lpc32xx: clean up header files
From: Sylvain Lemieux @ 2019-08-06 20:16 UTC (permalink / raw)
To: Arnd Bergmann
Cc: soc, moderated list:ARM PORT, Vladimir Zapolskiy, Russell King,
Gregory Clement, Linus Walleij, Jason Cooper, Andrew Lunn,
Sebastian Hesselbarth, David S. Miller, Greg Kroah-Hartman,
Alan Stern, Guenter Roeck, open list:GPIO SUBSYSTEM, Networking,
linux-serial, USB list, LINUXWATCHDOG, Linux Kernel Mailing List
In-Reply-To: <20190731195713.3150463-11-arnd@arndb.de>
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
On Wed, Jul 31, 2019 at 4:03 PM Arnd Bergmann <arnd@arndb.de> wrote:
>
> All device drivers have stopped relying on mach/*.h headers,
> so move the remaining headers into arch/arm/mach-lpc32xx/lpc32xx.h
> to prepare for multiplatform builds.
>
> The mach/entry-macro.S file has been unused for a long time now
> and can simply get removed.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> arch/arm/mach-lpc32xx/common.c | 3 +-
> .../mach-lpc32xx/include/mach/entry-macro.S | 28 -------------------
> arch/arm/mach-lpc32xx/include/mach/hardware.h | 25 -----------------
> .../mach-lpc32xx/include/mach/uncompress.h | 4 +--
> .../{include/mach/platform.h => lpc32xx.h} | 18 ++++++++++--
> arch/arm/mach-lpc32xx/pm.c | 3 +-
> arch/arm/mach-lpc32xx/serial.c | 3 +-
> arch/arm/mach-lpc32xx/suspend.S | 3 +-
> 8 files changed, 21 insertions(+), 66 deletions(-)
> delete mode 100644 arch/arm/mach-lpc32xx/include/mach/entry-macro.S
> delete mode 100644 arch/arm/mach-lpc32xx/include/mach/hardware.h
> rename arch/arm/mach-lpc32xx/{include/mach/platform.h => lpc32xx.h} (98%)
>
> diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
> index a475339333c1..304ea61a0716 100644
> --- a/arch/arm/mach-lpc32xx/common.c
> +++ b/arch/arm/mach-lpc32xx/common.c
> @@ -13,8 +13,7 @@
> #include <asm/mach/map.h>
> #include <asm/system_info.h>
>
> -#include <mach/hardware.h>
> -#include <mach/platform.h>
> +#include "lpc32xx.h"
> #include "common.h"
>
> /*
> diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
> deleted file mode 100644
> index eec0f5f7e722..000000000000
> --- a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
> +++ /dev/null
> @@ -1,28 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-or-later */
> -/*
> - * arch/arm/mach-lpc32xx/include/mach/entry-macro.S
> - *
> - * Author: Kevin Wells <kevin.wells@nxp.com>
> - *
> - * Copyright (C) 2010 NXP Semiconductors
> - */
> -
> -#include <mach/hardware.h>
> -#include <mach/platform.h>
> -
> -#define LPC32XX_INTC_MASKED_STATUS_OFS 0x8
> -
> - .macro get_irqnr_preamble, base, tmp
> - ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
> - .endm
> -
> -/*
> - * Return IRQ number in irqnr. Also return processor Z flag status in CPSR
> - * as set if an interrupt is pending.
> - */
> - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
> - ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS]
> - clz \irqnr, \irqstat
> - rsb \irqnr, \irqnr, #31
> - teq \irqstat, #0
> - .endm
> diff --git a/arch/arm/mach-lpc32xx/include/mach/hardware.h b/arch/arm/mach-lpc32xx/include/mach/hardware.h
> deleted file mode 100644
> index 4866f096ffce..000000000000
> --- a/arch/arm/mach-lpc32xx/include/mach/hardware.h
> +++ /dev/null
> @@ -1,25 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0-or-later */
> -/*
> - * arch/arm/mach-lpc32xx/include/mach/hardware.h
> - *
> - * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
> - */
> -
> -#ifndef __ASM_ARCH_HARDWARE_H
> -#define __ASM_ARCH_HARDWARE_H
> -
> -/*
> - * Start of virtual addresses for IO devices
> - */
> -#define IO_BASE 0xF0000000
> -
> -/*
> - * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
> - */
> -#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
> - IO_BASE)
> -
> -#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
> -#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
> -
> -#endif
> diff --git a/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
> index a568812a0b91..74b7aa0da0e4 100644
> --- a/arch/arm/mach-lpc32xx/include/mach/uncompress.h
> +++ b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
> @@ -12,15 +12,13 @@
>
> #include <linux/io.h>
>
> -#include <mach/hardware.h>
> -#include <mach/platform.h>
> -
> /*
> * Uncompress output is hardcoded to standard UART 5
> */
>
> #define UART_FIFO_CTL_TX_RESET (1 << 2)
> #define UART_STATUS_TX_MT (1 << 6)
> +#define LPC32XX_UART5_BASE 0x40090000
>
> #define _UARTREG(x) (void __iomem *)(LPC32XX_UART5_BASE + (x))
>
> diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/lpc32xx.h
> similarity index 98%
> rename from arch/arm/mach-lpc32xx/include/mach/platform.h
> rename to arch/arm/mach-lpc32xx/lpc32xx.h
> index 1c53790444fc..5eeb884a1993 100644
> --- a/arch/arm/mach-lpc32xx/include/mach/platform.h
> +++ b/arch/arm/mach-lpc32xx/lpc32xx.h
> @@ -7,8 +7,8 @@
> * Copyright (C) 2010 NXP Semiconductors
> */
>
> -#ifndef __ASM_ARCH_PLATFORM_H
> -#define __ASM_ARCH_PLATFORM_H
> +#ifndef __ARM_LPC32XX_H
> +#define __ARM_LPC32XX_H
>
> #define _SBF(f, v) ((v) << (f))
> #define _BIT(n) _SBF(n, 1)
> @@ -700,4 +700,18 @@
> #define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1)
> #define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0)
>
> +/*
> + * Start of virtual addresses for IO devices
> + */
> +#define IO_BASE 0xF0000000
> +
> +/*
> + * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
> + */
> +#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
> + IO_BASE)
> +
> +#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
> +#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
> +
> #endif
> diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
> index 32bca351a73b..b27fa1b9f56c 100644
> --- a/arch/arm/mach-lpc32xx/pm.c
> +++ b/arch/arm/mach-lpc32xx/pm.c
> @@ -70,8 +70,7 @@
>
> #include <asm/cacheflush.h>
>
> -#include <mach/hardware.h>
> -#include <mach/platform.h>
> +#include "lpc32xx.h"
> #include "common.h"
>
> #define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)
> diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
> index cfb35e5691cd..3e765c4bf986 100644
> --- a/arch/arm/mach-lpc32xx/serial.c
> +++ b/arch/arm/mach-lpc32xx/serial.c
> @@ -16,8 +16,7 @@
> #include <linux/clk.h>
> #include <linux/io.h>
>
> -#include <mach/hardware.h>
> -#include <mach/platform.h>
> +#include "lpc32xx.h"
> #include "common.h"
>
> #define LPC32XX_SUART_FIFO_SIZE 64
> diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S
> index 374f9f07fe48..3f0a8282ef6f 100644
> --- a/arch/arm/mach-lpc32xx/suspend.S
> +++ b/arch/arm/mach-lpc32xx/suspend.S
> @@ -11,8 +11,7 @@
> */
> #include <linux/linkage.h>
> #include <asm/assembler.h>
> -#include <mach/platform.h>
> -#include <mach/hardware.h>
> +#include "lpc32xx.h"
>
> /* Using named register defines makes the code easier to follow */
> #define WORK1_REG r0
> --
> 2.20.0
>
^ permalink raw reply
* Re: [PATCH v7 01/20] pinctrl: tegra: Add suspend and resume support
From: Sowjanya Komatineni @ 2019-08-06 21:51 UTC (permalink / raw)
To: Linus Walleij
Cc: thierry.reding@gmail.com, Jon Hunter, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Stefan Agner, Mark Rutland,
Peter De Schrijver, Prashant Gaikwad, Stephen Boyd, linux-clk,
open list:GPIO SUBSYSTEM, jckuo, Joseph Lo, talho, linux-tegra,
linux-kernel@vger.kernel.org, Mikko Perttunen, spatra,
Rob Herring, Dmitry Osipenko,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Rafael J. Wysocki, viresh kumar, Linux PM list
In-Reply-To: <CACRpkdZVR-i1c5eATL2hSPbLXcX1sR8NgXwa4j259XXUi57xug@mail.gmail.com>
On 8/5/19 2:20 AM, Linus Walleij wrote:
> On Wed, Jul 31, 2019 at 11:11 PM Sowjanya Komatineni
> <skomatineni@nvidia.com> wrote:
>
>> This patch adds support for Tegra pinctrl driver suspend and resume.
>>
>> During suspend, context of all pinctrl registers are stored and
>> on resume they are all restored to have all the pinmux and pad
>> configuration for normal operation.
>>
>> Acked-by: Thierry Reding <treding@nvidia.com>
>> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> Patch applied to the pinctrl tree.
>
> This patch seems finished.
>
> Also if the rest don't get merged for v5.4 then at least this is so
> your patch stack gets more shallow.
>
> I hope it's fine to merge this separately, else tell me and I'll
> pull it out.
>
> Yours,
> Linus Walleij
Yes, this patch can be merged separately. But, there's latest feedback
from Dmitry to add barrier after writes to make sure pinmux register
writes happen.
So will update this patch to add barrier in v8. So, need to wait for v8.
Thanks
Sowjanya
^ permalink raw reply
* Re: [PATCH v7 01/20] pinctrl: tegra: Add suspend and resume support
From: Sowjanya Komatineni @ 2019-08-06 21:54 UTC (permalink / raw)
To: Dmitry Osipenko, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree, rjw, viresh.kumar, linux-pm
In-Reply-To: <36351140-afd4-38c4-3722-4ee0894287fa@gmail.com>
On 8/6/19 10:59 AM, Dmitry Osipenko wrote:
> 05.08.2019 21:06, Sowjanya Komatineni пишет:
>> On 8/5/19 3:50 AM, Dmitry Osipenko wrote:
>>> 01.08.2019 0:10, Sowjanya Komatineni пишет:
>>>> This patch adds support for Tegra pinctrl driver suspend and resume.
>>>>
>>>> During suspend, context of all pinctrl registers are stored and
>>>> on resume they are all restored to have all the pinmux and pad
>>>> configuration for normal operation.
>>>>
>>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>>> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>> ---
>>>> drivers/pinctrl/tegra/pinctrl-tegra.c | 59
>>>> +++++++++++++++++++++++++++++++++++
>>>> drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++
>>>> 2 files changed, 62 insertions(+)
>>>>
>>>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c
>>>> b/drivers/pinctrl/tegra/pinctrl-tegra.c
>>>> index 186ef98e7b2b..e3a237534281 100644
>>>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
>>>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
>>>> @@ -631,6 +631,58 @@ static void
>>>> tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
>>>> }
>>>> }
>>>> +static size_t tegra_pinctrl_get_bank_size(struct device *dev,
>>>> + unsigned int bank_id)
>>>> +{
>>>> + struct platform_device *pdev = to_platform_device(dev);
>>>> + struct resource *res;
>>>> +
>>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id);
>>>> +
>>>> + return resource_size(res) / 4;
>>>> +}
>>>> +
>>>> +static int tegra_pinctrl_suspend(struct device *dev)
>>>> +{
>>>> + struct tegra_pmx *pmx = dev_get_drvdata(dev);
>>>> + u32 *backup_regs = pmx->backup_regs;
>>>> + u32 *regs;
>>>> + size_t bank_size;
>>>> + unsigned int i, k;
>>>> +
>>>> + for (i = 0; i < pmx->nbanks; i++) {
>>>> + bank_size = tegra_pinctrl_get_bank_size(dev, i);
>>>> + regs = pmx->regs[i];
>>>> + for (k = 0; k < bank_size; k++)
>>>> + *backup_regs++ = readl_relaxed(regs++);
>>>> + }
>>>> +
>>>> + return pinctrl_force_sleep(pmx->pctl);
>>>> +}
>>>> +
>>>> +static int tegra_pinctrl_resume(struct device *dev)
>>>> +{
>>>> + struct tegra_pmx *pmx = dev_get_drvdata(dev);
>>>> + u32 *backup_regs = pmx->backup_regs;
>>>> + u32 *regs;
>>>> + size_t bank_size;
>>>> + unsigned int i, k;
>>>> +
>>>> + for (i = 0; i < pmx->nbanks; i++) {
>>>> + bank_size = tegra_pinctrl_get_bank_size(dev, i);
>>>> + regs = pmx->regs[i];
>>>> + for (k = 0; k < bank_size; k++)
>>>> + writel_relaxed(*backup_regs++, regs++);
>>>> + }
>>> I'm now curious whether any kind of barrier is needed after the
>>> writings. The pmx_writel() doesn't insert a barrier after the write and
>>> seems it just misuses writel, which actually should be writel_relaxed()
>>> + barrier, IIUC.
>> pmx_writel uses writel and it has wmb before raw_write which complete
>> all writes initiated prior to this.
>>
>> By misusing writel, you mean to have barrier after register write?
> Yes, at least to me it doesn't make much sense for this driver to stall
> before the write. It's the pinctrl user which should be taking care
> about everything to be ready before making a change to the pinctrl's
> configuration.
>
>>> It's also not obvious whether PINCTRL HW has any kind of write-FIFO and
>>> thus maybe read-back + rmb() is needed in order ensure that writes are
>>> actually completed.
>> I believe adding write barrier wmb after writel_relaxed should be good
>> rather than doing readback + rmb
>>> The last thing which is not obvious is when the new configuration
>>> actually takes into effect, does it happen immediately or maybe some
>>> delay is needed?
>>>
>>> [snip]
>> Based on internal design there is no internal delay and it all depends
>> on APB rate that it takes to write to register.
>>
>> Pinmux value change to reflect internally might take couple of clock
>> cycles which is much faster than SW can read.
> Still not quite obvious if it's possible to have a case where some
> hardware is touched before necessary pinctrl change is fully completed
> and then to get into trouble because of it.
To be safer, will add write barrier after all writes in resume and also
will have separate patch for pmx_writel fix to use writel_relaxed
followed by write barrier.
Thanks
Sowjanya
^ permalink raw reply
* Re: [pinctrl:devel 16/46] drivers/pinctrl/bcm/pinctrl-bcm2835.c:995:10: error: incompatible types when assigning to type 'volatile struct SHIFTER' from type 'unsigned int'
From: Michael Schmitz @ 2019-08-06 22:41 UTC (permalink / raw)
To: Geert Uytterhoeven, kbuild test robot
Cc: Stefan Wahren, kbuild-all, open list:GPIO SUBSYSTEM,
Linus Walleij, linux-m68k
In-Reply-To: <CAMuHMdU1djc8-c1LvNLFyFa0eH9C3k8nxjN_6F40S43mYZH7Hw@mail.gmail.com>
Hi Geert,
could be renamed shifter_st, I suppose. Only used in
arch/m68k/atari/config.c and drivers/video/fbdev/atafb.c.
Cheers,
Michael
On 6/08/19 7:33 PM, Geert Uytterhoeven wrote:
> CC linux-m68k (shifter too generic a name?)
>
> On Tue, Aug 6, 2019 at 5:00 AM kbuild test robot <lkp@intel.com> wrote:
>> tree: https://kernel.googlesource.com/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
>> head: d55b7fdd58ac12e76ef65979af4a13b9c15fc00d
>> commit: e38a9a437fb93ddafab5030165e4c6a3a5021669 [16/46] pinctrl: bcm2835: Add support for BCM2711 pull-up functionality
>> config: m68k-allmodconfig (attached as .config)
>> compiler: m68k-linux-gcc (GCC) 7.4.0
>> reproduce:
>> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
>> chmod +x ~/bin/make.cross
>> git checkout e38a9a437fb93ddafab5030165e4c6a3a5021669
>> # save the attached .config to linux build tree
>> GCC_VERSION=7.4.0 make.cross ARCH=m68k
>>
>> If you fix the issue, kindly add following tag
>> Reported-by: kbuild test robot <lkp@intel.com>
>>
>> All error/warnings (new ones prefixed by >>):
>>
>> In file included from arch/m68k/include/asm/io_mm.h:32:0,
>> from arch/m68k/include/asm/io.h:8,
>> from include/linux/io.h:13,
>> from include/linux/irq.h:20,
>> from include/linux/gpio/driver.h:7,
>> from drivers/pinctrl/bcm/pinctrl-bcm2835.c:17:
>> drivers/pinctrl/bcm/pinctrl-bcm2835.c: In function 'bcm2711_pull_config_set':
>>>> arch/m68k/include/asm/atarihw.h:190:22: error: expected identifier or '(' before 'volatile'
>> # define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
>> ^
>>>> drivers/pinctrl/bcm/pinctrl-bcm2835.c:990:6: note: in expansion of macro 'shifter'
>> u32 shifter;
>> ^~~~~~~
>>>> arch/m68k/include/asm/atarihw.h:172:17: error: expected ')' before '(' token
>> #define SHF_BAS (0xffff8200)
>> ^
>>>> arch/m68k/include/asm/atarihw.h:190:48: note: in expansion of macro 'SHF_BAS'
>> # define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
>> ^~~~~~~
>>>> drivers/pinctrl/bcm/pinctrl-bcm2835.c:990:6: note: in expansion of macro 'shifter'
>> u32 shifter;
>> ^~~~~~~
>>>> drivers/pinctrl/bcm/pinctrl-bcm2835.c:995:10: error: incompatible types when assigning to type 'volatile struct SHIFTER' from type 'unsigned int'
>> shifter = PUD_2711_REG_SHIFT(pin);
>> ^
>>>> drivers/pinctrl/bcm/pinctrl-bcm2835.c:998:27: error: invalid operands to binary << (have 'int' and 'volatile struct SHIFTER')
>> value &= ~(PUD_2711_MASK << shifter);
>> ^~
>>>> drivers/pinctrl/bcm/pinctrl-bcm2835.c:999:16: error: invalid operands to binary << (have 'unsigned int' and 'volatile struct SHIFTER')
>> value |= (arg << shifter);
>> ^~
>> --
>> In file included from arch/m68k/include/asm/io_mm.h:32:0,
>> from arch/m68k/include/asm/io.h:8,
>> from include/linux/io.h:13,
>> from include/linux/irq.h:20,
>> from include/linux/gpio/driver.h:7,
>> from drivers/pinctrl//bcm/pinctrl-bcm2835.c:17:
>> drivers/pinctrl//bcm/pinctrl-bcm2835.c: In function 'bcm2711_pull_config_set':
>>>> arch/m68k/include/asm/atarihw.h:190:22: error: expected identifier or '(' before 'volatile'
>> # define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
>> ^
>> drivers/pinctrl//bcm/pinctrl-bcm2835.c:990:6: note: in expansion of macro 'shifter'
>> u32 shifter;
>> ^~~~~~~
>>>> arch/m68k/include/asm/atarihw.h:172:17: error: expected ')' before '(' token
>> #define SHF_BAS (0xffff8200)
>> ^
>>>> arch/m68k/include/asm/atarihw.h:190:48: note: in expansion of macro 'SHF_BAS'
>> # define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
>> ^~~~~~~
>> drivers/pinctrl//bcm/pinctrl-bcm2835.c:990:6: note: in expansion of macro 'shifter'
>> u32 shifter;
>> ^~~~~~~
>> drivers/pinctrl//bcm/pinctrl-bcm2835.c:995:10: error: incompatible types when assigning to type 'volatile struct SHIFTER' from type 'unsigned int'
>> shifter = PUD_2711_REG_SHIFT(pin);
>> ^
>> drivers/pinctrl//bcm/pinctrl-bcm2835.c:998:27: error: invalid operands to binary << (have 'int' and 'volatile struct SHIFTER')
>> value &= ~(PUD_2711_MASK << shifter);
>> ^~
>> drivers/pinctrl//bcm/pinctrl-bcm2835.c:999:16: error: invalid operands to binary << (have 'unsigned int' and 'volatile struct SHIFTER')
>> value |= (arg << shifter);
>> ^~
>>
>> vim +995 drivers/pinctrl/bcm/pinctrl-bcm2835.c
>>
>> ---
>> 0-DAY kernel test infrastructure Open Source Technology Center
>> https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply
* [PATCH] pinctrl: aspeed: g6: Remove const specifier from aspeed_g6_sig_expr_set's ctx parameter
From: Nathan Chancellor @ 2019-08-07 0:30 UTC (permalink / raw)
To: Andrew Jeffery, Linus Walleij
Cc: Joel Stanley, linux-aspeed, openbmc, linux-gpio, linux-arm-kernel,
linux-kernel, clang-built-linux, Nathan Chancellor
clang errors:
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2325:9: error: incompatible
pointer types initializing 'int (*)(struct aspeed_pinmux_data *, const
struct aspeed_sig_expr *, bool)' with an expression of type 'int (const
struct aspeed_pinmux_data *, const struct aspeed_sig_expr *, bool)'
[-Werror,-Wincompatible-pointer-types]
.set = aspeed_g6_sig_expr_set,
^~~~~~~~~~~~~~~~~~~~~~
1 error generated.
Commit 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps")
changed the set function pointer declaration and the g6 one wasn't
updated (I assume because it wasn't merged yet).
Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support")
Link: https://github.com/ClangBuiltLinux/linux/issues/632
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
---
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
index 6012d7d4a22a..648ddb7f038a 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
@@ -2267,7 +2267,7 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = {
* Return: 0 if the expression is configured as requested and a negative error
* code otherwise
*/
-static int aspeed_g6_sig_expr_set(const struct aspeed_pinmux_data *ctx,
+static int aspeed_g6_sig_expr_set(struct aspeed_pinmux_data *ctx,
const struct aspeed_sig_expr *expr,
bool enable)
{
--
2.23.0.rc1
^ permalink raw reply related
* Re: [PATCH] pinctrl: aspeed: g6: Remove const specifier from aspeed_g6_sig_expr_set's ctx parameter
From: Andrew Jeffery @ 2019-08-07 0:36 UTC (permalink / raw)
To: Nathan Chancellor, Linus Walleij
Cc: Joel Stanley, linux-aspeed, openbmc, linux-gpio, linux-arm-kernel,
linux-kernel, clang-built-linux
In-Reply-To: <20190807003037.48457-1-natechancellor@gmail.com>
On Wed, 7 Aug 2019, at 10:02, Nathan Chancellor wrote:
> clang errors:
>
> drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2325:9: error: incompatible
> pointer types initializing 'int (*)(struct aspeed_pinmux_data *, const
> struct aspeed_sig_expr *, bool)' with an expression of type 'int (const
> struct aspeed_pinmux_data *, const struct aspeed_sig_expr *, bool)'
> [-Werror,-Wincompatible-pointer-types]
> .set = aspeed_g6_sig_expr_set,
> ^~~~~~~~~~~~~~~~~~~~~~
> 1 error generated.
>
> Commit 674fa8daa8c9 ("pinctrl: aspeed-g5: Delay acquisition of regmaps")
> changed the set function pointer declaration and the g6 one wasn't
> updated (I assume because it wasn't merged yet).
>
> Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support")
> Link: https://github.com/ClangBuiltLinux/linux/issues/632
> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
That's exactly what happened. Thanks.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
^ permalink raw reply
* [PATCH v3] gpio: mpc8xxx: Add new platforms GPIO DT node description
From: Hui Song @ 2019-08-07 2:12 UTC (permalink / raw)
To: Shawn Guo, Li Yang, Rob Herring, Mark Rutland, Linus Walleij,
Bartosz Golaszewski
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-gpio, Song Hui
From: Song Hui <hui.song_1@nxp.com>
Update the NXP GPIO node dt-binding file for QorIQ and
Layerscape platforms, and add one more example with
ls1028a GPIO node.
Signed-off-by: Song Hui <hui.song_1@nxp.com>
---
Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt
index 69d4616..baf95d9 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-mpc8xxx.txt
@@ -4,7 +4,7 @@ Required properties:
- compatible : Should be "fsl,<soc>-gpio"
The following <soc>s are known to be supported:
mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq,
- ls1021a, ls1043a, ls2080a.
+ ls1021a, ls1043a, ls2080a, ls1028a.
- reg : Address and length of the register set for the device
- interrupts : Should be the port interrupt shared by all 32 pins.
- #gpio-cells : Should be two. The first cell is the pin number and
@@ -37,3 +37,17 @@ gpio0: gpio@2300000 {
interrupt-controller;
#interrupt-cells = <2>;
};
+
+
+Example of gpio-controller node for a ls1028a SoC:
+
+gpio1: gpio@2300000 {
+ compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ little-endian;
+};
--
2.9.5
^ permalink raw reply related
* RE: [PATCH RFC 5/7] pwm: rcar: remove a redundant condition in rcar_pwm_apply()
From: Yoshihiro Shimoda @ 2019-08-07 2:56 UTC (permalink / raw)
To: Uwe Kleine-König, Geert Uytterhoeven
Cc: Linus Walleij, Geert Uytterhoeven, Thierry Reding, Rob Herring,
Mark Rutland, open list:GPIO SUBSYSTEM, Linux PWM List,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas
In-Reply-To: <20190806160007.mqwzixddhzejbmcb@pengutronix.de>
Hello,
> From: Uwe Kleine-König, Sent: Wednesday, August 7, 2019 1:00 AM
>
> Hello,
>
> On Tue, Aug 06, 2019 at 11:05:30AM +0200, Geert Uytterhoeven wrote:
> > On Mon, Jul 8, 2019 at 11:08 AM Yoshihiro Shimoda
> > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > Since the rcar_pwm_apply() has already check whehter state->enabled
> > > is not set or not, this patch removes a redundant condition.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> >
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > This is completely independent from the rest of the series, and can be applied
> > immediately, right?
>
> The original patch didn't make it into my mailbox. I only see a few
> replies. Is it only me?
> https://patchwork.ozlabs.org/project/linux-pwm/list/ doesn't seem to
> have it either.
I don't know why but, linux-renesas-soc ML only got the patch series.
https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=143129
JFYI, but I submitted another patch yesterday, and it seemed to be archived on all MLs:
https://www.spinics.net/lists/stable/msg322085.html
https://lkml.org/lkml/2019/8/6/274
https://patchwork.kernel.org/patch/11078469/
Best regards,
Yoshihiro Shimoda
> Best regards
> Uwe
>
> --
> Pengutronix e.K. | Uwe Kleine-König |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* Re: [PATCH v7 01/20] pinctrl: tegra: Add suspend and resume support
From: Sowjanya Komatineni @ 2019-08-07 3:40 UTC (permalink / raw)
To: Linus Walleij
Cc: thierry.reding@gmail.com, Jon Hunter, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Stefan Agner, Mark Rutland,
Peter De Schrijver, Prashant Gaikwad, Stephen Boyd, linux-clk,
open list:GPIO SUBSYSTEM, jckuo, Joseph Lo, talho, linux-tegra,
linux-kernel@vger.kernel.org, Mikko Perttunen, spatra,
Rob Herring, Dmitry Osipenko,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Rafael J. Wysocki, viresh kumar, Linux PM list
In-Reply-To: <a2fb3795-5ec1-1d03-f496-f151d1270e90@nvidia.com>
On 8/6/19 2:51 PM, Sowjanya Komatineni wrote:
>
> On 8/5/19 2:20 AM, Linus Walleij wrote:
>> On Wed, Jul 31, 2019 at 11:11 PM Sowjanya Komatineni
>> <skomatineni@nvidia.com> wrote:
>>
>>> This patch adds support for Tegra pinctrl driver suspend and resume.
>>>
>>> During suspend, context of all pinctrl registers are stored and
>>> on resume they are all restored to have all the pinmux and pad
>>> configuration for normal operation.
>>>
>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> Patch applied to the pinctrl tree.
>>
>> This patch seems finished.
>>
>> Also if the rest don't get merged for v5.4 then at least this is so
>> your patch stack gets more shallow.
>>
>> I hope it's fine to merge this separately, else tell me and I'll
>> pull it out.
>>
>> Yours,
>> Linus Walleij
>
> Yes, this patch can be merged separately. But, there's latest feedback
> from Dmitry to add barrier after writes to make sure pinmux register
> writes happen.
>
> So will update this patch to add barrier in v8. So, need to wait for v8.
>
> Thanks
>
> Sowjanya
>
I see it merged. So will exclude suspend/resume patch and will add patch
for necessary write barrier fix in v8 version.
Thanks
Sowjanya
^ permalink raw reply
* Re: [PATCH RFC 5/7] pwm: rcar: remove a redundant condition in rcar_pwm_apply()
From: Uwe Kleine-König @ 2019-08-07 6:33 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: linus.walleij, geert+renesas, thierry.reding, robh+dt,
mark.rutland, linux-gpio, linux-pwm, devicetree,
linux-renesas-soc
In-Reply-To: <1562576868-8124-6-git-send-email-yoshihiro.shimoda.uh@renesas.com>
Hello,
On Mon, Jul 08, 2019 at 06:07:46PM +0900, Yoshihiro Shimoda wrote:
> Since the rcar_pwm_apply() has already check whehter state->enabled
> is not set or not, this patch removes a redundant condition.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
This patch (and also patch 6 of this series) doesn't seem to have made
it to the pwm list and pwm patchwork.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* Re: [pinctrl:devel 16/46] drivers/pinctrl/bcm/pinctrl-bcm2835.c:995:10: error: incompatible types when assigning to type 'volatile struct SHIFTER' from type 'unsigned int'
From: Geert Uytterhoeven @ 2019-08-07 6:50 UTC (permalink / raw)
To: Michael Schmitz
Cc: kbuild test robot, Stefan Wahren, kbuild-all,
open list:GPIO SUBSYSTEM, Linus Walleij, linux-m68k
In-Reply-To: <848e57bf-41a6-3e3e-6e72-3c15acd76902@gmail.com>
Hi Michael,
On Wed, Aug 7, 2019 at 12:41 AM Michael Schmitz <schmitzmic@gmail.com> wrote:
> could be renamed shifter_st, I suppose. Only used in
> arch/m68k/atari/config.c and drivers/video/fbdev/atafb.c.
Yeah, exactly my thought.
> On 6/08/19 7:33 PM, Geert Uytterhoeven wrote:
> > CC linux-m68k (shifter too generic a name?)
> >
> > On Tue, Aug 6, 2019 at 5:00 AM kbuild test robot <lkp@intel.com> wrote:
> >> tree: https://kernel.googlesource.com/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
> >> head: d55b7fdd58ac12e76ef65979af4a13b9c15fc00d
> >> commit: e38a9a437fb93ddafab5030165e4c6a3a5021669 [16/46] pinctrl: bcm2835: Add support for BCM2711 pull-up functionality
> >> config: m68k-allmodconfig (attached as .config)
> >> compiler: m68k-linux-gcc (GCC) 7.4.0
> >> reproduce:
> >> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> >> chmod +x ~/bin/make.cross
> >> git checkout e38a9a437fb93ddafab5030165e4c6a3a5021669
> >> # save the attached .config to linux build tree
> >> GCC_VERSION=7.4.0 make.cross ARCH=m68k
> >>
> >> If you fix the issue, kindly add following tag
> >> Reported-by: kbuild test robot <lkp@intel.com>
> >>
> >> All error/warnings (new ones prefixed by >>):
> >>
> >> In file included from arch/m68k/include/asm/io_mm.h:32:0,
> >> from arch/m68k/include/asm/io.h:8,
> >> from include/linux/io.h:13,
> >> from include/linux/irq.h:20,
> >> from include/linux/gpio/driver.h:7,
> >> from drivers/pinctrl/bcm/pinctrl-bcm2835.c:17:
> >> drivers/pinctrl/bcm/pinctrl-bcm2835.c: In function 'bcm2711_pull_config_set':
> >>>> arch/m68k/include/asm/atarihw.h:190:22: error: expected identifier or '(' before 'volatile'
> >> # define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
> >> ^
> >>>> drivers/pinctrl/bcm/pinctrl-bcm2835.c:990:6: note: in expansion of macro 'shifter'
> >> u32 shifter;
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH RFC 6/7] pwm: rcar: Add gpio support to output duty zero
From: Uwe Kleine-König @ 2019-08-07 7:03 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: linus.walleij, geert+renesas, thierry.reding, robh+dt,
mark.rutland, linux-gpio, linux-pwm, devicetree,
linux-renesas-soc
In-Reply-To: <1562576868-8124-7-git-send-email-yoshihiro.shimoda.uh@renesas.com>
Hello,
On Mon, Jul 08, 2019 at 06:07:47PM +0900, Yoshihiro Shimoda wrote:
> The R-Car SoCs PWM Timer cannot output duty zero. So, this patch
> adds gpio support to output it.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> ---
> drivers/pwm/pwm-rcar.c | 36 ++++++++++++++++++++++++++++++++++--
> 1 file changed, 34 insertions(+), 2 deletions(-)
I'd like to see a paragraph at the top of the driver describing the
limitations of this driver similar to what pwm-sifive.c does.
Something like:
diff --git a/drivers/pwm/pwm-rcar.c b/drivers/pwm/pwm-rcar.c
index 5b2b8ecc354c..b67ac84db834 100644
--- a/drivers/pwm/pwm-rcar.c
+++ b/drivers/pwm/pwm-rcar.c
@@ -3,6 +3,9 @@
* R-Car PWM Timer driver
*
* Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * Limitations:
+ * - The hardware cannot generate a 0% duty cycle.
*/
#include <linux/clk.h>
While at it: If there is a publicly available reference manual adding a line:
Reference Manual: https://...
would be great, too.
> diff --git a/drivers/pwm/pwm-rcar.c b/drivers/pwm/pwm-rcar.c
> index c8cd43f..1c19a8b 100644
> --- a/drivers/pwm/pwm-rcar.c
> +++ b/drivers/pwm/pwm-rcar.c
> @@ -7,6 +7,7 @@
>
> #include <linux/clk.h>
> #include <linux/err.h>
> +#include <linux/gpio/consumer.h>
> #include <linux/io.h>
> #include <linux/log2.h>
> #include <linux/math64.h>
> @@ -38,6 +39,7 @@ struct rcar_pwm_chip {
> struct pwm_chip chip;
> void __iomem *base;
> struct clk *clk;
> + struct gpio_desc *gpio;
> };
>
> static inline struct rcar_pwm_chip *to_rcar_pwm_chip(struct pwm_chip *chip)
> @@ -119,8 +121,11 @@ static int rcar_pwm_set_counter(struct rcar_pwm_chip *rp, int div, int duty_ns,
> ph = tmp & RCAR_PWMCNT_PH0_MASK;
>
> /* Avoid prohibited setting */
> - if (cyc == 0 || ph == 0)
> + if (cyc == 0)
> return -EINVAL;
> + /* Try to use GPIO to output duty zero */
> + if (ph == 0)
> + return -EAGAIN;
If there is no gpio requesting cyc=0 should still yield an error.
> rcar_pwm_write(rp, cyc | ph, RCAR_PWMCNT);
>
> @@ -157,6 +162,28 @@ static void rcar_pwm_disable(struct rcar_pwm_chip *rp)
> rcar_pwm_update(rp, RCAR_PWMCR_EN0, 0, RCAR_PWMCR);
> }
>
> +static int rcar_pwm_gpiod_get(struct rcar_pwm_chip *rp)
> +{
> + if (rp->gpio)
> + return 0;
> +
> + rp->gpio = gpiod_get(rp->chip.dev, "renesas,duty-zero", GPIOD_OUT_LOW);
> + if (!IS_ERR(rp->gpio))
> + return 0;
> +
> + rp->gpio = NULL;
> + return -EINVAL;
Please use gpiod_get_optional() instead of open coding it.
Does getting the gpio automatically switch the pinmuxing?
If yes, this is IMHO a really surprising mis-feature of the gpio
subsystem. I'd prefer to "get" the gpio at probe time and only switch
the pinmuxing in .apply(). This makes .apply() quicker, ensures that all
resources necessary for pwm operation are available, handles
-EPROBE_DEFER (and maybe other errors) correctly.
Note you're introducing a bug here because switching to gpio doesn't
ensure that the currently running period is completed.
> +static void rcar_pwm_gpiod_put(struct rcar_pwm_chip *rp)
> +{
> + if (!rp->gpio)
> + return;
> +
> + gpiod_put(rp->gpio);
> + rp->gpio = NULL;
> +}
> +
> static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> struct pwm_state *state)
> {
> @@ -171,6 +198,7 @@ static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
>
> if (!state->enabled) {
> rcar_pwm_disable(rp);
> + rcar_pwm_gpiod_put(rp);
From the framework's POV disabling a PWM is quite similar to duty cycle
0. Assuming disabling the PWM completes the currently running period[1]
it might be better and easier to disable instead of switching to gpio.
(Further assuming that disable really yields the inactive level which is
should and is another limitation if not.)
> return 0;
> }
>
> @@ -187,8 +215,12 @@ static int rcar_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> /* The SYNC should be set to 0 even if rcar_pwm_set_counter failed */
> rcar_pwm_update(rp, RCAR_PWMCR_SYNC, 0, RCAR_PWMCR);
>
> - if (!ret)
> + if (!ret) {
> ret = rcar_pwm_enable(rp);
> + rcar_pwm_gpiod_put(rp);
> + } else if (ret == -EAGAIN) {
> + ret = rcar_pwm_gpiod_get(rp);
> + }
>
> return ret;
> }
Best regards
Uwe
[1] if not, please add "Disabling doesn't complete the currently running
period" to the list of limitations.
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply related
* [PATCH] pinctrl: rza1: Use devm_platform_ioremap_resource() helper
From: Geert Uytterhoeven @ 2019-08-07 8:51 UTC (permalink / raw)
To: Linus Walleij
Cc: Jacopo Mondi, Chris Brandt, linux-renesas-soc, linux-gpio,
Geert Uytterhoeven
Use the devm_platform_ioremap_resource() helper instead of open-coding
the same operation.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
To be queued in sh-pfc-for-v5.4.
drivers/pinctrl/pinctrl-rza1.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c
index 021e37b7689e4fda..68aeefe29144822f 100644
--- a/drivers/pinctrl/pinctrl-rza1.c
+++ b/drivers/pinctrl/pinctrl-rza1.c
@@ -1359,7 +1359,6 @@ static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl)
static int rza1_pinctrl_probe(struct platform_device *pdev)
{
struct rza1_pinctrl *rza1_pctl;
- struct resource *res;
int ret;
rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL);
@@ -1368,8 +1367,7 @@ static int rza1_pinctrl_probe(struct platform_device *pdev)
rza1_pctl->dev = &pdev->dev;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- rza1_pctl->base = devm_ioremap_resource(&pdev->dev, res);
+ rza1_pctl->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(rza1_pctl->base))
return PTR_ERR(rza1_pctl->base);
--
2.17.1
^ permalink raw reply related
* Re: [PATCH v3] gpio: mpc8xxx: Add new platforms GPIO DT node description
From: Linus Walleij @ 2019-08-07 12:38 UTC (permalink / raw)
To: Hui Song
Cc: Shawn Guo, Li Yang, Rob Herring, Mark Rutland,
Bartosz Golaszewski, Linux ARM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org, open list:GPIO SUBSYSTEM
In-Reply-To: <20190807021254.49092-1-hui.song_1@nxp.com>
On Wed, Aug 7, 2019 at 4:22 AM Hui Song <hui.song_1@nxp.com> wrote:
> From: Song Hui <hui.song_1@nxp.com>
>
> Update the NXP GPIO node dt-binding file for QorIQ and
> Layerscape platforms, and add one more example with
> ls1028a GPIO node.
>
> Signed-off-by: Song Hui <hui.song_1@nxp.com>
Patch applied!
Thanks,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v3 1/2] dt-bindings: pinctrl: qcom: Add SC7180 pinctrl binding
From: Linus Walleij @ 2019-08-07 12:43 UTC (permalink / raw)
To: Rajendra Nayak
Cc: Bjorn Andersson, MSM, Andy Gross, Rob Herring,
open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org, Jitendra Sharma, Vivek Gautam,
Vinod Koul
In-Reply-To: <20190806060536.18094-1-rnayak@codeaurora.org>
On Tue, Aug 6, 2019 at 8:05 AM Rajendra Nayak <rnayak@codeaurora.org> wrote:
> From: Jitendra Sharma <shajit@codeaurora.org>
>
> Add the binding for the TLMM pinctrl block found in the SC7180 platform
>
> Signed-off-by: Jitendra Sharma <shajit@codeaurora.org>
> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
> [rnayak: Fix some copy-paste issues, sort and fix functions]
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Reviewed-by: Vinod Koul <vkoul@kernel.org>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v3 2/2] pinctrl: qcom: Add SC7180 pinctrl driver
From: Linus Walleij @ 2019-08-07 12:44 UTC (permalink / raw)
To: Rajendra Nayak
Cc: Bjorn Andersson, MSM, Andy Gross, Rob Herring,
open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org, Jitendra Sharma, Vivek Gautam,
Vinod Koul
In-Reply-To: <20190806060536.18094-2-rnayak@codeaurora.org>
On Tue, Aug 6, 2019 at 8:05 AM Rajendra Nayak <rnayak@codeaurora.org> wrote:
> From: Jitendra Sharma <shajit@codeaurora.org>
>
> Add initial pinctrl driver to support pin configuration with
> pinctrl framework for SC7180
>
> Signed-off-by: Jitendra Sharma <shajit@codeaurora.org>
> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
> [rnayak: modify to use upstream tile support
> sort and squash some functions]
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Reviewed-by: Vinod Koul <vkoul@kernel.org>
Patch applied!
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 0/3] CP115 pinctrl support
From: Linus Walleij @ 2019-08-07 12:47 UTC (permalink / raw)
To: Miquel Raynal
Cc: Rob Herring, Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Thomas Petazzoni, Gregory Clement, Antoine Tenart,
Maxime Chevallier, Nadav Haklai, open list:GPIO SUBSYSTEM,
Linux ARM, Grzegorz Jaszczyk, Marcin Wojtas, Stefan Chulski,
Yan Markman
In-Reply-To: <20190805101607.29811-1-miquel.raynal@bootlin.com>
On Mon, Aug 5, 2019 at 12:16 PM Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> This is the second batch of changes (out of three) to support the brand
> new Marvell CN9130 SoCs which are made of one AP807 and one CP115.
>
> We add a new compatible (and the relevant support in the pinctrl
> driver) before the addition in batch 3/3 of CN9130 SoCs DT using it.
Waiting for review from the Mvebu maintainers.
If it takes too long just nudge me, it looks good to me.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v7 01/20] pinctrl: tegra: Add suspend and resume support
From: Linus Walleij @ 2019-08-07 13:11 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: thierry.reding@gmail.com, Jon Hunter, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Stefan Agner, Mark Rutland,
Peter De Schrijver, Prashant Gaikwad, Stephen Boyd, linux-clk,
open list:GPIO SUBSYSTEM, jckuo, Joseph Lo, talho, linux-tegra,
linux-kernel@vger.kernel.org, Mikko Perttunen, spatra,
Rob Herring, Dmitry Osipenko,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Rafael J. Wysocki, viresh kumar, Linux PM list
In-Reply-To: <dadf0cc7-fba4-9ab5-6ac9-0c8699eb4401@nvidia.com>
On Wed, Aug 7, 2019 at 5:40 AM Sowjanya Komatineni
<skomatineni@nvidia.com> wrote:
> On 8/6/19 2:51 PM, Sowjanya Komatineni wrote:
> >
> > On 8/5/19 2:20 AM, Linus Walleij wrote:
> >> On Wed, Jul 31, 2019 at 11:11 PM Sowjanya Komatineni
> >> <skomatineni@nvidia.com> wrote:
> >>
> >>> This patch adds support for Tegra pinctrl driver suspend and resume.
> >>>
> >>> During suspend, context of all pinctrl registers are stored and
> >>> on resume they are all restored to have all the pinmux and pad
> >>> configuration for normal operation.
> >>>
> >>> Acked-by: Thierry Reding <treding@nvidia.com>
> >>> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
> >>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> >> Patch applied to the pinctrl tree.
> >>
> >> This patch seems finished.
> >>
> >> Also if the rest don't get merged for v5.4 then at least this is so
> >> your patch stack gets more shallow.
> >>
> >> I hope it's fine to merge this separately, else tell me and I'll
> >> pull it out.
> >>
> >> Yours,
> >> Linus Walleij
> >
> > Yes, this patch can be merged separately. But, there's latest feedback
> > from Dmitry to add barrier after writes to make sure pinmux register
> > writes happen.
> >
> > So will update this patch to add barrier in v8. So, need to wait for v8.
> >
> > Thanks
> >
> > Sowjanya
> >
> I see it merged. So will exclude suspend/resume patch and will add patch
> for necessary write barrier fix in v8 version.
Yeah just make an incremental patch, that's fine.
If you want to overdo it you can add a Fixes: tag to
the original patch, but I don't care much.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 0/4] gpio: hierarchical IRQ improvements
From: Linus Walleij @ 2019-08-07 13:41 UTC (permalink / raw)
To: Brian Masney
Cc: open list:GPIO SUBSYSTEM, Bartosz Golaszewski, Thomas Gleixner,
Marc Zyngier, Lina Iyer, Jon Hunter, Sowjanya Komatineni,
Bitan Biswas, linux-tegra, David Daney, Masahiro Yamada,
Thierry Reding, Bjorn Andersson, Andy Gross, MSM,
linux-kernel@vger.kernel.org
In-Reply-To: <20190708110138.24657-1-masneyb@onstation.org>
On Mon, Jul 8, 2019 at 1:01 PM Brian Masney <masneyb@onstation.org> wrote:
> This builds on top of Linus Walleij's existing patches that adds
> hierarchical IRQ support to the GPIO core [1] so that Qualcomm's
> spmi-gpio and ssbi-gpio can be converted to use these new helpers.
>
> Linus: Feel free to squash these into your existing patches if you'd
> like to use any of this code. Just give me some kind of mention in the
> commit description.
>
> [1] https://lore.kernel.org/linux-gpio/20190624132531.6184-1-linus.walleij@linaro.org/
>
> Brian Masney (4):
> gpio: introduce gpiochip_populate_parent_fwspec_{two,four}cell
> functions
> gpio: allow customizing hierarchical IRQ chips
> gpio: use handler in gpio_irq_chip instead of handle_bad_irq
> qcom: spmi-gpio: convert to hierarchical IRQ helpers in gpio core
I solved things like this:
- I kept patches 1 & 4 as-is
- I squashed patches 2 and 3 into the main patch with minor modifications.
- I added Co-developed-by: for your contributions
Now I need to address Masahiro's comments on top and let's see if the
result looks acceptable!
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v2] pinctrl: intel: Use NSEC_PER_USEC for debounce calculus
From: Andy Shevchenko @ 2019-08-07 13:41 UTC (permalink / raw)
To: Linus Walleij, linux-gpio, Mika Westerberg; +Cc: Andy Shevchenko
Replace hard coded constants with self-explanatory names, i.e.
use NSEC_PER_USEC for debounce calculus.
While here, add a unit suffix to debounce period constant.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
v2: Replace suffix NS -> NSEC (Mika)
drivers/pinctrl/intel/pinctrl-intel.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
index 335b08d7d609..899afb988fcf 100644
--- a/drivers/pinctrl/intel/pinctrl-intel.c
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -8,12 +8,13 @@
*/
#include <linux/acpi.h>
-#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/gpio/driver.h>
#include <linux/log2.h>
+#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/property.h>
+#include <linux/time.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
@@ -71,7 +72,7 @@
#define PADCFG2_DEBOUNCE_SHIFT 1
#define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
-#define DEBOUNCE_PERIOD 31250 /* ns */
+#define DEBOUNCE_PERIOD_NSEC 31250
struct intel_pad_context {
u32 padcfg0;
@@ -566,7 +567,7 @@ static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
return -EINVAL;
v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
- arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
+ arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
break;
}
@@ -683,7 +684,7 @@ static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
if (debounce) {
unsigned long v;
- v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
+ v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
if (v < 3 || v > 15) {
ret = -EINVAL;
goto exit_unlock;
--
2.20.1
^ permalink raw reply related
* Re: [PATCH 0/4] gpio: hierarchical IRQ improvements
From: Linus Walleij @ 2019-08-07 13:43 UTC (permalink / raw)
To: Brian Masney
Cc: open list:GPIO SUBSYSTEM, Bartosz Golaszewski, Thomas Gleixner,
Marc Zyngier, Lina Iyer, Jon Hunter, Sowjanya Komatineni,
Bitan Biswas, linux-tegra, David Daney, Masahiro Yamada,
Thierry Reding, Bjorn Andersson, Andy Gross, MSM,
linux-kernel@vger.kernel.org
In-Reply-To: <CACRpkdYQhyh1BW789OcxGTomMkC3e8hMr8sodbWz-z1=5s9fDw@mail.gmail.com>
On Wed, Aug 7, 2019 at 3:41 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> On Mon, Jul 8, 2019 at 1:01 PM Brian Masney <masneyb@onstation.org> wrote:
>
> > This builds on top of Linus Walleij's existing patches that adds
> > hierarchical IRQ support to the GPIO core [1] so that Qualcomm's
> > spmi-gpio and ssbi-gpio can be converted to use these new helpers.
> >
> > Linus: Feel free to squash these into your existing patches if you'd
> > like to use any of this code. Just give me some kind of mention in the
> > commit description.
> >
> > [1] https://lore.kernel.org/linux-gpio/20190624132531.6184-1-linus.walleij@linaro.org/
> >
> > Brian Masney (4):
> > gpio: introduce gpiochip_populate_parent_fwspec_{two,four}cell
> > functions
> > gpio: allow customizing hierarchical IRQ chips
> > gpio: use handler in gpio_irq_chip instead of handle_bad_irq
> > qcom: spmi-gpio: convert to hierarchical IRQ helpers in gpio core
>
> I solved things like this:
>
> - I kept patches 1 & 4 as-is
Ooops had to squash patch 1 as well...
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v2] pinctrl: intel: Use NSEC_PER_USEC for debounce calculus
From: Mika Westerberg @ 2019-08-07 13:50 UTC (permalink / raw)
To: Andy Shevchenko; +Cc: Linus Walleij, linux-gpio
In-Reply-To: <20190807134150.13492-1-andriy.shevchenko@linux.intel.com>
On Wed, Aug 07, 2019 at 04:41:50PM +0300, Andy Shevchenko wrote:
> Replace hard coded constants with self-explanatory names, i.e.
> use NSEC_PER_USEC for debounce calculus.
>
> While here, add a unit suffix to debounce period constant.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
^ permalink raw reply
* Re: [PATCH 0/4] gpio: hierarchical IRQ improvements
From: Brian Masney @ 2019-08-07 14:07 UTC (permalink / raw)
To: Linus Walleij
Cc: open list:GPIO SUBSYSTEM, Bartosz Golaszewski, Thomas Gleixner,
Marc Zyngier, Lina Iyer, Jon Hunter, Sowjanya Komatineni,
Bitan Biswas, linux-tegra, David Daney, Masahiro Yamada,
Thierry Reding, Bjorn Andersson, Andy Gross, MSM,
linux-kernel@vger.kernel.org
In-Reply-To: <CACRpkdYQhyh1BW789OcxGTomMkC3e8hMr8sodbWz-z1=5s9fDw@mail.gmail.com>
On Wed, Aug 07, 2019 at 03:41:05PM +0200, Linus Walleij wrote:
> On Mon, Jul 8, 2019 at 1:01 PM Brian Masney <masneyb@onstation.org> wrote:
>
> > This builds on top of Linus Walleij's existing patches that adds
> > hierarchical IRQ support to the GPIO core [1] so that Qualcomm's
> > spmi-gpio and ssbi-gpio can be converted to use these new helpers.
> >
> > Linus: Feel free to squash these into your existing patches if you'd
> > like to use any of this code. Just give me some kind of mention in the
> > commit description.
> >
> > [1] https://lore.kernel.org/linux-gpio/20190624132531.6184-1-linus.walleij@linaro.org/
> >
> > Brian Masney (4):
> > gpio: introduce gpiochip_populate_parent_fwspec_{two,four}cell
> > functions
> > gpio: allow customizing hierarchical IRQ chips
> > gpio: use handler in gpio_irq_chip instead of handle_bad_irq
> > qcom: spmi-gpio: convert to hierarchical IRQ helpers in gpio core
>
> I solved things like this:
>
> - I kept patches 1 & 4 as-is
> - I squashed patches 2 and 3 into the main patch with minor modifications.
> - I added Co-developed-by: for your contributions
>
> Now I need to address Masahiro's comments on top and let's see if the
> result looks acceptable!
> Ooops had to squash patch 1 as well...
All of this sounds good. I'll retest once you send out the updated
series.
Brian
^ permalink raw reply
* Re: [PATCH 1/4 v1] gpio: Add support for hierarchical IRQ domains
From: Linus Walleij @ 2019-08-07 14:43 UTC (permalink / raw)
To: Masahiro Yamada
Cc: open list:GPIO SUBSYSTEM, Bartosz Golaszewski, Thomas Gleixner,
Marc Zyngier, Lina Iyer, Jon Hunter, Sowjanya Komatineni,
Bitan Biswas, linux-tegra, David Daney, Brian Masney,
Thierry Reding
In-Reply-To: <CAK7LNASX2c6=X7P_qn31MgsgSdiYL7m+fD2wmk5_tn6o+1YJSw@mail.gmail.com>
Hi Masahiro,
On Thu, Jul 18, 2019 at 1:12 PM Masahiro Yamada
<yamada.masahiro@socionext.com> wrote:
> On Mon, Jun 24, 2019 at 10:25 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> > +static int gpiochip_hierarchy_irq_domain_alloc(struct irq_domain *d,
> > + unsigned int irq,
> > + unsigned int nr_irqs,
> > + void *data)
> > +{
> > + struct gpio_chip *gc = d->host_data;
> > + irq_hw_number_t hwirq;
> > + unsigned int type = IRQ_TYPE_NONE;
> > + struct irq_fwspec *fwspec = data;
> > + int ret;
> > + int i;
>
> We always expect nr_irqs is 1.
>
> As gpio-uniphier.c, you can error out with WARN_ON
> if nr_irqs != 1
Hm, yes I am pretty sure it is always 1.
But I'd like to defer changing this until/if Marc changes
the signature of the function to not pass nr_irqs anymore.
I try to design for the current prototype because I don't
know how e.g. ACPI works with respect to this.
> I see so many chip_info().
> I think they should be chip_dbg() or removed entirely.
I am keeping that right now as we're testing on several
different systems, so some extra debug prints should be
OK in a transitional period. We might change it into dbg
with a separate patch before the merge window.
The rest of your comments are addressed!
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 1/4 v1] gpio: Add support for hierarchical IRQ domains
From: Marc Zyngier @ 2019-08-07 15:00 UTC (permalink / raw)
To: Linus Walleij, Masahiro Yamada
Cc: open list:GPIO SUBSYSTEM, Bartosz Golaszewski, Thomas Gleixner,
Lina Iyer, Jon Hunter, Sowjanya Komatineni, Bitan Biswas,
linux-tegra, David Daney, Brian Masney, Thierry Reding
In-Reply-To: <CACRpkdYbTjQR6dDsy3WJ1w89Yyo=qfSgTheaYX8MHW5uE321sA@mail.gmail.com>
On 07/08/2019 15:43, Linus Walleij wrote:
> Hi Masahiro,
>
> On Thu, Jul 18, 2019 at 1:12 PM Masahiro Yamada
> <yamada.masahiro@socionext.com> wrote:
>> On Mon, Jun 24, 2019 at 10:25 PM Linus Walleij <linus.walleij@linaro.org> wrote:
>
>>> +static int gpiochip_hierarchy_irq_domain_alloc(struct irq_domain *d,
>>> + unsigned int irq,
>>> + unsigned int nr_irqs,
>>> + void *data)
>>> +{
>>> + struct gpio_chip *gc = d->host_data;
>>> + irq_hw_number_t hwirq;
>>> + unsigned int type = IRQ_TYPE_NONE;
>>> + struct irq_fwspec *fwspec = data;
>>> + int ret;
>>> + int i;
>>
>> We always expect nr_irqs is 1.
>>
>> As gpio-uniphier.c, you can error out with WARN_ON
>> if nr_irqs != 1
>
> Hm, yes I am pretty sure it is always 1.
>
> But I'd like to defer changing this until/if Marc changes
> the signature of the function to not pass nr_irqs anymore.
> I try to design for the current prototype because I don't
> know how e.g. ACPI works with respect to this.
nr_irqs is only here for one single case: PCI Multi-MSI, where we have
to allocate a bunch of contiguous hwirqs. In all other cases, nr_irqs is
always 1.
So yes, you can safely assume nr_irqs == 1, and WARN_ON otherwise.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
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