* Re: [PATCH 2/2 v3] pinctrl: rza2: Include the appropriate headers
From: Geert Uytterhoeven @ 2019-08-21 7:45 UTC (permalink / raw)
To: Linus Walleij
Cc: open list:GPIO SUBSYSTEM, Bartosz Golaszewski, Chris Brandt,
Geert Uytterhoeven
In-Reply-To: <20190820135955.14391-2-linus.walleij@linaro.org>
On Tue, Aug 20, 2019 at 4:00 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> This driver is implementing a GPIO driver so include
> <linux/gpio/driver.h> and not the legacy API <linux/gpio.h>.
> When testing it turns out it also relies on implicit
> inclusion of <linux/io.h> (readw etc) so make sure to
> include that as well.
>
> Cc: Chris Brandt <chris.brandt@renesas.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in sh-pfc-for-v5.4.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH 1/2 v3] pinctrl: rza2: Drop driver use of consumer flags
From: Geert Uytterhoeven @ 2019-08-21 7:44 UTC (permalink / raw)
To: Linus Walleij
Cc: open list:GPIO SUBSYSTEM, Bartosz Golaszewski, Chris Brandt,
Geert Uytterhoeven
In-Reply-To: <20190820135955.14391-1-linus.walleij@linaro.org>
On Tue, Aug 20, 2019 at 4:00 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> These flags are for consumers of GPIO lines, not for
> drivers.
>
> Cc: Chris Brandt <chris.brandt@renesas.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in sh-pfc-for-v5.4.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH] m68k: coldfire: Include the GPIO driver header
From: Geert Uytterhoeven @ 2019-08-21 7:19 UTC (permalink / raw)
To: Linus Walleij
Cc: open list:GPIO SUBSYSTEM, Bartosz Golaszewski, linux-m68k,
Greg Ungerer
In-Reply-To: <20190821070923.687-1-linus.walleij@linaro.org>
CC Greg (coldfire)
On Wed, Aug 21, 2019 at 9:09 AM Linus Walleij <linus.walleij@linaro.org> wrote:
> The Coldfire GPIO driver needs to explicitly incldue the
> GPIO driver header since it is providing a driver.
>
> Cc: Geert Uytterhoeven <geert@linux-m68k.org>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> Geert can you pick this up for m68k?
> ---
> arch/m68k/coldfire/gpio.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/m68k/coldfire/gpio.c b/arch/m68k/coldfire/gpio.c
> index a83898426127..ca26de257871 100644
> --- a/arch/m68k/coldfire/gpio.c
> +++ b/arch/m68k/coldfire/gpio.c
> @@ -9,6 +9,7 @@
> #include <linux/module.h>
> #include <linux/init.h>
> #include <linux/device.h>
> +#include <linux/gpio/driver.h>
>
> #include <linux/io.h>
> #include <asm/coldfire.h>
> --
> 2.21.0
^ permalink raw reply
* [PATCH] m68k: coldfire: Include the GPIO driver header
From: Linus Walleij @ 2019-08-21 7:09 UTC (permalink / raw)
To: linux-gpio; +Cc: Bartosz Golaszewski, Linus Walleij, Geert Uytterhoeven
The Coldfire GPIO driver needs to explicitly incldue the
GPIO driver header since it is providing a driver.
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Geert can you pick this up for m68k?
---
arch/m68k/coldfire/gpio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/m68k/coldfire/gpio.c b/arch/m68k/coldfire/gpio.c
index a83898426127..ca26de257871 100644
--- a/arch/m68k/coldfire/gpio.c
+++ b/arch/m68k/coldfire/gpio.c
@@ -9,6 +9,7 @@
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
+#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <asm/coldfire.h>
--
2.21.0
^ permalink raw reply related
* [pinctrl:for-next 59/63] drivers//pinctrl/pinctrl-st.c:1212:15: error: implicit declaration of function 'of_get_named_gpio'; did you mean 'of_get_address'?
From: kbuild test robot @ 2019-08-21 1:55 UTC (permalink / raw)
To: Linus Walleij; +Cc: kbuild-all, linux-gpio
[-- Attachment #1: Type: text/plain, Size: 8006 bytes --]
tree: https://kernel.googlesource.com/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
head: 2295f64645cbc4f9ca3002f12d1b36cff3d04ac5
commit: 712dfdaf62b6f6deb21d4c58c4e4261872b0ba9f [59/63] pinctrl: st: Include the right header
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 712dfdaf62b6f6deb21d4c58c4e4261872b0ba9f
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers//pinctrl/pinctrl-st.c: In function 'st_pctl_dt_parse_groups':
>> drivers//pinctrl/pinctrl-st.c:1212:15: error: implicit declaration of function 'of_get_named_gpio'; did you mean 'of_get_address'? [-Werror=implicit-function-declaration]
conf->pin = of_get_named_gpio(pins, pp->name, 0);
^~~~~~~~~~~~~~~~~
of_get_address
cc1: some warnings being treated as errors
vim +1212 drivers//pinctrl/pinctrl-st.c
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1157
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1158 /*
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1159 * Each pin is represented in of the below forms.
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1160 * <bank offset mux direction rt_type rt_delay rt_clk>
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1161 */
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1162 static int st_pctl_dt_parse_groups(struct device_node *np,
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1163 struct st_pctl_group *grp, struct st_pinctrl *info, int idx)
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1164 {
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1165 /* bank pad direction val altfunction */
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1166 const __be32 *list;
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1167 struct property *pp;
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1168 struct st_pinconf *conf;
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1169 struct device_node *pins;
483d70d73beaec Wen Yang 2019-04-12 1170 int i = 0, npins = 0, nr_props, ret = 0;
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1171
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1172 pins = of_get_child_by_name(np, "st,pins");
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1173 if (!pins)
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1174 return -ENODATA;
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1175
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1176 for_each_property_of_node(pins, pp) {
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1177 /* Skip those we do not want to proceed */
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1178 if (!strcmp(pp->name, "name"))
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1179 continue;
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1180
95bdb0ea3668d8 Heinrich Schuchardt 2016-11-05 1181 if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) {
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1182 npins++;
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1183 } else {
94f4e54cecaf3e Rob Herring 2018-08-27 1184 pr_warn("Invalid st,pins in %pOFn node\n", np);
483d70d73beaec Wen Yang 2019-04-12 1185 ret = -EINVAL;
483d70d73beaec Wen Yang 2019-04-12 1186 goto out_put_node;
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1187 }
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1188 }
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1189
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1190 grp->npins = npins;
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1191 grp->name = np->name;
a86854d0c599b3 Kees Cook 2018-06-12 1192 grp->pins = devm_kcalloc(info->dev, npins, sizeof(u32), GFP_KERNEL);
a86854d0c599b3 Kees Cook 2018-06-12 1193 grp->pin_conf = devm_kcalloc(info->dev,
a86854d0c599b3 Kees Cook 2018-06-12 1194 npins, sizeof(*conf), GFP_KERNEL);
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1195
483d70d73beaec Wen Yang 2019-04-12 1196 if (!grp->pins || !grp->pin_conf) {
483d70d73beaec Wen Yang 2019-04-12 1197 ret = -ENOMEM;
483d70d73beaec Wen Yang 2019-04-12 1198 goto out_put_node;
483d70d73beaec Wen Yang 2019-04-12 1199 }
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1200
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1201 /* <bank offset mux direction rt_type rt_delay rt_clk> */
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1202 for_each_property_of_node(pins, pp) {
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1203 if (!strcmp(pp->name, "name"))
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1204 continue;
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1205 nr_props = pp->length/sizeof(u32);
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1206 list = pp->value;
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1207 conf = &grp->pin_conf[i];
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1208
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1209 /* bank & offset */
1f978217a0c687 Rickard Strandqvist 2014-06-26 1210 be32_to_cpup(list++);
1f978217a0c687 Rickard Strandqvist 2014-06-26 1211 be32_to_cpup(list++);
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 @1212 conf->pin = of_get_named_gpio(pins, pp->name, 0);
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1213 conf->name = pp->name;
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1214 grp->pins[i] = conf->pin;
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1215 /* mux */
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1216 conf->altfunc = be32_to_cpup(list++);
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1217 conf->config = 0;
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1218 /* direction */
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1219 conf->config |= be32_to_cpup(list++);
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1220 /* rt_type rt_delay rt_clk */
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1221 if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) {
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1222 /* rt_type */
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1223 conf->config |= be32_to_cpup(list++);
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1224 /* rt_delay */
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1225 conf->config |= be32_to_cpup(list++);
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1226 /* rt_clk */
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1227 if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN)
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1228 conf->config |= be32_to_cpup(list++);
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1229 }
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1230 i++;
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1231 }
483d70d73beaec Wen Yang 2019-04-12 1232
483d70d73beaec Wen Yang 2019-04-12 1233 out_put_node:
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1234 of_node_put(pins);
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1235
483d70d73beaec Wen Yang 2019-04-12 1236 return ret;
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1237 }
701016c0cba594 Srinivas KANDAGATLA 2013-06-20 1238
:::::: The code at line 1212 was first introduced by commit
:::::: 701016c0cba594d5dbd26652ed1e52b0fe2926fd pinctrl: st: Add pinctrl and pinconf support.
:::::: TO: Srinivas KANDAGATLA <srinivas.kandagatla@st.com>
:::::: CC: Mark Brown <broonie@linaro.org>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 71358 bytes --]
^ permalink raw reply
* Re: [pinctrl:for-next 54/63] drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2325:9: error: initialization from incompatible pointer type
From: Andrew Jeffery @ 2019-08-21 1:09 UTC (permalink / raw)
To: kbuild test robot, Nathan Chancellor
Cc: kbuild-all, linux-gpio, Linus Walleij
In-Reply-To: <201908210839.fFMuc6Yx%lkp@intel.com>
On Wed, 21 Aug 2019, at 10:19, kbuild test robot wrote:
> tree:
> https://kernel.googlesource.com/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
> head: 2295f64645cbc4f9ca3002f12d1b36cff3d04ac5
> commit: 21b2920fb587e570b43973300a11b921c3a61d3e [54/63] pinctrl:
> aspeed: g6: Remove const specifier from aspeed_g6_sig_expr_set's ctx
> parameter
> config: arm-allmodconfig (attached as .config)
> compiler: arm-linux-gnueabi-gcc (GCC) 7.4.0
> reproduce:
> wget
> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> git checkout 21b2920fb587e570b43973300a11b921c3a61d3e
> # save the attached .config to linux build tree
> GCC_VERSION=7.4.0 make.cross ARCH=arm
>
> If you fix the issue, kindly add following tag
> Reported-by: kbuild test robot <lkp@intel.com>
>
> All errors (new ones prefixed by >>):
>
> >> drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2325:9: error:
> initialization from incompatible pointer type
> [-Werror=incompatible-pointer-types]
> .set = aspeed_g6_sig_expr_set,
> ^~~~~~~~~~~~~~~~~~~~~~
> drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2325:9: note: (near
> initialization for 'aspeed_g5_ops.set')
> cc1: some warnings being treated as errors
>
> vim +2325 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
>
> 2eda1cdec49f8a Andrew Jeffery 2019-07-11 2323
> 2eda1cdec49f8a Andrew Jeffery 2019-07-11 2324 static const struct
> aspeed_pinmux_ops aspeed_g5_ops = {
> 2eda1cdec49f8a Andrew Jeffery 2019-07-11 @2325 .set =
> aspeed_g6_sig_expr_set,
> 2eda1cdec49f8a Andrew Jeffery 2019-07-11 2326 };
> 2eda1cdec49f8a Andrew Jeffery 2019-07-11 2327
>
> :::::: The code at line 2325 was first introduced by commit
> :::::: 2eda1cdec49f8ae7878e60d1b06bd8157a95424f pinctrl: aspeed: Add
> AST2600 pinmux support
>
> :::::: TO: Andrew Jeffery <andrew@aj.id.au>
> :::::: CC: Linus Walleij <linus.walleij@linaro.org>
>
This is resolved by back-merging the pinctrl-v5.3-2 into pinctrl/devel
or pinctrl/for-next as mentioned in the thread on Nathan's patch.
Alternatively it will be fixed if pinctrl/devel is merged as is into 5.4 which
contains the change that changes the interface - patch 674fa8daa8c9
("pinctrl: aspeed-g5: Delay acquisition of regmaps").
Andrew
^ permalink raw reply
* [pinctrl:for-next 54/63] drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2325:9: error: initialization from incompatible pointer type
From: kbuild test robot @ 2019-08-21 0:48 UTC (permalink / raw)
To: Nathan Chancellor; +Cc: kbuild-all, linux-gpio, Linus Walleij, Andrew Jeffery
[-- Attachment #1: Type: text/plain, Size: 2001 bytes --]
tree: https://kernel.googlesource.com/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
head: 2295f64645cbc4f9ca3002f12d1b36cff3d04ac5
commit: 21b2920fb587e570b43973300a11b921c3a61d3e [54/63] pinctrl: aspeed: g6: Remove const specifier from aspeed_g6_sig_expr_set's ctx parameter
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 21b2920fb587e570b43973300a11b921c3a61d3e
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2325:9: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
.set = aspeed_g6_sig_expr_set,
^~~~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c:2325:9: note: (near initialization for 'aspeed_g5_ops.set')
cc1: some warnings being treated as errors
vim +2325 drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c
2eda1cdec49f8a Andrew Jeffery 2019-07-11 2323
2eda1cdec49f8a Andrew Jeffery 2019-07-11 2324 static const struct aspeed_pinmux_ops aspeed_g5_ops = {
2eda1cdec49f8a Andrew Jeffery 2019-07-11 @2325 .set = aspeed_g6_sig_expr_set,
2eda1cdec49f8a Andrew Jeffery 2019-07-11 2326 };
2eda1cdec49f8a Andrew Jeffery 2019-07-11 2327
:::::: The code at line 2325 was first introduced by commit
:::::: 2eda1cdec49f8ae7878e60d1b06bd8157a95424f pinctrl: aspeed: Add AST2600 pinmux support
:::::: TO: Andrew Jeffery <andrew@aj.id.au>
:::::: CC: Linus Walleij <linus.walleij@linaro.org>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 71394 bytes --]
^ permalink raw reply
* [v7 2/2] gpio: aspeed: Add SGPIO driver
From: Hongwei Zhang @ 2019-08-20 21:35 UTC (permalink / raw)
To: Andrew Jeffery, Linus Walleij, linux-gpio
Cc: Hongwei Zhang, Joel Stanley, linux-aspeed, Bartosz Golaszewski,
linux-kernel, linux-arm-kernel
In-Reply-To: <1564603297-1391-1-git-send-email-hongweiz@ami.com>
Hello Linus,
Thanks for your review! I just submitted v8 to the list, please help to review it again.
Since you have already merged the dt-binding document [v7 1/2], and I don't have your
update to this file, so to avoid confusion, I only include the driver code in v8.
Regards,
--Hongwei
> From: Linus Walleij <linus.walleij@linaro.org>
> Sent: Wednesday, August 14, 2019 4:09 AM
> To: Hongwei Zhang
> Cc: Andrew Jeffery; open list:GPIO SUBSYSTEM; Joel Stanley; linux-aspeed; Bartosz Golaszewski;
> linux-kernel@vger.kernel.org; Linux ARM
> Subject: Re: [v7 2/2] gpio: aspeed: Add SGPIO driver
>
> Hi Hongwei,
>
> thanks for your patch!
>
> I have now merged the bindings so you only need to respin this patch.
>
> On Wed, Jul 31, 2019 at 10:02 PM Hongwei Zhang <hongweiz@ami.com> wrote:
>
> > Add SGPIO driver support for Aspeed AST2500 SoC.
> >
> > Signed-off-by: Hongwei Zhang <hongweiz@ami.com>
> > Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
>
> I guess I need to go with this, there are some minor things I still want to be fixed:
>
> > +static void __aspeed_sgpio_set(struct gpio_chip *gc, unsigned int
> > +offset, int val)
>
> I don't like __underscore_functions because their semantic is ambiguous.
>
done, please see v8.
> Rename this something like aspeed_sgpio_commit() or whatever best fits the actual use.
>
> > +static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
> > + struct platform_device *pdev) {
> (...)
> > + rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_sgpio_irqchip,
> > + 0, handle_bad_irq, IRQ_TYPE_NONE);
> (...)
> > + gpiochip_set_chained_irqchip(&gpio->chip, &aspeed_sgpio_irqchip,
> > + gpio->irq,
> > + aspeed_sgpio_irq_handler);
>
> We do not set up chained irqchips like this anymore, sorry.
>
> I am currently rewriting all existing chained drivers to pass an initialized irqchip when registering the
> whole gpio chip.
> See drivers/gpio/TODO.
>
> Here are examples:
> https://lore.kernel.org/linux-gpio/20190811080539.15647-1-linus.walleij@linaro.org/
> https://lore.kernel.org/linux-gpio/20190812132554.18313-1-linus.walleij@linaro.org/
>
done, please see v8.
> > + /* set all SGPIO pins as input (1). */
> > + memset(gpio->dir_in, 0xff, sizeof(gpio->dir_in));
>
> Do the irqchip set-up here, before adding the gpio_chip.
>
> > + rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
> > + if (rc < 0)
> > + return rc;
> > +
> > + return aspeed_sgpio_setup_irqs(gpio, pdev);
>
> Yours,
> Linus Walleij
^ permalink raw reply
* [v8 1/1] gpio: aspeed: Add SGPIO driver
From: Hongwei Zhang @ 2019-08-20 21:05 UTC (permalink / raw)
To: Linus Walleij, Andrew Jeffery, linux-gpio
Cc: Hongwei Zhang, Joel Stanley, devicetree, linux-aspeed,
Bartosz Golaszewski, Rob Herring, linux-kernel, linux-arm-kernel
In-Reply-To: <1566335128-31498-1-git-send-email-hongweiz@ami.com>
Add SGPIO driver support for Aspeed AST2500 SoC.
Signed-off-by: Hongwei Zhang <hongweiz@ami.com>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/gpio/sgpio-aspeed.c | 533 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 533 insertions(+)
create mode 100644 drivers/gpio/sgpio-aspeed.c
diff --git a/drivers/gpio/sgpio-aspeed.c b/drivers/gpio/sgpio-aspeed.c
new file mode 100644
index 0000000..7e99860
--- /dev/null
+++ b/drivers/gpio/sgpio-aspeed.c
@@ -0,0 +1,533 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2019 American Megatrends International LLC.
+ *
+ * Author: Karthikeyan Mani <karthikeyanm@amiindia.co.in>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/hashtable.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+
+#define MAX_NR_SGPIO 80
+
+#define ASPEED_SGPIO_CTRL 0x54
+
+#define ASPEED_SGPIO_PINS_MASK GENMASK(9, 6)
+#define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16)
+#define ASPEED_SGPIO_ENABLE BIT(0)
+
+struct aspeed_sgpio {
+ struct gpio_chip chip;
+ struct clk *pclk;
+ spinlock_t lock;
+ void __iomem *base;
+ uint32_t dir_in[3];
+ int irq;
+};
+
+struct aspeed_sgpio_bank {
+ uint16_t val_regs;
+ uint16_t rdata_reg;
+ uint16_t irq_regs;
+ const char names[4][3];
+};
+
+/*
+ * Note: The "value" register returns the input value when the GPIO is
+ * configured as an input.
+ *
+ * The "rdata" register returns the output value when the GPIO is
+ * configured as an output.
+ */
+static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
+ {
+ .val_regs = 0x0000,
+ .rdata_reg = 0x0070,
+ .irq_regs = 0x0004,
+ .names = { "A", "B", "C", "D" },
+ },
+ {
+ .val_regs = 0x001C,
+ .rdata_reg = 0x0074,
+ .irq_regs = 0x0020,
+ .names = { "E", "F", "G", "H" },
+ },
+ {
+ .val_regs = 0x0038,
+ .rdata_reg = 0x0078,
+ .irq_regs = 0x003C,
+ .names = { "I", "J" },
+ },
+};
+
+enum aspeed_sgpio_reg {
+ reg_val,
+ reg_rdata,
+ reg_irq_enable,
+ reg_irq_type0,
+ reg_irq_type1,
+ reg_irq_type2,
+ reg_irq_status,
+};
+
+#define GPIO_VAL_VALUE 0x00
+#define GPIO_IRQ_ENABLE 0x00
+#define GPIO_IRQ_TYPE0 0x04
+#define GPIO_IRQ_TYPE1 0x08
+#define GPIO_IRQ_TYPE2 0x0C
+#define GPIO_IRQ_STATUS 0x10
+
+static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
+ const struct aspeed_sgpio_bank *bank,
+ const enum aspeed_sgpio_reg reg)
+{
+ switch (reg) {
+ case reg_val:
+ return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
+ case reg_rdata:
+ return gpio->base + bank->rdata_reg;
+ case reg_irq_enable:
+ return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
+ case reg_irq_type0:
+ return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
+ case reg_irq_type1:
+ return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
+ case reg_irq_type2:
+ return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
+ case reg_irq_status:
+ return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
+ default:
+ /* acturally if code runs to here, it's an error case */
+ BUG_ON(1);
+ }
+}
+
+#define GPIO_BANK(x) ((x) >> 5)
+#define GPIO_OFFSET(x) ((x) & 0x1f)
+#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
+
+static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
+{
+ unsigned int bank = GPIO_BANK(offset);
+
+ WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
+ return &aspeed_sgpio_banks[bank];
+}
+
+static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+ struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+ const struct aspeed_sgpio_bank *bank = to_bank(offset);
+ unsigned long flags;
+ enum aspeed_sgpio_reg reg;
+ bool is_input;
+ int rc = 0;
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ is_input = gpio->dir_in[GPIO_BANK(offset)] & GPIO_BIT(offset);
+ reg = is_input ? reg_val : reg_rdata;
+ rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ return rc;
+}
+
+static void sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
+{
+ struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+ const struct aspeed_sgpio_bank *bank = to_bank(offset);
+ void __iomem *addr;
+ u32 reg = 0;
+
+ addr = bank_reg(gpio, bank, reg_val);
+ reg = ioread32(addr);
+
+ if (val)
+ reg |= GPIO_BIT(offset);
+ else
+ reg &= ~GPIO_BIT(offset);
+
+ iowrite32(reg, addr);
+}
+
+static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
+{
+ struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ sgpio_set_value(gc, offset, val);
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+}
+
+static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
+{
+ struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpio->lock, flags);
+ gpio->dir_in[GPIO_BANK(offset)] |= GPIO_BIT(offset);
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ return 0;
+}
+
+static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
+{
+ struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ gpio->dir_in[GPIO_BANK(offset)] &= ~GPIO_BIT(offset);
+ sgpio_set_value(gc, offset, val);
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ return 0;
+}
+
+static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
+{
+ int dir_status;
+ struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpio->lock, flags);
+ dir_status = gpio->dir_in[GPIO_BANK(offset)] & GPIO_BIT(offset);
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ return dir_status;
+
+}
+
+static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
+ struct aspeed_sgpio **gpio,
+ const struct aspeed_sgpio_bank **bank,
+ u32 *bit, int *offset)
+{
+ struct aspeed_sgpio *internal;
+
+ *offset = irqd_to_hwirq(d);
+ internal = irq_data_get_irq_chip_data(d);
+ WARN_ON(!internal);
+
+ *gpio = internal;
+ *bank = to_bank(*offset);
+ *bit = GPIO_BIT(*offset);
+}
+
+static void aspeed_sgpio_irq_ack(struct irq_data *d)
+{
+ const struct aspeed_sgpio_bank *bank;
+ struct aspeed_sgpio *gpio;
+ unsigned long flags;
+ void __iomem *status_addr;
+ int offset;
+ u32 bit;
+
+ irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
+
+ status_addr = bank_reg(gpio, bank, reg_irq_status);
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ iowrite32(bit, status_addr);
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+}
+
+static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set)
+{
+ const struct aspeed_sgpio_bank *bank;
+ struct aspeed_sgpio *gpio;
+ unsigned long flags;
+ u32 reg, bit;
+ void __iomem *addr;
+ int offset;
+
+ irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
+ addr = bank_reg(gpio, bank, reg_irq_enable);
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ reg = ioread32(addr);
+ if (set)
+ reg |= bit;
+ else
+ reg &= ~bit;
+
+ iowrite32(reg, addr);
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+}
+
+static void aspeed_sgpio_irq_mask(struct irq_data *d)
+{
+ aspeed_sgpio_irq_set_mask(d, false);
+}
+
+static void aspeed_sgpio_irq_unmask(struct irq_data *d)
+{
+ aspeed_sgpio_irq_set_mask(d, true);
+}
+
+static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type)
+{
+ u32 type0 = 0;
+ u32 type1 = 0;
+ u32 type2 = 0;
+ u32 bit, reg;
+ const struct aspeed_sgpio_bank *bank;
+ irq_flow_handler_t handler;
+ struct aspeed_sgpio *gpio;
+ unsigned long flags;
+ void __iomem *addr;
+ int offset;
+
+ irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
+
+ switch (type & IRQ_TYPE_SENSE_MASK) {
+ case IRQ_TYPE_EDGE_BOTH:
+ type2 |= bit;
+ /* fall through */
+ case IRQ_TYPE_EDGE_RISING:
+ type0 |= bit;
+ /* fall through */
+ case IRQ_TYPE_EDGE_FALLING:
+ handler = handle_edge_irq;
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ type0 |= bit;
+ /* fall through */
+ case IRQ_TYPE_LEVEL_LOW:
+ type1 |= bit;
+ handler = handle_level_irq;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ addr = bank_reg(gpio, bank, reg_irq_type0);
+ reg = ioread32(addr);
+ reg = (reg & ~bit) | type0;
+ iowrite32(reg, addr);
+
+ addr = bank_reg(gpio, bank, reg_irq_type1);
+ reg = ioread32(addr);
+ reg = (reg & ~bit) | type1;
+ iowrite32(reg, addr);
+
+ addr = bank_reg(gpio, bank, reg_irq_type2);
+ reg = ioread32(addr);
+ reg = (reg & ~bit) | type2;
+ iowrite32(reg, addr);
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ irq_set_handler_locked(d, handler);
+
+ return 0;
+}
+
+static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
+{
+ struct gpio_chip *gc = irq_desc_get_handler_data(desc);
+ struct irq_chip *ic = irq_desc_get_chip(desc);
+ struct aspeed_sgpio *data = gpiochip_get_data(gc);
+ unsigned int i, p, girq;
+ unsigned long reg;
+
+ chained_irq_enter(ic, desc);
+
+ for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
+ const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i];
+
+ reg = ioread32(bank_reg(data, bank, reg_irq_status));
+
+ for_each_set_bit(p, ®, 32) {
+ girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
+ generic_handle_irq(girq);
+ }
+
+ }
+
+ chained_irq_exit(ic, desc);
+}
+
+static struct irq_chip aspeed_sgpio_irqchip = {
+ .name = "aspeed-sgpio",
+ .irq_ack = aspeed_sgpio_irq_ack,
+ .irq_mask = aspeed_sgpio_irq_mask,
+ .irq_unmask = aspeed_sgpio_irq_unmask,
+ .irq_set_type = aspeed_sgpio_set_type,
+};
+
+static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
+ struct platform_device *pdev)
+{
+ int rc, i;
+ const struct aspeed_sgpio_bank *bank;
+ struct gpio_irq_chip *irq;
+
+ rc = platform_get_irq(pdev, 0);
+ if (rc < 0)
+ return rc;
+
+ gpio->irq = rc;
+
+ /* Disable IRQ and clear Interrupt status registers for all SPGIO Pins. */
+ for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
+ bank = &aspeed_sgpio_banks[i];
+ /* disable irq enable bits */
+ iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable));
+ /* clear status bits */
+ iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
+ }
+
+ irq = &gpio->chip.irq;
+ irq->chip = &aspeed_sgpio_irqchip;
+ irq->handler = handle_bad_irq;
+ irq->default_type = IRQ_TYPE_NONE;
+ irq->parent_handler = aspeed_sgpio_irq_handler;
+ irq->parent_handler_data = gpio;
+ irq->parents = &gpio->irq;
+ irq->num_parents = 1;
+
+ /* set IRQ settings and Enable Interrupt */
+ for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
+ bank = &aspeed_sgpio_banks[i];
+ /* set falling or level-low irq */
+ iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0));
+ /* trigger type is edge */
+ iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1));
+ /* dual edge trigger mode. */
+ iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_type2));
+ /* enable irq */
+ iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_enable));
+ }
+
+ return 0;
+}
+
+static const struct of_device_id aspeed_sgpio_of_table[] = {
+ { .compatible = "aspeed,ast2400-sgpio" },
+ { .compatible = "aspeed,ast2500-sgpio" },
+ {}
+};
+
+MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
+
+static int __init aspeed_sgpio_probe(struct platform_device *pdev)
+{
+ struct aspeed_sgpio *gpio;
+ u32 nr_gpios, sgpio_freq, sgpio_clk_div;
+ int rc;
+ unsigned long apb_freq;
+
+ gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
+ if (!gpio)
+ return -ENOMEM;
+
+ gpio->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(gpio->base))
+ return PTR_ERR(gpio->base);
+
+ rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
+ if (rc < 0) {
+ dev_err(&pdev->dev, "Could not read ngpios property\n");
+ return -EINVAL;
+ } else if (nr_gpios > MAX_NR_SGPIO) {
+ dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: %d\n",
+ MAX_NR_SGPIO, nr_gpios);
+ return -EINVAL;
+ }
+
+ rc = of_property_read_u32(pdev->dev.of_node, "bus-frequency", &sgpio_freq);
+ if (rc < 0) {
+ dev_err(&pdev->dev, "Could not read bus-frequency property\n");
+ return -EINVAL;
+ }
+
+ gpio->pclk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(gpio->pclk)) {
+ dev_err(&pdev->dev, "devm_clk_get failed\n");
+ return PTR_ERR(gpio->pclk);
+ }
+
+ apb_freq = clk_get_rate(gpio->pclk);
+
+ /*
+ * From the datasheet,
+ * SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
+ * period = 2 * (GPIO254[31:16] + 1) / PCLK
+ * frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
+ * frequency = PCLK / (2 * (GPIO254[31:16] + 1))
+ * frequency * 2 * (GPIO254[31:16] + 1) = PCLK
+ * GPIO254[31:16] = PCLK / (frequency * 2) - 1
+ */
+ if (sgpio_freq == 0)
+ return -EINVAL;
+
+ sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;
+
+ if (sgpio_clk_div > (1 << 16) - 1)
+ return -EINVAL;
+
+ iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) |
+ FIELD_PREP(ASPEED_SGPIO_PINS_MASK, (nr_gpios / 8)) |
+ ASPEED_SGPIO_ENABLE,
+ gpio->base + ASPEED_SGPIO_CTRL);
+
+ spin_lock_init(&gpio->lock);
+
+ gpio->chip.parent = &pdev->dev;
+ gpio->chip.ngpio = nr_gpios;
+ gpio->chip.direction_input = aspeed_sgpio_dir_in;
+ gpio->chip.direction_output = aspeed_sgpio_dir_out;
+ gpio->chip.get_direction = aspeed_sgpio_get_direction;
+ gpio->chip.request = NULL;
+ gpio->chip.free = NULL;
+ gpio->chip.get = aspeed_sgpio_get;
+ gpio->chip.set = aspeed_sgpio_set;
+ gpio->chip.set_config = NULL;
+ gpio->chip.label = dev_name(&pdev->dev);
+ gpio->chip.base = -1;
+
+ /* set all SGPIO pins as input (1). */
+ memset(gpio->dir_in, 0xff, sizeof(gpio->dir_in));
+
+ aspeed_sgpio_setup_irqs(gpio, pdev);
+
+ rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
+ if (rc < 0)
+ return rc;
+
+ return 0;
+}
+
+static struct platform_driver aspeed_sgpio_driver = {
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .of_match_table = aspeed_sgpio_of_table,
+ },
+};
+
+module_platform_driver_probe(aspeed_sgpio_driver, aspeed_sgpio_probe);
+MODULE_DESCRIPTION("Aspeed Serial GPIO Driver");
+MODULE_LICENSE("GPL");
--
2.7.4
^ permalink raw reply related
* [v8] gpio: aspeed: Add SGPIO driver
From: Hongwei Zhang @ 2019-08-20 21:05 UTC (permalink / raw)
To: Andrew Jeffery, Linus Walleij, linux-gpio
Cc: Hongwei Zhang, Joel Stanley, devicetree, linux-aspeed,
Bartosz Golaszewski, Rob Herring, Mark Rutland, linux-kernel,
linux-arm-kernel
Hello,
This short series introduce dt-binding document and a driver for the
Aspeed AST2500 SGPIO controller. Please review.
[v8]: Changes between v7 and v8:
- v7 updates based on Linus' feedback
- since Linus has already merged sgpio-aspeed.txt, I only include
the driver here to avoid confusion.
[v7]: Changes between v6 and v7:
- fix missing variable 'reg' assign issue in aspeed_sgpio_set()
- v6 feedback updates
[v6]: Changes between v5 and v6:
- fix a bug in aspeed_sgpio_dir_out()
- v5 feedback updates, some comments cleanup
The related SGPM pinmux dt-binding document, dts, and pinctrl driver
updates have been accepted and merged:
_http://patchwork.ozlabs.org/patch/1110210/
Hongwei Zhang (1):
gpio: aspeed: Add SGPIO driver
drivers/gpio/sgpio-aspeed.c | 533 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 533 insertions(+)
create mode 100644 drivers/gpio/sgpio-aspeed.c
--
2.7.4
^ permalink raw reply
* [PATCH 2/2 v3] pinctrl: rza2: Include the appropriate headers
From: Linus Walleij @ 2019-08-20 13:59 UTC (permalink / raw)
To: linux-gpio
Cc: Bartosz Golaszewski, Linus Walleij, Chris Brandt,
Geert Uytterhoeven
In-Reply-To: <20190820135955.14391-1-linus.walleij@linaro.org>
This driver is implementing a GPIO driver so include
<linux/gpio/driver.h> and not the legacy API <linux/gpio.h>.
When testing it turns out it also relies on implicit
inclusion of <linux/io.h> (readw etc) so make sure to
include that as well.
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLov v2->v3:
- Fix one more instance.
- Test compile properly.
ChangeLog v1->v2:
- Remove the use of GPIOF_* consumer flags in the driver.
---
drivers/pinctrl/pinctrl-rza2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-rza2.c b/drivers/pinctrl/pinctrl-rza2.c
index b0806667e94c..3be1d833bf25 100644
--- a/drivers/pinctrl/pinctrl-rza2.c
+++ b/drivers/pinctrl/pinctrl-rza2.c
@@ -11,7 +11,8 @@
*/
#include <linux/bitops.h>
-#include <linux/gpio.h>
+#include <linux/gpio/driver.h>
+#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinmux.h>
--
2.21.0
^ permalink raw reply related
* [PATCH 1/2 v3] pinctrl: rza2: Drop driver use of consumer flags
From: Linus Walleij @ 2019-08-20 13:59 UTC (permalink / raw)
To: linux-gpio
Cc: Bartosz Golaszewski, Linus Walleij, Chris Brandt,
Geert Uytterhoeven
These flags are for consumers of GPIO lines, not for
drivers.
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v3:
- New patch for just this.
---
drivers/pinctrl/pinctrl-rza2.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rza2.c b/drivers/pinctrl/pinctrl-rza2.c
index 5b951c7422cc..b0806667e94c 100644
--- a/drivers/pinctrl/pinctrl-rza2.c
+++ b/drivers/pinctrl/pinctrl-rza2.c
@@ -115,7 +115,7 @@ static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset,
mask16 = RZA2_PDR_MASK << (pin * 2);
reg16 &= ~mask16;
- if (dir == GPIOF_DIR_IN)
+ if (dir)
reg16 |= RZA2_PDR_INPUT << (pin * 2); /* pin as input */
else
reg16 |= RZA2_PDR_OUTPUT << (pin * 2); /* pin as output */
@@ -134,18 +134,18 @@ static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK;
if (reg16 == RZA2_PDR_OUTPUT)
- return GPIOF_DIR_OUT;
+ return 0;
if (reg16 == RZA2_PDR_INPUT)
- return GPIOF_DIR_IN;
+ return 1;
/*
* This GPIO controller has a default Hi-Z state that is not input or
* output, so force the pin to input now.
*/
- rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN);
+ rza2_pin_to_gpio(priv->base, offset, 1);
- return GPIOF_DIR_IN;
+ return 1;
}
static int rza2_chip_direction_input(struct gpio_chip *chip,
@@ -153,7 +153,7 @@ static int rza2_chip_direction_input(struct gpio_chip *chip,
{
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
- rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN);
+ rza2_pin_to_gpio(priv->base, offset, 1);
return 0;
}
@@ -191,7 +191,7 @@ static int rza2_chip_direction_output(struct gpio_chip *chip,
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
rza2_chip_set(chip, offset, val);
- rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_OUT);
+ rza2_pin_to_gpio(priv->base, offset, 0);
return 0;
}
--
2.21.0
^ permalink raw reply related
* Re: [PATCH v2] pinctrl: rza2: Include the appropriate headers
From: Geert Uytterhoeven @ 2019-08-20 13:37 UTC (permalink / raw)
To: Linus Walleij
Cc: open list:GPIO SUBSYSTEM, Bartosz Golaszewski, Chris Brandt,
Geert Uytterhoeven
In-Reply-To: <20190820132548.4012-1-linus.walleij@linaro.org>
Hi Linus,
On Tue, Aug 20, 2019 at 3:25 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> This driver is implementing a GPIO driver so include
> <linux/gpio/driver.h> and not the legacy API <linux/gpio.h>.
> When testing it turns out it also relies on implicit
> inclusion of <linux/io.h> (readw etc) so make sure to
> include that as well.
>
> The GPIOF_* flags used in the driver is not for driver use,
> these are consumer flags. Replace these with literal 0/1.
Perhaps this should be extracted into a separate patch?
> Cc: Chris Brandt <chris.brandt@renesas.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> ChangeLog v1->v2:
> - Remove the use of GPIOF_* consumer flags in the driver.
Thanks for the update!
> --- a/drivers/pinctrl/pinctrl-rza2.c
> +++ b/drivers/pinctrl/pinctrl-rza2.c
> @@ -145,7 +146,7 @@ static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
> */
> rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN);
Oops:
drivers/pinctrl/pinctrl-rza2.c: In function ‘rza2_chip_get_direction’:
drivers/pinctrl/pinctrl-rza2.c:147:39: error: ‘GPIOF_DIR_IN’
undeclared (first use in this function); did you mean ‘_IOC_DIRBITS’?
What happened to your arm cross-compiler? ;-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Status of Subsystems - MICROCHIP SAMA5D2-COMPATIBLE PIOBU GPIO
From: Sebastian Duda @ 2019-08-20 13:27 UTC (permalink / raw)
To: Andrei Stefanescu
Cc: linux-arm-kernel, linux-gpio, linux-kernel, lukas.bulwahn
Hello Andrei,
in my master thesis, I'm using the association of subsystems to
maintainers/reviewers and its status given in the MAINTAINERS file.
During the research I noticed that there are several subsystems without
a status in the maintainers file. One of them is the subsystem
`MICROCHIP SAMA5D2-COMPATIBLE PIOBU GPIO` where you're mentioned as
maintainer.
Is it intended not to mention a status for your subsystems?
What is the current status of your subsystem?
Kind regards
Sebastian Duda
^ permalink raw reply
* [PATCH v2] pinctrl: rza2: Include the appropriate headers
From: Linus Walleij @ 2019-08-20 13:25 UTC (permalink / raw)
To: linux-gpio
Cc: Bartosz Golaszewski, Linus Walleij, Chris Brandt,
Geert Uytterhoeven
This driver is implementing a GPIO driver so include
<linux/gpio/driver.h> and not the legacy API <linux/gpio.h>.
When testing it turns out it also relies on implicit
inclusion of <linux/io.h> (readw etc) so make sure to
include that as well.
The GPIOF_* flags used in the driver is not for driver use,
these are consumer flags. Replace these with literal 0/1.
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v2:
- Remove the use of GPIOF_* consumer flags in the driver.
Geert: assuming you will pick this up if you're happy
with it.
---
drivers/pinctrl/pinctrl-rza2.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rza2.c b/drivers/pinctrl/pinctrl-rza2.c
index 5b951c7422cc..ecb5d7ee5078 100644
--- a/drivers/pinctrl/pinctrl-rza2.c
+++ b/drivers/pinctrl/pinctrl-rza2.c
@@ -11,7 +11,8 @@
*/
#include <linux/bitops.h>
-#include <linux/gpio.h>
+#include <linux/gpio/driver.h>
+#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinmux.h>
@@ -115,7 +116,7 @@ static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset,
mask16 = RZA2_PDR_MASK << (pin * 2);
reg16 &= ~mask16;
- if (dir == GPIOF_DIR_IN)
+ if (dir)
reg16 |= RZA2_PDR_INPUT << (pin * 2); /* pin as input */
else
reg16 |= RZA2_PDR_OUTPUT << (pin * 2); /* pin as output */
@@ -134,10 +135,10 @@ static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK;
if (reg16 == RZA2_PDR_OUTPUT)
- return GPIOF_DIR_OUT;
+ return 0;
if (reg16 == RZA2_PDR_INPUT)
- return GPIOF_DIR_IN;
+ return 1;
/*
* This GPIO controller has a default Hi-Z state that is not input or
@@ -145,7 +146,7 @@ static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
*/
rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN);
- return GPIOF_DIR_IN;
+ return 1;
}
static int rza2_chip_direction_input(struct gpio_chip *chip,
@@ -153,7 +154,7 @@ static int rza2_chip_direction_input(struct gpio_chip *chip,
{
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
- rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN);
+ rza2_pin_to_gpio(priv->base, offset, 1);
return 0;
}
@@ -191,7 +192,7 @@ static int rza2_chip_direction_output(struct gpio_chip *chip,
struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
rza2_chip_set(chip, offset, val);
- rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_OUT);
+ rza2_pin_to_gpio(priv->base, offset, 0);
return 0;
}
--
2.21.0
^ permalink raw reply related
* Re: [PATCH] pinctrl: rza2: Include the appropriate headers
From: Linus Walleij @ 2019-08-20 13:22 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: open list:GPIO SUBSYSTEM, Chris Brandt, Geert Uytterhoeven
In-Reply-To: <CAMuHMdWMA6r_-esqHUVkbMvQZs2o_BMyB_XS8UZUTrqwOMGCPw@mail.gmail.com>
On Tue, Aug 20, 2019 at 1:05 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Tue, Aug 20, 2019 at 12:44 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> > This driver is implementing a GPIO driver so include
> > <linux/gpio/driver.h> and not the legacy API <linux/gpio.h>.
> > When testing it turns out it also relies on implicit
> > inclusion of <linux/io.h> (readw etc) so make sure to
> > include that as well.
> >
> > Cc: Chris Brandt <chris.brandt@renesas.com>
> > Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> > Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> > ---
> > Geert: assuming you will pick this up if you're happy
> > with it.
>
> Unfortunately shmobile_defconfig is not happy with it:
>
> drivers/pinctrl/pinctrl-rza2.c: In function ‘rza2_pin_to_gpio’:
> drivers/pinctrl/pinctrl-rza2.c:119:13: error: ‘GPIOF_DIR_IN’
Oh drivers should not use these defines.
OK I spin a v2 fixing that too, no problem.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 0/6] arm64: dts: ti: k3-j721e: Add gpio nodes
From: Lokesh Vutla @ 2019-08-20 12:49 UTC (permalink / raw)
To: Tero Kristo, Nishanth Menon, linus.walleij
Cc: Keerthy, Rob Herring, linux-gpio, Device Tree Mailing List,
Linux ARM Mailing List
In-Reply-To: <20190809082947.30590-1-lokeshvutla@ti.com>
Tero,
On 09/08/19 1:59 PM, Lokesh Vutla wrote:
> This series adds gpio nodes for J721E SoC and enable gpio keys
> in J72E common process board.
>
> Tested Boot log: https://pastebin.ubuntu.com/p/P6QqmZYtSC/
>
> This series depends on Power-domain cells update series:
> https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=15210
Can you merge the patches 2-6?
Thanks and regards,
Lokesh
^ permalink raw reply
* [pinctrl:for-next 16/63] drivers/pinctrl/bcm/pinctrl-bcm2835.c:995:10: error: incompatible types when assigning to type 'volatile struct SHIFTER' from type 'unsigned int'
From: kbuild test robot @ 2019-08-20 11:19 UTC (permalink / raw)
To: Stefan Wahren; +Cc: kbuild-all, linux-gpio, Linus Walleij
[-- Attachment #1: Type: text/plain, Size: 5181 bytes --]
Hi Stefan,
FYI, the error/warning still remains.
tree: https://kernel.googlesource.com/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git for-next
head: 2295f64645cbc4f9ca3002f12d1b36cff3d04ac5
commit: e38a9a437fb93ddafab5030165e4c6a3a5021669 [16/63] pinctrl: bcm2835: Add support for BCM2711 pull-up functionality
config: m68k-allmodconfig (attached as .config)
compiler: m68k-linux-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout e38a9a437fb93ddafab5030165e4c6a3a5021669
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=m68k
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from arch/m68k/include/asm/io_mm.h:32:0,
from arch/m68k/include/asm/io.h:8,
from include/linux/io.h:13,
from include/linux/irq.h:20,
from include/linux/gpio/driver.h:7,
from drivers/pinctrl/bcm/pinctrl-bcm2835.c:17:
drivers/pinctrl/bcm/pinctrl-bcm2835.c: In function 'bcm2711_pull_config_set':
>> arch/m68k/include/asm/atarihw.h:190:22: error: expected identifier or '(' before 'volatile'
# define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
^
drivers/pinctrl/bcm/pinctrl-bcm2835.c:990:6: note: in expansion of macro 'shifter'
u32 shifter;
^~~~~~~
>> arch/m68k/include/asm/atarihw.h:172:17: error: expected ')' before '(' token
#define SHF_BAS (0xffff8200)
^
arch/m68k/include/asm/atarihw.h:190:48: note: in expansion of macro 'SHF_BAS'
# define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
^~~~~~~
drivers/pinctrl/bcm/pinctrl-bcm2835.c:990:6: note: in expansion of macro 'shifter'
u32 shifter;
^~~~~~~
>> drivers/pinctrl/bcm/pinctrl-bcm2835.c:995:10: error: incompatible types when assigning to type 'volatile struct SHIFTER' from type 'unsigned int'
shifter = PUD_2711_REG_SHIFT(pin);
^
>> drivers/pinctrl/bcm/pinctrl-bcm2835.c:998:27: error: invalid operands to binary << (have 'int' and 'volatile struct SHIFTER')
value &= ~(PUD_2711_MASK << shifter);
^~
>> drivers/pinctrl/bcm/pinctrl-bcm2835.c:999:16: error: invalid operands to binary << (have 'unsigned int' and 'volatile struct SHIFTER')
value |= (arg << shifter);
^~
--
In file included from arch/m68k/include/asm/io_mm.h:32:0,
from arch/m68k/include/asm/io.h:8,
from include/linux/io.h:13,
from include/linux/irq.h:20,
from include/linux/gpio/driver.h:7,
from drivers/pinctrl//bcm/pinctrl-bcm2835.c:17:
drivers/pinctrl//bcm/pinctrl-bcm2835.c: In function 'bcm2711_pull_config_set':
>> arch/m68k/include/asm/atarihw.h:190:22: error: expected identifier or '(' before 'volatile'
# define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
^
drivers/pinctrl//bcm/pinctrl-bcm2835.c:990:6: note: in expansion of macro 'shifter'
u32 shifter;
^~~~~~~
>> arch/m68k/include/asm/atarihw.h:172:17: error: expected ')' before '(' token
#define SHF_BAS (0xffff8200)
^
arch/m68k/include/asm/atarihw.h:190:48: note: in expansion of macro 'SHF_BAS'
# define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
^~~~~~~
drivers/pinctrl//bcm/pinctrl-bcm2835.c:990:6: note: in expansion of macro 'shifter'
u32 shifter;
^~~~~~~
drivers/pinctrl//bcm/pinctrl-bcm2835.c:995:10: error: incompatible types when assigning to type 'volatile struct SHIFTER' from type 'unsigned int'
shifter = PUD_2711_REG_SHIFT(pin);
^
drivers/pinctrl//bcm/pinctrl-bcm2835.c:998:27: error: invalid operands to binary << (have 'int' and 'volatile struct SHIFTER')
value &= ~(PUD_2711_MASK << shifter);
^~
drivers/pinctrl//bcm/pinctrl-bcm2835.c:999:16: error: invalid operands to binary << (have 'unsigned int' and 'volatile struct SHIFTER')
value |= (arg << shifter);
^~
vim +995 drivers/pinctrl/bcm/pinctrl-bcm2835.c
986
987 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
988 unsigned int pin, unsigned int arg)
989 {
> 990 u32 shifter;
991 u32 value;
992 u32 off;
993
994 off = PUD_2711_REG_OFFSET(pin);
> 995 shifter = PUD_2711_REG_SHIFT(pin);
996
997 value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
> 998 value &= ~(PUD_2711_MASK << shifter);
> 999 value |= (arg << shifter);
1000 bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1001 }
1002
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 50937 bytes --]
^ permalink raw reply
* [PATCH v2] pinctrl: st: Include the right header
From: Linus Walleij @ 2019-08-20 11:11 UTC (permalink / raw)
To: linux-gpio; +Cc: Linus Walleij, Patrice Chotard, Maxime Coquelin
The ST pinctrl driver wants to provode a gpio_chip but is not
including the header for this, fix the inclusion to use the right
header. <linux/of_gpio.h> has to remain as the driver is calling
of_get_named_gpio().
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Maxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v1->v2:
- Include <linux/of_gpio.h> again, the driver is indeed using
it.
- Add an explanatory comment.
---
drivers/pinctrl/pinctrl-st.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index b9688ea548da..25236b716fb3 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -12,8 +12,9 @@
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_irq.h>
-#include <linux/of_gpio.h>
+#include <linux/of_gpio.h> /* of_get_named_gpio() */
#include <linux/of_address.h>
+#include <linux/gpio/driver.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/pinctrl/pinctrl.h>
--
2.21.0
^ permalink raw reply related
* Re: [PATCH] pinctrl: rza2: Include the appropriate headers
From: Geert Uytterhoeven @ 2019-08-20 11:05 UTC (permalink / raw)
To: Linus Walleij; +Cc: open list:GPIO SUBSYSTEM, Chris Brandt, Geert Uytterhoeven
In-Reply-To: <20190820104252.8255-1-linus.walleij@linaro.org>
Hi Linus,
On Tue, Aug 20, 2019 at 12:44 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> This driver is implementing a GPIO driver so include
> <linux/gpio/driver.h> and not the legacy API <linux/gpio.h>.
> When testing it turns out it also relies on implicit
> inclusion of <linux/io.h> (readw etc) so make sure to
> include that as well.
>
> Cc: Chris Brandt <chris.brandt@renesas.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> Geert: assuming you will pick this up if you're happy
> with it.
Unfortunately shmobile_defconfig is not happy with it:
drivers/pinctrl/pinctrl-rza2.c: In function ‘rza2_pin_to_gpio’:
drivers/pinctrl/pinctrl-rza2.c:119:13: error: ‘GPIOF_DIR_IN’
undeclared (first use in this function); did you mean ‘_IOC_DIRBITS’?
drivers/pinctrl/pinctrl-rza2.c:119:13: note: each undeclared
identifier is reported only once for each function it appears in
drivers/pinctrl/pinctrl-rza2.c: In function ‘rza2_chip_get_direction’:
drivers/pinctrl/pinctrl-rza2.c:138:10: error: ‘GPIOF_DIR_OUT’
undeclared (first use in this function); did you mean ‘IOC_INOUT’?
drivers/pinctrl/pinctrl-rza2.c:141:10: error: ‘GPIOF_DIR_IN’
undeclared (first use in this function); did you mean ‘GPIOF_DIR_OUT’?
drivers/pinctrl/pinctrl-rza2.c: In function ‘rza2_chip_direction_input’:
drivers/pinctrl/pinctrl-rza2.c:157:39: error: ‘GPIOF_DIR_IN’
undeclared (first use in this function); did you mean ‘_IOC_DIRBITS’?
drivers/pinctrl/pinctrl-rza2.c: In function ‘rza2_chip_direction_output’:
drivers/pinctrl/pinctrl-rza2.c:195:39: error: ‘GPIOF_DIR_OUT’
undeclared (first use in this function); did you mean ‘IOC_INOUT’?
Are there prerequisites? It even fails on gpio/for-next.
> --- a/drivers/pinctrl/pinctrl-rza2.c
> +++ b/drivers/pinctrl/pinctrl-rza2.c
> @@ -11,7 +11,8 @@
> */
>
> #include <linux/bitops.h>
> -#include <linux/gpio.h>
> +#include <linux/gpio/driver.h>
> +#include <linux/io.h>
> #include <linux/module.h>
> #include <linux/of_device.h>
> #include <linux/pinctrl/pinmux.h>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* linusw/fixes boot: 50 boots: 1 failed, 49 passed (v5.3-rc4-4-g607ff4deb08f)
From: kernelci.org bot @ 2019-08-20 10:45 UTC (permalink / raw)
To: linux-gpio, fellows
linusw/fixes boot: 50 boots: 1 failed, 49 passed (v5.3-rc4-4-g607ff4deb08f)
Full Boot Summary: https://kernelci.org/boot/all/job/linusw/branch/fixes/kernel/v5.3-rc4-4-g607ff4deb08f/
Full Build Summary: https://kernelci.org/build/linusw/branch/fixes/kernel/v5.3-rc4-4-g607ff4deb08f/
Tree: linusw
Branch: fixes
Git Describe: v5.3-rc4-4-g607ff4deb08f
Git Commit: 607ff4deb08f986753f0b40e2d7840b61e11a46d
Git URL: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/
Tested: 35 unique boards, 15 SoC families, 3 builds out of 6
Boot Regressions Detected:
arm64:
defconfig:
gcc-8:
meson-gxm-khadas-vim2:
lab-baylibre: new failure (last pass: v5.3-rc4-3-gdf451f83e1fc)
Boot Failure Detected:
arm64:
defconfig:
gcc-8:
meson-gxm-khadas-vim2: 1 failed lab
---
For more info write to <info@kernelci.org>
^ permalink raw reply
* linusw/for-next boot: 51 boots: 1 failed, 50 passed (v5.3-rc4-40-g67d5826a3303)
From: kernelci.org bot @ 2019-08-20 10:45 UTC (permalink / raw)
To: linux-gpio, fellows
linusw/for-next boot: 51 boots: 1 failed, 50 passed (v5.3-rc4-40-g67d5826a3303)
Full Boot Summary: https://kernelci.org/boot/all/job/linusw/branch/for-next/kernel/v5.3-rc4-40-g67d5826a3303/
Full Build Summary: https://kernelci.org/build/linusw/branch/for-next/kernel/v5.3-rc4-40-g67d5826a3303/
Tree: linusw
Branch: for-next
Git Describe: v5.3-rc4-40-g67d5826a3303
Git Commit: 67d5826a3303594c16292293ffe7b180f8a87352
Git URL: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/
Tested: 35 unique boards, 15 SoC families, 3 builds out of 6
Boot Regressions Detected:
arm64:
defconfig:
gcc-8:
meson-gxm-khadas-vim2:
lab-baylibre: new failure (last pass: v5.3-rc4-35-g984078b26420)
Boot Failure Detected:
arm64:
defconfig:
gcc-8:
meson-gxm-khadas-vim2: 1 failed lab
---
For more info write to <info@kernelci.org>
^ permalink raw reply
* [PATCH] pinctrl: rza2: Include the appropriate headers
From: Linus Walleij @ 2019-08-20 10:42 UTC (permalink / raw)
To: linux-gpio; +Cc: Linus Walleij, Chris Brandt, Geert Uytterhoeven
This driver is implementing a GPIO driver so include
<linux/gpio/driver.h> and not the legacy API <linux/gpio.h>.
When testing it turns out it also relies on implicit
inclusion of <linux/io.h> (readw etc) so make sure to
include that as well.
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
Geert: assuming you will pick this up if you're happy
with it.
---
drivers/pinctrl/pinctrl-rza2.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-rza2.c b/drivers/pinctrl/pinctrl-rza2.c
index 5b951c7422cc..a39e1c35724e 100644
--- a/drivers/pinctrl/pinctrl-rza2.c
+++ b/drivers/pinctrl/pinctrl-rza2.c
@@ -11,7 +11,8 @@
*/
#include <linux/bitops.h>
-#include <linux/gpio.h>
+#include <linux/gpio/driver.h>
+#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinmux.h>
--
2.21.0
^ permalink raw reply related
* linusw/devel boot: 51 boots: 1 failed, 50 passed (v5.3-rc1-35-ga7e42142926f)
From: kernelci.org bot @ 2019-08-20 10:42 UTC (permalink / raw)
To: linux-gpio, fellows
linusw/devel boot: 51 boots: 1 failed, 50 passed (v5.3-rc1-35-ga7e42142926f)
Full Boot Summary: https://kernelci.org/boot/all/job/linusw/branch/devel/kernel/v5.3-rc1-35-ga7e42142926f/
Full Build Summary: https://kernelci.org/build/linusw/branch/devel/kernel/v5.3-rc1-35-ga7e42142926f/
Tree: linusw
Branch: devel
Git Describe: v5.3-rc1-35-ga7e42142926f
Git Commit: a7e42142926f815c776f745d027f69a53415d99c
Git URL: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/
Tested: 35 unique boards, 15 SoC families, 3 builds out of 6
Boot Regressions Detected:
arm64:
defconfig:
gcc-8:
apq8016-sbc:
lab-mhart: failing since 21 days (last pass: v5.2-10808-g9637d517347e - first fail: v5.3-rc1-5-ga299726da44f)
Boot Failure Detected:
arm64:
defconfig:
gcc-8:
apq8016-sbc: 1 failed lab
---
For more info write to <info@kernelci.org>
^ permalink raw reply
* [gpio:devel-cleanup-irqchip 47/47] drivers/pinctrl/intel/pinctrl-cherryview.c:1632:8: error: 'struct gpio_irq_chip' has no member named 'default_handler'; did you mean 'default_type'?
From: kbuild test robot @ 2019-08-20 10:37 UTC (permalink / raw)
To: Linus Walleij; +Cc: kbuild-all, linux-gpio
[-- Attachment #1: Type: text/plain, Size: 5257 bytes --]
tree: https://kernel.googlesource.com/pub/scm/linux/kernel/git/linusw/linux-gpio.git devel-cleanup-irqchip
head: cbf47c505ab7882591e402576063e8b1600978ed
commit: cbf47c505ab7882591e402576063e8b1600978ed [47/47] RFC: pinctrl: cherryview: Pass irqchip when adding gpiochip
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-10) 7.4.0
reproduce:
git checkout cbf47c505ab7882591e402576063e8b1600978ed
# save the attached .config to linux build tree
make ARCH=x86_64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/pinctrl/intel/pinctrl-cherryview.c: In function 'chv_gpio_probe':
>> drivers/pinctrl/intel/pinctrl-cherryview.c:1632:8: error: 'struct gpio_irq_chip' has no member named 'default_handler'; did you mean 'default_type'?
girq->default_handler = IRQ_TYPE_NONE;
^~~~~~~~~~~~~~~
default_type
vim +1632 drivers/pinctrl/intel/pinctrl-cherryview.c
1545
1546 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1547 {
1548 const struct chv_gpio_pinrange *range;
1549 struct gpio_chip *chip = &pctrl->chip;
1550 struct gpio_irq_chip *girq;
1551 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1552 const struct chv_community *community = pctrl->community;
1553 int ret, i, irq_base;
1554
1555 *chip = chv_gpio_chip;
1556
1557 chip->ngpio = community->pins[community->npins - 1].number + 1;
1558 chip->label = dev_name(pctrl->dev);
1559 chip->parent = pctrl->dev;
1560 chip->base = -1;
1561 chip->irq.need_valid_mask = need_valid_mask;
1562
1563 for (i = 0; i < community->ngpio_ranges; i++) {
1564 range = &community->gpio_ranges[i];
1565 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
1566 range->base, range->base,
1567 range->npins);
1568 if (ret) {
1569 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1570 return ret;
1571 }
1572 }
1573
1574 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1575 for (i = 0; i < community->npins; i++) {
1576 const struct pinctrl_pin_desc *desc;
1577 u32 intsel;
1578
1579 desc = &community->pins[i];
1580
1581 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
1582 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1583 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1584
1585 if (need_valid_mask && intsel >= community->nirqs)
1586 clear_bit(i, chip->irq.valid_mask);
1587 }
1588
1589 /*
1590 * The same set of machines in chv_no_valid_mask[] have incorrectly
1591 * configured GPIOs that generate spurious interrupts so we use
1592 * this same list to apply another quirk for them.
1593 *
1594 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
1595 */
1596 if (!need_valid_mask) {
1597 /*
1598 * Mask all interrupts the community is able to generate
1599 * but leave the ones that can only generate GPEs unmasked.
1600 */
1601 chv_writel(GENMASK(31, pctrl->community->nirqs),
1602 pctrl->regs + CHV_INTMASK);
1603 }
1604
1605 /* Clear all interrupts */
1606 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1607
1608 /*
1609 * FIXME: this picks as many IRQs as there are lines in the
1610 * "community", which is then later associated per-range below
1611 * registering the gpio_chip. This is actually hierarchical IRQ.
1612 */
1613 if (!need_valid_mask) {
1614 irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
1615 community->npins, NUMA_NO_NODE);
1616 if (irq_base < 0) {
1617 dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
1618 return irq_base;
1619 }
1620 }
1621
1622 girq = &chip->irq;
1623 girq->chip = &chv_gpio_irqchip;
1624 girq->parent_handler = chv_gpio_irq_handler;
1625 girq->num_parents = 1;
1626 girq->parents = devm_kcalloc(pctrl->dev, 1,
1627 sizeof(*girq->parents),
1628 GFP_KERNEL);
1629 if (!girq->parents)
1630 return -ENOMEM;
1631 girq->parents[0] = irq;
> 1632 girq->default_handler = IRQ_TYPE_NONE;
1633 girq->handler = handle_bad_irq;
1634
1635 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1636 if (ret) {
1637 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1638 return ret;
1639 }
1640
1641 /*
1642 * FIXME: this associates a different IRQ with each discrete range
1643 * inside the community. If we use the hierarchical irq support,
1644 * the .translate() function can do this translation for each IRQ.
1645 */
1646 if (!need_valid_mask) {
1647 for (i = 0; i < community->ngpio_ranges; i++) {
1648 range = &community->gpio_ranges[i];
1649
1650 irq_domain_associate_many(chip->irq.domain, irq_base,
1651 range->base, range->npins);
1652 irq_base += range->npins;
1653 }
1654 }
1655
1656 return 0;
1657 }
1658
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 69532 bytes --]
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