* Re: [PATCH 00/25] Rid W=1 warnings in Pinctrl
From: Linus Walleij @ 2020-07-16 13:05 UTC (permalink / raw)
To: Lee Jones; +Cc: linux-kernel@vger.kernel.org, open list:GPIO SUBSYSTEM
In-Reply-To: <20200713144930.1034632-1-lee.jones@linaro.org>
On Mon, Jul 13, 2020 at 4:49 PM Lee Jones <lee.jones@linaro.org> wrote:
> pinctrl: pinctrl-single: Fix struct/function documentation blocks
This patch didn't apply to v5.8-rc1 so I applied that one separately
after merging in all the other patches from a branch.
Seems to work! So all applied.
Also THANKS for doing this!!
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v2] [RFC] dt-bindings: gpio: introduce hog properties with less ambiguity
From: Linus Walleij @ 2020-07-16 12:57 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Bartosz Golaszewski, Rob Herring, open list:GPIO SUBSYSTEM,
Sascha Hauer,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <20200711045441.19464-1-u.kleine-koenig@pengutronix.de>
On Sat, Jul 11, 2020 at 6:54 AM Uwe Kleine-König
<u.kleine-koenig@pengutronix.de> wrote:
> For active low lines the semantic of output-low and output-high is hard
> to grasp because there is a double negation involved and so output-low
> is actually a request to drive the line high (aka inactive).
>
> So introduce output-inactive and output-active with the same semantic as
> output-low and output-high respectively have today, but with a more
> sensible name.
>
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> ---
> Hello,
>
> compared to (implicit) v1, changed to ..asserted from ...active as Linus
> Walleij suggested.
I'm fine to apply this but would prefer if I can apply it back-to-back
with a patch adding support to the kernel.
I know the bindings and the OS should be decoupled in theory
but ... feels better for me.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v3 0/3] Allow for qcom-pdc to be loadable as a module
From: Linus Walleij @ 2020-07-16 12:51 UTC (permalink / raw)
To: John Stultz
Cc: lkml, Andy Gross, Bjorn Andersson, Joerg Roedel, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Lina Iyer, Maulik Shah,
Saravana Kannan, Todd Kjos, Greg Kroah-Hartman, MSM,
list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org>, Joerg Roedel <joro@8bytes.org>,,
open list:GPIO SUBSYSTEM
In-Reply-To: <20200710231824.60699-1-john.stultz@linaro.org>
On Sat, Jul 11, 2020 at 1:18 AM John Stultz <john.stultz@linaro.org> wrote:
> This patch series provides exports and config tweaks to allow
> the qcom-pdc driver to be able to be configured as a permement
> modules (particularlly useful for the Android Generic Kernel
> Image efforts).
>
> This was part of a larger patch series, to enable qcom_scm
> driver to be a module as well, but I've split it out as there
> are some outstanding objections I still need to address with
> the follow-on patches, and wanted to see if progress could be
> made on this subset of the series in the meantime.
>
> New in v3:
> * Drop conditional usage of IRQCHIP_DECLARE as suggested by
> Stephen Boyd and Marc Zyngier
This patch set looks entirely reasonable to me.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v9 0/4] Introduce the for_each_set_clump macro
From: Linus Walleij @ 2020-07-16 12:49 UTC (permalink / raw)
To: Syed Nayyar Waris
Cc: Andy Shevchenko, William Breathitt Gray, Michal Simek,
Arnd Bergmann, Robert Richter, Bartosz Golaszewski,
Masahiro Yamada, Zhang Rui, Daniel Lezcano, Amit Kucheria,
linux-arch, open list:GPIO SUBSYSTEM,
linux-kernel@vger.kernel.org, Linux ARM, Linux PM list
In-Reply-To: <cover.1593243079.git.syednwaris@gmail.com>
Hi Syed,
sorry for taking so long. I was on vacation and a bit snowed
under by work.
On Sat, Jun 27, 2020 at 10:10 AM Syed Nayyar Waris <syednwaris@gmail.com> wrote:
> Since this patchset primarily affects GPIO drivers, would you like
> to pick it up through your GPIO tree?
I have applied the patches to an immutable branch and pushed
to kernelorg for testing (autobuilders will play with it I hope).
If all works fine I will merge this into my devel branch for v5.9.
It would be desirable if Andrew gave his explicit ACK on it too.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v1] pinctrl: intel: Add Intel Emmitsburg pin controller support
From: Andy Shevchenko @ 2020-07-16 12:42 UTC (permalink / raw)
To: Mika Westerberg, linux-gpio, Linus Walleij; +Cc: Andy Shevchenko
This driver adds pinctrl/GPIO support for Intel Emmitsburg PCH. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/intel/Kconfig | 8 +
drivers/pinctrl/intel/Makefile | 1 +
drivers/pinctrl/intel/pinctrl-emmitsburg.c | 387 +++++++++++++++++++++
3 files changed, 396 insertions(+)
create mode 100644 drivers/pinctrl/intel/pinctrl-emmitsburg.c
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index 787833e343a4..b3e6060db52d 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -95,6 +95,14 @@ config PINCTRL_DENVERTON
This pinctrl driver provides an interface that allows configuring
of Intel Denverton SoC pins and using them as GPIOs.
+config PINCTRL_EMMITSBURG
+ tristate "Intel Emmitsburg pinctrl and GPIO driver"
+ depends on ACPI
+ select PINCTRL_INTEL
+ help
+ This pinctrl driver provides an interface that allows configuring
+ of Intel Emmitsburg pins and using them as GPIOs.
+
config PINCTRL_GEMINILAKE
tristate "Intel Gemini Lake SoC pinctrl and GPIO driver"
depends on ACPI
diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile
index f6f63eb8100f..1c1c316f98b9 100644
--- a/drivers/pinctrl/intel/Makefile
+++ b/drivers/pinctrl/intel/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o
obj-$(CONFIG_PINCTRL_CEDARFORK) += pinctrl-cedarfork.o
obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o
+obj-$(CONFIG_PINCTRL_EMMITSBURG) += pinctrl-emmitsburg.o
obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o
obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o
obj-$(CONFIG_PINCTRL_JASPERLAKE) += pinctrl-jasperlake.o
diff --git a/drivers/pinctrl/intel/pinctrl-emmitsburg.c b/drivers/pinctrl/intel/pinctrl-emmitsburg.c
new file mode 100644
index 000000000000..f6114dbf7520
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-emmitsburg.c
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Intel Emmitsburg PCH pinctrl/GPIO driver
+ *
+ * Copyright (C) 2020, Intel Corporation
+ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-intel.h"
+
+#define EBG_PAD_OWN 0x0a0
+#define EBG_PADCFGLOCK 0x100
+#define EBG_HOSTSW_OWN 0x130
+#define EBG_GPI_IS 0x200
+#define EBG_GPI_IE 0x210
+
+#define EBG_GPP(r, s, e) \
+ { \
+ .reg_num = (r), \
+ .base = (s), \
+ .size = ((e) - (s) + 1), \
+ }
+
+#define EBG_COMMUNITY(b, s, e, g) \
+ { \
+ .barno = (b), \
+ .padown_offset = EBG_PAD_OWN, \
+ .padcfglock_offset = EBG_PADCFGLOCK, \
+ .hostown_offset = EBG_HOSTSW_OWN, \
+ .is_offset = EBG_GPI_IS, \
+ .ie_offset = EBG_GPI_IE, \
+ .pin_base = (s), \
+ .npins = ((e) - (s) + 1), \
+ .gpps = (g), \
+ .ngpps = ARRAY_SIZE(g), \
+ }
+
+/* Emmitsburg */
+static const struct pinctrl_pin_desc ebg_pins[] = {
+ /* GPP_A */
+ PINCTRL_PIN(0, "ESPI_ALERT0B"),
+ PINCTRL_PIN(1, "ESPI_ALERT1B"),
+ PINCTRL_PIN(2, "ESPI_IO_0"),
+ PINCTRL_PIN(3, "ESPI_IO_1"),
+ PINCTRL_PIN(4, "ESPI_IO_2"),
+ PINCTRL_PIN(5, "ESPI_IO_3"),
+ PINCTRL_PIN(6, "ESPI_CS0B"),
+ PINCTRL_PIN(7, "ESPI_CS1B"),
+ PINCTRL_PIN(8, "ESPI_RESETB"),
+ PINCTRL_PIN(9, "ESPI_CLK"),
+ PINCTRL_PIN(10, "SRCCLKREQB_0"),
+ PINCTRL_PIN(11, "SRCCLKREQB_1"),
+ PINCTRL_PIN(12, "SRCCLKREQB_2"),
+ PINCTRL_PIN(13, "SRCCLKREQB_3"),
+ PINCTRL_PIN(14, "SRCCLKREQB_4"),
+ PINCTRL_PIN(15, "SRCCLKREQB_5"),
+ PINCTRL_PIN(16, "SRCCLKREQB_6"),
+ PINCTRL_PIN(17, "SRCCLKREQB_7"),
+ PINCTRL_PIN(18, "SRCCLKREQB_8"),
+ PINCTRL_PIN(19, "SRCCLKREQB_9"),
+ PINCTRL_PIN(20, "ESPI_CLK_LOOPBK"),
+ /* GPP_B */
+ PINCTRL_PIN(21, "GSXDOUT"),
+ PINCTRL_PIN(22, "GSXSLOAD"),
+ PINCTRL_PIN(23, "GSXDIN"),
+ PINCTRL_PIN(24, "GSXSRESETB"),
+ PINCTRL_PIN(25, "GSXCLK"),
+ PINCTRL_PIN(26, "USB2_OCB_0"),
+ PINCTRL_PIN(27, "USB2_OCB_1"),
+ PINCTRL_PIN(28, "USB2_OCB_2"),
+ PINCTRL_PIN(29, "USB2_OCB_3"),
+ PINCTRL_PIN(30, "USB2_OCB_4"),
+ PINCTRL_PIN(31, "USB2_OCB_5"),
+ PINCTRL_PIN(32, "USB2_OCB_6"),
+ PINCTRL_PIN(33, "HS_UART0_RXD"),
+ PINCTRL_PIN(34, "HS_UART0_TXD"),
+ PINCTRL_PIN(35, "HS_UART0_RTSB"),
+ PINCTRL_PIN(36, "HS_UART0_CTSB"),
+ PINCTRL_PIN(37, "HS_UART1_RXD"),
+ PINCTRL_PIN(38, "HS_UART1_TXD"),
+ PINCTRL_PIN(39, "HS_UART1_RTSB"),
+ PINCTRL_PIN(40, "HS_UART1_CTSB"),
+ PINCTRL_PIN(41, "GPPC_B_20"),
+ PINCTRL_PIN(42, "GPPC_B_21"),
+ PINCTRL_PIN(43, "GPPC_B_22"),
+ PINCTRL_PIN(44, "PS_ONB"),
+ /* SPI */
+ PINCTRL_PIN(45, "SPI0_IO_2"),
+ PINCTRL_PIN(46, "SPI0_IO_3"),
+ PINCTRL_PIN(47, "SPI0_MOSI_IO_0"),
+ PINCTRL_PIN(48, "SPI0_MISO_IO_1"),
+ PINCTRL_PIN(49, "SPI0_TPM_CSB"),
+ PINCTRL_PIN(50, "SPI0_FLASH_0_CSB"),
+ PINCTRL_PIN(51, "SPI0_FLASH_1_CSB"),
+ PINCTRL_PIN(52, "SPI0_CLK"),
+ PINCTRL_PIN(53, "TIME_SYNC_0"),
+ PINCTRL_PIN(54, "SPKR"),
+ PINCTRL_PIN(55, "CPU_GP_0"),
+ PINCTRL_PIN(56, "CPU_GP_1"),
+ PINCTRL_PIN(57, "CPU_GP_2"),
+ PINCTRL_PIN(58, "CPU_GP_3"),
+ PINCTRL_PIN(59, "SUSWARNB_SUSPWRDNACK"),
+ PINCTRL_PIN(60, "SUSACKB"),
+ PINCTRL_PIN(61, "NMIB"),
+ PINCTRL_PIN(62, "SMIB"),
+ PINCTRL_PIN(63, "GPPC_S_10"),
+ PINCTRL_PIN(64, "GPPC_S_11"),
+ PINCTRL_PIN(65, "SPI_CLK_LOOPBK"),
+ /* GPP_C */
+ PINCTRL_PIN(66, "ME_SML0CLK"),
+ PINCTRL_PIN(67, "ME_SML0DATA"),
+ PINCTRL_PIN(68, "ME_SML0ALERTB"),
+ PINCTRL_PIN(69, "ME_SML0BDATA"),
+ PINCTRL_PIN(70, "ME_SML0BCLK"),
+ PINCTRL_PIN(71, "ME_SML0BALERTB"),
+ PINCTRL_PIN(72, "ME_SML1CLK"),
+ PINCTRL_PIN(73, "ME_SML1DATA"),
+ PINCTRL_PIN(74, "ME_SML1ALERTB"),
+ PINCTRL_PIN(75, "ME_SML2CLK"),
+ PINCTRL_PIN(76, "ME_SML2DATA"),
+ PINCTRL_PIN(77, "ME_SML2ALERTB"),
+ PINCTRL_PIN(78, "ME_SML3CLK"),
+ PINCTRL_PIN(79, "ME_SML3DATA"),
+ PINCTRL_PIN(80, "ME_SML3ALERTB"),
+ PINCTRL_PIN(81, "ME_SML4CLK"),
+ PINCTRL_PIN(82, "ME_SML4DATA"),
+ PINCTRL_PIN(83, "ME_SML4ALERTB"),
+ PINCTRL_PIN(84, "GPPC_C_18"),
+ PINCTRL_PIN(85, "MC_SMBCLK"),
+ PINCTRL_PIN(86, "MC_SMBDATA"),
+ PINCTRL_PIN(87, "MC_SMBALERTB"),
+ /* GPP_D */
+ PINCTRL_PIN(88, "HS_SMBCLK"),
+ PINCTRL_PIN(89, "HS_SMBDATA"),
+ PINCTRL_PIN(90, "HS_SMBALERTB"),
+ PINCTRL_PIN(91, "GBE_SMB_ALRT_N"),
+ PINCTRL_PIN(92, "GBE_SMB_CLK"),
+ PINCTRL_PIN(93, "GBE_SMB_DATA"),
+ PINCTRL_PIN(94, "GBE_GPIO10"),
+ PINCTRL_PIN(95, "GBE_GPIO11"),
+ PINCTRL_PIN(96, "CRASHLOG_TRIG_N"),
+ PINCTRL_PIN(97, "PMEB"),
+ PINCTRL_PIN(98, "BM_BUSYB"),
+ PINCTRL_PIN(99, "PLTRSTB"),
+ PINCTRL_PIN(100, "PCHHOTB"),
+ PINCTRL_PIN(101, "ADR_COMPLETE"),
+ PINCTRL_PIN(102, "ADR_TRIGGER_N"),
+ PINCTRL_PIN(103, "VRALERTB"),
+ PINCTRL_PIN(104, "ADR_ACK"),
+ PINCTRL_PIN(105, "THERMTRIP_N"),
+ PINCTRL_PIN(106, "MEMTRIP_N"),
+ PINCTRL_PIN(107, "MSMI_N"),
+ PINCTRL_PIN(108, "CATERR_N"),
+ PINCTRL_PIN(109, "GLB_RST_WARN_B"),
+ PINCTRL_PIN(110, "USB2_OCB_7"),
+ PINCTRL_PIN(111, "GPP_D_23"),
+ /* GPP_E */
+ PINCTRL_PIN(112, "SATA1_XPCIE_0"),
+ PINCTRL_PIN(113, "SATA1_XPCIE_1"),
+ PINCTRL_PIN(114, "SATA1_XPCIE_2"),
+ PINCTRL_PIN(115, "SATA1_XPCIE_3"),
+ PINCTRL_PIN(116, "SATA0_XPCIE_2"),
+ PINCTRL_PIN(117, "SATA0_XPCIE_3"),
+ PINCTRL_PIN(118, "SATA0_USB3_XPCIE_0"),
+ PINCTRL_PIN(119, "SATA0_USB3_XPCIE_1"),
+ PINCTRL_PIN(120, "SATA0_SCLOCK"),
+ PINCTRL_PIN(121, "SATA0_SLOAD"),
+ PINCTRL_PIN(122, "SATA0_SDATAOUT"),
+ PINCTRL_PIN(123, "SATA1_SCLOCK"),
+ PINCTRL_PIN(124, "SATA1_SLOAD"),
+ PINCTRL_PIN(125, "SATA1_SDATAOUT"),
+ PINCTRL_PIN(126, "SATA2_SCLOCK"),
+ PINCTRL_PIN(127, "SATA2_SLOAD"),
+ PINCTRL_PIN(128, "SATA2_SDATAOUT"),
+ PINCTRL_PIN(129, "ERR0_N"),
+ PINCTRL_PIN(130, "ERR1_N"),
+ PINCTRL_PIN(131, "ERR2_N"),
+ PINCTRL_PIN(132, "GBE_UART_RXD"),
+ PINCTRL_PIN(133, "GBE_UART_TXD"),
+ PINCTRL_PIN(134, "GBE_UART_RTSB"),
+ PINCTRL_PIN(135, "GBE_UART_CTSB"),
+ /* JTAG */
+ PINCTRL_PIN(136, "JTAG_TDO"),
+ PINCTRL_PIN(137, "JTAG_TDI"),
+ PINCTRL_PIN(138, "JTAG_TCK"),
+ PINCTRL_PIN(139, "JTAG_TMS"),
+ PINCTRL_PIN(140, "JTAGX"),
+ PINCTRL_PIN(141, "PRDYB"),
+ PINCTRL_PIN(142, "PREQB"),
+ PINCTRL_PIN(143, "GLB_PC_DISABLE"),
+ PINCTRL_PIN(144, "DBG_PMODE"),
+ PINCTRL_PIN(145, "GLB_EXT_ACC_DISABLE"),
+ /* GPP_H */
+ PINCTRL_PIN(146, "GBE_GPIO12"),
+ PINCTRL_PIN(147, "GBE_GPIO13"),
+ PINCTRL_PIN(148, "GBE_SDP_TIMESYNC0_S2N"),
+ PINCTRL_PIN(149, "GBE_SDP_TIMESYNC1_S2N"),
+ PINCTRL_PIN(150, "GBE_SDP_TIMESYNC2_S2N"),
+ PINCTRL_PIN(151, "GBE_SDP_TIMESYNC3_S2N"),
+ PINCTRL_PIN(152, "GPPC_H_6"),
+ PINCTRL_PIN(153, "GPPC_H_7"),
+ PINCTRL_PIN(154, "NCSI_CLK_IN"),
+ PINCTRL_PIN(155, "NCSI_CRS_DV"),
+ PINCTRL_PIN(156, "NCSI_RXD0"),
+ PINCTRL_PIN(157, "NCSI_RXD1"),
+ PINCTRL_PIN(158, "NCSI_TX_EN"),
+ PINCTRL_PIN(159, "NCSI_TXD0"),
+ PINCTRL_PIN(160, "NCSI_TXD1"),
+ PINCTRL_PIN(161, "NAC_NCSI_CLK_OUT_0"),
+ PINCTRL_PIN(162, "NAC_NCSI_CLK_OUT_1"),
+ PINCTRL_PIN(163, "NAC_NCSI_CLK_OUT_2"),
+ PINCTRL_PIN(164, "PMCALERTB"),
+ PINCTRL_PIN(165, "GPPC_H_19"),
+ /* GPP_J */
+ PINCTRL_PIN(166, "CPUPWRGD"),
+ PINCTRL_PIN(167, "CPU_THRMTRIP_N"),
+ PINCTRL_PIN(168, "PLTRST_CPUB"),
+ PINCTRL_PIN(169, "TRIGGER0_N"),
+ PINCTRL_PIN(170, "TRIGGER1_N"),
+ PINCTRL_PIN(171, "CPU_PWR_DEBUG_N"),
+ PINCTRL_PIN(172, "CPU_MEMTRIP_N"),
+ PINCTRL_PIN(173, "CPU_MSMI_N"),
+ PINCTRL_PIN(174, "ME_PECI"),
+ PINCTRL_PIN(175, "NAC_SPARE0"),
+ PINCTRL_PIN(176, "NAC_SPARE1"),
+ PINCTRL_PIN(177, "NAC_SPARE2"),
+ PINCTRL_PIN(178, "CPU_ERR0_N"),
+ PINCTRL_PIN(179, "CPU_CATERR_N"),
+ PINCTRL_PIN(180, "CPU_ERR1_N"),
+ PINCTRL_PIN(181, "CPU_ERR2_N"),
+ PINCTRL_PIN(182, "GPP_J_16"),
+ PINCTRL_PIN(183, "GPP_J_17"),
+ /* GPP_I */
+ PINCTRL_PIN(184, "GBE_GPIO4"),
+ PINCTRL_PIN(185, "GBE_GPIO5"),
+ PINCTRL_PIN(186, "GBE_GPIO6"),
+ PINCTRL_PIN(187, "GBE_GPIO7"),
+ PINCTRL_PIN(188, "GBE1_LED1"),
+ PINCTRL_PIN(189, "GBE1_LED2"),
+ PINCTRL_PIN(190, "GBE2_LED0"),
+ PINCTRL_PIN(191, "GBE2_LED1"),
+ PINCTRL_PIN(192, "GBE2_LED2"),
+ PINCTRL_PIN(193, "GBE3_LED0"),
+ PINCTRL_PIN(194, "GBE3_LED1"),
+ PINCTRL_PIN(195, "GBE3_LED2"),
+ PINCTRL_PIN(196, "GBE0_I2C_CLK"),
+ PINCTRL_PIN(197, "GBE0_I2C_DATA"),
+ PINCTRL_PIN(198, "GBE1_I2C_CLK"),
+ PINCTRL_PIN(199, "GBE1_I2C_DATA"),
+ PINCTRL_PIN(200, "GBE2_I2C_CLK"),
+ PINCTRL_PIN(201, "GBE2_I2C_DATA"),
+ PINCTRL_PIN(202, "GBE3_I2C_CLK"),
+ PINCTRL_PIN(203, "GBE3_I2C_DATA"),
+ PINCTRL_PIN(204, "GBE4_I2C_CLK"),
+ PINCTRL_PIN(205, "GBE4_I2C_DATA"),
+ PINCTRL_PIN(206, "GBE_GPIO8"),
+ PINCTRL_PIN(207, "GBE_GPIO9"),
+ /* GPP_L */
+ PINCTRL_PIN(208, "PM_SYNC_0"),
+ PINCTRL_PIN(209, "PM_DOWN_0"),
+ PINCTRL_PIN(210, "PM_SYNC_CLK_0"),
+ PINCTRL_PIN(211, "GPP_L_3"),
+ PINCTRL_PIN(212, "GPP_L_4"),
+ PINCTRL_PIN(213, "GPP_L_5"),
+ PINCTRL_PIN(214, "GPP_L_6"),
+ PINCTRL_PIN(215, "GPP_L_7"),
+ PINCTRL_PIN(216, "GPP_L_8"),
+ PINCTRL_PIN(217, "NAC_GBE_GPIO0_S2N"),
+ PINCTRL_PIN(218, "NAC_GBE_GPIO1_S2N"),
+ PINCTRL_PIN(219, "NAC_GBE_GPIO2_S2N"),
+ PINCTRL_PIN(220, "NAC_GBE_GPIO3_S2N"),
+ PINCTRL_PIN(221, "NAC_GBE_SMB_DATA_IN"),
+ PINCTRL_PIN(222, "NAC_GBE_SMB_DATA_OUT"),
+ PINCTRL_PIN(223, "NAC_GBE_SMB_ALRT_N"),
+ PINCTRL_PIN(224, "NAC_GBE_SMB_CLK_IN"),
+ PINCTRL_PIN(225, "NAC_GBE_SMB_CLK_OUT"),
+ /* GPP_M */
+ PINCTRL_PIN(226, "GPP_M_0"),
+ PINCTRL_PIN(227, "GPP_M_1"),
+ PINCTRL_PIN(228, "GPP_M_2"),
+ PINCTRL_PIN(229, "GPP_M_3"),
+ PINCTRL_PIN(230, "NAC_WAKE_N"),
+ PINCTRL_PIN(231, "GPP_M_5"),
+ PINCTRL_PIN(232, "GPP_M_6"),
+ PINCTRL_PIN(233, "GPP_M_7"),
+ PINCTRL_PIN(234, "GPP_M_8"),
+ PINCTRL_PIN(235, "NAC_SBLINK_S2N"),
+ PINCTRL_PIN(236, "NAC_SBLINK_N2S"),
+ PINCTRL_PIN(237, "NAC_SBLINK_CLK_N2S"),
+ PINCTRL_PIN(238, "NAC_SBLINK_CLK_S2N"),
+ PINCTRL_PIN(239, "NAC_XTAL_VALID"),
+ PINCTRL_PIN(240, "NAC_RESET_NAC_N"),
+ PINCTRL_PIN(241, "GPP_M_15"),
+ PINCTRL_PIN(242, "GPP_M_16"),
+ PINCTRL_PIN(243, "GPP_M_17"),
+ /* GPP_N */
+ PINCTRL_PIN(244, "GPP_N_0"),
+ PINCTRL_PIN(245, "NAC_NCSI_TXD0"),
+ PINCTRL_PIN(246, "GPP_N_2"),
+ PINCTRL_PIN(247, "GPP_N_3"),
+ PINCTRL_PIN(248, "NAC_NCSI_REFCLK_IN"),
+ PINCTRL_PIN(249, "GPP_N_5"),
+ PINCTRL_PIN(250, "GPP_N_6"),
+ PINCTRL_PIN(251, "GPP_N_7"),
+ PINCTRL_PIN(252, "NAC_NCSI_RXD0"),
+ PINCTRL_PIN(253, "NAC_NCSI_RXD1"),
+ PINCTRL_PIN(254, "NAC_NCSI_CRS_DV"),
+ PINCTRL_PIN(255, "NAC_NCSI_CLK_IN"),
+ PINCTRL_PIN(256, "NAC_NCSI_REFCLK_OUT"),
+ PINCTRL_PIN(257, "NAC_NCSI_TX_EN"),
+ PINCTRL_PIN(258, "NAC_NCSI_TXD1"),
+ PINCTRL_PIN(259, "NAC_NCSI_OE_N"),
+ PINCTRL_PIN(260, "NAC_GR_N"),
+ PINCTRL_PIN(261, "NAC_INIT_SX_WAKE_N"),
+};
+
+static const struct intel_padgroup ebg_community0_gpps[] = {
+ EBG_GPP(0, 0, 20), /* GPP_A */
+ EBG_GPP(1, 21, 44), /* GPP_B */
+ EBG_GPP(2, 45, 65), /* SPI */
+};
+
+static const struct intel_padgroup ebg_community1_gpps[] = {
+ EBG_GPP(0, 66, 87), /* GPP_C */
+ EBG_GPP(1, 88, 111), /* GPP_D */
+};
+
+static const struct intel_padgroup ebg_community3_gpps[] = {
+ EBG_GPP(0, 112, 135), /* GPP_E */
+ EBG_GPP(1, 136, 145), /* JTAG */
+};
+
+static const struct intel_padgroup ebg_community4_gpps[] = {
+ EBG_GPP(0, 146, 165), /* GPP_H */
+ EBG_GPP(1, 166, 183), /* GPP_J */
+};
+
+static const struct intel_padgroup ebg_community5_gpps[] = {
+ EBG_GPP(0, 184, 207), /* GPP_I */
+ EBG_GPP(1, 208, 225), /* GPP_L */
+ EBG_GPP(2, 226, 243), /* GPP_M */
+ EBG_GPP(3, 244, 261), /* GPP_N */
+};
+
+static const struct intel_community ebg_communities[] = {
+ EBG_COMMUNITY(0, 0, 65, ebg_community0_gpps),
+ EBG_COMMUNITY(1, 66, 111, ebg_community1_gpps),
+ EBG_COMMUNITY(2, 112, 145, ebg_community3_gpps),
+ EBG_COMMUNITY(3, 146, 183, ebg_community4_gpps),
+ EBG_COMMUNITY(4, 184, 261, ebg_community5_gpps),
+};
+
+static const struct intel_pinctrl_soc_data ebg_soc_data = {
+ .pins = ebg_pins,
+ .npins = ARRAY_SIZE(ebg_pins),
+ .communities = ebg_communities,
+ .ncommunities = ARRAY_SIZE(ebg_communities),
+};
+
+static const struct acpi_device_id ebg_pinctrl_acpi_match[] = {
+ { "INTC1071", (kernel_ulong_t)&ebg_soc_data },
+ { }
+};
+MODULE_DEVICE_TABLE(acpi, ebg_pinctrl_acpi_match);
+
+static INTEL_PINCTRL_PM_OPS(ebg_pinctrl_pm_ops);
+
+static struct platform_driver ebg_pinctrl_driver = {
+ .probe = intel_pinctrl_probe_by_hid,
+ .driver = {
+ .name = "emmitsburg-pinctrl",
+ .acpi_match_table = ebg_pinctrl_acpi_match,
+ .pm = &ebg_pinctrl_pm_ops,
+ },
+};
+
+module_platform_driver(ebg_pinctrl_driver);
+
+MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
+MODULE_DESCRIPTION("Intel Emmitsburg PCH pinctrl/GPIO driver");
+MODULE_LICENSE("GPL v2");
--
2.27.0
^ permalink raw reply related
* Re: [PATCH v3 2/2] dt-bindings: gpio: Add bindings for NXP PCA9570
From: Linus Walleij @ 2020-07-16 12:37 UTC (permalink / raw)
To: Sungbo Eo
Cc: Bartosz Golaszewski, Rob Herring, linux-kernel@vger.kernel.org,
open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <20200630160934.1197066-1-mans0n@gorani.run>
On Tue, Jun 30, 2020 at 6:10 PM Sungbo Eo <mans0n@gorani.run> wrote:
> This patch adds device tree bindings for the NXP PCA9570,
> a 4-bit I2C GPO expander.
>
> Signed-off-by: Sungbo Eo <mans0n@gorani.run>
> ---
> v3:
This v3 patch applied, thanks!
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v6 1/2] gpio: add GPO driver for PCA9570
From: Linus Walleij @ 2020-07-16 12:35 UTC (permalink / raw)
To: Sungbo Eo
Cc: Bartosz Golaszewski, Andy Shevchenko, Michael Walle,
linux-kernel@vger.kernel.org, open list:GPIO SUBSYSTEM
In-Reply-To: <20200709134829.216393-1-mans0n@gorani.run>
On Thu, Jul 9, 2020 at 3:48 PM Sungbo Eo <mans0n@gorani.run> wrote:
> NXP PCA9570 is a 4-bit I2C GPO expander without interrupt functionality.
> Its ports are controlled only by a data byte without register address.
>
> Datasheet: https://www.nxp.com/docs/en/data-sheet/PCA9570.pdf
> Signed-off-by: Sungbo Eo <mans0n@gorani.run>
> ---
> v6:
> * removed client
> * re-added mutex
> * removed template_chip
This v6 version applied, thanks to everyone who helped out
reviewing this driver!!
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] gpio: adnp: Use irqchip template
From: Linus Walleij @ 2020-07-16 12:03 UTC (permalink / raw)
To: linux-gpio
Cc: Bartosz Golaszewski, Linus Walleij, Roland Stigge, Lars Poeschel
This makes the driver use the irqchip template to assign
properties to the gpio_irq_chip instead of using the
explicit calls to gpiochip_irqchip_add_nested() and
gpiochip_set_nested_irqchip(). The irqchip is instead
added while adding the gpiochip.
Cc: Roland Stigge <stigge@antcom.de>
Cc: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/gpio/gpio-adnp.c | 95 ++++++++++++++++++++--------------------
1 file changed, 48 insertions(+), 47 deletions(-)
diff --git a/drivers/gpio/gpio-adnp.c b/drivers/gpio/gpio-adnp.c
index b9fcaab2a931..8eedfc6451df 100644
--- a/drivers/gpio/gpio-adnp.c
+++ b/drivers/gpio/gpio-adnp.c
@@ -238,36 +238,6 @@ static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
mutex_unlock(&adnp->i2c_lock);
}
-static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios)
-{
- struct gpio_chip *chip = &adnp->gpio;
- int err;
-
- adnp->reg_shift = get_count_order(num_gpios) - 3;
-
- chip->direction_input = adnp_gpio_direction_input;
- chip->direction_output = adnp_gpio_direction_output;
- chip->get = adnp_gpio_get;
- chip->set = adnp_gpio_set;
- chip->can_sleep = true;
-
- if (IS_ENABLED(CONFIG_DEBUG_FS))
- chip->dbg_show = adnp_gpio_dbg_show;
-
- chip->base = -1;
- chip->ngpio = num_gpios;
- chip->label = adnp->client->name;
- chip->parent = &adnp->client->dev;
- chip->of_node = chip->parent->of_node;
- chip->owner = THIS_MODULE;
-
- err = devm_gpiochip_add_data(&adnp->client->dev, chip, adnp);
- if (err)
- return err;
-
- return 0;
-}
-
static irqreturn_t adnp_irq(int irq, void *data)
{
struct adnp *adnp = data;
@@ -464,18 +434,54 @@ static int adnp_irq_setup(struct adnp *adnp)
return err;
}
- err = gpiochip_irqchip_add_nested(chip,
- &adnp_irq_chip,
- 0,
- handle_simple_irq,
- IRQ_TYPE_NONE);
- if (err) {
- dev_err(chip->parent,
- "could not connect irqchip to gpiochip\n");
- return err;
+ return 0;
+}
+
+static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios,
+ bool is_irq_controller)
+{
+ struct gpio_chip *chip = &adnp->gpio;
+ int err;
+
+ adnp->reg_shift = get_count_order(num_gpios) - 3;
+
+ chip->direction_input = adnp_gpio_direction_input;
+ chip->direction_output = adnp_gpio_direction_output;
+ chip->get = adnp_gpio_get;
+ chip->set = adnp_gpio_set;
+ chip->can_sleep = true;
+
+ if (IS_ENABLED(CONFIG_DEBUG_FS))
+ chip->dbg_show = adnp_gpio_dbg_show;
+
+ chip->base = -1;
+ chip->ngpio = num_gpios;
+ chip->label = adnp->client->name;
+ chip->parent = &adnp->client->dev;
+ chip->of_node = chip->parent->of_node;
+ chip->owner = THIS_MODULE;
+
+ if (is_irq_controller) {
+ struct gpio_irq_chip *girq;
+
+ err = adnp_irq_setup(adnp);
+ if (err)
+ return err;
+
+ girq = &chip->irq;
+ girq->chip = &adnp_irq_chip;
+ /* This will let us handle the parent IRQ in the driver */
+ girq->parent_handler = NULL;
+ girq->num_parents = 0;
+ girq->parents = NULL;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_simple_irq;
+ girq->threaded = true;
}
- gpiochip_set_nested_irqchip(chip, &adnp_irq_chip, adnp->client->irq);
+ err = devm_gpiochip_add_data(&adnp->client->dev, chip, adnp);
+ if (err)
+ return err;
return 0;
}
@@ -503,16 +509,11 @@ static int adnp_i2c_probe(struct i2c_client *client,
mutex_init(&adnp->i2c_lock);
adnp->client = client;
- err = adnp_gpio_setup(adnp, num_gpios);
+ err = adnp_gpio_setup(adnp, num_gpios,
+ of_property_read_bool(np, "interrupt-controller"));
if (err)
return err;
- if (of_find_property(np, "interrupt-controller", NULL)) {
- err = adnp_irq_setup(adnp);
- if (err)
- return err;
- }
-
i2c_set_clientdata(client, adnp);
return 0;
--
2.26.2
^ permalink raw reply related
* Re: [PATCH 1/3] dt-bindings: pinctrl: Add bindings for Actions S500 SoC
From: Cristian Ciocaltea @ 2020-07-16 10:43 UTC (permalink / raw)
To: Rob Herring
Cc: Andreas Färber, Manivannan Sadhasivam, Linus Walleij,
linux-arm-kernel, linux-gpio, devicetree, linux-kernel,
linux-actions
In-Reply-To: <20200715200309.GA722435@bogus>
On Wed, Jul 15, 2020 at 02:03:09PM -0600, Rob Herring wrote:
> On Thu, Jun 25, 2020 at 11:16:18PM +0300, Cristian Ciocaltea wrote:
> > Add pinctrl and gpio bindings for Actions Semi S500 SoC.
> >
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > ---
> > .../pinctrl/actions,s500-pinctrl.yaml | 228 ++++++++++++++++++
> > 1 file changed, 228 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml
> > new file mode 100644
> > index 000000000000..856947c70844
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml
> > @@ -0,0 +1,228 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Actions Semi S500 SoC pinmux & GPIO controller
> > +
> > +maintainers:
> > + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > +
> > +description: |
> > + Pinmux & GPIO controller manages pin multiplexing & configuration including
> > + GPIO function selection & GPIO attributes configuration. Please refer to
> > + pinctrl-bindings.txt in this directory for common binding part and usage.
> > +
> > +properties:
> > + compatible:
> > + const: actions,s500-pinctrl
> > +
> > + reg:
> > + minItems: 1
> > + maxItems: 4
>
> Need to enumerate what each register range is.
Hi Rob,
Thanks for the review!
Would the update below suffice?
reg:
description: |
Specifies the memory region(s) associated with the pin-controller.
To improve granularity, up to four register ranges can be provided:
* GPIO Output + GPIO Input + GPIO Data
* Multiplexing Control
* PAD Pull Control + PAD Schmitt Trigger enable + PAD Control
* PAD Drive Capacity Select
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + gpio-controller: true
> > +
> > + gpio-ranges:
> > + maxItems: 1
> > +
> > + '#gpio-cells':
> > + description:
> > + Specifies the pin number and flags, as defined in
> > + include/dt-bindings/gpio/gpio.h
> > + const: 2
> > +
> > + interrupt-controller: true
> > +
> > + '#interrupt-cells':
> > + description:
> > + Specifies the pin number and flags, as defined in
> > + include/dt-bindings/interrupt-controller/irq.h
> > + const: 2
> > +
> > + interrupts:
> > + description:
> > + One interrupt per each of the 5 GPIO ports supported by the controller,
> > + sorted by port number ascending order.
> > + minItems: 5
> > + maxItems: 5
> > +
> > +patternProperties:
> > + '^.*$':
> > + if:
> > + type: object
>
> For a new binding, can you do '-pins$' for the node names so we don't
> need this if/then hack.
Right, the idea was to be consistent with the existing bindings for
S700 and S900, which allow free node names, although they are not yet
converted to yaml format.
> > + then:
> > + patternProperties:
> > + 'pinmux$':
>
> Is this really a pattern? Can't tell from the example.
pinmux and pinconf subnodes may appear multiple times, that's why I
decided to match their names based on the suffix.
The example is not complex enough, I will change it to the following:
mmc0_default: mmc0_default {
pinmux {
groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
"sd0_cmd_mfp", "sd0_clk_mfp";
function = "sd0";
};
drv_pinconf {
groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv";
drive-strength = <8>;
};
bias_pinconf {
pins = "sd0_d0", "sd0_d1", "sd0_d2",
"sd0_d3", "sd0_cmd";
bias-pull-up;
};
};
> > + type: object
> > + description:
> > + Pinctrl node's client devices specify pin muxes using subnodes,
> > + which in turn use the standard properties below.
> > + $ref: pinmux-node.yaml#
> > +
> > + properties:
> > + groups:
> > + description:
> > + List of gpio pin groups affected by the functions specified in
> > + this subnode.
> > + items:
> > + oneOf:
> > + - enum: [lcd0_d18_mfp, rmii_crs_dv_mfp, rmii_txd0_mfp,
> > + rmii_txd1_mfp, rmii_txen_mfp, rmii_rxen_mfp,
> > + rmii_rxd1_mfp, rmii_rxd0_mfp, rmii_ref_clk_mfp,
> > + i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp,
> > + i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp,
> > + ks_in3_mfp, ks_out0_mfp, ks_out1_mfp, ks_out2_mfp,
> > + lvds_o_pn_mfp, dsi_dn0_mfp, dsi_dp2_mfp, lcd0_d17_mfp,
> > + dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp, lvds_ee_pn_mfp,
> > + spi0_i2c_pcm_mfp, spi0_i2s_pcm_mfp, dsi_dnp1_cp_mfp,
> > + lvds_e_pn_mfp, dsi_dn2_mfp, uart2_rtsb_mfp,
> > + uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp,
> > + sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp, sd1_d0_d3_mfp,
> > + sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp, uart0_rx_mfp,
> > + clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp,
> > + uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp,
> > + pcm1_in_mfp, pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp,
> > + dnand_data_wr_mfp, dnand_acle_ce0_mfp, nand_ceb2_mfp,
> > + nand_ceb3_mfp]
> > + minItems: 1
> > + maxItems: 32
> > +
> > + function:
> > + description:
> > + Specify the alternative function to be configured for the
> > + given gpio pin groups.
> > + enum: [nor, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
> > + sens1, uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0,
> > + i2s1, pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
> > + p0, sd0, sd1, sd2, i2c0, i2c1, i2c3, dsi, lvds, usb30, clko_25m,
> > + mipi_csi, nand, spdif, ts, lcd0]
> > +
> > + required:
> > + - groups
> > + - function
> > +
> > + additionalProperties: false
> > +
> > + 'pinconf$':
> > + type: object
> > + description:
> > + Pinctrl node's client devices specify pin configurations using
> > + subnodes, which in turn use the standard properties below.
> > + $ref: pincfg-node.yaml#
> > +
> > + properties:
> > + groups:
> > + description:
> > + List of gpio pin groups affected by the drive-strength property
> > + specified in this subnode.
> > + items:
> > + oneOf:
> > + - enum: [sirq_drv, rmii_txd01_txen_drv, rmii_rxer_drv,
> > + rmii_crs_drv, rmii_rxd10_drv, rmii_ref_clk_drv,
> > + smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv,
> > + i2s13_drv, pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv,
> > + lcd_dsi_drv, dsi_drv, sd0_d0_d3_drv, sd1_d0_d3_drv,
> > + sd0_cmd_drv, sd0_clk_drv, sd1_cmd_drv, sd1_clk_drv,
> > + spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv,
> > + i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv,
> > + sens0_ckout_drv, uart3_all_drv]
> > + minItems: 1
> > + maxItems: 32
> > +
> > + pins:
> > + description:
> > + List of gpio pins affected by the bias-pull-* and
> > + input-schmitt-* properties specified in this subnode.
> > + items:
> > + oneOf:
> > + - enum: [dnand_dqs, dnand_dqsn, eth_txd0, eth_txd1, eth_txen,
> > + eth_rxer, eth_crs_dv, eth_rxd1, eth_rxd0, eth_ref_clk,
> > + eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,
> > + i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1,
> > + i2s_mclk1, ks_in0, ks_in1, ks_in2, ks_in3, ks_out0,
> > + ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp, lvds_odn,
> > + lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap,
> > + lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn,
> > + lvds_ecp, lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap,
> > + lvds_ean, lcd0_d18, lcd0_d17, dsi_dp3, dsi_dn3, dsi_dp1,
> > + dsi_dn1, dsi_cp, dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2,
> > + dsi_dn2, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, sd1_d1,
> > + sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
> > + spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,
> > + uart0_tx, i2c0_sclk, i2c0_sdata, sensor0_pclk,
> > + sensor0_ckout, dnand_ale, dnand_cle, dnand_ceb0,
> > + dnand_ceb1, dnand_ceb2, dnand_ceb3, uart2_rx, uart2_tx,
> > + uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb,
> > + uart3_ctsb, pcm1_in, pcm1_clk, pcm1_sync, pcm1_out,
> > + i2c1_sclk, i2c1_sdata, i2c2_sclk, i2c2_sdata, csi_dn0,
> > + csi_dp0, csi_dn1, csi_dp1, csi_dn2, csi_dp2, csi_dn3,
> > + csi_dp3, csi_cn, csi_cp, dnand_d0, dnand_d1, dnand_d2,
> > + dnand_d3, dnand_d4, dnand_d5, dnand_d6, dnand_d7,
> > + dnand_rb, dnand_rdb, dnand_rdbn, dnand_wrb, porb,
> > + clko_25m, bsel, pkg0, pkg1, pkg2, pkg3]
> > + minItems: 1
> > + maxItems: 64
> > +
> > + bias-pull-up: true
> > + bias-pull-down: true
> > +
> > + drive-strength:
> > + description:
> > + Selects the drive strength for the specified pins, in mA.
> > + enum: [2, 4, 8, 12]
> > +
> > + input-schmitt-enable: true
> > + input-schmitt-disable: true
> > +
> > + additionalProperties: false
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - gpio-controller
> > + - gpio-ranges
> > + - '#gpio-cells'
> > + - interrupt-controller
> > + - '#interrupt-cells'
> > + - interrupts
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + pinctrl: pinctrl@b01b0000 {
> > + compatible = "actions,s500-pinctrl";
> > + reg = <0xe01b0000 0x1000>;
> > + clocks = <&cmu 20>;
> > + gpio-controller;
> > + gpio-ranges = <&pinctrl 0 0 132>;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > + i2c0_default: i2c0_default {
> > + pinmux {
> > + groups = "i2c0_mfp";
> > + function = "i2c0";
> > + };
> > +
> > + pinconf {
> > + pins = "i2c0_sclk", "i2c0_sdata";
> > + bias-pull-up;
> > + };
> > + };
> > + };
> > +
> > +...
> > --
> > 2.27.0
> >
^ permalink raw reply
* [PATCH] gpio: stmpe: Use irqchip template
From: Linus Walleij @ 2020-07-16 10:06 UTC (permalink / raw)
To: linux-gpio
Cc: Bartosz Golaszewski, Linus Walleij, Patrice Chotard,
Alexandre TORGUE
This makes the driver use the irqchip template to assign
properties to the gpio_irq_chip instead of using the
explicit calls to gpiochip_irqchip_add_nested() and
gpiochip_set_nested_irqchip(). The irqchip is instead
added while adding the gpiochip.
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/gpio/gpio-stmpe.c | 24 +++++++++++-------------
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
index 542706a852e6..395ee51445ea 100644
--- a/drivers/gpio/gpio-stmpe.c
+++ b/drivers/gpio/gpio-stmpe.c
@@ -507,6 +507,8 @@ static int stmpe_gpio_probe(struct platform_device *pdev)
}
if (irq > 0) {
+ struct gpio_irq_chip *girq;
+
ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
stmpe_gpio_irq, IRQF_ONESHOT,
"stmpe-gpio", stmpe_gpio);
@@ -514,20 +516,16 @@ static int stmpe_gpio_probe(struct platform_device *pdev)
dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
goto out_disable;
}
- ret = gpiochip_irqchip_add_nested(&stmpe_gpio->chip,
- &stmpe_gpio_irq_chip,
- 0,
- handle_simple_irq,
- IRQ_TYPE_NONE);
- if (ret) {
- dev_err(&pdev->dev,
- "could not connect irqchip to gpiochip\n");
- goto out_disable;
- }
- gpiochip_set_nested_irqchip(&stmpe_gpio->chip,
- &stmpe_gpio_irq_chip,
- irq);
+ girq = &stmpe_gpio->chip.irq;
+ girq->chip = &stmpe_gpio_irq_chip;
+ /* This will let us handle the parent IRQ in the driver */
+ girq->parent_handler = NULL;
+ girq->num_parents = 0;
+ girq->parents = NULL;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_simple_irq;
+ girq->threaded = true;
}
platform_set_drvdata(pdev, stmpe_gpio);
--
2.26.2
^ permalink raw reply related
* [PATCH] gpio: tc35892: Use irqchip template
From: Linus Walleij @ 2020-07-16 9:34 UTC (permalink / raw)
To: linux-gpio; +Cc: Bartosz Golaszewski, Linus Walleij
This makes the driver use the irqchip template to assign
properties to the gpio_irq_chip instead of using the
explicit calls to gpiochip_irqchip_add_nested() and
gpiochip_set_nested_irqchip(). The irqchip is instead
added while adding the gpiochip.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/gpio/gpio-tc3589x.c | 26 +++++++++++---------------
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/drivers/gpio/gpio-tc3589x.c b/drivers/gpio/gpio-tc3589x.c
index 6be0684cfa49..58b0da9eb76f 100644
--- a/drivers/gpio/gpio-tc3589x.c
+++ b/drivers/gpio/gpio-tc3589x.c
@@ -289,6 +289,7 @@ static int tc3589x_gpio_probe(struct platform_device *pdev)
struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
struct device_node *np = pdev->dev.of_node;
struct tc3589x_gpio *tc3589x_gpio;
+ struct gpio_irq_chip *girq;
int ret;
int irq;
@@ -317,6 +318,16 @@ static int tc3589x_gpio_probe(struct platform_device *pdev)
tc3589x_gpio->chip.base = -1;
tc3589x_gpio->chip.of_node = np;
+ girq = &tc3589x_gpio->chip.irq;
+ girq->chip = &tc3589x_gpio_irq_chip;
+ /* This will let us handle the parent IRQ in the driver */
+ girq->parent_handler = NULL;
+ girq->num_parents = 0;
+ girq->parents = NULL;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_simple_irq;
+ girq->threaded = true;
+
/* Bring the GPIO module out of reset */
ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
TC3589x_RSTCTRL_GPIRST, 0);
@@ -339,21 +350,6 @@ static int tc3589x_gpio_probe(struct platform_device *pdev)
return ret;
}
- ret = gpiochip_irqchip_add_nested(&tc3589x_gpio->chip,
- &tc3589x_gpio_irq_chip,
- 0,
- handle_simple_irq,
- IRQ_TYPE_NONE);
- if (ret) {
- dev_err(&pdev->dev,
- "could not connect irqchip to gpiochip\n");
- return ret;
- }
-
- gpiochip_set_nested_irqchip(&tc3589x_gpio->chip,
- &tc3589x_gpio_irq_chip,
- irq);
-
platform_set_drvdata(pdev, tc3589x_gpio);
return 0;
--
2.26.2
^ permalink raw reply related
* [PATCH] gpio: max77620: Use helper variable and clarify
From: Linus Walleij @ 2020-07-16 9:28 UTC (permalink / raw)
To: linux-gpio; +Cc: Bartosz Golaszewski, Linus Walleij, Dmitry Osipenko
Most other drivers fill out the gpio_irq_chip using a
struct gpio_irq_chip *girq helper variable for ease of
reading.
We also make a habit of explicitly assigning NULL and
zero to the parent IRQs when using ordinary IRQ handlers
in the driver, mostly for code readability and
maintenance.
Cc: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/gpio/gpio-max77620.c | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
index e090979659eb..7c0a9ef0b500 100644
--- a/drivers/gpio/gpio-max77620.c
+++ b/drivers/gpio/gpio-max77620.c
@@ -288,6 +288,7 @@ static int max77620_gpio_probe(struct platform_device *pdev)
{
struct max77620_chip *chip = dev_get_drvdata(pdev->dev.parent);
struct max77620_gpio *mgpio;
+ struct gpio_irq_chip *girq;
unsigned int gpio_irq;
int ret;
@@ -316,11 +317,16 @@ static int max77620_gpio_probe(struct platform_device *pdev)
mgpio->gpio_chip.can_sleep = 1;
mgpio->gpio_chip.base = -1;
- mgpio->gpio_chip.irq.chip = &max77620_gpio_irqchip;
- mgpio->gpio_chip.irq.default_type = IRQ_TYPE_NONE;
- mgpio->gpio_chip.irq.handler = handle_edge_irq;
- mgpio->gpio_chip.irq.init_hw = max77620_gpio_irq_init_hw,
- mgpio->gpio_chip.irq.threaded = true;
+ girq = &mgpio->gpio_chip.irq;
+ girq->chip = &max77620_gpio_irqchip;
+ /* This will let us handle the parent IRQ in the driver */
+ girq->parent_handler = NULL;
+ girq->num_parents = 0;
+ girq->parents = NULL;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_edge_irq;
+ girq->init_hw = max77620_gpio_irq_init_hw,
+ girq->threaded = true;
platform_set_drvdata(pdev, mgpio);
--
2.26.2
^ permalink raw reply related
* Re: [PATCH v10 4/4] media: i2c: Add RDACM20 driver
From: Kieran Bingham @ 2020-07-16 9:07 UTC (permalink / raw)
To: Kieran Bingham, linux-renesas-soc, linux-media, linux-gpio,
devicetree, linux-kernel, Mauro Carvalho Chehab, sakari.ailus
Cc: Laurent Pinchart, Jacopo Mondi, Niklas Söderlund,
Hans Verkuil, Hyun Kwon, Manivannan Sadhasivam, Rob Herring,
Linus Walleij, Jacopo Mondi, Laurent Pinchart,
Niklas Söderlund, Rob Herring
In-Reply-To: <20200612144713.502006-5-kieran.bingham+renesas@ideasonboard.com>
Hi Sakari,
These are the checkpatch warnings from this patch:
> ./patches/gmsl/v10/v10-0003-dt-bindings-media-i2c-Add-bindings-for-IMI-RDACM.patch has style problems, please review.
> --------------------------------------------------------------
> ./patches/gmsl/v10/v10-0004-media-i2c-Add-RDACM20-driver.patch
> --------------------------------------------------------------
> WARNING: Misordered MAINTAINERS entry - list file patterns in alphabetic order
> #123: FILE: MAINTAINERS:14228:
> +F: drivers/media/i2c/rdacm20.c
> +F: drivers/media/i2c/max9271.c
Damn, that one snuck in without me noticing ...
I'll send a fix up.
> CHECK: Prefer using the BIT macro
> #535: FILE: drivers/media/i2c/max9271.h:17:
> +#define MAX9271_SPREAD_SPECT_05 (1 << 5)
>
> CHECK: Prefer using the BIT macro
> #550: FILE: drivers/media/i2c/max9271.h:32:
> +#define MAX9271_INTTYPE_UART (1 << 2)
>
> CHECK: Prefer using the BIT macro
> #561: FILE: drivers/media/i2c/max9271.h:43:
> +#define MAX9271_EDC_6BIT_CRC (1 << 0)
>
> CHECK: Prefer using the BIT macro
> #574: FILE: drivers/media/i2c/max9271.h:56:
> +#define MAX9271_I2CSLVSH_469NS_234NS (1 << 5)
>
> CHECK: Prefer using the BIT macro
> #582: FILE: drivers/media/i2c/max9271.h:64:
> +#define MAX9271_I2CMSTBT_28KBPS (1 << 2)
>
> CHECK: Prefer using the BIT macro
> #586: FILE: drivers/media/i2c/max9271.h:68:
> +#define MAX9271_I2CSLVTO_256US (1 << 0)
>
As with the max9286, these are all field definitions, not bit
definitions, so the BIT macro isn't appropriate.
> total: 0 errors, 1 warnings, 6 checks, 1277 lines checked
>
> NOTE: For some of the reported defects, checkpatch may be able to
> mechanically convert to the typical style using --fix or --fix-inplace.
>
> ./patches/gmsl/v10/v10-0004-media-i2c-Add-RDACM20-driver.patch has style problems, please review.
>
> NOTE: If any of the errors are false positives, please report
> them to the maintainer, see CHECKPATCH in MAINTAINERS.
--
Kieran
On 12/06/2020 15:47, Kieran Bingham wrote:
> From: Jacopo Mondi <jacopo+renesas@jmondi.org>
>
> The RDACM20 is a GMSL camera supporting 1280x800 resolution images
> developed by IMI based on an Omnivision 10635 sensor and a Maxim MAX9271
> GMSL serializer.
>
> The GMSL link carries power, control (I2C) and video data over a
> single coax cable.
>
> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
>
> ---
> v2:
> - Fix MAINTAINERS entry
>
> v3:
> - Use new V4L2_MBUS_CSI2_DPHY bus type
> - Remove 'always zero' error print
> - Fix module description
>
> v5:
> - use sleep rather than busy loops for 10 ms delays
> - Return ov10635_set_regs directly
> - Use devm_kzalloc instead of kzalloc in probe()
> - Or in the flags: dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE
> - Ensure v4l2_ctrl_handler_free() is called
> - rdacm20_probe converted to use .probe_new and drop i2c device id
> tables
> - Remove rdacm20_g_mbus_config
>
> v7:
> - Use new i2c_new_dummy_device API
>
> v8:
> - Almost a new version, main changes are:
> - Split max9271 out
> - Rework bindings to yaml format and include forthcoming RDACM21
> - Remove unecessary header file
> - Add pixel rate calculation
> - Drop unused fields and dead code
> - Rebase on media-master v5.7-rc1
> - A detailed list of changes provided as fixup patches is avilable at
> git://jmondi.org/linux #gmsl/jmondi/media-master/max9286-v8+old-rdacm20+split
>
> which includes the following list of patches:
> squash!: rdacm20: Report pixel rate
> squash!: rdacm20: Force sensor ID re-read
> squash!: rdamc20: Check register programming result
> squash!: rdacm20: Update to use the new max9271 APIs
> squash!: rdacm20: Start with serial link disabled
> squash!: rdacm20: Hard reset the sensor
> squash!: rdacm20: Cache i2c addresses
> squash!: rdacm20: Adjust to use new max9271 API
> squash!: rdacm20: Drop unused format definition
> squash!: rdacm20: Refresh file header
> squash!: max9271: Add two functions to control addresses
> squash!: max9271: Do not rewrite i2c address
> squash!: max9271: Improve gpio handling
> squash!: max9271: Rework core functions
> squash!: max9271 refresh
> squash!: rdacm20: Update maintainers file
> squash!: rdacm20: Remove unsued/duplicated defines
> squash!: rdacm20: Remove header file
> squash!: rdacm20: Move content of header into C file
> squash!: rdacm20: Reorganize register table
> squash!: rdacm20: Fix subdevice flag creation
> squash!: rdacm20: Drop i2c id table
> squash!: rdacm20: Release control handler
> squash!: rdacm20: Better handle i2c dummy error
> squash!: rdacm20: Use devm_kzalloc
> squash!: rdacm20: Use probe_new()
> squash!: rdacm20: Drop deprecated g_mbus_config
> media: i2c: rdacm20: Break max9271 out from rdacm20
> squash!: rdacm20: Rebase on latest media/maste
> media: i2c: Add RDACM20 driver
> dt-bindings: media: i2c: Add bindings for IMI RDACM2x
>
> v9:
> - Drop OV10635_FORMAT and use MEDIA_BUS_FMT_UYVY8_2X8 as suggested by
> Hans
>
> v10:
> - Use usleep_range over mdelay(10)
>
> MAINTAINERS | 12 +
> drivers/media/i2c/Kconfig | 13 +
> drivers/media/i2c/Makefile | 2 +
> drivers/media/i2c/max9271.c | 341 ++++++++++++++++++
> drivers/media/i2c/max9271.h | 224 ++++++++++++
> drivers/media/i2c/rdacm20.c | 667 ++++++++++++++++++++++++++++++++++++
> 6 files changed, 1259 insertions(+)
> create mode 100644 drivers/media/i2c/max9271.c
> create mode 100644 drivers/media/i2c/max9271.h
> create mode 100644 drivers/media/i2c/rdacm20.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7534df72033f..2cf9f33c9c74 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -14216,6 +14216,18 @@ S: Supported
> T: git git://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git dev
> F: tools/testing/selftests/rcutorture
>
> +RDACM20 Camera Sensor
> +M: Jacopo Mondi <jacopo+renesas@jmondi.org>
> +M: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> +M: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> +M: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> +L: linux-media@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/media/i2c/imi,rdacm2x-gmsl.yaml
> +F: drivers/media/i2c/rdacm20.c
> +F: drivers/media/i2c/max9271.c
> +F: drivers/media/i2c/max9271.h
> +
> RDC R-321X SoC
> M: Florian Fainelli <florian@openwrt.org>
> S: Maintained
> diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
> index 0a083407aa3e..9dd9fc1bb978 100644
> --- a/drivers/media/i2c/Kconfig
> +++ b/drivers/media/i2c/Kconfig
> @@ -1170,6 +1170,19 @@ config VIDEO_NOON010PC30
>
> source "drivers/media/i2c/m5mols/Kconfig"
>
> +config VIDEO_RDACM20
> + tristate "IMI RDACM20 camera support"
> + depends on I2C
> + select V4L2_FWNODE
> + select VIDEO_V4L2_SUBDEV_API
> + select MEDIA_CONTROLLER
> + help
> + This driver supports the IMI RDACM20 GMSL camera, used in
> + ADAS systems.
> +
> + This camera should be used in conjunction with a GMSL
> + deserialiser such as the MAX9286.
> +
> config VIDEO_RJ54N1
> tristate "Sharp RJ54N1CB0C sensor support"
> depends on I2C && VIDEO_V4L2
> diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
> index c8010d77e1a3..bfb9b4a03d0d 100644
> --- a/drivers/media/i2c/Makefile
> +++ b/drivers/media/i2c/Makefile
> @@ -119,6 +119,8 @@ obj-$(CONFIG_VIDEO_IMX290) += imx290.o
> obj-$(CONFIG_VIDEO_IMX319) += imx319.o
> obj-$(CONFIG_VIDEO_IMX355) += imx355.o
> obj-$(CONFIG_VIDEO_MAX9286) += max9286.o
> +rdacm20-camera_module-objs := rdacm20.o max9271.o
> +obj-$(CONFIG_VIDEO_RDACM20) += rdacm20-camera_module.o
> obj-$(CONFIG_VIDEO_ST_MIPID02) += st-mipid02.o
>
> obj-$(CONFIG_SDR_MAX2175) += max2175.o
> diff --git a/drivers/media/i2c/max9271.c b/drivers/media/i2c/max9271.c
> new file mode 100644
> index 000000000000..0f6f7a092a46
> --- /dev/null
> +++ b/drivers/media/i2c/max9271.c
> @@ -0,0 +1,341 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2017-2020 Jacopo Mondi
> + * Copyright (C) 2017-2020 Kieran Bingham
> + * Copyright (C) 2017-2020 Laurent Pinchart
> + * Copyright (C) 2017-2020 Niklas Söderlund
> + * Copyright (C) 2016 Renesas Electronics Corporation
> + * Copyright (C) 2015 Cogent Embedded, Inc.
> + *
> + * This file exports functions to control the Maxim MAX9271 GMSL serializer
> + * chip. This is not a self-contained driver, as MAX9271 is usually embedded in
> + * camera modules with at least one image sensor and optional additional
> + * components, such as uController units or ISPs/DSPs.
> + *
> + * Drivers for the camera modules (i.e. rdacm20/21) are expected to use
> + * functions exported from this library driver to maximize code re-use.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/i2c.h>
> +
> +#include "max9271.h"
> +
> +static int max9271_read(struct max9271_device *dev, u8 reg)
> +{
> + int ret;
> +
> + dev_dbg(&dev->client->dev, "%s(0x%02x)\n", __func__, reg);
> +
> + ret = i2c_smbus_read_byte_data(dev->client, reg);
> + if (ret < 0)
> + dev_dbg(&dev->client->dev,
> + "%s: register 0x%02x read failed (%d)\n",
> + __func__, reg, ret);
> +
> + return ret;
> +}
> +
> +static int max9271_write(struct max9271_device *dev, u8 reg, u8 val)
> +{
> + int ret;
> +
> + dev_dbg(&dev->client->dev, "%s(0x%02x, 0x%02x)\n", __func__, reg, val);
> +
> + ret = i2c_smbus_write_byte_data(dev->client, reg, val);
> + if (ret < 0)
> + dev_err(&dev->client->dev,
> + "%s: register 0x%02x write failed (%d)\n",
> + __func__, reg, ret);
> +
> + return ret;
> +}
> +
> +/*
> + * max9271_pclk_detect() - Detect valid pixel clock from image sensor
> + *
> + * Wait up to 10ms for a valid pixel clock.
> + *
> + * Returns 0 for success, < 0 for pixel clock not properly detected
> + */
> +static int max9271_pclk_detect(struct max9271_device *dev)
> +{
> + unsigned int i;
> + int ret;
> +
> + for (i = 0; i < 100; i++) {
> + ret = max9271_read(dev, 0x15);
> + if (ret < 0)
> + return ret;
> +
> + if (ret & MAX9271_PCLKDET)
> + return 0;
> +
> + usleep_range(50, 100);
> + }
> +
> + dev_err(&dev->client->dev, "Unable to detect valid pixel clock\n");
> +
> + return -EIO;
> +}
> +
> +int max9271_set_serial_link(struct max9271_device *dev, bool enable)
> +{
> + int ret;
> + u8 val = MAX9271_REVCCEN | MAX9271_FWDCCEN;
> +
> + if (enable) {
> + ret = max9271_pclk_detect(dev);
> + if (ret)
> + return ret;
> +
> + val |= MAX9271_SEREN;
> + } else {
> + val |= MAX9271_CLINKEN;
> + }
> +
> + /*
> + * The serializer temporarily disables the reverse control channel for
> + * 350µs after starting/stopping the forward serial link, but the
> + * deserializer synchronization time isn't clearly documented.
> + *
> + * According to the serializer datasheet we should wait 3ms, while
> + * according to the deserializer datasheet we should wait 5ms.
> + *
> + * Short delays here appear to show bit-errors in the writes following.
> + * Therefore a conservative delay seems best here.
> + */
> + max9271_write(dev, 0x04, val);
> + usleep_range(5000, 8000);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(max9271_set_serial_link);
> +
> +int max9271_configure_i2c(struct max9271_device *dev, u8 i2c_config)
> +{
> + int ret;
> +
> + ret = max9271_write(dev, 0x0d, i2c_config);
> + if (ret)
> + return ret;
> +
> + /* The delay required after an I2C bus configuration change is not
> + * characterized in the serializer manual. Sleep up to 5msec to
> + * stay safe.
> + */
> + usleep_range(3500, 5000);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(max9271_configure_i2c);
> +
> +int max9271_set_high_threshold(struct max9271_device *dev, bool enable)
> +{
> + int ret;
> +
> + ret = max9271_read(dev, 0x08);
> + if (ret < 0)
> + return ret;
> +
> + /*
> + * Enable or disable reverse channel high threshold to increase
> + * immunity to power supply noise.
> + */
> + max9271_write(dev, 0x08, enable ? ret | BIT(0) : ret & ~BIT(0));
> + usleep_range(2000, 2500);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(max9271_set_high_threshold);
> +
> +int max9271_configure_gmsl_link(struct max9271_device *dev)
> +{
> + /*
> + * Configure the GMSL link:
> + *
> + * - Double input mode, high data rate, 24-bit mode
> + * - Latch input data on PCLKIN rising edge
> + * - Enable HS/VS encoding
> + * - 1-bit parity error detection
> + *
> + * TODO: Make the GMSL link configuration parametric.
> + */
> + max9271_write(dev, 0x07, MAX9271_DBL | MAX9271_HVEN |
> + MAX9271_EDC_1BIT_PARITY);
> + usleep_range(5000, 8000);
> +
> + /*
> + * Adjust spread spectrum to +4% and auto-detect pixel clock
> + * and serial link rate.
> + */
> + max9271_write(dev, 0x02, MAX9271_SPREAD_SPECT_4 | MAX9271_R02_RES |
> + MAX9271_PCLK_AUTODETECT | MAX9271_SERIAL_AUTODETECT);
> + usleep_range(5000, 8000);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(max9271_configure_gmsl_link);
> +
> +int max9271_set_gpios(struct max9271_device *dev, u8 gpio_mask)
> +{
> + int ret;
> +
> + ret = max9271_read(dev, 0x0f);
> + if (ret < 0)
> + return 0;
> +
> + ret |= gpio_mask;
> + ret = max9271_write(dev, 0x0f, ret);
> + if (ret < 0) {
> + dev_err(&dev->client->dev, "Failed to set gpio (%d)\n", ret);
> + return ret;
> + }
> +
> + usleep_range(3500, 5000);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(max9271_set_gpios);
> +
> +int max9271_clear_gpios(struct max9271_device *dev, u8 gpio_mask)
> +{
> + int ret;
> +
> + ret = max9271_read(dev, 0x0f);
> + if (ret < 0)
> + return 0;
> +
> + ret &= ~gpio_mask;
> + ret = max9271_write(dev, 0x0f, ret);
> + if (ret < 0) {
> + dev_err(&dev->client->dev, "Failed to clear gpio (%d)\n", ret);
> + return ret;
> + }
> +
> + usleep_range(3500, 5000);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(max9271_clear_gpios);
> +
> +int max9271_enable_gpios(struct max9271_device *dev, u8 gpio_mask)
> +{
> + int ret;
> +
> + ret = max9271_read(dev, 0x0f);
> + if (ret < 0)
> + return 0;
> +
> + /* BIT(0) reserved: GPO is always enabled. */
> + ret |= gpio_mask | BIT(0);
> + ret = max9271_write(dev, 0x0e, ret);
> + if (ret < 0) {
> + dev_err(&dev->client->dev, "Failed to enable gpio (%d)\n", ret);
> + return ret;
> + }
> +
> + usleep_range(3500, 5000);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(max9271_enable_gpios);
> +
> +int max9271_disable_gpios(struct max9271_device *dev, u8 gpio_mask)
> +{
> + int ret;
> +
> + ret = max9271_read(dev, 0x0f);
> + if (ret < 0)
> + return 0;
> +
> + /* BIT(0) reserved: GPO cannot be disabled */
> + ret &= (~gpio_mask | BIT(0));
> + ret = max9271_write(dev, 0x0e, ret);
> + if (ret < 0) {
> + dev_err(&dev->client->dev, "Failed to disable gpio (%d)\n", ret);
> + return ret;
> + }
> +
> + usleep_range(3500, 5000);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(max9271_disable_gpios);
> +
> +int max9271_verify_id(struct max9271_device *dev)
> +{
> + int ret;
> +
> + ret = max9271_read(dev, 0x1e);
> + if (ret < 0) {
> + dev_err(&dev->client->dev, "MAX9271 ID read failed (%d)\n",
> + ret);
> + return ret;
> + }
> +
> + if (ret != MAX9271_ID) {
> + dev_err(&dev->client->dev, "MAX9271 ID mismatch (0x%02x)\n",
> + ret);
> + return -ENXIO;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(max9271_verify_id);
> +
> +int max9271_set_address(struct max9271_device *dev, u8 addr)
> +{
> + int ret;
> +
> + ret = max9271_write(dev, 0x00, addr << 1);
> + if (ret < 0) {
> + dev_err(&dev->client->dev,
> + "MAX9271 I2C address change failed (%d)\n", ret);
> + return ret;
> + }
> + usleep_range(3500, 5000);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(max9271_set_address);
> +
> +int max9271_set_deserializer_address(struct max9271_device *dev, u8 addr)
> +{
> + int ret;
> +
> + ret = max9271_write(dev, 0x01, addr << 1);
> + if (ret < 0) {
> + dev_err(&dev->client->dev,
> + "MAX9271 deserializer address set failed (%d)\n", ret);
> + return ret;
> + }
> + usleep_range(3500, 5000);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(max9271_set_deserializer_address);
> +
> +int max9271_set_translation(struct max9271_device *dev, u8 source, u8 dest)
> +{
> + int ret;
> +
> + ret = max9271_write(dev, 0x09, source << 1);
> + if (ret < 0) {
> + dev_err(&dev->client->dev,
> + "MAX9271 I2C translation setup failed (%d)\n", ret);
> + return ret;
> + }
> + usleep_range(3500, 5000);
> +
> + ret = max9271_write(dev, 0x0a, dest << 1);
> + if (ret < 0) {
> + dev_err(&dev->client->dev,
> + "MAX9271 I2C translation setup failed (%d)\n", ret);
> + return ret;
> + }
> + usleep_range(3500, 5000);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(max9271_set_translation);
> diff --git a/drivers/media/i2c/max9271.h b/drivers/media/i2c/max9271.h
> new file mode 100644
> index 000000000000..d78fb21441e9
> --- /dev/null
> +++ b/drivers/media/i2c/max9271.h
> @@ -0,0 +1,224 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2017-2020 Jacopo Mondi
> + * Copyright (C) 2017-2020 Kieran Bingham
> + * Copyright (C) 2017-2020 Laurent Pinchart
> + * Copyright (C) 2017-2020 Niklas Söderlund
> + * Copyright (C) 2016 Renesas Electronics Corporation
> + * Copyright (C) 2015 Cogent Embedded, Inc.
> + */
> +
> +#include <linux/i2c.h>
> +
> +#define MAX9271_DEFAULT_ADDR 0x40
> +
> +/* Register 0x02 */
> +#define MAX9271_SPREAD_SPECT_0 (0 << 5)
> +#define MAX9271_SPREAD_SPECT_05 (1 << 5)
> +#define MAX9271_SPREAD_SPECT_15 (2 << 5)
> +#define MAX9271_SPREAD_SPECT_1 (5 << 5)
> +#define MAX9271_SPREAD_SPECT_2 (3 << 5)
> +#define MAX9271_SPREAD_SPECT_3 (6 << 5)
> +#define MAX9271_SPREAD_SPECT_4 (7 << 5)
> +#define MAX9271_R02_RES BIT(4)
> +#define MAX9271_PCLK_AUTODETECT (3 << 2)
> +#define MAX9271_SERIAL_AUTODETECT (0x03)
> +/* Register 0x04 */
> +#define MAX9271_SEREN BIT(7)
> +#define MAX9271_CLINKEN BIT(6)
> +#define MAX9271_PRBSEN BIT(5)
> +#define MAX9271_SLEEP BIT(4)
> +#define MAX9271_INTTYPE_I2C (0 << 2)
> +#define MAX9271_INTTYPE_UART (1 << 2)
> +#define MAX9271_INTTYPE_NONE (2 << 2)
> +#define MAX9271_REVCCEN BIT(1)
> +#define MAX9271_FWDCCEN BIT(0)
> +/* Register 0x07 */
> +#define MAX9271_DBL BIT(7)
> +#define MAX9271_DRS BIT(6)
> +#define MAX9271_BWS BIT(5)
> +#define MAX9271_ES BIT(4)
> +#define MAX9271_HVEN BIT(2)
> +#define MAX9271_EDC_1BIT_PARITY (0 << 0)
> +#define MAX9271_EDC_6BIT_CRC (1 << 0)
> +#define MAX9271_EDC_6BIT_HAMMING (2 << 0)
> +/* Register 0x08 */
> +#define MAX9271_INVVS BIT(7)
> +#define MAX9271_INVHS BIT(6)
> +#define MAX9271_REV_LOGAIN BIT(3)
> +#define MAX9271_REV_HIVTH BIT(0)
> +/* Register 0x09 */
> +#define MAX9271_ID 0x09
> +/* Register 0x0d */
> +#define MAX9271_I2CLOCACK BIT(7)
> +#define MAX9271_I2CSLVSH_1046NS_469NS (3 << 5)
> +#define MAX9271_I2CSLVSH_938NS_352NS (2 << 5)
> +#define MAX9271_I2CSLVSH_469NS_234NS (1 << 5)
> +#define MAX9271_I2CSLVSH_352NS_117NS (0 << 5)
> +#define MAX9271_I2CMSTBT_837KBPS (7 << 2)
> +#define MAX9271_I2CMSTBT_533KBPS (6 << 2)
> +#define MAX9271_I2CMSTBT_339KBPS (5 << 2)
> +#define MAX9271_I2CMSTBT_173KBPS (4 << 2)
> +#define MAX9271_I2CMSTBT_105KBPS (3 << 2)
> +#define MAX9271_I2CMSTBT_84KBPS (2 << 2)
> +#define MAX9271_I2CMSTBT_28KBPS (1 << 2)
> +#define MAX9271_I2CMSTBT_8KBPS (0 << 2)
> +#define MAX9271_I2CSLVTO_NONE (3 << 0)
> +#define MAX9271_I2CSLVTO_1024US (2 << 0)
> +#define MAX9271_I2CSLVTO_256US (1 << 0)
> +#define MAX9271_I2CSLVTO_64US (0 << 0)
> +/* Register 0x0f */
> +#define MAX9271_GPIO5OUT BIT(5)
> +#define MAX9271_GPIO4OUT BIT(4)
> +#define MAX9271_GPIO3OUT BIT(3)
> +#define MAX9271_GPIO2OUT BIT(2)
> +#define MAX9271_GPIO1OUT BIT(1)
> +#define MAX9271_GPO BIT(0)
> +/* Register 0x15 */
> +#define MAX9271_PCLKDET BIT(0)
> +
> +/**
> + * struct max9271_device - max9271 device
> + * @client: The i2c client for the max9271 instance
> + */
> +struct max9271_device {
> + struct i2c_client *client;
> +};
> +
> +/**
> + * max9271_set_serial_link() - Enable/disable serial link
> + * @dev: The max9271 device
> + * @enable: Serial link enable/disable flag
> + *
> + * Return 0 on success or a negative error code on failure
> + */
> +int max9271_set_serial_link(struct max9271_device *dev, bool enable);
> +
> +/**
> + * max9271_configure_i2c() - Configure I2C bus parameters
> + * @dev: The max9271 device
> + * @i2c_config: The I2C bus configuration bit mask
> + *
> + * Configure MAX9271 I2C interface. The bus configuration provided in the
> + * @i2c_config parameter shall be assembled using bit values defined by the
> + * MAX9271_I2C* macros.
> + *
> + * Return 0 on success or a negative error code on failure
> + */
> +int max9271_configure_i2c(struct max9271_device *dev, u8 i2c_config);
> +
> +/**
> + * max9271_set_high_threshold() - Enable or disable reverse channel high
> + * threshold
> + * @dev: The max9271 device
> + * @enable: High threshold enable/disable flag
> + *
> + * Return 0 on success or a negative error code on failure
> + */
> +int max9271_set_high_threshold(struct max9271_device *dev, bool enable);
> +
> +/**
> + * max9271_configure_gmsl_link() - Configure the GMSL link
> + * @dev: The max9271 device
> + *
> + * FIXME: the GMSL link configuration is currently hardcoded and performed
> + * by programming registers 0x04, 0x07 and 0x02.
> + *
> + * Return 0 on success or a negative error code on failure
> + */
> +int max9271_configure_gmsl_link(struct max9271_device *dev);
> +
> +/**
> + * max9271_set_gpios() - Set gpio lines to physical high value
> + * @dev: The max9271 device
> + * @gpio_mask: The mask of gpio lines to set to high value
> + *
> + * The @gpio_mask parameter shall be assembled using the MAX9271_GP[IO|O]*
> + * bit values.
> + *
> + * Return 0 on success or a negative error code on failure
> + */
> +int max9271_set_gpios(struct max9271_device *dev, u8 gpio_mask);
> +
> +/**
> + * max9271_clear_gpios() - Set gpio lines to physical low value
> + * @dev: The max9271 device
> + * @gpio_mask: The mask of gpio lines to set to low value
> + *
> + * The @gpio_mask parameter shall be assembled using the MAX9271_GP[IO|O]*
> + * bit values.
> + *
> + * Return 0 on success or a negative error code on failure
> + */
> +int max9271_clear_gpios(struct max9271_device *dev, u8 gpio_mask);
> +
> +/**
> + * max9271_enable_gpios() - Enable gpio lines
> + * @dev: The max9271 device
> + * @gpio_mask: The mask of gpio lines to enable
> + *
> + * The @gpio_mask parameter shall be assembled using the MAX9271_GPIO*
> + * bit values. GPO line is always enabled by default.
> + *
> + * Return 0 on success or a negative error code on failure
> + */
> +int max9271_enable_gpios(struct max9271_device *dev, u8 gpio_mask);
> +
> +/**
> + * max9271_disable_gpios() - Disable gpio lines
> + * @dev: The max9271 device
> + * @gpio_mask: The mask of gpio lines to disable
> + *
> + * The @gpio_mask parameter shall be assembled using the MAX9271_GPIO*
> + * bit values. GPO line is always enabled by default and cannot be disabled.
> + *
> + * Return 0 on success or a negative error code on failure
> + */
> +int max9271_disable_gpios(struct max9271_device *dev, u8 gpio_mask);
> +
> +/**
> + * max9271_verify_id() - Read and verify MAX9271 id
> + * @dev: The max9271 device
> + *
> + * Return 0 on success or a negative error code on failure
> + */
> +int max9271_verify_id(struct max9271_device *dev);
> +
> +/**
> + * max9271_set_address() - Program a new I2C address
> + * @dev: The max9271 device
> + * @addr: The new I2C address in 7-bit format
> + *
> + * This function only takes care of programming the new I2C address @addr to
> + * in the MAX9271 chip registers, it is responsiblity of the caller to set
> + * the i2c address client to the @addr value to be able to communicate with
> + * the MAX9271 chip using the I2C framework APIs after this function returns.
> + *
> + * Return 0 on success or a negative error code on failure
> + */
> +int max9271_set_address(struct max9271_device *dev, u8 addr);
> +
> +/**
> + * max9271_set_deserializer_address() - Program the remote deserializer address
> + * @dev: The max9271 device
> + * @addr: The deserializer I2C address in 7-bit format
> + *
> + * Return 0 on success or a negative error code on failure
> + */
> +int max9271_set_deserializer_address(struct max9271_device *dev, u8 addr);
> +
> +/**
> + * max9271_set_translation() - Program I2C address translation
> + * @dev: The max9271 device
> + * @source: The I2C source address
> + * @dest: The I2C destination address
> + *
> + * Program address translation from @source to @dest. This is required to
> + * communicate with local devices that do not support address reprogramming.
> + *
> + * TODO: The device supports translation of two address, this function currently
> + * supports a single one.
> + *
> + * Return 0 on success or a negative error code on failure
> + */
> +int max9271_set_translation(struct max9271_device *dev, u8 source, u8 dest);
> diff --git a/drivers/media/i2c/rdacm20.c b/drivers/media/i2c/rdacm20.c
> new file mode 100644
> index 000000000000..1ed928c4ca70
> --- /dev/null
> +++ b/drivers/media/i2c/rdacm20.c
> @@ -0,0 +1,667 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * IMI RDACM20 GMSL Camera Driver
> + *
> + * Copyright (C) 2017-2020 Jacopo Mondi
> + * Copyright (C) 2017-2020 Kieran Bingham
> + * Copyright (C) 2017-2019 Laurent Pinchart
> + * Copyright (C) 2017-2019 Niklas Söderlund
> + * Copyright (C) 2016 Renesas Electronics Corporation
> + * Copyright (C) 2015 Cogent Embedded, Inc.
> + */
> +
> +/*
> + * The camera is made of an Omnivision OV10635 sensor connected to a Maxim
> + * MAX9271 GMSL serializer.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/fwnode.h>
> +#include <linux/init.h>
> +#include <linux/i2c.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/videodev2.h>
> +
> +#include <media/v4l2-async.h>
> +#include <media/v4l2-ctrls.h>
> +#include <media/v4l2-subdev.h>
> +
> +#include "max9271.h"
> +
> +#define OV10635_I2C_ADDRESS 0x30
> +
> +#define OV10635_SOFTWARE_RESET 0x0103
> +#define OV10635_PID 0x300a
> +#define OV10635_VER 0x300b
> +#define OV10635_SC_CMMN_SCCB_ID 0x300c
> +#define OV10635_SC_CMMN_SCCB_ID_SELECT BIT(0)
> +#define OV10635_VERSION 0xa635
> +
> +#define OV10635_WIDTH 1280
> +#define OV10635_HEIGHT 800
> +
> +/* VTS = PCLK / FPS / HTS / 2 (= 88MHz / 1572 / 30 / 2) */
> +#define OV10635_HTS 1572
> +/* FPS = 29,9998 */
> +#define OV10635_VTS 933
> +
> +/*
> + * As the drivers supports a single MEDIA_BUS_FMT_UYVY8_2X8 format we
> + * can harcode the pixel rate.
> + *
> + * PCLK is fed through the system clock, programmed @88MHz.
> + * MEDIA_BUS_FMT_UYVY8_2X8 format = 2 samples per pixel.
> + *
> + * Pixelrate = PCLK / 2
> + * FPS = (OV10635_VTS * OV10635_HTS) / PixelRate
> + * = 29,9998
> + */
> +#define OV10635_PIXEL_RATE (44000000)
> +
> +static const struct ov10635_reg {
> + u16 reg;
> + u8 val;
> +} ov10635_regs_wizard[] = {
> + { 0x301b, 0xff }, { 0x301c, 0xff }, { 0x301a, 0xff }, { 0x3011, 0x42 },
> + { 0x6900, 0x0c }, { 0x6901, 0x19 }, { 0x3503, 0x10 }, { 0x3025, 0x03 },
> + { 0x3003, 0x16 }, { 0x3004, 0x30 }, { 0x3005, 0x40 }, { 0x3006, 0x91 },
> + { 0x3600, 0x74 }, { 0x3601, 0x2b }, { 0x3612, 0x00 }, { 0x3611, 0x67 },
> + { 0x3633, 0xca }, { 0x3602, 0xaf }, { 0x3603, 0x04 }, { 0x3630, 0x28 },
> + { 0x3631, 0x16 }, { 0x3714, 0x10 }, { 0x371d, 0x01 }, { 0x4300, 0x3a },
> + { 0x3007, 0x01 }, { 0x3024, 0x03 }, { 0x3020, 0x0a }, { 0x3702, 0x0d },
> + { 0x3703, 0x20 }, { 0x3704, 0x15 }, { 0x3709, 0xa8 }, { 0x370c, 0xc7 },
> + { 0x370d, 0x80 }, { 0x3712, 0x00 }, { 0x3713, 0x20 }, { 0x3715, 0x04 },
> + { 0x381d, 0x40 }, { 0x381c, 0x00 }, { 0x3822, 0x50 }, { 0x3824, 0x10 },
> + { 0x3815, 0x8c }, { 0x3804, 0x05 }, { 0x3805, 0x1f }, { 0x3800, 0x00 },
> + { 0x3801, 0x00 }, { 0x3806, 0x03 }, { 0x3807, 0x28 }, { 0x3802, 0x00 },
> + { 0x3803, 0x07 }, { 0x3808, 0x05 }, { 0x3809, 0x00 }, { 0x380a, 0x03 },
> + { 0x380b, 0x20 }, { 0x380c, OV10635_HTS >> 8 },
> + { 0x380d, OV10635_HTS & 0xff }, { 0x380e, OV10635_VTS >> 8 },
> + { 0x380f, OV10635_VTS & 0xff }, { 0x3813, 0x02 }, { 0x3811, 0x08 },
> + { 0x381f, 0x0c }, { 0x3819, 0x04 }, { 0x3804, 0x01 }, { 0x3805, 0x00 },
> + { 0x3828, 0x03 }, { 0x3829, 0x10 }, { 0x382a, 0x10 }, { 0x3621, 0x63 },
> + { 0x5005, 0x08 }, { 0x56d5, 0x00 }, { 0x56d6, 0x80 }, { 0x56d7, 0x00 },
> + { 0x56d8, 0x00 }, { 0x56d9, 0x00 }, { 0x56da, 0x80 }, { 0x56db, 0x00 },
> + { 0x56dc, 0x00 }, { 0x56e8, 0x00 }, { 0x56e9, 0x7f }, { 0x56ea, 0x00 },
> + { 0x56eb, 0x7f }, { 0x5100, 0x00 }, { 0x5101, 0x80 }, { 0x5102, 0x00 },
> + { 0x5103, 0x80 }, { 0x5104, 0x00 }, { 0x5105, 0x80 }, { 0x5106, 0x00 },
> + { 0x5107, 0x80 }, { 0x5108, 0x00 }, { 0x5109, 0x00 }, { 0x510a, 0x00 },
> + { 0x510b, 0x00 }, { 0x510c, 0x00 }, { 0x510d, 0x00 }, { 0x510e, 0x00 },
> + { 0x510f, 0x00 }, { 0x5110, 0x00 }, { 0x5111, 0x80 }, { 0x5112, 0x00 },
> + { 0x5113, 0x80 }, { 0x5114, 0x00 }, { 0x5115, 0x80 }, { 0x5116, 0x00 },
> + { 0x5117, 0x80 }, { 0x5118, 0x00 }, { 0x5119, 0x00 }, { 0x511a, 0x00 },
> + { 0x511b, 0x00 }, { 0x511c, 0x00 }, { 0x511d, 0x00 }, { 0x511e, 0x00 },
> + { 0x511f, 0x00 }, { 0x56d0, 0x00 }, { 0x5006, 0x04 }, { 0x5608, 0x05 },
> + { 0x52d7, 0x06 }, { 0x528d, 0x08 }, { 0x5293, 0x12 }, { 0x52d3, 0x12 },
> + { 0x5288, 0x06 }, { 0x5289, 0x20 }, { 0x52c8, 0x06 }, { 0x52c9, 0x20 },
> + { 0x52cd, 0x04 }, { 0x5381, 0x00 }, { 0x5382, 0xff }, { 0x5589, 0x76 },
> + { 0x558a, 0x47 }, { 0x558b, 0xef }, { 0x558c, 0xc9 }, { 0x558d, 0x49 },
> + { 0x558e, 0x30 }, { 0x558f, 0x67 }, { 0x5590, 0x3f }, { 0x5591, 0xf0 },
> + { 0x5592, 0x10 }, { 0x55a2, 0x6d }, { 0x55a3, 0x55 }, { 0x55a4, 0xc3 },
> + { 0x55a5, 0xb5 }, { 0x55a6, 0x43 }, { 0x55a7, 0x38 }, { 0x55a8, 0x5f },
> + { 0x55a9, 0x4b }, { 0x55aa, 0xf0 }, { 0x55ab, 0x10 }, { 0x5581, 0x52 },
> + { 0x5300, 0x01 }, { 0x5301, 0x00 }, { 0x5302, 0x00 }, { 0x5303, 0x0e },
> + { 0x5304, 0x00 }, { 0x5305, 0x0e }, { 0x5306, 0x00 }, { 0x5307, 0x36 },
> + { 0x5308, 0x00 }, { 0x5309, 0xd9 }, { 0x530a, 0x00 }, { 0x530b, 0x0f },
> + { 0x530c, 0x00 }, { 0x530d, 0x2c }, { 0x530e, 0x00 }, { 0x530f, 0x59 },
> + { 0x5310, 0x00 }, { 0x5311, 0x7b }, { 0x5312, 0x00 }, { 0x5313, 0x22 },
> + { 0x5314, 0x00 }, { 0x5315, 0xd5 }, { 0x5316, 0x00 }, { 0x5317, 0x13 },
> + { 0x5318, 0x00 }, { 0x5319, 0x18 }, { 0x531a, 0x00 }, { 0x531b, 0x26 },
> + { 0x531c, 0x00 }, { 0x531d, 0xdc }, { 0x531e, 0x00 }, { 0x531f, 0x02 },
> + { 0x5320, 0x00 }, { 0x5321, 0x24 }, { 0x5322, 0x00 }, { 0x5323, 0x56 },
> + { 0x5324, 0x00 }, { 0x5325, 0x85 }, { 0x5326, 0x00 }, { 0x5327, 0x20 },
> + { 0x5609, 0x01 }, { 0x560a, 0x40 }, { 0x560b, 0x01 }, { 0x560c, 0x40 },
> + { 0x560d, 0x00 }, { 0x560e, 0xfa }, { 0x560f, 0x00 }, { 0x5610, 0xfa },
> + { 0x5611, 0x02 }, { 0x5612, 0x80 }, { 0x5613, 0x02 }, { 0x5614, 0x80 },
> + { 0x5615, 0x01 }, { 0x5616, 0x2c }, { 0x5617, 0x01 }, { 0x5618, 0x2c },
> + { 0x563b, 0x01 }, { 0x563c, 0x01 }, { 0x563d, 0x01 }, { 0x563e, 0x01 },
> + { 0x563f, 0x03 }, { 0x5640, 0x03 }, { 0x5641, 0x03 }, { 0x5642, 0x05 },
> + { 0x5643, 0x09 }, { 0x5644, 0x05 }, { 0x5645, 0x05 }, { 0x5646, 0x05 },
> + { 0x5647, 0x05 }, { 0x5651, 0x00 }, { 0x5652, 0x80 }, { 0x521a, 0x01 },
> + { 0x521b, 0x03 }, { 0x521c, 0x06 }, { 0x521d, 0x0a }, { 0x521e, 0x0e },
> + { 0x521f, 0x12 }, { 0x5220, 0x16 }, { 0x5223, 0x02 }, { 0x5225, 0x04 },
> + { 0x5227, 0x08 }, { 0x5229, 0x0c }, { 0x522b, 0x12 }, { 0x522d, 0x18 },
> + { 0x522f, 0x1e }, { 0x5241, 0x04 }, { 0x5242, 0x01 }, { 0x5243, 0x03 },
> + { 0x5244, 0x06 }, { 0x5245, 0x0a }, { 0x5246, 0x0e }, { 0x5247, 0x12 },
> + { 0x5248, 0x16 }, { 0x524a, 0x03 }, { 0x524c, 0x04 }, { 0x524e, 0x08 },
> + { 0x5250, 0x0c }, { 0x5252, 0x12 }, { 0x5254, 0x18 }, { 0x5256, 0x1e },
> + /* fifo_line_length = 2*hts */
> + { 0x4606, (2 * OV10635_HTS) >> 8 }, { 0x4607, (2 * OV10635_HTS) & 0xff },
> + /* fifo_hsync_start = 2*(hts - xres) */
> + { 0x460a, (2 * (OV10635_HTS - OV10635_WIDTH)) >> 8 },
> + { 0x460b, (2 * (OV10635_HTS - OV10635_WIDTH)) & 0xff },
> + { 0x460c, 0x00 }, { 0x4620, 0x0e },
> + /* BT601: 0x08 is also acceptable as HS/VS mode */
> + { 0x4700, 0x04 }, { 0x4701, 0x00 }, { 0x4702, 0x01 }, { 0x4004, 0x04 },
> + { 0x4005, 0x18 }, { 0x4001, 0x06 }, { 0x4050, 0x22 }, { 0x4051, 0x24 },
> + { 0x4052, 0x02 }, { 0x4057, 0x9c }, { 0x405a, 0x00 }, { 0x4202, 0x02 },
> + { 0x3023, 0x10 }, { 0x0100, 0x01 }, { 0x0100, 0x01 }, { 0x6f10, 0x07 },
> + { 0x6f11, 0x82 }, { 0x6f12, 0x04 }, { 0x6f13, 0x00 }, { 0xd000, 0x19 },
> + { 0xd001, 0xa0 }, { 0xd002, 0x00 }, { 0xd003, 0x01 }, { 0xd004, 0xa9 },
> + { 0xd005, 0xad }, { 0xd006, 0x10 }, { 0xd007, 0x40 }, { 0xd008, 0x44 },
> + { 0xd009, 0x00 }, { 0xd00a, 0x68 }, { 0xd00b, 0x00 }, { 0xd00c, 0x15 },
> + { 0xd00d, 0x00 }, { 0xd00e, 0x00 }, { 0xd00f, 0x00 }, { 0xd040, 0x9c },
> + { 0xd041, 0x21 }, { 0xd042, 0xff }, { 0xd043, 0xf8 }, { 0xd044, 0xd4 },
> + { 0xd045, 0x01 }, { 0xd046, 0x48 }, { 0xd047, 0x00 }, { 0xd048, 0xd4 },
> + { 0xd049, 0x01 }, { 0xd04a, 0x50 }, { 0xd04b, 0x04 }, { 0xd04c, 0x18 },
> + { 0xd04d, 0x60 }, { 0xd04e, 0x00 }, { 0xd04f, 0x01 }, { 0xd050, 0xa8 },
> + { 0xd051, 0x63 }, { 0xd052, 0x02 }, { 0xd053, 0xa4 }, { 0xd054, 0x85 },
> + { 0xd055, 0x43 }, { 0xd056, 0x00 }, { 0xd057, 0x00 }, { 0xd058, 0x18 },
> + { 0xd059, 0x60 }, { 0xd05a, 0x00 }, { 0xd05b, 0x01 }, { 0xd05c, 0xa8 },
> + { 0xd05d, 0x63 }, { 0xd05e, 0x03 }, { 0xd05f, 0xf0 }, { 0xd060, 0x98 },
> + { 0xd061, 0xa3 }, { 0xd062, 0x00 }, { 0xd063, 0x00 }, { 0xd064, 0x8c },
> + { 0xd065, 0x6a }, { 0xd066, 0x00 }, { 0xd067, 0x6e }, { 0xd068, 0xe5 },
> + { 0xd069, 0x85 }, { 0xd06a, 0x18 }, { 0xd06b, 0x00 }, { 0xd06c, 0x10 },
> + { 0xd06d, 0x00 }, { 0xd06e, 0x00 }, { 0xd06f, 0x10 }, { 0xd070, 0x9c },
> + { 0xd071, 0x80 }, { 0xd072, 0x00 }, { 0xd073, 0x03 }, { 0xd074, 0x18 },
> + { 0xd075, 0x60 }, { 0xd076, 0x00 }, { 0xd077, 0x01 }, { 0xd078, 0xa8 },
> + { 0xd079, 0x63 }, { 0xd07a, 0x07 }, { 0xd07b, 0x80 }, { 0xd07c, 0x07 },
> + { 0xd07d, 0xff }, { 0xd07e, 0xf9 }, { 0xd07f, 0x03 }, { 0xd080, 0x8c },
> + { 0xd081, 0x63 }, { 0xd082, 0x00 }, { 0xd083, 0x00 }, { 0xd084, 0xa5 },
> + { 0xd085, 0x6b }, { 0xd086, 0x00 }, { 0xd087, 0xff }, { 0xd088, 0x18 },
> + { 0xd089, 0x80 }, { 0xd08a, 0x00 }, { 0xd08b, 0x01 }, { 0xd08c, 0xa8 },
> + { 0xd08d, 0x84 }, { 0xd08e, 0x01 }, { 0xd08f, 0x04 }, { 0xd090, 0xe1 },
> + { 0xd091, 0x6b }, { 0xd092, 0x58 }, { 0xd093, 0x00 }, { 0xd094, 0x94 },
> + { 0xd095, 0x6a }, { 0xd096, 0x00 }, { 0xd097, 0x70 }, { 0xd098, 0xe1 },
> + { 0xd099, 0x6b }, { 0xd09a, 0x20 }, { 0xd09b, 0x00 }, { 0xd09c, 0x95 },
> + { 0xd09d, 0x6b }, { 0xd09e, 0x00 }, { 0xd09f, 0x00 }, { 0xd0a0, 0xe4 },
> + { 0xd0a1, 0x8b }, { 0xd0a2, 0x18 }, { 0xd0a3, 0x00 }, { 0xd0a4, 0x0c },
> + { 0xd0a5, 0x00 }, { 0xd0a6, 0x00 }, { 0xd0a7, 0x23 }, { 0xd0a8, 0x15 },
> + { 0xd0a9, 0x00 }, { 0xd0aa, 0x00 }, { 0xd0ab, 0x00 }, { 0xd0ac, 0x18 },
> + { 0xd0ad, 0x60 }, { 0xd0ae, 0x80 }, { 0xd0af, 0x06 }, { 0xd0b0, 0xa8 },
> + { 0xd0b1, 0x83 }, { 0xd0b2, 0x40 }, { 0xd0b3, 0x08 }, { 0xd0b4, 0xa8 },
> + { 0xd0b5, 0xe3 }, { 0xd0b6, 0x38 }, { 0xd0b7, 0x2a }, { 0xd0b8, 0xa8 },
> + { 0xd0b9, 0xc3 }, { 0xd0ba, 0x40 }, { 0xd0bb, 0x09 }, { 0xd0bc, 0xa8 },
> + { 0xd0bd, 0xa3 }, { 0xd0be, 0x38 }, { 0xd0bf, 0x29 }, { 0xd0c0, 0x8c },
> + { 0xd0c1, 0x65 }, { 0xd0c2, 0x00 }, { 0xd0c3, 0x00 }, { 0xd0c4, 0xd8 },
> + { 0xd0c5, 0x04 }, { 0xd0c6, 0x18 }, { 0xd0c7, 0x00 }, { 0xd0c8, 0x8c },
> + { 0xd0c9, 0x67 }, { 0xd0ca, 0x00 }, { 0xd0cb, 0x00 }, { 0xd0cc, 0xd8 },
> + { 0xd0cd, 0x06 }, { 0xd0ce, 0x18 }, { 0xd0cf, 0x00 }, { 0xd0d0, 0x18 },
> + { 0xd0d1, 0x60 }, { 0xd0d2, 0x80 }, { 0xd0d3, 0x06 }, { 0xd0d4, 0xa8 },
> + { 0xd0d5, 0xe3 }, { 0xd0d6, 0x67 }, { 0xd0d7, 0x02 }, { 0xd0d8, 0xa9 },
> + { 0xd0d9, 0x03 }, { 0xd0da, 0x67 }, { 0xd0db, 0x03 }, { 0xd0dc, 0xa8 },
> + { 0xd0dd, 0xc3 }, { 0xd0de, 0x3d }, { 0xd0df, 0x05 }, { 0xd0e0, 0x8c },
> + { 0xd0e1, 0x66 }, { 0xd0e2, 0x00 }, { 0xd0e3, 0x00 }, { 0xd0e4, 0xb8 },
> + { 0xd0e5, 0x63 }, { 0xd0e6, 0x00 }, { 0xd0e7, 0x18 }, { 0xd0e8, 0xb8 },
> + { 0xd0e9, 0x63 }, { 0xd0ea, 0x00 }, { 0xd0eb, 0x98 }, { 0xd0ec, 0xbc },
> + { 0xd0ed, 0x03 }, { 0xd0ee, 0x00 }, { 0xd0ef, 0x00 }, { 0xd0f0, 0x10 },
> + { 0xd0f1, 0x00 }, { 0xd0f2, 0x00 }, { 0xd0f3, 0x16 }, { 0xd0f4, 0xb8 },
> + { 0xd0f5, 0x83 }, { 0xd0f6, 0x00 }, { 0xd0f7, 0x19 }, { 0xd0f8, 0x8c },
> + { 0xd0f9, 0x67 }, { 0xd0fa, 0x00 }, { 0xd0fb, 0x00 }, { 0xd0fc, 0xb8 },
> + { 0xd0fd, 0xa4 }, { 0xd0fe, 0x00 }, { 0xd0ff, 0x98 }, { 0xd100, 0xb8 },
> + { 0xd101, 0x83 }, { 0xd102, 0x00 }, { 0xd103, 0x08 }, { 0xd104, 0x8c },
> + { 0xd105, 0x68 }, { 0xd106, 0x00 }, { 0xd107, 0x00 }, { 0xd108, 0xe0 },
> + { 0xd109, 0x63 }, { 0xd10a, 0x20 }, { 0xd10b, 0x04 }, { 0xd10c, 0xe0 },
> + { 0xd10d, 0x65 }, { 0xd10e, 0x18 }, { 0xd10f, 0x00 }, { 0xd110, 0xa4 },
> + { 0xd111, 0x83 }, { 0xd112, 0xff }, { 0xd113, 0xff }, { 0xd114, 0xb8 },
> + { 0xd115, 0x64 }, { 0xd116, 0x00 }, { 0xd117, 0x48 }, { 0xd118, 0xd8 },
> + { 0xd119, 0x07 }, { 0xd11a, 0x18 }, { 0xd11b, 0x00 }, { 0xd11c, 0xd8 },
> + { 0xd11d, 0x08 }, { 0xd11e, 0x20 }, { 0xd11f, 0x00 }, { 0xd120, 0x9c },
> + { 0xd121, 0x60 }, { 0xd122, 0x00 }, { 0xd123, 0x00 }, { 0xd124, 0xd8 },
> + { 0xd125, 0x06 }, { 0xd126, 0x18 }, { 0xd127, 0x00 }, { 0xd128, 0x00 },
> + { 0xd129, 0x00 }, { 0xd12a, 0x00 }, { 0xd12b, 0x08 }, { 0xd12c, 0x15 },
> + { 0xd12d, 0x00 }, { 0xd12e, 0x00 }, { 0xd12f, 0x00 }, { 0xd130, 0x8c },
> + { 0xd131, 0x6a }, { 0xd132, 0x00 }, { 0xd133, 0x76 }, { 0xd134, 0xbc },
> + { 0xd135, 0x23 }, { 0xd136, 0x00 }, { 0xd137, 0x00 }, { 0xd138, 0x13 },
> + { 0xd139, 0xff }, { 0xd13a, 0xff }, { 0xd13b, 0xe6 }, { 0xd13c, 0x18 },
> + { 0xd13d, 0x60 }, { 0xd13e, 0x80 }, { 0xd13f, 0x06 }, { 0xd140, 0x03 },
> + { 0xd141, 0xff }, { 0xd142, 0xff }, { 0xd143, 0xdd }, { 0xd144, 0xa8 },
> + { 0xd145, 0x83 }, { 0xd146, 0x40 }, { 0xd147, 0x08 }, { 0xd148, 0x85 },
> + { 0xd149, 0x21 }, { 0xd14a, 0x00 }, { 0xd14b, 0x00 }, { 0xd14c, 0x85 },
> + { 0xd14d, 0x41 }, { 0xd14e, 0x00 }, { 0xd14f, 0x04 }, { 0xd150, 0x44 },
> + { 0xd151, 0x00 }, { 0xd152, 0x48 }, { 0xd153, 0x00 }, { 0xd154, 0x9c },
> + { 0xd155, 0x21 }, { 0xd156, 0x00 }, { 0xd157, 0x08 }, { 0x6f0e, 0x03 },
> + { 0x6f0f, 0x00 }, { 0x460e, 0x08 }, { 0x460f, 0x01 }, { 0x4610, 0x00 },
> + { 0x4611, 0x01 }, { 0x4612, 0x00 }, { 0x4613, 0x01 },
> + /* 8 bits */
> + { 0x4605, 0x08 },
> + /* Swap data bits order [9:0] -> [0:9] */
> + { 0x4709, 0x10 }, { 0x4608, 0x00 }, { 0x4609, 0x08 }, { 0x6804, 0x00 },
> + { 0x6805, 0x06 }, { 0x6806, 0x00 }, { 0x5120, 0x00 }, { 0x3510, 0x00 },
> + { 0x3504, 0x00 }, { 0x6800, 0x00 }, { 0x6f0d, 0x01 },
> + /* PCLK falling edge */
> + { 0x4708, 0x01 }, { 0x5000, 0xff }, { 0x5001, 0xbf }, { 0x5002, 0x7e },
> + { 0x503d, 0x00 }, { 0xc450, 0x01 }, { 0xc452, 0x04 }, { 0xc453, 0x00 },
> + { 0xc454, 0x00 }, { 0xc455, 0x01 }, { 0xc456, 0x01 }, { 0xc457, 0x00 },
> + { 0xc458, 0x00 }, { 0xc459, 0x00 }, { 0xc45b, 0x00 }, { 0xc45c, 0x01 },
> + { 0xc45d, 0x00 }, { 0xc45e, 0x00 }, { 0xc45f, 0x00 }, { 0xc460, 0x00 },
> + { 0xc461, 0x01 }, { 0xc462, 0x01 }, { 0xc464, 0x03 }, { 0xc465, 0x00 },
> + { 0xc466, 0x8a }, { 0xc467, 0x00 }, { 0xc468, 0x86 }, { 0xc469, 0x00 },
> + { 0xc46a, 0x40 }, { 0xc46b, 0x50 }, { 0xc46c, 0x30 }, { 0xc46d, 0x28 },
> + { 0xc46e, 0x60 }, { 0xc46f, 0x40 }, { 0xc47c, 0x01 }, { 0xc47d, 0x38 },
> + { 0xc47e, 0x00 }, { 0xc47f, 0x00 }, { 0xc480, 0x00 }, { 0xc481, 0xff },
> + { 0xc482, 0x00 }, { 0xc483, 0x40 }, { 0xc484, 0x00 }, { 0xc485, 0x18 },
> + { 0xc486, 0x00 }, { 0xc487, 0x18 },
> + { 0xc488, (OV10635_VTS - 8) * 16 >> 8},
> + { 0xc489, (OV10635_VTS - 8) * 16 & 0xff},
> + { 0xc48a, (OV10635_VTS - 8) * 16 >> 8},
> + { 0xc48b, (OV10635_VTS - 8) * 16 & 0xff}, { 0xc48c, 0x00 },
> + { 0xc48d, 0x04 }, { 0xc48e, 0x00 }, { 0xc48f, 0x04 }, { 0xc490, 0x03 },
> + { 0xc492, 0x20 }, { 0xc493, 0x08 }, { 0xc498, 0x02 }, { 0xc499, 0x00 },
> + { 0xc49a, 0x02 }, { 0xc49b, 0x00 }, { 0xc49c, 0x02 }, { 0xc49d, 0x00 },
> + { 0xc49e, 0x02 }, { 0xc49f, 0x60 }, { 0xc4a0, 0x03 }, { 0xc4a1, 0x00 },
> + { 0xc4a2, 0x04 }, { 0xc4a3, 0x00 }, { 0xc4a4, 0x00 }, { 0xc4a5, 0x10 },
> + { 0xc4a6, 0x00 }, { 0xc4a7, 0x40 }, { 0xc4a8, 0x00 }, { 0xc4a9, 0x80 },
> + { 0xc4aa, 0x0d }, { 0xc4ab, 0x00 }, { 0xc4ac, 0x0f }, { 0xc4ad, 0xc0 },
> + { 0xc4b4, 0x01 }, { 0xc4b5, 0x01 }, { 0xc4b6, 0x00 }, { 0xc4b7, 0x01 },
> + { 0xc4b8, 0x00 }, { 0xc4b9, 0x01 }, { 0xc4ba, 0x01 }, { 0xc4bb, 0x00 },
> + { 0xc4bc, 0x01 }, { 0xc4bd, 0x60 }, { 0xc4be, 0x02 }, { 0xc4bf, 0x33 },
> + { 0xc4c8, 0x03 }, { 0xc4c9, 0xd0 }, { 0xc4ca, 0x0e }, { 0xc4cb, 0x00 },
> + { 0xc4cc, 0x0e }, { 0xc4cd, 0x51 }, { 0xc4ce, 0x0e }, { 0xc4cf, 0x51 },
> + { 0xc4d0, 0x04 }, { 0xc4d1, 0x80 }, { 0xc4e0, 0x04 }, { 0xc4e1, 0x02 },
> + { 0xc4e2, 0x01 }, { 0xc4e4, 0x10 }, { 0xc4e5, 0x20 }, { 0xc4e6, 0x30 },
> + { 0xc4e7, 0x40 }, { 0xc4e8, 0x50 }, { 0xc4e9, 0x60 }, { 0xc4ea, 0x70 },
> + { 0xc4eb, 0x80 }, { 0xc4ec, 0x90 }, { 0xc4ed, 0xa0 }, { 0xc4ee, 0xb0 },
> + { 0xc4ef, 0xc0 }, { 0xc4f0, 0xd0 }, { 0xc4f1, 0xe0 }, { 0xc4f2, 0xf0 },
> + { 0xc4f3, 0x80 }, { 0xc4f4, 0x00 }, { 0xc4f5, 0x20 }, { 0xc4f6, 0x02 },
> + { 0xc4f7, 0x00 }, { 0xc4f8, 0x00 }, { 0xc4f9, 0x00 }, { 0xc4fa, 0x00 },
> + { 0xc4fb, 0x01 }, { 0xc4fc, 0x01 }, { 0xc4fd, 0x00 }, { 0xc4fe, 0x04 },
> + { 0xc4ff, 0x02 }, { 0xc500, 0x48 }, { 0xc501, 0x74 }, { 0xc502, 0x58 },
> + { 0xc503, 0x80 }, { 0xc504, 0x05 }, { 0xc505, 0x80 }, { 0xc506, 0x03 },
> + { 0xc507, 0x80 }, { 0xc508, 0x01 }, { 0xc509, 0xc0 }, { 0xc50a, 0x01 },
> + { 0xc50b, 0xa0 }, { 0xc50c, 0x01 }, { 0xc50d, 0x2c }, { 0xc50e, 0x01 },
> + { 0xc50f, 0x0a }, { 0xc510, 0x00 }, { 0xc511, 0x00 }, { 0xc512, 0xe5 },
> + { 0xc513, 0x14 }, { 0xc514, 0x04 }, { 0xc515, 0x00 }, { 0xc518, OV10635_VTS >> 8},
> + { 0xc519, OV10635_VTS & 0xff}, { 0xc51a, OV10635_HTS >> 8},
> + { 0xc51b, OV10635_HTS & 0xff}, { 0xc2e0, 0x00 }, { 0xc2e1, 0x51 },
> + { 0xc2e2, 0x00 }, { 0xc2e3, 0xd6 }, { 0xc2e4, 0x01 }, { 0xc2e5, 0x5e },
> + { 0xc2e9, 0x01 }, { 0xc2ea, 0x7a }, { 0xc2eb, 0x90 }, { 0xc2ed, 0x00 },
> + { 0xc2ee, 0x7a }, { 0xc2ef, 0x64 }, { 0xc308, 0x00 }, { 0xc309, 0x00 },
> + { 0xc30a, 0x00 }, { 0xc30c, 0x00 }, { 0xc30d, 0x01 }, { 0xc30e, 0x00 },
> + { 0xc30f, 0x00 }, { 0xc310, 0x01 }, { 0xc311, 0x60 }, { 0xc312, 0xff },
> + { 0xc313, 0x08 }, { 0xc314, 0x01 }, { 0xc315, 0x00 }, { 0xc316, 0xff },
> + { 0xc317, 0x0b }, { 0xc318, 0x00 }, { 0xc319, 0x0c }, { 0xc31a, 0x00 },
> + { 0xc31b, 0xe0 }, { 0xc31c, 0x00 }, { 0xc31d, 0x14 }, { 0xc31e, 0x00 },
> + { 0xc31f, 0xc5 }, { 0xc320, 0xff }, { 0xc321, 0x4b }, { 0xc322, 0xff },
> + { 0xc323, 0xf0 }, { 0xc324, 0xff }, { 0xc325, 0xe8 }, { 0xc326, 0x00 },
> + { 0xc327, 0x46 }, { 0xc328, 0xff }, { 0xc329, 0xd2 }, { 0xc32a, 0xff },
> + { 0xc32b, 0xe4 }, { 0xc32c, 0xff }, { 0xc32d, 0xbb }, { 0xc32e, 0x00 },
> + { 0xc32f, 0x61 }, { 0xc330, 0xff }, { 0xc331, 0xf9 }, { 0xc332, 0x00 },
> + { 0xc333, 0xd9 }, { 0xc334, 0x00 }, { 0xc335, 0x2e }, { 0xc336, 0x00 },
> + { 0xc337, 0xb1 }, { 0xc338, 0xff }, { 0xc339, 0x64 }, { 0xc33a, 0xff },
> + { 0xc33b, 0xeb }, { 0xc33c, 0xff }, { 0xc33d, 0xe8 }, { 0xc33e, 0x00 },
> + { 0xc33f, 0x48 }, { 0xc340, 0xff }, { 0xc341, 0xd0 }, { 0xc342, 0xff },
> + { 0xc343, 0xed }, { 0xc344, 0xff }, { 0xc345, 0xad }, { 0xc346, 0x00 },
> + { 0xc347, 0x66 }, { 0xc348, 0x01 }, { 0xc349, 0x00 }, { 0x6700, 0x04 },
> + { 0x6701, 0x7b }, { 0x6702, 0xfd }, { 0x6703, 0xf9 }, { 0x6704, 0x3d },
> + { 0x6705, 0x71 }, { 0x6706, 0x78 }, { 0x6708, 0x05 }, { 0x6f06, 0x6f },
> + { 0x6f07, 0x00 }, { 0x6f0a, 0x6f }, { 0x6f0b, 0x00 }, { 0x6f00, 0x03 },
> + { 0xc34c, 0x01 }, { 0xc34d, 0x00 }, { 0xc34e, 0x46 }, { 0xc34f, 0x55 },
> + { 0xc350, 0x00 }, { 0xc351, 0x40 }, { 0xc352, 0x00 }, { 0xc353, 0xff },
> + { 0xc354, 0x04 }, { 0xc355, 0x08 }, { 0xc356, 0x01 }, { 0xc357, 0xef },
> + { 0xc358, 0x30 }, { 0xc359, 0x01 }, { 0xc35a, 0x64 }, { 0xc35b, 0x46 },
> + { 0xc35c, 0x00 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 },
> + { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 },
> + { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 },
> + { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 },
> + { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 },
> + { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 },
> + { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0x3042, 0xf0 }, { 0xc261, 0x01 },
> + { 0x301b, 0xf0 }, { 0x301c, 0xf0 }, { 0x301a, 0xf0 }, { 0x6f00, 0xc3 },
> + { 0xc46a, 0x30 }, { 0xc46d, 0x20 }, { 0xc464, 0x84 }, { 0xc465, 0x00 },
> + { 0x6f00, 0x03 }, { 0x6f00, 0x43 }, { 0x381c, 0x00 }, { 0x381d, 0x40 },
> + { 0xc454, 0x01 }, { 0x6f00, 0xc3 }, { 0xc454, 0x00 }, { 0xc4b1, 0x02 },
> + { 0xc4b2, 0x01 }, { 0xc4b3, 0x03 }, { 0x6f00, 0x03 }, { 0x6f00, 0x43 },
> + /* enable FSIN (FRAMESYNC input) functionality */
> + { 0x3832, (0x0d + 2 * 0x20 + 0x15 + 38) >> 8 },
> + { 0x3833, (0x0d + 2 * 0x20 + 0x15 + 38) & 0xff },
> + { 0x3834, OV10635_VTS >> 8 }, { 0x3835, OV10635_VTS & 0xff },
> + { 0x302e, 0x01 },
> +};
> +
> +struct rdacm20_device {
> + struct device *dev;
> + struct max9271_device *serializer;
> + struct i2c_client *sensor;
> + struct v4l2_subdev sd;
> + struct media_pad pad;
> + struct v4l2_ctrl_handler ctrls;
> + u32 addrs[2];
> +};
> +
> +static inline struct rdacm20_device *sd_to_rdacm20(struct v4l2_subdev *sd)
> +{
> + return container_of(sd, struct rdacm20_device, sd);
> +}
> +
> +static inline struct rdacm20_device *i2c_to_rdacm20(struct i2c_client *client)
> +{
> + return sd_to_rdacm20(i2c_get_clientdata(client));
> +}
> +
> +static int ov10635_read16(struct rdacm20_device *dev, u16 reg)
> +{
> + u8 buf[2] = { reg >> 8, reg & 0xff };
> + int ret;
> +
> + ret = i2c_master_send(dev->sensor, buf, 2);
> + if (ret != 2) {
> + dev_dbg(dev->dev, "%s: register 0x%04x write failed (%d)\n",
> + __func__, reg, ret);
> + return ret;
> + }
> +
> + ret = i2c_master_recv(dev->sensor, buf, 2);
> + if (ret < 0) {
> + dev_dbg(dev->dev, "%s: register 0x%04x read failed (%d)\n",
> + __func__, reg, ret);
> + return ret;
> + }
> +
> + return (buf[0] << 8) | buf[1];
> +}
> +
> +static int __ov10635_write(struct rdacm20_device *dev, u16 reg, u8 val)
> +{
> + u8 buf[3] = { reg >> 8, reg & 0xff, val };
> + int ret;
> +
> + dev_dbg(dev->dev, "%s(0x%04x, 0x%02x)\n", __func__, reg, val);
> +
> + ret = i2c_master_send(dev->sensor, buf, 3);
> + return ret < 0 ? ret : 0;
> +}
> +
> +static int ov10635_write(struct rdacm20_device *dev, u16 reg, u8 val)
> +{
> + int ret;
> +
> + ret = __ov10635_write(dev, reg, val);
> + if (ret < 0)
> + dev_err(dev->dev, "%s: register 0x%04x write failed (%d)\n",
> + __func__, reg, ret);
> +
> + return ret;
> +}
> +
> +static int ov10635_set_regs(struct rdacm20_device *dev,
> + const struct ov10635_reg *regs,
> + unsigned int nr_regs)
> +{
> + unsigned int i;
> + int ret;
> +
> + for (i = 0; i < nr_regs; i++) {
> + ret = __ov10635_write(dev, regs[i].reg, regs[i].val);
> + if (ret) {
> + dev_err(dev->dev,
> + "%s: register %u (0x%04x) write failed (%d)\n",
> + __func__, i, regs[i].reg, ret);
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int rdacm20_s_stream(struct v4l2_subdev *sd, int enable)
> +{
> + struct rdacm20_device *dev = sd_to_rdacm20(sd);
> +
> + return max9271_set_serial_link(dev->serializer, enable);
> +}
> +
> +static int rdacm20_enum_mbus_code(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_mbus_code_enum *code)
> +{
> + if (code->pad || code->index > 0)
> + return -EINVAL;
> +
> + code->code = MEDIA_BUS_FMT_UYVY8_2X8;
> +
> + return 0;
> +}
> +
> +static int rdacm20_get_fmt(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_format *format)
> +{
> + struct v4l2_mbus_framefmt *mf = &format->format;
> +
> + if (format->pad)
> + return -EINVAL;
> +
> + mf->width = OV10635_WIDTH;
> + mf->height = OV10635_HEIGHT;
> + mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
> + mf->colorspace = V4L2_COLORSPACE_RAW;
> + mf->field = V4L2_FIELD_NONE;
> + mf->ycbcr_enc = V4L2_YCBCR_ENC_601;
> + mf->quantization = V4L2_QUANTIZATION_FULL_RANGE;
> + mf->xfer_func = V4L2_XFER_FUNC_NONE;
> +
> + return 0;
> +}
> +
> +static struct v4l2_subdev_video_ops rdacm20_video_ops = {
> + .s_stream = rdacm20_s_stream,
> +};
> +
> +static const struct v4l2_subdev_pad_ops rdacm20_subdev_pad_ops = {
> + .enum_mbus_code = rdacm20_enum_mbus_code,
> + .get_fmt = rdacm20_get_fmt,
> + .set_fmt = rdacm20_get_fmt,
> +};
> +
> +static struct v4l2_subdev_ops rdacm20_subdev_ops = {
> + .video = &rdacm20_video_ops,
> + .pad = &rdacm20_subdev_pad_ops,
> +};
> +
> +static int rdacm20_initialize(struct rdacm20_device *dev)
> +{
> + unsigned int retry = 3;
> + int ret;
> +
> + /* Verify communication with the MAX9271: ping to wakeup. */
> + dev->serializer->client->addr = MAX9271_DEFAULT_ADDR;
> + i2c_smbus_read_byte(dev->serializer->client);
> +
> + /* Serial link disabled during config as it needs a valid pixel clock. */
> + ret = max9271_set_serial_link(dev->serializer, false);
> + if (ret)
> + return ret;
> +
> + /*
> + * Ensure that we have a good link configuration before attempting to
> + * identify the device.
> + */
> + max9271_configure_i2c(dev->serializer, MAX9271_I2CSLVSH_469NS_234NS |
> + MAX9271_I2CSLVTO_1024US |
> + MAX9271_I2CMSTBT_105KBPS);
> +
> + max9271_configure_gmsl_link(dev->serializer);
> +
> + ret = max9271_verify_id(dev->serializer);
> + if (ret < 0)
> + return ret;
> +
> + ret = max9271_set_address(dev->serializer, dev->addrs[0]);
> + if (ret < 0)
> + return ret;
> + dev->serializer->client->addr = dev->addrs[0];
> +
> + /*
> + * Reset the sensor by cycling the OV10635 reset signal connected to the
> + * MAX9271 GPIO1 and verify communication with the OV10635.
> + */
> + max9271_clear_gpios(dev->serializer, MAX9271_GPIO1OUT);
> + usleep_range(10000, 15000);
> + max9271_set_gpios(dev->serializer, MAX9271_GPIO1OUT);
> + usleep_range(10000, 15000);
> +
> +again:
> + ret = ov10635_read16(dev, OV10635_PID);
> + if (ret < 0) {
> + if (retry--)
> + goto again;
> +
> + dev_err(dev->dev, "OV10635 ID read failed (%d)\n",
> + ret);
> + return -ENXIO;
> + }
> +
> + if (ret != OV10635_VERSION) {
> + if (retry--)
> + goto again;
> +
> + dev_err(dev->dev, "OV10635 ID mismatch (0x%04x)\n",
> + ret);
> + return -ENXIO;
> + }
> +
> + /* Change the sensor I2C address. */
> + ret = ov10635_write(dev, OV10635_SC_CMMN_SCCB_ID,
> + (dev->addrs[1] << 1) |
> + OV10635_SC_CMMN_SCCB_ID_SELECT);
> + if (ret < 0) {
> + dev_err(dev->dev,
> + "OV10635 I2C address change failed (%d)\n", ret);
> + return ret;
> + }
> + dev->sensor->addr = dev->addrs[1];
> + usleep_range(3500, 5000);
> +
> + /* Program the 0V10635 initial configuration. */
> + ret = ov10635_set_regs(dev, ov10635_regs_wizard,
> + ARRAY_SIZE(ov10635_regs_wizard));
> + if (ret)
> + return ret;
> +
> + dev_info(dev->dev, "Identified MAX9271 + OV10635 device\n");
> +
> + return 0;
> +}
> +
> +static int rdacm20_probe(struct i2c_client *client)
> +{
> + struct rdacm20_device *dev;
> + struct fwnode_handle *ep;
> + int ret;
> +
> + dev = devm_kzalloc(&client->dev, sizeof(*dev), GFP_KERNEL);
> + if (!dev)
> + return -ENOMEM;
> + dev->dev = &client->dev;
> +
> + dev->serializer = devm_kzalloc(&client->dev, sizeof(*dev->serializer),
> + GFP_KERNEL);
> + if (!dev->serializer)
> + return -ENOMEM;
> +
> + dev->serializer->client = client;
> +
> + ret = of_property_read_u32_array(client->dev.of_node, "reg",
> + dev->addrs, 2);
> + if (ret < 0) {
> + dev_err(dev->dev, "Invalid DT reg property: %d\n", ret);
> + return -EINVAL;
> + }
> +
> + /* Create the dummy I2C client for the sensor. */
> + dev->sensor = i2c_new_dummy_device(client->adapter,
> + OV10635_I2C_ADDRESS);
> + if (IS_ERR(dev->sensor)) {
> + ret = PTR_ERR(dev->sensor);
> + goto error;
> + }
> +
> + /* Initialize the hardware. */
> + ret = rdacm20_initialize(dev);
> + if (ret < 0)
> + goto error;
> +
> + /* Initialize and register the subdevice. */
> + v4l2_i2c_subdev_init(&dev->sd, client, &rdacm20_subdev_ops);
> + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
> +
> + v4l2_ctrl_handler_init(&dev->ctrls, 1);
> + v4l2_ctrl_new_std(&dev->ctrls, NULL, V4L2_CID_PIXEL_RATE,
> + OV10635_PIXEL_RATE, OV10635_PIXEL_RATE, 1,
> + OV10635_PIXEL_RATE);
> + dev->sd.ctrl_handler = &dev->ctrls;
> +
> + ret = dev->ctrls.error;
> + if (ret)
> + goto error_free_ctrls;
> +
> + dev->pad.flags = MEDIA_PAD_FL_SOURCE;
> + dev->sd.entity.flags |= MEDIA_ENT_F_CAM_SENSOR;
> + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad);
> + if (ret < 0)
> + goto error_free_ctrls;
> +
> + ep = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL);
> + if (!ep) {
> + dev_err(&client->dev,
> + "Unable to get endpoint in node %pOF\n",
> + client->dev.of_node);
> + ret = -ENOENT;
> + goto error_free_ctrls;
> + }
> + dev->sd.fwnode = ep;
> +
> + ret = v4l2_async_register_subdev(&dev->sd);
> + if (ret)
> + goto error_put_node;
> +
> + return 0;
> +
> +error_put_node:
> + fwnode_handle_put(ep);
> +error_free_ctrls:
> + v4l2_ctrl_handler_free(&dev->ctrls);
> +error:
> + media_entity_cleanup(&dev->sd.entity);
> + if (dev->sensor)
> + i2c_unregister_device(dev->sensor);
> +
> + dev_err(&client->dev, "probe failed\n");
> +
> + return ret;
> +}
> +
> +static int rdacm20_remove(struct i2c_client *client)
> +{
> + struct rdacm20_device *dev = i2c_to_rdacm20(client);
> +
> + fwnode_handle_put(dev->sd.fwnode);
> + v4l2_async_unregister_subdev(&dev->sd);
> + v4l2_ctrl_handler_free(&dev->ctrls);
> + media_entity_cleanup(&dev->sd.entity);
> + i2c_unregister_device(dev->sensor);
> +
> + return 0;
> +}
> +
> +static void rdacm20_shutdown(struct i2c_client *client)
> +{
> + struct rdacm20_device *dev = i2c_to_rdacm20(client);
> +
> + /* make sure stream off during shutdown (reset/reboot) */
> + rdacm20_s_stream(&dev->sd, 0);
> +}
> +
> +static const struct of_device_id rdacm20_of_ids[] = {
> + { .compatible = "imi,rdacm20", },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, rdacm20_of_ids);
> +
> +static struct i2c_driver rdacm20_i2c_driver = {
> + .driver = {
> + .name = "rdacm20",
> + .of_match_table = rdacm20_of_ids,
> + },
> + .probe_new = rdacm20_probe,
> + .remove = rdacm20_remove,
> + .shutdown = rdacm20_shutdown,
> +};
> +
> +module_i2c_driver(rdacm20_i2c_driver);
> +
> +MODULE_DESCRIPTION("GMSL Camera driver for RDACM20");
> +MODULE_AUTHOR("Vladimir Barinov");
> +MODULE_LICENSE("GPL");
>
--
Regards
--
Kieran
^ permalink raw reply
* Re: [PATCH v10 2/4] media: i2c: Add MAX9286 driver
From: Kieran Bingham @ 2020-07-16 9:02 UTC (permalink / raw)
To: Kieran Bingham, linux-renesas-soc, linux-media, linux-gpio,
devicetree, linux-kernel, Mauro Carvalho Chehab, sakari.ailus
Cc: Laurent Pinchart, Jacopo Mondi, Niklas Söderlund,
Hans Verkuil, Hyun Kwon, Manivannan Sadhasivam, Rob Herring,
Linus Walleij, Jacopo Mondi, Laurent Pinchart,
Niklas Söderlund
In-Reply-To: <20200612144713.502006-3-kieran.bingham+renesas@ideasonboard.com>
Hi Sakari,
This is the output of checkpatch --strict on this driver. Sorry for not
detailing this in the commit or cover letter.
> ./patches/gmsl/v10/v10-0001-dt-bindings-media-i2c-Add-bindings-for-Maxim-Int.patch has style problems, please review.
> --------------------------------------------------------------
> ./patches/gmsl/v10/v10-0002-media-i2c-Add-MAX9286-driver.patch
> --------------------------------------------------------------
> CHECK: Prefer using the BIT macro
> #246: FILE: drivers/media/i2c/max9286.c:40:
> +#define MAX9286_FSYNCMODE_INT_OUT (1 << 6)
>
> CHECK: Prefer using the BIT macro
> #251: FILE: drivers/media/i2c/max9286.c:45:
> +#define MAX9286_FSYNCMETH_SEMI_AUTO (1 << 0)
>
> CHECK: Prefer using the BIT macro
> #262: FILE: drivers/media/i2c/max9286.c:56:
> +#define MAX9286_EDC_6BIT_CRC (1 << 5)
>
> CHECK: Prefer using the BIT macro
> #268: FILE: drivers/media/i2c/max9286.c:62:
> +#define MAX9286_HVSRC_D14 (1 << 0)
>
> CHECK: Prefer using the BIT macro
> #286: FILE: drivers/media/i2c/max9286.c:80:
> +#define MAX9286_DATATYPE_RGB565 (1 << 0)
>
> CHECK: Prefer using the BIT macro
> #304: FILE: drivers/media/i2c/max9286.c:98:
> +#define MAX9286_I2CSLVSH_469NS_234NS (1 << 5)
>
> CHECK: Prefer using the BIT macro
> #312: FILE: drivers/media/i2c/max9286.c:106:
> +#define MAX9286_I2CMSTBT_28KBPS (1 << 2)
>
> CHECK: Prefer using the BIT macro
> #316: FILE: drivers/media/i2c/max9286.c:110:
> +#define MAX9286_I2CSLVTO_256US (1 << 0)
None of those are appropriate to use the BIT() macro, as they are all
entries of a specific field with a shift, such as:
#define MAX9286_FSYNCMODE_ECU (3 << 6)
#define MAX9286_FSYNCMODE_EXT (2 << 6)
#define MAX9286_FSYNCMODE_INT_OUT (1 << 6)
#define MAX9286_FSYNCMODE_INT_HIZ (0 << 6)
Checkpatch is only picking up on the "1 << x" variant of each entry.
> CHECK: Macro argument reuse 'source' - possible side-effects?
> #399: FILE: drivers/media/i2c/max9286.c:193:
> +#define for_each_source(priv, source) \
> + for ((source) = NULL; ((source) = next_source((priv), (source))); )
This warns against possible side effects, but the 're-use' effects are
desired ;-)
If you'd prefer this macro to be re-written please let me know.
> CHECK: Lines should not end with a '('
> #1372: FILE: drivers/media/i2c/max9286.c:1166:
> + ret = v4l2_fwnode_endpoint_parse(
Full code block:
> ret = v4l2_fwnode_endpoint_parse(
> of_fwnode_handle(node), &vep);
> if (ret) {
> of_node_put(node);
> return ret;
> }
That one is awkward, and I chose to keep it as a lesser evil.
Of course now that we can officially go up to 120 chars, I could move
this line up.
If you'd like this to be moved to a single line now we can go over 80
chars, please confirm.
>
> CHECK: Lines should not end with a '('
> #1398: FILE: drivers/media/i2c/max9286.c:1192:
> + source->fwnode = fwnode_graph_get_remote_endpoint(
Same here, it was unavoidable to go over 80 chars, so this was the break
point.
If you would now like to join these lines, I can do so.
>
> total: 0 errors, 0 warnings, 11 checks, 1362 lines checked
--
Kieran
On 12/06/2020 15:47, Kieran Bingham wrote:
> The MAX9286 is a 4-channel GMSL deserializer with coax or STP input and
> CSI-2 output. The device supports multicamera streaming applications,
> and features the ability to synchronise the attached cameras.
>
> CSI-2 output can be configured with 1 to 4 lanes, and a control channel
> is supported over I2C, which implements an I2C mux to facilitate
> communications with connected cameras across the reverse control
> channel.
>
> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
>
> --
> v2:
> - Fix MAINTAINERS entry
>
> This posting is released with the following modifications to work
> without Sakari's VC developments:
> - max9286_g_mbus_config() re-instated
> - max9286_get_frame_desc() is not bus/csi aware
> - max9286_{get,set}_routing() removed
>
> v3:
> - Initialise notifier with v4l2_async_notifier_init
> - Update for new mbus csi2 format V4L2_MBUS_CSI2_DPHY
>
> v4: - Re-introduce required code to function with the VC series.
>
> - Implement max9286_get_routing, max9286_set_routing
> - Remove max9286_g_mbus_config
>
> v5: (internal release)
> - Fix printk formatting for hex value
> - max9286->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE (add |)
> - MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER -> MEDIA_ENT_F_VID_IF_BRIDGE
> - Remove 'device is bound' workaround
>
> v6:
> - v4l2_subdev_krouting instead of v4l2_subdev_routing separated
> to allow integration without the VC/V4L2-Mux series.
> - convert sd_to_max9286 to inline function
> - rename max9286_device to max9286_priv
> - Cleanup the v4l2_async_notifier
> - Extend MODULE_AUTHOR
> - Replace of_graph_get_endpoint_by_regs with fwnode_graph_get_endpoint_by_id
> - Pass default bus type when parsing fwnode endpoint (Manivannan Sadhasivam)
> - Use new YAML file reference in MAINTAINERS
> - Parse new i2c-mux node in max9286_get_i2c_by_id
> (This could/should be refactored to parse these separately first)
> - Spelling and calculation fixes in the FSYNC_LOCKED check comments
> - Identify each enabled i2c-mux channel in a single pass
> - max9286: Improve mux-state readbility [v2]
> - Fix frame sync lock durations
> - Add comment to describe /why/ we must open the mux in s_stream
> - use -EXDEV as return code for failed link synchronisation.
> - Fix reference counting of the dt nodeS
> - Convert to probe_new for I2C
> - Remove redundant max9286_i2c_mux_state
> - Provide optional enable-gpio (max9286-pwdn)
>
> v7:
> [Kieran]
> - Ensure powerdown lines are optional
> - Add a 4ms power-up delay
> - Add max9286_check_config_link() to core
> - Add GPIO chip controller for GPIO0OUT and GPIO1OUT
> - Fix GPIO registration
> - max9286: Split out async registration
> (fixes regulator -EPROBE_DEFERs failures)
> - Collect all V4L2 registrations
> - balance v4l2_async refcnting
> - Rename max9286_v4l2_async_ => max9286_v4l2_notifier_
>
> [Jacopo]
> - Remove redundanct MAXIM_I2C_SPEED macros
> - Move notifiers operations
> - Add delay after reverse channel reconfiguration
> - Move link setup to completion
> - Fix up max9286_check_config_link() implementation
> - Remove redundant dual configuration of reverse channel
>
> v8:
>
> [Kieran]
> - Update the bound_sources mask on unbind
> - Convert probe kzalloc usage to devm_ variant
> - Fix up cleanup path from GPIO PowerDown registration
> - cleanup GPIO device registration fail path
> - Convert to use devm_regulator_get()
> - Fit max9286_parse_dt print on one line
> - Move multi-device workarounds out of upstream driver
> - Remove I2C mod-table
> - Lock format changes
> - Describe pad index usage
> - Remove poc_enabled workaround
> - Rename the max9286_gpio to be more explicit on it's actions.
> - Move max9286_init_format call
> - Rework probe sequence and simplify error paths.
> - Simplify i2c comments
> - Implement Pixelrate control
> - Disable overlap window
>
> [Jacopo]
> - Adapt Kconfig to latest upstream changes
> - Put of node on error
> - Calculate pixel rate
> - Simplify overlap window disablement
>
> v9:
>
> [Kieran]
> - Kconfig: Depend on OF
> - Re-sort addition to Makefile
>
> v10:
>
> [Kieran]
> - Use the same default mbus_fmt everywhere
> - Don't provide GPIO names
> - Fix dev->of_node refcnting
> - Fix whitespace indent
> - Use single sample per pixel
> - Remove redundant DPHY check
> - Remove redundant v4l2_fwnode_endpoint_free call
> - Validate link formats
> ---
> MAINTAINERS | 10 +
> drivers/media/i2c/Kconfig | 13 +
> drivers/media/i2c/Makefile | 1 +
> drivers/media/i2c/max9286.c | 1320 +++++++++++++++++++++++++++++++++++
> 4 files changed, 1344 insertions(+)
> create mode 100644 drivers/media/i2c/max9286.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 791d2a862e41..7534df72033f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -10274,6 +10274,16 @@ F: Documentation/hwmon/max6697.rst
> F: drivers/hwmon/max6697.c
> F: include/linux/platform_data/max6697.h
>
> +MAX9286 QUAD GMSL DESERIALIZER DRIVER
> +M: Jacopo Mondi <jacopo+renesas@jmondi.org>
> +M: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
> +M: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> +M: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> +L: linux-media@vger.kernel.org
> +S: Maintained
> +F: Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml
> +F: drivers/media/i2c/max9286.c
> +
> MAX9860 MONO AUDIO VOICE CODEC DRIVER
> M: Peter Rosin <peda@axentia.se>
> L: alsa-devel@alsa-project.org (moderated for non-subscribers)
> diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
> index da11036ad804..0a083407aa3e 100644
> --- a/drivers/media/i2c/Kconfig
> +++ b/drivers/media/i2c/Kconfig
> @@ -464,6 +464,19 @@ config VIDEO_VPX3220
> To compile this driver as a module, choose M here: the
> module will be called vpx3220.
>
> +config VIDEO_MAX9286
> + tristate "Maxim MAX9286 GMSL deserializer support"
> + depends on I2C && I2C_MUX
> + depends on OF
> + select V4L2_FWNODE
> + select VIDEO_V4L2_SUBDEV_API
> + select MEDIA_CONTROLLER
> + help
> + This driver supports the Maxim MAX9286 GMSL deserializer.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called max9286.
> +
> comment "Video and audio decoders"
>
> config VIDEO_SAA717X
> diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
> index 993acab81b2c..c8010d77e1a3 100644
> --- a/drivers/media/i2c/Makefile
> +++ b/drivers/media/i2c/Makefile
> @@ -118,6 +118,7 @@ obj-$(CONFIG_VIDEO_IMX274) += imx274.o
> obj-$(CONFIG_VIDEO_IMX290) += imx290.o
> obj-$(CONFIG_VIDEO_IMX319) += imx319.o
> obj-$(CONFIG_VIDEO_IMX355) += imx355.o
> +obj-$(CONFIG_VIDEO_MAX9286) += max9286.o
> obj-$(CONFIG_VIDEO_ST_MIPID02) += st-mipid02.o
>
> obj-$(CONFIG_SDR_MAX2175) += max2175.o
> diff --git a/drivers/media/i2c/max9286.c b/drivers/media/i2c/max9286.c
> new file mode 100644
> index 000000000000..47f280518fdb
> --- /dev/null
> +++ b/drivers/media/i2c/max9286.c
> @@ -0,0 +1,1320 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Maxim MAX9286 GMSL Deserializer Driver
> + *
> + * Copyright (C) 2017-2019 Jacopo Mondi
> + * Copyright (C) 2017-2019 Kieran Bingham
> + * Copyright (C) 2017-2019 Laurent Pinchart
> + * Copyright (C) 2017-2019 Niklas Söderlund
> + * Copyright (C) 2016 Renesas Electronics Corporation
> + * Copyright (C) 2015 Cogent Embedded, Inc.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/fwnode.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/gpio/driver.h>
> +#include <linux/i2c.h>
> +#include <linux/i2c-mux.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/of_graph.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/slab.h>
> +
> +#include <media/v4l2-async.h>
> +#include <media/v4l2-ctrls.h>
> +#include <media/v4l2-device.h>
> +#include <media/v4l2-fwnode.h>
> +#include <media/v4l2-subdev.h>
> +
> +/* Register 0x00 */
> +#define MAX9286_MSTLINKSEL_AUTO (7 << 5)
> +#define MAX9286_MSTLINKSEL(n) ((n) << 5)
> +#define MAX9286_EN_VS_GEN BIT(4)
> +#define MAX9286_LINKEN(n) (1 << (n))
> +/* Register 0x01 */
> +#define MAX9286_FSYNCMODE_ECU (3 << 6)
> +#define MAX9286_FSYNCMODE_EXT (2 << 6)
> +#define MAX9286_FSYNCMODE_INT_OUT (1 << 6)
> +#define MAX9286_FSYNCMODE_INT_HIZ (0 << 6)
> +#define MAX9286_GPIEN BIT(5)
> +#define MAX9286_ENLMO_RSTFSYNC BIT(2)
> +#define MAX9286_FSYNCMETH_AUTO (2 << 0)
> +#define MAX9286_FSYNCMETH_SEMI_AUTO (1 << 0)
> +#define MAX9286_FSYNCMETH_MANUAL (0 << 0)
> +#define MAX9286_REG_FSYNC_PERIOD_L 0x06
> +#define MAX9286_REG_FSYNC_PERIOD_M 0x07
> +#define MAX9286_REG_FSYNC_PERIOD_H 0x08
> +/* Register 0x0a */
> +#define MAX9286_FWDCCEN(n) (1 << ((n) + 4))
> +#define MAX9286_REVCCEN(n) (1 << (n))
> +/* Register 0x0c */
> +#define MAX9286_HVEN BIT(7)
> +#define MAX9286_EDC_6BIT_HAMMING (2 << 5)
> +#define MAX9286_EDC_6BIT_CRC (1 << 5)
> +#define MAX9286_EDC_1BIT_PARITY (0 << 5)
> +#define MAX9286_DESEL BIT(4)
> +#define MAX9286_INVVS BIT(3)
> +#define MAX9286_INVHS BIT(2)
> +#define MAX9286_HVSRC_D0 (2 << 0)
> +#define MAX9286_HVSRC_D14 (1 << 0)
> +#define MAX9286_HVSRC_D18 (0 << 0)
> +/* Register 0x0f */
> +#define MAX9286_0X0F_RESERVED BIT(3)
> +/* Register 0x12 */
> +#define MAX9286_CSILANECNT(n) (((n) - 1) << 6)
> +#define MAX9286_CSIDBL BIT(5)
> +#define MAX9286_DBL BIT(4)
> +#define MAX9286_DATATYPE_USER_8BIT (11 << 0)
> +#define MAX9286_DATATYPE_USER_YUV_12BIT (10 << 0)
> +#define MAX9286_DATATYPE_USER_24BIT (9 << 0)
> +#define MAX9286_DATATYPE_RAW14 (8 << 0)
> +#define MAX9286_DATATYPE_RAW11 (7 << 0)
> +#define MAX9286_DATATYPE_RAW10 (6 << 0)
> +#define MAX9286_DATATYPE_RAW8 (5 << 0)
> +#define MAX9286_DATATYPE_YUV422_10BIT (4 << 0)
> +#define MAX9286_DATATYPE_YUV422_8BIT (3 << 0)
> +#define MAX9286_DATATYPE_RGB555 (2 << 0)
> +#define MAX9286_DATATYPE_RGB565 (1 << 0)
> +#define MAX9286_DATATYPE_RGB888 (0 << 0)
> +/* Register 0x15 */
> +#define MAX9286_VC(n) ((n) << 5)
> +#define MAX9286_VCTYPE BIT(4)
> +#define MAX9286_CSIOUTEN BIT(3)
> +#define MAX9286_0X15_RESV (3 << 0)
> +/* Register 0x1b */
> +#define MAX9286_SWITCHIN(n) (1 << ((n) + 4))
> +#define MAX9286_ENEQ(n) (1 << (n))
> +/* Register 0x27 */
> +#define MAX9286_LOCKED BIT(7)
> +/* Register 0x31 */
> +#define MAX9286_FSYNC_LOCKED BIT(6)
> +/* Register 0x34 */
> +#define MAX9286_I2CLOCACK BIT(7)
> +#define MAX9286_I2CSLVSH_1046NS_469NS (3 << 5)
> +#define MAX9286_I2CSLVSH_938NS_352NS (2 << 5)
> +#define MAX9286_I2CSLVSH_469NS_234NS (1 << 5)
> +#define MAX9286_I2CSLVSH_352NS_117NS (0 << 5)
> +#define MAX9286_I2CMSTBT_837KBPS (7 << 2)
> +#define MAX9286_I2CMSTBT_533KBPS (6 << 2)
> +#define MAX9286_I2CMSTBT_339KBPS (5 << 2)
> +#define MAX9286_I2CMSTBT_173KBPS (4 << 2)
> +#define MAX9286_I2CMSTBT_105KBPS (3 << 2)
> +#define MAX9286_I2CMSTBT_84KBPS (2 << 2)
> +#define MAX9286_I2CMSTBT_28KBPS (1 << 2)
> +#define MAX9286_I2CMSTBT_8KBPS (0 << 2)
> +#define MAX9286_I2CSLVTO_NONE (3 << 0)
> +#define MAX9286_I2CSLVTO_1024US (2 << 0)
> +#define MAX9286_I2CSLVTO_256US (1 << 0)
> +#define MAX9286_I2CSLVTO_64US (0 << 0)
> +/* Register 0x3b */
> +#define MAX9286_REV_TRF(n) ((n) << 4)
> +#define MAX9286_REV_AMP(n) ((((n) - 30) / 10) << 1) /* in mV */
> +#define MAX9286_REV_AMP_X BIT(0)
> +/* Register 0x3f */
> +#define MAX9286_EN_REV_CFG BIT(6)
> +#define MAX9286_REV_FLEN(n) ((n) - 20)
> +/* Register 0x49 */
> +#define MAX9286_VIDEO_DETECT_MASK 0x0f
> +/* Register 0x69 */
> +#define MAX9286_LFLTBMONMASKED BIT(7)
> +#define MAX9286_LOCKMONMASKED BIT(6)
> +#define MAX9286_AUTOCOMBACKEN BIT(5)
> +#define MAX9286_AUTOMASKEN BIT(4)
> +#define MAX9286_MASKLINK(n) ((n) << 0)
> +
> +/*
> + * The sink and source pads are created to match the OF graph port numbers so
> + * that their indexes can be used interchangeably.
> + */
> +#define MAX9286_NUM_GMSL 4
> +#define MAX9286_N_SINKS 4
> +#define MAX9286_N_PADS 5
> +#define MAX9286_SRC_PAD 4
> +
> +struct max9286_source {
> + struct v4l2_async_subdev asd;
> + struct v4l2_subdev *sd;
> + struct fwnode_handle *fwnode;
> +};
> +
> +#define asd_to_max9286_source(_asd) \
> + container_of(_asd, struct max9286_source, asd)
> +
> +struct max9286_priv {
> + struct i2c_client *client;
> + struct gpio_desc *gpiod_pwdn;
> + struct v4l2_subdev sd;
> + struct media_pad pads[MAX9286_N_PADS];
> + struct regulator *regulator;
> +
> + struct gpio_chip gpio;
> + u8 gpio_state;
> +
> + struct i2c_mux_core *mux;
> + unsigned int mux_channel;
> + bool mux_open;
> +
> + struct v4l2_ctrl_handler ctrls;
> + struct v4l2_ctrl *pixelrate;
> +
> + struct v4l2_mbus_framefmt fmt[MAX9286_N_SINKS];
> +
> + /* Protects controls and fmt structures */
> + struct mutex mutex;
> +
> + unsigned int nsources;
> + unsigned int source_mask;
> + unsigned int route_mask;
> + unsigned int bound_sources;
> + unsigned int csi2_data_lanes;
> + struct max9286_source sources[MAX9286_NUM_GMSL];
> + struct v4l2_async_notifier notifier;
> +};
> +
> +static struct max9286_source *next_source(struct max9286_priv *priv,
> + struct max9286_source *source)
> +{
> + if (!source)
> + source = &priv->sources[0];
> + else
> + source++;
> +
> + for (; source < &priv->sources[MAX9286_NUM_GMSL]; source++) {
> + if (source->fwnode)
> + return source;
> + }
> +
> + return NULL;
> +}
> +
> +#define for_each_source(priv, source) \
> + for ((source) = NULL; ((source) = next_source((priv), (source))); )
> +
> +#define to_index(priv, source) ((source) - &(priv)->sources[0])
> +
> +static inline struct max9286_priv *sd_to_max9286(struct v4l2_subdev *sd)
> +{
> + return container_of(sd, struct max9286_priv, sd);
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * I2C IO
> + */
> +
> +static int max9286_read(struct max9286_priv *priv, u8 reg)
> +{
> + int ret;
> +
> + ret = i2c_smbus_read_byte_data(priv->client, reg);
> + if (ret < 0)
> + dev_err(&priv->client->dev,
> + "%s: register 0x%02x read failed (%d)\n",
> + __func__, reg, ret);
> +
> + return ret;
> +}
> +
> +static int max9286_write(struct max9286_priv *priv, u8 reg, u8 val)
> +{
> + int ret;
> +
> + ret = i2c_smbus_write_byte_data(priv->client, reg, val);
> + if (ret < 0)
> + dev_err(&priv->client->dev,
> + "%s: register 0x%02x write failed (%d)\n",
> + __func__, reg, ret);
> +
> + return ret;
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * I2C Multiplexer
> + */
> +
> +static void max9286_i2c_mux_configure(struct max9286_priv *priv, u8 conf)
> +{
> + max9286_write(priv, 0x0a, conf);
> +
> + /*
> + * We must sleep after any change to the forward or reverse channel
> + * configuration.
> + */
> + usleep_range(3000, 5000);
> +}
> +
> +static void max9286_i2c_mux_open(struct max9286_priv *priv)
> +{
> + /* Open all channels on the MAX9286 */
> + max9286_i2c_mux_configure(priv, 0xff);
> +
> + priv->mux_open = true;
> +}
> +
> +static void max9286_i2c_mux_close(struct max9286_priv *priv)
> +{
> + /*
> + * Ensure that both the forward and reverse channel are disabled on the
> + * mux, and that the channel ID is invalidated to ensure we reconfigure
> + * on the next max9286_i2c_mux_select() call.
> + */
> + max9286_i2c_mux_configure(priv, 0x00);
> +
> + priv->mux_open = false;
> + priv->mux_channel = -1;
> +}
> +
> +static int max9286_i2c_mux_select(struct i2c_mux_core *muxc, u32 chan)
> +{
> + struct max9286_priv *priv = i2c_mux_priv(muxc);
> +
> + /* Channel select is disabled when configured in the opened state. */
> + if (priv->mux_open)
> + return 0;
> +
> + if (priv->mux_channel == chan)
> + return 0;
> +
> + priv->mux_channel = chan;
> +
> + max9286_i2c_mux_configure(priv,
> + MAX9286_FWDCCEN(chan) |
> + MAX9286_REVCCEN(chan));
> +
> + return 0;
> +}
> +
> +static int max9286_i2c_mux_init(struct max9286_priv *priv)
> +{
> + struct max9286_source *source;
> + int ret;
> +
> + if (!i2c_check_functionality(priv->client->adapter,
> + I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
> + return -ENODEV;
> +
> + priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev,
> + priv->nsources, 0, I2C_MUX_LOCKED,
> + max9286_i2c_mux_select, NULL);
> + if (!priv->mux)
> + return -ENOMEM;
> +
> + priv->mux->priv = priv;
> +
> + for_each_source(priv, source) {
> + unsigned int index = to_index(priv, source);
> +
> + ret = i2c_mux_add_adapter(priv->mux, 0, index, 0);
> + if (ret < 0)
> + goto error;
> + }
> +
> + return 0;
> +
> +error:
> + i2c_mux_del_adapters(priv->mux);
> + return ret;
> +}
> +
> +static void max9286_configure_i2c(struct max9286_priv *priv, bool localack)
> +{
> + u8 config = MAX9286_I2CSLVSH_469NS_234NS | MAX9286_I2CSLVTO_1024US |
> + MAX9286_I2CMSTBT_105KBPS;
> +
> + if (localack)
> + config |= MAX9286_I2CLOCACK;
> +
> + max9286_write(priv, 0x34, config);
> + usleep_range(3000, 5000);
> +}
> +
> +/*
> + * max9286_check_video_links() - Make sure video links are detected and locked
> + *
> + * Performs safety checks on video link status. Make sure they are detected
> + * and all enabled links are locked.
> + *
> + * Returns 0 for success, -EIO for errors.
> + */
> +static int max9286_check_video_links(struct max9286_priv *priv)
> +{
> + unsigned int i;
> + int ret;
> +
> + /*
> + * Make sure valid video links are detected.
> + * The delay is not characterized in de-serializer manual, wait up
> + * to 5 ms.
> + */
> + for (i = 0; i < 10; i++) {
> + ret = max9286_read(priv, 0x49);
> + if (ret < 0)
> + return -EIO;
> +
> + if ((ret & MAX9286_VIDEO_DETECT_MASK) == priv->source_mask)
> + break;
> +
> + usleep_range(350, 500);
> + }
> +
> + if (i == 10) {
> + dev_err(&priv->client->dev,
> + "Unable to detect video links: 0x%02x\n", ret);
> + return -EIO;
> + }
> +
> + /* Make sure all enabled links are locked (4ms max). */
> + for (i = 0; i < 10; i++) {
> + ret = max9286_read(priv, 0x27);
> + if (ret < 0)
> + return -EIO;
> +
> + if (ret & MAX9286_LOCKED)
> + break;
> +
> + usleep_range(350, 450);
> + }
> +
> + if (i == 10) {
> + dev_err(&priv->client->dev, "Not all enabled links locked\n");
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +/*
> + * max9286_check_config_link() - Detect and wait for configuration links
> + *
> + * Determine if the configuration channel is up and settled for a link.
> + *
> + * Returns 0 for success, -EIO for errors.
> + */
> +static int max9286_check_config_link(struct max9286_priv *priv,
> + unsigned int source_mask)
> +{
> + unsigned int conflink_mask = (source_mask & 0x0f) << 4;
> + unsigned int i;
> + int ret;
> +
> + /*
> + * Make sure requested configuration links are detected.
> + * The delay is not characterized in the chip manual: wait up
> + * to 5 milliseconds.
> + */
> + for (i = 0; i < 10; i++) {
> + ret = max9286_read(priv, 0x49) & 0xf0;
> + if (ret < 0)
> + return -EIO;
> +
> + if (ret == conflink_mask)
> + break;
> +
> + usleep_range(350, 500);
> + }
> +
> + if (ret != conflink_mask) {
> + dev_err(&priv->client->dev,
> + "Unable to detect configuration links: 0x%02x expected 0x%02x\n",
> + ret, conflink_mask);
> + return -EIO;
> + }
> +
> + dev_info(&priv->client->dev,
> + "Successfully detected configuration links after %u loops: 0x%02x\n",
> + i, conflink_mask);
> +
> + return 0;
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * V4L2 Subdev
> + */
> +
> +static int max9286_set_pixelrate(struct max9286_priv *priv)
> +{
> + struct max9286_source *source = NULL;
> + u64 pixelrate = 0;
> +
> + for_each_source(priv, source) {
> + struct v4l2_ctrl *ctrl;
> + u64 source_rate = 0;
> +
> + /* Pixel rate is mandatory to be reported by sources. */
> + ctrl = v4l2_ctrl_find(source->sd->ctrl_handler,
> + V4L2_CID_PIXEL_RATE);
> + if (!ctrl) {
> + pixelrate = 0;
> + break;
> + }
> +
> + /* All source must report the same pixel rate. */
> + source_rate = v4l2_ctrl_g_ctrl_int64(ctrl);
> + if (!pixelrate) {
> + pixelrate = source_rate;
> + } else if (pixelrate != source_rate) {
> + dev_err(&priv->client->dev,
> + "Unable to calculate pixel rate\n");
> + return -EINVAL;
> + }
> + }
> +
> + if (!pixelrate) {
> + dev_err(&priv->client->dev,
> + "No pixel rate control available in sources\n");
> + return -EINVAL;
> + }
> +
> + /*
> + * The CSI-2 transmitter pixel rate is the single source rate multiplied
> + * by the number of available sources.
> + */
> + return v4l2_ctrl_s_ctrl_int64(priv->pixelrate,
> + pixelrate * priv->nsources);
> +}
> +
> +static int max9286_notify_bound(struct v4l2_async_notifier *notifier,
> + struct v4l2_subdev *subdev,
> + struct v4l2_async_subdev *asd)
> +{
> + struct max9286_priv *priv = sd_to_max9286(notifier->sd);
> + struct max9286_source *source = asd_to_max9286_source(asd);
> + unsigned int index = to_index(priv, source);
> + unsigned int src_pad;
> + int ret;
> +
> + ret = media_entity_get_fwnode_pad(&subdev->entity,
> + source->fwnode,
> + MEDIA_PAD_FL_SOURCE);
> + if (ret < 0) {
> + dev_err(&priv->client->dev,
> + "Failed to find pad for %s\n", subdev->name);
> + return ret;
> + }
> +
> + priv->bound_sources |= BIT(index);
> + source->sd = subdev;
> + src_pad = ret;
> +
> + ret = media_create_pad_link(&source->sd->entity, src_pad,
> + &priv->sd.entity, index,
> + MEDIA_LNK_FL_ENABLED |
> + MEDIA_LNK_FL_IMMUTABLE);
> + if (ret) {
> + dev_err(&priv->client->dev,
> + "Unable to link %s:%u -> %s:%u\n",
> + source->sd->name, src_pad, priv->sd.name, index);
> + return ret;
> + }
> +
> + dev_dbg(&priv->client->dev, "Bound %s pad: %u on index %u\n",
> + subdev->name, src_pad, index);
> +
> + /*
> + * We can only register v4l2_async_notifiers, which do not provide a
> + * means to register a complete callback. bound_sources allows us to
> + * identify when all remote serializers have completed their probe.
> + */
> + if (priv->bound_sources != priv->source_mask)
> + return 0;
> +
> + /*
> + * All enabled sources have probed and enabled their reverse control
> + * channels:
> + *
> + * - Verify all configuration links are properly detected
> + * - Disable auto-ack as communication on the control channel are now
> + * stable.
> + */
> + max9286_check_config_link(priv, priv->source_mask);
> +
> + /*
> + * Re-configure I2C with local acknowledge disabled after cameras have
> + * probed.
> + */
> + max9286_configure_i2c(priv, false);
> +
> + return max9286_set_pixelrate(priv);
> +}
> +
> +static void max9286_notify_unbind(struct v4l2_async_notifier *notifier,
> + struct v4l2_subdev *subdev,
> + struct v4l2_async_subdev *asd)
> +{
> + struct max9286_priv *priv = sd_to_max9286(notifier->sd);
> + struct max9286_source *source = asd_to_max9286_source(asd);
> + unsigned int index = to_index(priv, source);
> +
> + source->sd = NULL;
> + priv->bound_sources &= ~BIT(index);
> +}
> +
> +static const struct v4l2_async_notifier_operations max9286_notify_ops = {
> + .bound = max9286_notify_bound,
> + .unbind = max9286_notify_unbind,
> +};
> +
> +static int max9286_v4l2_notifier_register(struct max9286_priv *priv)
> +{
> + struct device *dev = &priv->client->dev;
> + struct max9286_source *source = NULL;
> + int ret;
> +
> + if (!priv->nsources)
> + return 0;
> +
> + v4l2_async_notifier_init(&priv->notifier);
> +
> + for_each_source(priv, source) {
> + unsigned int i = to_index(priv, source);
> +
> + source->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
> + source->asd.match.fwnode = source->fwnode;
> +
> + ret = v4l2_async_notifier_add_subdev(&priv->notifier,
> + &source->asd);
> + if (ret) {
> + dev_err(dev, "Failed to add subdev for source %d", i);
> + v4l2_async_notifier_cleanup(&priv->notifier);
> + return ret;
> + }
> +
> + /*
> + * Balance the reference counting handled through
> + * v4l2_async_notifier_cleanup()
> + */
> + fwnode_handle_get(source->fwnode);
> + }
> +
> + priv->notifier.ops = &max9286_notify_ops;
> +
> + ret = v4l2_async_subdev_notifier_register(&priv->sd, &priv->notifier);
> + if (ret) {
> + dev_err(dev, "Failed to register subdev_notifier");
> + v4l2_async_notifier_cleanup(&priv->notifier);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static void max9286_v4l2_notifier_unregister(struct max9286_priv *priv)
> +{
> + if (!priv->nsources)
> + return;
> +
> + v4l2_async_notifier_unregister(&priv->notifier);
> + v4l2_async_notifier_cleanup(&priv->notifier);
> +}
> +
> +static int max9286_s_stream(struct v4l2_subdev *sd, int enable)
> +{
> + struct max9286_priv *priv = sd_to_max9286(sd);
> + struct max9286_source *source;
> + unsigned int i;
> + bool sync = false;
> + int ret;
> +
> + if (enable) {
> + /*
> + * The frame sync between cameras is transmitted across the
> + * reverse channel as GPIO. We must open all channels while
> + * streaming to allow this synchronisation signal to be shared.
> + */
> + max9286_i2c_mux_open(priv);
> +
> + /* Start all cameras. */
> + for_each_source(priv, source) {
> + ret = v4l2_subdev_call(source->sd, video, s_stream, 1);
> + if (ret)
> + return ret;
> + }
> +
> + ret = max9286_check_video_links(priv);
> + if (ret)
> + return ret;
> +
> + /*
> + * Wait until frame synchronization is locked.
> + *
> + * Manual says frame sync locking should take ~6 VTS.
> + * From practical experience at least 8 are required. Give
> + * 12 complete frames time (~400ms at 30 fps) to achieve frame
> + * locking before returning error.
> + */
> + for (i = 0; i < 40; i++) {
> + if (max9286_read(priv, 0x31) & MAX9286_FSYNC_LOCKED) {
> + sync = true;
> + break;
> + }
> + usleep_range(9000, 11000);
> + }
> +
> + if (!sync) {
> + dev_err(&priv->client->dev,
> + "Failed to get frame synchronization\n");
> + return -EXDEV; /* Invalid cross-device link */
> + }
> +
> + /*
> + * Enable CSI output, VC set according to link number.
> + * Bit 7 must be set (chip manual says it's 0 and reserved).
> + */
> + max9286_write(priv, 0x15, 0x80 | MAX9286_VCTYPE |
> + MAX9286_CSIOUTEN | MAX9286_0X15_RESV);
> + } else {
> + max9286_write(priv, 0x15, MAX9286_VCTYPE | MAX9286_0X15_RESV);
> +
> + /* Stop all cameras. */
> + for_each_source(priv, source)
> + v4l2_subdev_call(source->sd, video, s_stream, 0);
> +
> + max9286_i2c_mux_close(priv);
> + }
> +
> + return 0;
> +}
> +
> +static int max9286_enum_mbus_code(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_mbus_code_enum *code)
> +{
> + if (code->pad || code->index > 0)
> + return -EINVAL;
> +
> + code->code = MEDIA_BUS_FMT_UYVY8_1X16;
> +
> + return 0;
> +}
> +
> +static struct v4l2_mbus_framefmt *
> +max9286_get_pad_format(struct max9286_priv *priv,
> + struct v4l2_subdev_pad_config *cfg,
> + unsigned int pad, u32 which)
> +{
> + switch (which) {
> + case V4L2_SUBDEV_FORMAT_TRY:
> + return v4l2_subdev_get_try_format(&priv->sd, cfg, pad);
> + case V4L2_SUBDEV_FORMAT_ACTIVE:
> + return &priv->fmt[pad];
> + default:
> + return NULL;
> + }
> +}
> +
> +static int max9286_set_fmt(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_format *format)
> +{
> + struct max9286_priv *priv = sd_to_max9286(sd);
> + struct v4l2_mbus_framefmt *cfg_fmt;
> +
> + if (format->pad == MAX9286_SRC_PAD)
> + return -EINVAL;
> +
> + /* Refuse non YUV422 formats as we hardcode DT to 8 bit YUV422 */
> + switch (format->format.code) {
> + case MEDIA_BUS_FMT_UYVY8_1X16:
> + case MEDIA_BUS_FMT_VYUY8_1X16:
> + case MEDIA_BUS_FMT_YUYV8_1X16:
> + case MEDIA_BUS_FMT_YVYU8_1X16:
> + break;
> + default:
> + format->format.code = MEDIA_BUS_FMT_UYVY8_1X16;
> + break;
> + }
> +
> + cfg_fmt = max9286_get_pad_format(priv, cfg, format->pad, format->which);
> + if (!cfg_fmt)
> + return -EINVAL;
> +
> + mutex_lock(&priv->mutex);
> + *cfg_fmt = format->format;
> + mutex_unlock(&priv->mutex);
> +
> + return 0;
> +}
> +
> +static int max9286_get_fmt(struct v4l2_subdev *sd,
> + struct v4l2_subdev_pad_config *cfg,
> + struct v4l2_subdev_format *format)
> +{
> + struct max9286_priv *priv = sd_to_max9286(sd);
> + struct v4l2_mbus_framefmt *cfg_fmt;
> + unsigned int pad = format->pad;
> +
> + /*
> + * Multiplexed Stream Support: Support link validation by returning the
> + * format of the first bound link. All links must have the same format,
> + * as we do not support mixing and matching of cameras connected to the
> + * max9286.
> + */
> + if (pad == MAX9286_SRC_PAD)
> + pad = __ffs(priv->bound_sources);
> +
> + cfg_fmt = max9286_get_pad_format(priv, cfg, pad, format->which);
> + if (!cfg_fmt)
> + return -EINVAL;
> +
> + mutex_lock(&priv->mutex);
> + format->format = *cfg_fmt;
> + mutex_unlock(&priv->mutex);
> +
> + return 0;
> +}
> +
> +static const struct v4l2_subdev_video_ops max9286_video_ops = {
> + .s_stream = max9286_s_stream,
> +};
> +
> +static const struct v4l2_subdev_pad_ops max9286_pad_ops = {
> + .enum_mbus_code = max9286_enum_mbus_code,
> + .get_fmt = max9286_get_fmt,
> + .set_fmt = max9286_set_fmt,
> +};
> +
> +static const struct v4l2_subdev_ops max9286_subdev_ops = {
> + .video = &max9286_video_ops,
> + .pad = &max9286_pad_ops,
> +};
> +
> +static void max9286_init_format(struct v4l2_mbus_framefmt *fmt)
> +{
> + fmt->width = 1280;
> + fmt->height = 800;
> + fmt->code = MEDIA_BUS_FMT_UYVY8_1X16;
> + fmt->colorspace = V4L2_COLORSPACE_SRGB;
> + fmt->field = V4L2_FIELD_NONE;
> + fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
> + fmt->quantization = V4L2_QUANTIZATION_DEFAULT;
> + fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
> +}
> +
> +static int max9286_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
> +{
> + struct v4l2_mbus_framefmt *format;
> + unsigned int i;
> +
> + for (i = 0; i < MAX9286_N_SINKS; i++) {
> + format = v4l2_subdev_get_try_format(subdev, fh->pad, i);
> + max9286_init_format(format);
> + }
> +
> + return 0;
> +}
> +
> +static const struct v4l2_subdev_internal_ops max9286_subdev_internal_ops = {
> + .open = max9286_open,
> +};
> +
> +static int max9286_s_ctrl(struct v4l2_ctrl *ctrl)
> +{
> + switch (ctrl->id) {
> + case V4L2_CID_PIXEL_RATE:
> + return 0;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static const struct v4l2_ctrl_ops max9286_ctrl_ops = {
> + .s_ctrl = max9286_s_ctrl,
> +};
> +
> +static int max9286_v4l2_register(struct max9286_priv *priv)
> +{
> + struct device *dev = &priv->client->dev;
> + struct fwnode_handle *ep;
> + int ret;
> + int i;
> +
> + /* Register v4l2 async notifiers for connected Camera subdevices */
> + ret = max9286_v4l2_notifier_register(priv);
> + if (ret) {
> + dev_err(dev, "Unable to register V4L2 async notifiers\n");
> + return ret;
> + }
> +
> + /* Configure V4L2 for the MAX9286 itself */
> +
> + for (i = 0; i < MAX9286_N_SINKS; i++)
> + max9286_init_format(&priv->fmt[i]);
> +
> + v4l2_i2c_subdev_init(&priv->sd, priv->client, &max9286_subdev_ops);
> + priv->sd.internal_ops = &max9286_subdev_internal_ops;
> + priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
> +
> + v4l2_ctrl_handler_init(&priv->ctrls, 1);
> + priv->pixelrate = v4l2_ctrl_new_std(&priv->ctrls,
> + &max9286_ctrl_ops,
> + V4L2_CID_PIXEL_RATE,
> + 1, INT_MAX, 1, 50000000);
> +
> + priv->sd.ctrl_handler = &priv->ctrls;
> + ret = priv->ctrls.error;
> + if (ret)
> + goto err_async;
> +
> + priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
> +
> + priv->pads[MAX9286_SRC_PAD].flags = MEDIA_PAD_FL_SOURCE;
> + for (i = 0; i < MAX9286_SRC_PAD; i++)
> + priv->pads[i].flags = MEDIA_PAD_FL_SINK;
> + ret = media_entity_pads_init(&priv->sd.entity, MAX9286_N_PADS,
> + priv->pads);
> + if (ret)
> + goto err_async;
> +
> + ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), MAX9286_SRC_PAD,
> + 0, 0);
> + if (!ep) {
> + dev_err(dev, "Unable to retrieve endpoint on \"port@4\"\n");
> + ret = -ENOENT;
> + goto err_async;
> + }
> + priv->sd.fwnode = ep;
> +
> + ret = v4l2_async_register_subdev(&priv->sd);
> + if (ret < 0) {
> + dev_err(dev, "Unable to register subdevice\n");
> + goto err_put_node;
> + }
> +
> + return 0;
> +
> +err_put_node:
> + fwnode_handle_put(ep);
> +err_async:
> + max9286_v4l2_notifier_unregister(priv);
> +
> + return ret;
> +}
> +
> +static void max9286_v4l2_unregister(struct max9286_priv *priv)
> +{
> + fwnode_handle_put(priv->sd.fwnode);
> + v4l2_async_unregister_subdev(&priv->sd);
> + max9286_v4l2_notifier_unregister(priv);
> +}
> +
> +/* -----------------------------------------------------------------------------
> + * Probe/Remove
> + */
> +
> +static int max9286_setup(struct max9286_priv *priv)
> +{
> + /*
> + * Link ordering values for all enabled links combinations. Orders must
> + * be assigned sequentially from 0 to the number of enabled links
> + * without leaving any hole for disabled links. We thus assign orders to
> + * enabled links first, and use the remaining order values for disabled
> + * links are all links must have a different order value;
> + */
> + static const u8 link_order[] = {
> + (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxxx */
> + (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxx0 */
> + (3 << 6) | (2 << 4) | (0 << 2) | (1 << 0), /* xx0x */
> + (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xx10 */
> + (3 << 6) | (0 << 4) | (2 << 2) | (1 << 0), /* x0xx */
> + (3 << 6) | (1 << 4) | (2 << 2) | (0 << 0), /* x1x0 */
> + (3 << 6) | (1 << 4) | (0 << 2) | (2 << 0), /* x10x */
> + (3 << 6) | (1 << 4) | (1 << 2) | (0 << 0), /* x210 */
> + (0 << 6) | (3 << 4) | (2 << 2) | (1 << 0), /* 0xxx */
> + (1 << 6) | (3 << 4) | (2 << 2) | (0 << 0), /* 1xx0 */
> + (1 << 6) | (3 << 4) | (0 << 2) | (2 << 0), /* 1x0x */
> + (2 << 6) | (3 << 4) | (1 << 2) | (0 << 0), /* 2x10 */
> + (1 << 6) | (0 << 4) | (3 << 2) | (2 << 0), /* 10xx */
> + (2 << 6) | (1 << 4) | (3 << 2) | (0 << 0), /* 21x0 */
> + (2 << 6) | (1 << 4) | (0 << 2) | (3 << 0), /* 210x */
> + (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* 3210 */
> + };
> +
> + /*
> + * Set the I2C bus speed.
> + *
> + * Enable I2C Local Acknowledge during the probe sequences of the camera
> + * only. This should be disabled after the mux is initialised.
> + */
> + max9286_configure_i2c(priv, true);
> +
> + /*
> + * Reverse channel setup.
> + *
> + * - Enable custom reverse channel configuration (through register 0x3f)
> + * and set the first pulse length to 35 clock cycles.
> + * - Increase the reverse channel amplitude to 170mV to accommodate the
> + * high threshold enabled by the serializer driver.
> + */
> + max9286_write(priv, 0x3f, MAX9286_EN_REV_CFG | MAX9286_REV_FLEN(35));
> + max9286_write(priv, 0x3b, MAX9286_REV_TRF(1) | MAX9286_REV_AMP(70) |
> + MAX9286_REV_AMP_X);
> + usleep_range(2000, 2500);
> +
> + /*
> + * Enable GMSL links, mask unused ones and autodetect link
> + * used as CSI clock source.
> + */
> + max9286_write(priv, 0x00, MAX9286_MSTLINKSEL_AUTO | priv->route_mask);
> + max9286_write(priv, 0x0b, link_order[priv->route_mask]);
> + max9286_write(priv, 0x69, (0xf & ~priv->route_mask));
> +
> + /*
> + * Video format setup:
> + * Disable CSI output, VC is set according to Link number.
> + */
> + max9286_write(priv, 0x15, MAX9286_VCTYPE | MAX9286_0X15_RESV);
> +
> + /* Enable CSI-2 Lane D0-D3 only, DBL mode, YUV422 8-bit. */
> + max9286_write(priv, 0x12, MAX9286_CSIDBL | MAX9286_DBL |
> + MAX9286_CSILANECNT(priv->csi2_data_lanes) |
> + MAX9286_DATATYPE_YUV422_8BIT);
> +
> + /* Automatic: FRAMESYNC taken from the slowest Link. */
> + max9286_write(priv, 0x01, MAX9286_FSYNCMODE_INT_HIZ |
> + MAX9286_FSYNCMETH_AUTO);
> +
> + /* Enable HS/VS encoding, use D14/15 for HS/VS, invert VS. */
> + max9286_write(priv, 0x0c, MAX9286_HVEN | MAX9286_INVVS |
> + MAX9286_HVSRC_D14);
> +
> + /*
> + * The overlap window seems to provide additional validation by tracking
> + * the delay between vsync and frame sync, generating an error if the
> + * delay is bigger than the programmed window, though it's not yet clear
> + * what value should be set.
> + *
> + * As it's an optional value and can be disabled, we do so by setting
> + * a 0 overlap value.
> + */
> + max9286_write(priv, 0x63, 0);
> + max9286_write(priv, 0x64, 0);
> +
> + /*
> + * Wait for 2ms to allow the link to resynchronize after the
> + * configuration change.
> + */
> + usleep_range(2000, 5000);
> +
> + return 0;
> +}
> +
> +static void max9286_gpio_set(struct gpio_chip *chip,
> + unsigned int offset, int value)
> +{
> + struct max9286_priv *priv = gpiochip_get_data(chip);
> +
> + if (value)
> + priv->gpio_state |= BIT(offset);
> + else
> + priv->gpio_state &= ~BIT(offset);
> +
> + max9286_write(priv, 0x0f, MAX9286_0X0F_RESERVED | priv->gpio_state);
> +}
> +
> +static int max9286_gpio_get(struct gpio_chip *chip, unsigned int offset)
> +{
> + struct max9286_priv *priv = gpiochip_get_data(chip);
> +
> + return priv->gpio_state & BIT(offset);
> +}
> +
> +static int max9286_register_gpio(struct max9286_priv *priv)
> +{
> + struct device *dev = &priv->client->dev;
> + struct gpio_chip *gpio = &priv->gpio;
> + int ret;
> +
> + /* Configure the GPIO */
> + gpio->label = dev_name(dev);
> + gpio->parent = dev;
> + gpio->owner = THIS_MODULE;
> + gpio->of_node = dev->of_node;
> + gpio->ngpio = 2;
> + gpio->base = -1;
> + gpio->set = max9286_gpio_set;
> + gpio->get = max9286_gpio_get;
> + gpio->can_sleep = true;
> +
> + /* GPIO values default to high */
> + priv->gpio_state = BIT(0) | BIT(1);
> +
> + ret = devm_gpiochip_add_data(dev, gpio, priv);
> + if (ret)
> + dev_err(dev, "Unable to create gpio_chip\n");
> +
> + return ret;
> +}
> +
> +static int max9286_init(struct device *dev)
> +{
> + struct max9286_priv *priv;
> + struct i2c_client *client;
> + int ret;
> +
> + client = to_i2c_client(dev);
> + priv = i2c_get_clientdata(client);
> +
> + /* Enable the bus power. */
> + ret = regulator_enable(priv->regulator);
> + if (ret < 0) {
> + dev_err(&client->dev, "Unable to turn PoC on\n");
> + return ret;
> + }
> +
> + ret = max9286_setup(priv);
> + if (ret) {
> + dev_err(dev, "Unable to setup max9286\n");
> + goto err_regulator;
> + }
> +
> + /*
> + * Register all V4L2 interactions for the MAX9286 and notifiers for
> + * any subdevices connected.
> + */
> + ret = max9286_v4l2_register(priv);
> + if (ret) {
> + dev_err(dev, "Failed to register with V4L2\n");
> + goto err_regulator;
> + }
> +
> + ret = max9286_i2c_mux_init(priv);
> + if (ret) {
> + dev_err(dev, "Unable to initialize I2C multiplexer\n");
> + goto err_v4l2_register;
> + }
> +
> + /* Leave the mux channels disabled until they are selected. */
> + max9286_i2c_mux_close(priv);
> +
> + return 0;
> +
> +err_v4l2_register:
> + max9286_v4l2_unregister(priv);
> +err_regulator:
> + regulator_disable(priv->regulator);
> +
> + return ret;
> +}
> +
> +static void max9286_cleanup_dt(struct max9286_priv *priv)
> +{
> + struct max9286_source *source;
> +
> + for_each_source(priv, source) {
> + fwnode_handle_put(source->fwnode);
> + source->fwnode = NULL;
> + }
> +}
> +
> +static int max9286_parse_dt(struct max9286_priv *priv)
> +{
> + struct device *dev = &priv->client->dev;
> + struct device_node *i2c_mux;
> + struct device_node *node = NULL;
> + unsigned int i2c_mux_mask = 0;
> +
> + /* Balance the of_node_put() performed by of_find_node_by_name(). */
> + of_node_get(dev->of_node);
> + i2c_mux = of_find_node_by_name(dev->of_node, "i2c-mux");
> + if (!i2c_mux) {
> + dev_err(dev, "Failed to find i2c-mux node\n");
> + return -EINVAL;
> + }
> +
> + /* Identify which i2c-mux channels are enabled */
> + for_each_child_of_node(i2c_mux, node) {
> + u32 id = 0;
> +
> + of_property_read_u32(node, "reg", &id);
> + if (id >= MAX9286_NUM_GMSL)
> + continue;
> +
> + if (!of_device_is_available(node)) {
> + dev_dbg(dev, "Skipping disabled I2C bus port %u\n", id);
> + continue;
> + }
> +
> + i2c_mux_mask |= BIT(id);
> + }
> + of_node_put(node);
> + of_node_put(i2c_mux);
> +
> + /* Parse the endpoints */
> + for_each_endpoint_of_node(dev->of_node, node) {
> + struct max9286_source *source;
> + struct of_endpoint ep;
> +
> + of_graph_parse_endpoint(node, &ep);
> + dev_dbg(dev, "Endpoint %pOF on port %d",
> + ep.local_node, ep.port);
> +
> + if (ep.port > MAX9286_NUM_GMSL) {
> + dev_err(dev, "Invalid endpoint %s on port %d",
> + of_node_full_name(ep.local_node), ep.port);
> + continue;
> + }
> +
> + /* For the source endpoint just parse the bus configuration. */
> + if (ep.port == MAX9286_SRC_PAD) {
> + struct v4l2_fwnode_endpoint vep = {
> + .bus_type = V4L2_MBUS_CSI2_DPHY
> + };
> + int ret;
> +
> + ret = v4l2_fwnode_endpoint_parse(
> + of_fwnode_handle(node), &vep);
> + if (ret) {
> + of_node_put(node);
> + return ret;
> + }
> +
> + priv->csi2_data_lanes =
> + vep.bus.mipi_csi2.num_data_lanes;
> +
> + continue;
> + }
> +
> + /* Skip if the corresponding GMSL link is unavailable. */
> + if (!(i2c_mux_mask & BIT(ep.port)))
> + continue;
> +
> + if (priv->sources[ep.port].fwnode) {
> + dev_err(dev,
> + "Multiple port endpoints are not supported: %d",
> + ep.port);
> +
> + continue;
> + }
> +
> + source = &priv->sources[ep.port];
> + source->fwnode = fwnode_graph_get_remote_endpoint(
> + of_fwnode_handle(node));
> + if (!source->fwnode) {
> + dev_err(dev,
> + "Endpoint %pOF has no remote endpoint connection\n",
> + ep.local_node);
> +
> + continue;
> + }
> +
> + priv->source_mask |= BIT(ep.port);
> + priv->nsources++;
> + }
> + of_node_put(node);
> +
> + priv->route_mask = priv->source_mask;
> +
> + return 0;
> +}
> +
> +static int max9286_probe(struct i2c_client *client)
> +{
> + struct max9286_priv *priv;
> + int ret;
> +
> + priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + mutex_init(&priv->mutex);
> +
> + priv->client = client;
> + i2c_set_clientdata(client, priv);
> +
> + priv->gpiod_pwdn = devm_gpiod_get_optional(&client->dev, "enable",
> + GPIOD_OUT_HIGH);
> + if (IS_ERR(priv->gpiod_pwdn))
> + return PTR_ERR(priv->gpiod_pwdn);
> +
> + gpiod_set_consumer_name(priv->gpiod_pwdn, "max9286-pwdn");
> + gpiod_set_value_cansleep(priv->gpiod_pwdn, 1);
> +
> + /* Wait at least 4ms before the I2C lines latch to the address */
> + if (priv->gpiod_pwdn)
> + usleep_range(4000, 5000);
> +
> + /*
> + * The MAX9286 starts by default with all ports enabled, we disable all
> + * ports early to ensure that all channels are disabled if we error out
> + * and keep the bus consistent.
> + */
> + max9286_i2c_mux_close(priv);
> +
> + /*
> + * The MAX9286 initialises with auto-acknowledge enabled by default.
> + * This can be invasive to other transactions on the same bus, so
> + * disable it early. It will be enabled only as and when needed.
> + */
> + max9286_configure_i2c(priv, false);
> +
> + ret = max9286_register_gpio(priv);
> + if (ret)
> + goto err_powerdown;
> +
> + priv->regulator = devm_regulator_get(&client->dev, "poc");
> + if (IS_ERR(priv->regulator)) {
> + if (PTR_ERR(priv->regulator) != -EPROBE_DEFER)
> + dev_err(&client->dev,
> + "Unable to get PoC regulator (%ld)\n",
> + PTR_ERR(priv->regulator));
> + ret = PTR_ERR(priv->regulator);
> + goto err_powerdown;
> + }
> +
> + ret = max9286_parse_dt(priv);
> + if (ret)
> + goto err_powerdown;
> +
> + ret = max9286_init(&client->dev);
> + if (ret < 0)
> + goto err_cleanup_dt;
> +
> + return 0;
> +
> +err_cleanup_dt:
> + max9286_cleanup_dt(priv);
> +err_powerdown:
> + gpiod_set_value_cansleep(priv->gpiod_pwdn, 0);
> +
> + return ret;
> +}
> +
> +static int max9286_remove(struct i2c_client *client)
> +{
> + struct max9286_priv *priv = i2c_get_clientdata(client);
> +
> + i2c_mux_del_adapters(priv->mux);
> +
> + max9286_v4l2_unregister(priv);
> +
> + regulator_disable(priv->regulator);
> +
> + gpiod_set_value_cansleep(priv->gpiod_pwdn, 0);
> +
> + max9286_cleanup_dt(priv);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id max9286_dt_ids[] = {
> + { .compatible = "maxim,max9286" },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, max9286_dt_ids);
> +
> +static struct i2c_driver max9286_i2c_driver = {
> + .driver = {
> + .name = "max9286",
> + .of_match_table = of_match_ptr(max9286_dt_ids),
> + },
> + .probe_new = max9286_probe,
> + .remove = max9286_remove,
> +};
> +
> +module_i2c_driver(max9286_i2c_driver);
> +
> +MODULE_DESCRIPTION("Maxim MAX9286 GMSL Deserializer Driver");
> +MODULE_AUTHOR("Jacopo Mondi, Kieran Bingham, Laurent Pinchart, Niklas Söderlund, Vladimir Barinov");
> +MODULE_LICENSE("GPL");
>
--
Regards
--
Kieran
^ permalink raw reply
* Re: [PATCH v4 5/6] gpio: max77620: Use irqchip template
From: Linus Walleij @ 2020-07-16 8:55 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Thierry Reding, Jonathan Hunter, Laxman Dewangan,
Bartosz Golaszewski, Andy Shevchenko, linux-tegra,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org
In-Reply-To: <20200709171203.12950-6-digetx@gmail.com>
On Thu, Jul 9, 2020 at 7:12 PM Dmitry Osipenko <digetx@gmail.com> wrote:
> + mgpio->gpio_chip.irq.chip = &max77620_gpio_irqchip;
> + mgpio->gpio_chip.irq.default_type = IRQ_TYPE_NONE;
> + mgpio->gpio_chip.irq.handler = handle_edge_irq;
> + mgpio->gpio_chip.irq.threaded = true;
And I didn't even realize one could do this.
> - gpiochip_irqchip_add_nested(&mgpio->gpio_chip, &max77620_gpio_irqchip,
> - 0, handle_edge_irq, IRQ_TYPE_NONE);
> -
(...)
> - gpiochip_set_nested_irqchip(&mgpio->gpio_chip, &max77620_gpio_irqchip,
> - gpio_irq);
And get rid of these two.
I suppose I can just do the same for the remaining users of
gpiochip_irqchip_add_nested() and gpiochip_set_nested_irqchip()
and get rid of these two functions altogether!
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v4 0/6] Improvements for MAX77620 GPIO driver
From: Linus Walleij @ 2020-07-16 8:52 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Thierry Reding, Jonathan Hunter, Laxman Dewangan,
Bartosz Golaszewski, Andy Shevchenko, linux-tegra,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org
In-Reply-To: <20200709171203.12950-1-digetx@gmail.com>
On Thu, Jul 9, 2020 at 7:12 PM Dmitry Osipenko <digetx@gmail.com> wrote:
> This series addresses a problem that I discovered on Nexus 7 device where
> GPIO interrupts may be left enabled after bootloader and the driver isn't
> prepared to this. It also makes a small improvements to the code, fixes the
> non-released interrupt bug and converts driver to use irqchip template.
>
> Changelog:
>
> v4: - Added stable-tag to the patch "Fix missing release of interrupt".
This v4 series applied, thanks a *LOT* for your patient work on this!
I need to fix the USB port on my Nexus 7 so I can test how the
mainline support is working these days!
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 1/2] pinctrl: qcom: ipq4019: add open drain support
From: Linus Walleij @ 2020-07-16 8:47 UTC (permalink / raw)
To: Brian Norris
Cc: Bjorn Andersson, Andy Gross, Rob Herring, MSM,
open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Jaiganesh Narayanan
In-Reply-To: <20200703080646.23233-1-computersforpeace@gmail.com>
On Fri, Jul 3, 2020 at 10:06 AM Brian Norris
<computersforpeace@gmail.com> wrote:
> From: Jaiganesh Narayanan <njaigane@codeaurora.org>
>
> Signed-off-by: Jaiganesh Narayanan <njaigane@codeaurora.org>
> [ Brian: adapted from from the Chromium OS kernel used on IPQ4019-based
> WiFi APs. ]
> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Patch applied because this looks innocent and Rob
ACKed the binding.
If Bjorn opposes, I will simply pull the patch out again.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH] pinctrl: aspeed: Describe the heartbeat function on ball Y23
From: Linus Walleij @ 2020-07-16 8:32 UTC (permalink / raw)
To: Joel Stanley
Cc: Andrew Jeffery, linux-aspeed, open list:GPIO SUBSYSTEM,
linux-kernel@vger.kernel.org
In-Reply-To: <20200701030756.2834657-1-joel@jms.id.au>
On Wed, Jul 1, 2020 at 5:08 AM Joel Stanley <joel@jms.id.au> wrote:
> From: Andrew Jeffery <andrew@aj.id.au>
>
> The default pinmux configuration for Y23 is to route a heartbeat to
> drive a LED. Previous revisions of the AST2600 datasheet did not include
> a description of this function.
>
> Fixes: 2eda1cdec49f ("pinctrl: aspeed: Add AST2600 pinmux support")
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Patch applied, thanks!
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH] pinctrl: aspeed: Improve debug output
From: Linus Walleij @ 2020-07-16 8:31 UTC (permalink / raw)
To: Joel Stanley
Cc: linux-aspeed, open list:GPIO SUBSYSTEM,
linux-kernel@vger.kernel.org, Andrew Jeffery
In-Reply-To: <20200701030039.2834418-1-joel@jms.id.au>
On Wed, Jul 1, 2020 at 5:00 AM Joel Stanley <joel@jms.id.au> wrote:
> From: Andrew Jeffery <andrew@aj.id.au>
>
> We need to iterate over each pin in a group for a function and
> disable higher priority mux configurations on the pin before finally
> muxing the relevant function's signal. With the current debug output it
> is hard to track what register output is relevant to which operation, so
> break up the actions in the debug output by providing some more context.
>
> Before:
>
> [ 5.446656] aspeed-g6-pinctrl 1e6e2000.syscon:pinctrl: request pin 37 (B26) for 1e780000.gpio:341
> [ 5.447377] Want SCU414[0x00000020]=0x1, got 0x0 from 0x00000000
> [ 5.447854] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000
> [ 5.448340] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000
>
> After:
>
> [ 5.298053] Muxing pin 37 for GPIO
> [ 5.298294] Disabling signal NRI4 for NRI4
> [ 5.298593] Want SCU414[0x00000020]=0x1, got 0x0 from 0x00000000
> [ 5.298983] Disabling signal RGMII4RXD1 for RGMII4
> [ 5.299309] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000
> [ 5.299694] Disabling signal RMII4RXD1 for RMII4
> [ 5.300014] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000
> [ 5.300396] Enabling signal GPIOE5 for GPIOE5
> [ 5.300687] Muxed pin 37 as GPIOE5
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
Patch applied, thanks!
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v2] gpio: omap: handle pin config bias flags
From: Linus Walleij @ 2020-07-16 8:29 UTC (permalink / raw)
To: Drew Fustini
Cc: Tony Lindgren, Haojian Zhuang, Grygorii Strashko, Linux-OMAP,
open list:GPIO SUBSYSTEM, Jason Kridner, Robert Nelson
In-Reply-To: <20200715213738.1640030-1-drew@beagleboard.org>
On Wed, Jul 15, 2020 at 11:37 PM Drew Fustini <drew@beagleboard.org> wrote:
> Modify omap_gpio_set_config() to handle pin config bias flags by calling
> gpiochip_generic_config().
>
> The pin group for the gpio line must have the corresponding pinconf
> properties:
>
> PIN_CONFIG_BIAS_PULL_UP requires "pinctrl-single,bias-pullup"
> PIN_CONFIG_BIAS_PULL_DOWN requires "pinctrl-single,bias-pulldown"
>
> This is necessary for pcs_pinconf_set() to find the requested bias
> parameter in the PIN_MAP_TYPE_CONFIGS_GROUP pinctrl map.
>
> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com>
> Acked-by: Tony Lindgren <tony@atomide.com>
> Signed-off-by: Drew Fustini <drew@beagleboard.org>
This v2 version applied!
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH] dt-bindings: pinctrl: renesas,rza2-pinctrl: Convert to json-schema
From: Geert Uytterhoeven @ 2020-07-16 8:27 UTC (permalink / raw)
To: Rob Herring
Cc: Chris Brandt, Rob Herring, Linux-Renesas, Linus Walleij,
open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <20200715201037.GA740389@bogus>
On Wed, Jul 15, 2020 at 10:10 PM Rob Herring <robh@kernel.org> wrote:
> On Fri, 26 Jun 2020 16:36:38 +0200, Geert Uytterhoeven wrote:
> > Convert the Renesas RZ/A2 combined Pin and GPIO controller Device Tree
> > binding documentation to json-schema.
> >
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > .../bindings/pinctrl/renesas,rza2-pinctrl.txt | 87 ---------------
> > .../pinctrl/renesas,rza2-pinctrl.yaml | 100 ++++++++++++++++++
> > 2 files changed, 100 insertions(+), 87 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.txt
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml
> >
>
> Reviewed-by: Rob Herring <robh@kernel.org>
Thanks, queueing in sh-pfc-for-v5.9.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v5 07/13] pwm: add support for sl28cpld PWM controller
From: Uwe Kleine-König @ 2020-07-16 6:10 UTC (permalink / raw)
To: Michael Walle
Cc: Thierry Reding, linux-gpio, devicetree, linux-kernel, linux-hwmon,
linux-pwm, linux-watchdog, linux-arm-kernel, Linus Walleij,
Bartosz Golaszewski, Rob Herring, Jean Delvare, Guenter Roeck,
Lee Jones, Wim Van Sebroeck, Shawn Guo, Li Yang, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Mark Brown, Greg Kroah-Hartman,
Andy Shevchenko
In-Reply-To: <8debe0ee9aff2c49a7567069d7bb9477@walle.cc>
[-- Attachment #1: Type: text/plain, Size: 4871 bytes --]
Hello Michael,
On Wed, Jul 15, 2020 at 10:41:25PM +0200, Michael Walle wrote:
> Am 2020-07-15 20:18, schrieb Uwe Kleine-König:
> > On Wed, Jul 15, 2020 at 07:45:10PM +0200, Michael Walle wrote:
> > >
> > > Am 2020-07-15 18:36, schrieb Uwe Kleine-König:
> > > > On Tue, Jul 14, 2020 at 11:09:28PM +0200, Michael Walle wrote:
> > > > > > My wishlist (just as it comes to my mind, so no guarantee of
> > > > > > completeness):
> > > > > >
> > > > > > - can do 0% duty cycle for all supported period lengths
> > > > > > - can do 100% duty cycle for all supported period lengths
> > > > > > - supports both polarities
> > > > > > - supports immediate change of configuration and after completion of
> > > > > > the currently running period
> > > > > > - atomic update (i.e. if you go from configuration A to configuration B
> > > > > > the hardware guarantees to only emit periods of type A and then type
> > > > > > B. (Depending on the item above, the last A period might be cut off.)
> > > > >
> > > > > We actually discussed this, because the implementation would be
> > > > > easier. But
> > > > > if the change takes place immediately you might end up with a longer
> > > > > duty
> > > > > cycle. Assume the PWM runs at 80% duty cycle and starts with the
> > > > > on-period.
> > > > > If you now change that to 50% you might end up with one successive
> > > > > duty
> > > > > cycle of "130%". Eg. the 80% of the old and right after that you
> > > > > switch to
> > > > > the new 50% and then you'd have a high output which corresponds to a
> > > > > 130%
> > > > > cycle. I don't know if that is acceptable for all applications.
> > > >
> > > > I thought this is a "change takes place immediately" implementation?! So
> > > > these problems are actually real here. (And this not happening is
> > > > exactly
> > > > my wish here. Is there a mis-understanding?)
> > >
> > > I wasn't talking about the sl28cpld btw. What is the difference
> > > between
> > > your proposed "change take place immediately" and "after the cycle".
> > > I understand how the after the cycle should work. But how would the
> > > immediate change work in your ideal PWM?
> >
> > If the PWM is running at 1/3 duty cycle and reconfigured for 2/3, then
> > the two scenarios are (the * marks the moment where pwm_apply_state() is
> > called, ^ marks the start of a period):
> >
> > immediately:
> >
> > __ __ _____ _____
> > / \_____/ \__/ \__/
> > ^ ^ ^ ^
> > *
>
> Ok lets assume 2/3 and change it to 1/3:
>
> ____ ______ __
> / \___/ \____/ \____
> ^ ^ ^ ^
> *
> This will then have a longer on period than any of the settings.
I think we agree here. With an immediate change to the new setting both
too long and too short signals can heppen. How bad this is depends on
the use. The consumers currently in the kernel probably don't care too
much.
> > > > > > > > What about disable()?
> > > > > > >
> > > > > > > Mhh well, it would do one 100% cycle.. mhh ;) Lets see if there we can
> > > > > > > fix that (in hardware), not much we can do in the driver here. We are
> > > > > > > _very_ constraint in size, therefore all that little edge cases fall
> > > > > > > off
> > > > > > > the table.
> > > > > >
> > > > > > You're saying that on disable the hardware emits a constant high level
> > > > > > for one cycle? I hope not ...
> > > > >
> > > > > Mh, I was mistaken, disabling the PWM will turn it off immediately,
> > > > > but
> > > >
> > > > And does turn off mean, the output gets inactive?
> > > > If so you might also disable the hardware if a 0% duty cycle is
> > > > configured assuming this saves some energy without modifying the
> > > > resulting wave form.
> > >
> > > Disabling it has some side effects like switching to another function
> > > for this multi function pin. So I'd rather keep it on ;)
> >
> > So IMHO you should also keep it on when pwm_apply_state is called with
> > state.enabled = false to ensure a low output.
>
> That won't work either, because that is how you would turn on that multi
> function. Ie. it is GPIO (default input) as long as the PWM is not enabled,
> otherwise its PWM.
I think you misunderstood what I wrote. The intended behaviour for a
disabled PWM (as in: pwm_apply_state() was called with state.enabled =
false) is that the output is a constant low (assuming a normal
polarity). If disabling your hardware results in something else, don't
disable the hardware. That's another item in the Limitations paragraph.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* RE: [PATCH 2/9] iommu/ipmmu-vmsa: Hook up R8A774E1 DT matching code
From: Yoshihiro Shimoda @ 2020-07-16 4:42 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Lad, Prabhakar, Prabhakar Mahadev Lad, Vinod Koul, Rob Herring,
Linus Walleij, Bartosz Golaszewski, Joerg Roedel, Sergei Shtylyov,
David S. Miller, Jakub Kicinski, Magnus Damm, dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:GPIO SUBSYSTEM, Linux IOMMU, netdev, Linux-Renesas,
Linux Kernel Mailing List
In-Reply-To: <CAMuHMdUry12MnLvVgmd7NJ+Gv4mA86qKKfsQobP1o-ohzKm=RQ@mail.gmail.com>
Hi Geert-san,
> From: Geert Uytterhoeven, Sent: Tuesday, July 14, 2020 9:40 PM
>
> Hi Shimoda-san,
>
> On Tue, Jul 14, 2020 at 1:42 PM Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > From: Geert Uytterhoeven, Sent: Tuesday, July 14, 2020 5:42 PM
> > > On Tue, Jul 14, 2020 at 10:30 AM Lad, Prabhakar
> > > <prabhakar.csengg@gmail.com> wrote:
> > > > On Tue, Jul 14, 2020 at 9:09 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > > > > On Mon, Jul 13, 2020 at 11:35 PM Lad Prabhakar
> > > > Also the recent patch to add
> > > > "r8a77961" just adds to soc_rcar_gen3_whitelist.
> > >
> > > Oops, commit 17fe16181639801b ("iommu/renesas: Add support for r8a77961")
> > > did it wrong, too.
> >
> > Thank you for the point it out. We should add r8a77961 to the soc_rcar_gen3[].
> > However, I don't know why I could not realize this issue...
> > So, I investigated this a little and then, IIUC, glob_match() which
> > soc_device_match() uses seems to return true, if *pat = "r8a7796" and *str = "r8a77961".
>
> Are you sure about this?
I'm very sorry. I completely misunderstood the glob_match() behavior.
And, now I understood why the current code can use IPMMU on r8a77961...
# Since the first soc_device_match() will return false, ipmmu_slave_whitelist()
# will return true and then the ipmmu_of_xlate() will be succeeded.
> I enabled CONFIG_GLOB_SELFTEST, and globtest succeeded.
> It does test glob_match("a", "aa"), which is a similar test.
>
> To be 100% sure, I added:
>
> --- a/lib/globtest.c
> +++ b/lib/globtest.c
> @@ -59,6 +59,7 @@ static char const glob_tests[] __initconst =
> "1" "a\0" "a\0"
> "0" "a\0" "b\0"
> "0" "a\0" "aa\0"
> + "0" "r8a7796\0" "r8a77961\0"
> "0" "a\0" "\0"
> "1" "\0" "\0"
> "0" "\0" "a\0"
>
> and it still succeeded.
I'm very sorry to waste your time about this...
Best regards,
Yoshihiro Shimoda
^ permalink raw reply
* Re: [PATCH v8 6/7] arm64: dts: add dts nodes for MT6779
From: Hanks Chen @ 2020-07-16 4:04 UTC (permalink / raw)
To: Matthias Brugger
Cc: Linus Walleij, Rob Herring, Michael Turquette, Stephen Boyd,
Sean Wang, mtk01761, Andy Teng, linux-gpio, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, wsd_upstream,
CC Hwang, Loda Chou
In-Reply-To: <1b335463-b0af-9010-feed-c4b673ebb6c5@gmail.com>
On Tue, 2020-07-14 at 20:14 +0200, Matthias Brugger wrote:
>
> On 14/07/2020 11:20, Hanks Chen wrote:
> > this adds initial MT6779 dts settings for board support,
> > including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
> >
> > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
> > arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 ++++++++++++++++++++
> > 3 files changed, 303 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
> >
> [...]
> > +
> > + uart0: serial@11002000 {
> > + compatible = "mediatek,mt6779-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11002000 0 0x400>;
> > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + uart1: serial@11003000 {
> > + compatible = "mediatek,mt6779-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11003000 0 0x400>;
> > + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial@11004000 {
> > + compatible = "mediatek,mt6779-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11004000 0 0x400>;
> > + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>;
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
>
> Devicetree describes the HW we have. As far as I know, we have 4 UARTs on
> MT6779. So we should list them all here.
>
Actually, We have only 3 UARTs HW on MT6779, but have 4 UART clk in
header file of clk.
CLK_INFRA_UART3 is a dummy clk interface, it has no effect on the
operation of the read/write instruction.
If you think it is not good, I can remove it in the header file of clk.
Thanks
> Regards,
> Matthias
^ permalink raw reply
* [PATCH v2 5/8] dt-bindings: pinctrl: realtek: Add Realtek DHC SoC rtd1295
From: TY Chang @ 2020-07-16 2:33 UTC (permalink / raw)
To: linux-realtek-soc, afaerber
Cc: linus.walleij, linux-gpio, robh+dt, devicetree, linux-kernel
In-Reply-To: <20200716023338.14922-1-tychang@realtek.com>
Add device tree binding Documentation for rtd1295
pinctrl driver.
Signed-off-by: TY Chang <tychang@realtek.com>
---
.../pinctrl/realtek,rtd1295-pinctrl.yaml | 121 ++++++++++++++++++
1 file changed, 121 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/realtek,rtd1295-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1295-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1295-pinctrl.yaml
new file mode 100644
index 000000000000..8cd6cfa2282e
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1295-pinctrl.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1295-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek DHC RTD1295 pin control
+
+maintainers:
+ - Andreas Farber <afaerber@suse.de>
+
+properties:
+ compatible:
+ enum:
+ - realtek,rtd1295-iso-pinctrl
+ - realtek,rtd1295-sb2-pinctrl
+ - realtek,rtd1295-disp-pinctrl
+ - realtek,rtd1295-cr-pinctrl
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ allOf:
+ - $ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+ properties:
+ groups:
+ items:
+ enum: [ iso_gpio_0, iso_gpio_1, iso_gpio_2, iso_gpio_3, iso_gpio_4,
+ iso_gpio_5, hdmi_hpd, iso_gpio_7, ir_rx, ir_tx, ur0_rx,
+ ur0_tx, ur1_rx, ur1_tx, ur1_cts_n, ur1_rts_n, i2c_scl_0,
+ i2c_sda_0, i2c_scl_1, i2c_sda_1, i2c_scl_6, iso_gpio_21,
+ iso_gpio_22, iso_gpio_23, iso_gpio_24, iso_gpio_25,
+ i2c_sda_6, etn_led_link, etn_led_rxtx, nat_led_0,
+ nat_led_1, nat_led_2, nat_led_3, iso_gpio_33,
+ iso_gpio_34, pwm_23_loc0, pwm_01_loc0, pwm_23_loc1,
+ pwm_01_loc1, ejtag_avcpu_loc, ur2_loc, i2c0, i2c1,
+ i2c6, uart0, uart1, uart2_0, uart2_1, gpio_0, gpio_1,
+ gpio_2, gpio_3, gpio_4, gpio_5, gpio_6, gpio_7, gpio_8,
+ gpio_9, tp1_sync, i2c_scl_4, i2c_sda_4, i2c_scl_5,
+ i2c_sda_5, usb_id, sensor_cko_0, sensor_cko_1, sensor_rst,
+ sensor_stb_0, sensor_stb_1, tp0_data, tp0_clk, tp0_valid,
+ tp0_sync, tp1_data, tp1_clk, tp1_valid, rgmii0_txc,
+ rgmii0_tx_ctl,rgmii0_txd_0, rgmii0_txd_1, rgmii0_txd_2,
+ rgmii0_txd_3, rgmii0_rxc, rgmii0_rx_ctl, rgmii0_rxd_0,
+ rgmii0_rxd_1, rgmii0_rxd_2, rgmii0_rxd_3, rgmii0_mdio,
+ rgmii0_mdc, rgmii1_txc, rgmii1_tx_ctl, rgmii1_txd_0,
+ rgmii1_txd_1, rgmii1_txd_2, rgmii1_txd_3, rgmii1_rxc,
+ rgmii1_rx_ctl, rgmii1_rxd_0, rgmii1_rxd_1, rgmii1_rxd_2,
+ rgmii1_rxd_3, hif_loc, ejtag_scpu_loc, sf_en, tp0_loc,
+ tp1_loc, spdif, dmic_clk, dmic_data, ao_lrck, ao_bck,
+ aock, ao_sd_0, ao_sd_1, ao_sd_2, ao_sd_3, nf_cle,
+ nf_ale, nf_rd_n, nf_wr_n, nf_rdy, nf_dd_7, nf_dd_6,
+ nf_dd_5, nf_dd_4, nf_dd_3, nf_dd_2, nf_dd_1, nf_dd_0,
+ nf_dqs, nf_ce_n_0, nf_ce_n_1, emmc_dd_sb, mmc_cmd,
+ mmc_clk, mmc_wp, mmc_cd, mmc_data_0, mmc_data_1,
+ mmc_data_2, mmc_data_3, sdio_cmd, sdio_clk, sdio_data_0,
+ sdio_data_1, sdio_data_2, sdio_data_3, pcie_clkreq_0,
+ pcie_clkreq_1, prob_0, prob_1, prob_2, prob_3, sdio_loc ]
+ minItems: 1
+
+ function:
+ enum: [ gpio, acpu_ejtag_loc_iso, edp_hpd, etn_led, i2c0, i2c1, i2c6,
+ ir_rx, ir_tx, nat_led, pwm_0, pwm_1, rtc, sc, standby_dbg,
+ uart0, uart1, uart2_0, uart2_1, pwm_01_loc0_normal,
+ pwm_23_loc0_normal, pwm_01_loc0_open_drain, pwm_23_loc0_open_drain,
+ pwm_01_loc1_normal, pwm_23_loc1_normal, pwm_01_loc1_open_drain,
+ pwm_23_loc1_open_drain, acpu_ejtag_loc_nf, ai, dc_fan_sensor,
+ eth_gpy, gspi, i2c2, i2c3, i2c4, i2c5, nand, rgmii, scpu_ejtag_loc_gpio,
+ sensor_cko_output, spi, test_loop_dis, tp0_loc_rgmii0_tx, tp0_loc_tp0,
+ tp0_loc_tp1, tp1_loc_rgmii0_rx, tp1_loc_tp0, tp1_loc_tp1,
+ usb_clock_output, hif_loc_misc, hif_loc_nf, scpu_ejtag_loc_cr, ao,
+ dmic, spdif_out, avcpu_ej, emmc, hif, nand, p2s, pcie, pll_test,
+ scpu_ejtag_loc_cr, sd_card, sdio_0, sdio_1 ]
+
+ drive-strength:
+ enum: [2, 4, 8]
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ input-schmitt-disable: true
+
+ input-schmitt-enable: true
+
+ required:
+ - groups
+ - function
+
+ additionalProperties: false
+
+examples:
+ - |
+ iso_pinctrl: pinctrl@300 {
+ compatible = "realtek,rtd1295-iso-pinctrl";
+ reg = <0x300 0x24>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&etn_led_pins>;
+
+ etn_led_pins: etn-led-pins {
+ function = "etn_led";
+ groups = "etn_led_link", "etn_led_rxtx";
+ bias-pull-up;
+ drive-strength = <4>;
+ };
+ };
+
--
2.27.0
^ permalink raw reply related
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