* [PATCH] dt-bindings: ingenic,pinctrl: Support pinmux/pinconf nodes
From: Paul Cercueil @ 2020-07-16 23:32 UTC (permalink / raw)
To: Rob Herring, Linus Walleij
Cc: od, linux-gpio, devicetree, linux-kernel, Paul Cercueil
Add YAML to describe the pinmux/pinconf sub-nodes of the pinctrl IP on
Ingenic SoCs.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
In-Reply-To: CAL_Jsq+nHZsbOMPpXC7NWp1etgVL57Q+o=gr6BJ6ijAq1pLJUw@mail.gmail.com
---
.../bindings/pinctrl/ingenic,pinctrl.yaml | 41 ++++++++++++++++++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
index adf462cc2737..9d374f55ebb1 100644
--- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
@@ -110,7 +110,46 @@ required:
- "#address-cells"
- "#size-cells"
-additionalProperties: false
+additionalProperties:
+ anyOf:
+ - type: object
+ allOf:
+ - $ref: pincfg-node.yaml#
+ - $ref: pinmux-node.yaml#
+
+ properties:
+ phandle: true
+ function: true
+ groups: true
+ pins: true
+ bias-disable: true
+ bias-pull-up: true
+ bias-pull-down: true
+ output-low: true
+ output-high: true
+ additionalProperties: false
+
+ - type: object
+ properties:
+ phandle: true
+ additionalProperties:
+ type: object
+ allOf:
+ - $ref: pincfg-node.yaml#
+ - $ref: pinmux-node.yaml#
+
+ properties:
+ phandle: true
+ function: true
+ groups: true
+ pins: true
+ bias-disable: true
+ bias-pull-up: true
+ bias-pull-down: true
+ output-low: true
+ output-high: true
+ additionalProperties: false
+
examples:
- |
--
2.27.0
^ permalink raw reply related
* Re: [PATCH v3 3/5] pinctrl: qcom: Use return value from irq_set_wake call
From: Doug Anderson @ 2020-07-16 21:51 UTC (permalink / raw)
To: Linus Walleij
Cc: Maulik Shah, Bjorn Andersson, Marc Zyngier, Stephen Boyd,
Evan Green, Matthias Kaehlcke, linux-kernel@vger.kernel.org, MSM,
open list:GPIO SUBSYSTEM, Andy Gross, Thomas Gleixner,
Jason Cooper, Rajendra Nayak, Lina Iyer,
open list:GPIO SUBSYSTEM <linux-gpio@vger.kernel.org>, Andy Gross <agross@kernel.org>, Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Doug Anderson <dianders@chromium.org>, Rajendra Nayak <rnayak@codeaurora.org>, Lina Iyer <ilina@codeaurora.org>,
In-Reply-To: <CACRpkdb-3Tf4s5=Gxjhy62GX=HUYkLOcPKZ6JWaLTQipz-0r6A@mail.gmail.com>
Hi,
On Thu, Jul 16, 2020 at 6:19 AM Linus Walleij <linus.walleij@linaro.org> wrote:
>
> On Mon, Jun 22, 2020 at 11:32 AM Maulik Shah <mkshah@codeaurora.org> wrote:
>
> > msmgpio irqchip is not using return value of irq_set_wake call.
> > Start using it.
> >
> > Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy")
> > Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
>
> Is this something that's causing regressions so I should apply it for
> fixes, or is it fine to keep this with the rest of the series for v5.9?
I would let Maulik comment more, but as far as I can tell the function
has been ignoring the return value of irq_set_irq_wake() for much
longer. Presumably one could logically say:
Fixes: 6aced33f4974 ("pinctrl: msm: drop wake_irqs bitmap")
...though when you get past the commit that Maulik tagged you need a
backport rather than a straight cherry-pick.
That would make me believe that there is no real hurry to land the fix here.
-Doug
^ permalink raw reply
* [PATCH v2 2/2] pinctrl: qcom: Add msm8226 pinctrl driver.
From: Bartosz Dudziak @ 2020-07-16 20:55 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Bartosz Dudziak, Andy Gross, Linus Walleij, Rob Herring,
linux-arm-msm, linux-gpio, devicetree, linux-kernel
In-Reply-To: <20200716205530.22910-1-bartosz.dudziak@snejp.pl>
Add initial Qualcomm msm8226 pinctrl driver to support pin configuration
with pinctrl framework for msm8226 SoC.
- Initial formatting and style was taken from the msm8x74 pinctrl driver
added by Björn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
---
drivers/pinctrl/qcom/Kconfig | 9 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-msm8226.c | 631 +++++++++++++++++++++++++
3 files changed, 641 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8226.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index ff1ee159dc..97ddc535fc 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -60,6 +60,15 @@ config PINCTRL_IPQ6018
Qualcomm Technologies Inc. IPQ6018 platform. Select this for
IPQ6018.
+config PINCTRL_MSM8226
+ tristate "Qualcomm 8226 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc MSM8226 platform.
+
config PINCTRL_MSM8660
tristate "Qualcomm 8660 pin controller driver"
depends on GPIOLIB && OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 061ec9fb65..9e3d9c91a4 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o
+obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o
obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c
new file mode 100644
index 0000000000..82010703c3
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c
@@ -0,0 +1,631 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+static const struct pinctrl_pin_desc msm8226_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+ PINCTRL_PIN(70, "GPIO_70"),
+ PINCTRL_PIN(71, "GPIO_71"),
+ PINCTRL_PIN(72, "GPIO_72"),
+ PINCTRL_PIN(73, "GPIO_73"),
+ PINCTRL_PIN(74, "GPIO_74"),
+ PINCTRL_PIN(75, "GPIO_75"),
+ PINCTRL_PIN(76, "GPIO_76"),
+ PINCTRL_PIN(77, "GPIO_77"),
+ PINCTRL_PIN(78, "GPIO_78"),
+ PINCTRL_PIN(79, "GPIO_79"),
+ PINCTRL_PIN(80, "GPIO_80"),
+ PINCTRL_PIN(81, "GPIO_81"),
+ PINCTRL_PIN(82, "GPIO_82"),
+ PINCTRL_PIN(83, "GPIO_83"),
+ PINCTRL_PIN(84, "GPIO_84"),
+ PINCTRL_PIN(85, "GPIO_85"),
+ PINCTRL_PIN(86, "GPIO_86"),
+ PINCTRL_PIN(87, "GPIO_87"),
+ PINCTRL_PIN(88, "GPIO_88"),
+ PINCTRL_PIN(89, "GPIO_89"),
+ PINCTRL_PIN(90, "GPIO_90"),
+ PINCTRL_PIN(91, "GPIO_91"),
+ PINCTRL_PIN(92, "GPIO_92"),
+ PINCTRL_PIN(93, "GPIO_93"),
+ PINCTRL_PIN(94, "GPIO_94"),
+ PINCTRL_PIN(95, "GPIO_95"),
+ PINCTRL_PIN(96, "GPIO_96"),
+ PINCTRL_PIN(97, "GPIO_97"),
+ PINCTRL_PIN(98, "GPIO_98"),
+ PINCTRL_PIN(99, "GPIO_99"),
+ PINCTRL_PIN(100, "GPIO_100"),
+ PINCTRL_PIN(101, "GPIO_101"),
+ PINCTRL_PIN(102, "GPIO_102"),
+ PINCTRL_PIN(103, "GPIO_103"),
+ PINCTRL_PIN(104, "GPIO_104"),
+ PINCTRL_PIN(105, "GPIO_105"),
+ PINCTRL_PIN(106, "GPIO_106"),
+ PINCTRL_PIN(107, "GPIO_107"),
+ PINCTRL_PIN(108, "GPIO_108"),
+ PINCTRL_PIN(109, "GPIO_109"),
+ PINCTRL_PIN(110, "GPIO_110"),
+ PINCTRL_PIN(111, "GPIO_111"),
+ PINCTRL_PIN(112, "GPIO_112"),
+ PINCTRL_PIN(113, "GPIO_113"),
+ PINCTRL_PIN(114, "GPIO_114"),
+ PINCTRL_PIN(115, "GPIO_115"),
+ PINCTRL_PIN(116, "GPIO_116"),
+
+ PINCTRL_PIN(117, "SDC1_CLK"),
+ PINCTRL_PIN(118, "SDC1_CMD"),
+ PINCTRL_PIN(119, "SDC1_DATA"),
+ PINCTRL_PIN(120, "SDC2_CLK"),
+ PINCTRL_PIN(121, "SDC2_CMD"),
+ PINCTRL_PIN(122, "SDC2_DATA"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+DECLARE_MSM_GPIO_PINS(65);
+DECLARE_MSM_GPIO_PINS(66);
+DECLARE_MSM_GPIO_PINS(67);
+DECLARE_MSM_GPIO_PINS(68);
+DECLARE_MSM_GPIO_PINS(69);
+DECLARE_MSM_GPIO_PINS(70);
+DECLARE_MSM_GPIO_PINS(71);
+DECLARE_MSM_GPIO_PINS(72);
+DECLARE_MSM_GPIO_PINS(73);
+DECLARE_MSM_GPIO_PINS(74);
+DECLARE_MSM_GPIO_PINS(75);
+DECLARE_MSM_GPIO_PINS(76);
+DECLARE_MSM_GPIO_PINS(77);
+DECLARE_MSM_GPIO_PINS(78);
+DECLARE_MSM_GPIO_PINS(79);
+DECLARE_MSM_GPIO_PINS(80);
+DECLARE_MSM_GPIO_PINS(81);
+DECLARE_MSM_GPIO_PINS(82);
+DECLARE_MSM_GPIO_PINS(83);
+DECLARE_MSM_GPIO_PINS(84);
+DECLARE_MSM_GPIO_PINS(85);
+DECLARE_MSM_GPIO_PINS(86);
+DECLARE_MSM_GPIO_PINS(87);
+DECLARE_MSM_GPIO_PINS(88);
+DECLARE_MSM_GPIO_PINS(89);
+DECLARE_MSM_GPIO_PINS(90);
+DECLARE_MSM_GPIO_PINS(91);
+DECLARE_MSM_GPIO_PINS(92);
+DECLARE_MSM_GPIO_PINS(93);
+DECLARE_MSM_GPIO_PINS(94);
+DECLARE_MSM_GPIO_PINS(95);
+DECLARE_MSM_GPIO_PINS(96);
+DECLARE_MSM_GPIO_PINS(97);
+DECLARE_MSM_GPIO_PINS(98);
+DECLARE_MSM_GPIO_PINS(99);
+DECLARE_MSM_GPIO_PINS(100);
+DECLARE_MSM_GPIO_PINS(101);
+DECLARE_MSM_GPIO_PINS(102);
+DECLARE_MSM_GPIO_PINS(103);
+DECLARE_MSM_GPIO_PINS(104);
+DECLARE_MSM_GPIO_PINS(105);
+DECLARE_MSM_GPIO_PINS(106);
+DECLARE_MSM_GPIO_PINS(107);
+DECLARE_MSM_GPIO_PINS(108);
+DECLARE_MSM_GPIO_PINS(109);
+DECLARE_MSM_GPIO_PINS(110);
+DECLARE_MSM_GPIO_PINS(111);
+DECLARE_MSM_GPIO_PINS(112);
+DECLARE_MSM_GPIO_PINS(113);
+DECLARE_MSM_GPIO_PINS(114);
+DECLARE_MSM_GPIO_PINS(115);
+DECLARE_MSM_GPIO_PINS(116);
+
+static const unsigned int sdc1_clk_pins[] = { 117 };
+static const unsigned int sdc1_cmd_pins[] = { 118 };
+static const unsigned int sdc1_data_pins[] = { 119 };
+static const unsigned int sdc2_clk_pins[] = { 120 };
+static const unsigned int sdc2_cmd_pins[] = { 121 };
+static const unsigned int sdc2_data_pins[] = { 122 };
+
+#define FUNCTION(fname) \
+ [MSM_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ MSM_MUX_gpio, \
+ MSM_MUX_##f1, \
+ MSM_MUX_##f2, \
+ MSM_MUX_##f3, \
+ MSM_MUX_##f4, \
+ MSM_MUX_##f5, \
+ MSM_MUX_##f6, \
+ MSM_MUX_##f7 \
+ }, \
+ .nfuncs = 8, \
+ .ctl_reg = 0x1000 + 0x10 * id, \
+ .io_reg = 0x1004 + 0x10 * id, \
+ .intr_cfg_reg = 0x1008 + 0x10 * id, \
+ .intr_status_reg = 0x100c + 0x10 * id, \
+ .intr_target_reg = 0x1008 + 0x10 * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 4, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_target_kpss_val = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
+/*
+ * TODO: Add the rest of the possible functions and fill out
+ * the pingroup table below.
+ */
+enum msm8226_functions {
+ MSM_MUX_gpio,
+ MSM_MUX_cci_i2c0,
+ MSM_MUX_blsp_i2c1,
+ MSM_MUX_blsp_i2c2,
+ MSM_MUX_blsp_i2c3,
+ MSM_MUX_blsp_i2c5,
+ MSM_MUX_blsp_spi1,
+ MSM_MUX_blsp_spi2,
+ MSM_MUX_blsp_spi3,
+ MSM_MUX_blsp_spi5,
+ MSM_MUX_blsp_uart1,
+ MSM_MUX_blsp_uart2,
+ MSM_MUX_blsp_uart3,
+ MSM_MUX_blsp_uart5,
+ MSM_MUX_blsp_uim1,
+ MSM_MUX_blsp_uim2,
+ MSM_MUX_blsp_uim3,
+ MSM_MUX_blsp_uim5,
+ MSM_MUX_cam_mclk0,
+ MSM_MUX_cam_mclk1,
+ MSM_MUX_wlan,
+ MSM_MUX_NA,
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
+ "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
+ "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
+ "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
+ "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
+};
+
+static const char * const blsp_uart1_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3"
+};
+
+static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" };
+static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" };
+static const char * const blsp_spi1_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3"
+};
+
+static const char * const blsp_uart2_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7"
+};
+
+static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" };
+static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" };
+static const char * const blsp_spi2_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7"
+};
+
+static const char * const blsp_uart3_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+
+static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" };
+static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" };
+static const char * const blsp_spi3_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+
+static const char * const blsp_uart5_groups[] = {
+ "gpio16", "gpio17", "gpio18", "gpio19"
+};
+
+static const char * const blsp_uim5_groups[] = { "gpio16", "gpio17" };
+static const char * const blsp_i2c5_groups[] = { "gpio18", "gpio19" };
+static const char * const blsp_spi5_groups[] = {
+ "gpio16", "gpio17", "gpio18", "gpio19"
+};
+
+static const char * const cci_i2c0_groups[] = { "gpio29", "gpio30" };
+
+static const char * const cam_mclk0_groups[] = { "gpio26" };
+static const char * const cam_mclk1_groups[] = { "gpio27" };
+
+static const char * const wlan_groups[] = {
+ "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"
+};
+
+static const struct msm_function msm8226_functions[] = {
+ FUNCTION(gpio),
+ FUNCTION(cci_i2c0),
+ FUNCTION(blsp_uim1),
+ FUNCTION(blsp_uim2),
+ FUNCTION(blsp_uim3),
+ FUNCTION(blsp_uim5),
+ FUNCTION(blsp_i2c1),
+ FUNCTION(blsp_i2c2),
+ FUNCTION(blsp_i2c3),
+ FUNCTION(blsp_i2c5),
+ FUNCTION(blsp_spi1),
+ FUNCTION(blsp_spi2),
+ FUNCTION(blsp_spi3),
+ FUNCTION(blsp_spi5),
+ FUNCTION(blsp_uart1),
+ FUNCTION(blsp_uart2),
+ FUNCTION(blsp_uart3),
+ FUNCTION(blsp_uart5),
+ FUNCTION(cam_mclk0),
+ FUNCTION(cam_mclk1),
+ FUNCTION(wlan),
+};
+
+static const struct msm_pingroup msm8226_groups[] = {
+ PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
+ PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
+ PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
+ PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
+ PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
+ PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
+ PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
+ PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
+ PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, NA, NA, NA, NA),
+ PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, NA, NA, NA, NA),
+ PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
+ PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
+ PINGROUP(12, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(13, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(14, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(15, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(16, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
+ PINGROUP(17, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
+ PINGROUP(18, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
+ PINGROUP(19, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
+ PINGROUP(20, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(21, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(22, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(23, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(24, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(25, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(26, cam_mclk0, NA, NA, NA, NA, NA, NA),
+ PINGROUP(27, cam_mclk1, NA, NA, NA, NA, NA, NA),
+ PINGROUP(28, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(29, cci_i2c0, NA, NA, NA, NA, NA, NA),
+ PINGROUP(30, cci_i2c0, NA, NA, NA, NA, NA, NA),
+ PINGROUP(31, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(32, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(33, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(34, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(35, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(36, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(37, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(38, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(39, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(40, wlan, NA, NA, NA, NA, NA, NA),
+ PINGROUP(41, wlan, NA, NA, NA, NA, NA, NA),
+ PINGROUP(42, wlan, NA, NA, NA, NA, NA, NA),
+ PINGROUP(43, wlan, NA, NA, NA, NA, NA, NA),
+ PINGROUP(44, wlan, NA, NA, NA, NA, NA, NA),
+ PINGROUP(45, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(46, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(47, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(48, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(49, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(50, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(51, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(52, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(53, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(54, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(55, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(56, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(57, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(58, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(59, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(60, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(61, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(62, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(63, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(64, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(65, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(66, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(67, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(68, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(69, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(70, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(71, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(72, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(73, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(74, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(75, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(76, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(77, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(78, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(79, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(80, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(81, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(82, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(83, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(84, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(85, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(86, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(87, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(88, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(89, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(90, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(91, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(92, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(93, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(94, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(95, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(96, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(97, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(98, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(99, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(100, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(101, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(102, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(103, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(104, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(105, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(106, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(107, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(108, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(109, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(110, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(111, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(112, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(113, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(114, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(115, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(116, NA, NA, NA, NA, NA, NA, NA),
+ SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6),
+ SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3),
+ SDC_PINGROUP(sdc1_data, 0x2044, 9, 0),
+ SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6),
+ SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3),
+ SDC_PINGROUP(sdc2_data, 0x2048, 9, 0),
+};
+
+#define NUM_GPIO_PINGROUPS 117
+
+static const struct msm_pinctrl_soc_data msm8226_pinctrl = {
+ .pins = msm8226_pins,
+ .npins = ARRAY_SIZE(msm8226_pins),
+ .functions = msm8226_functions,
+ .nfunctions = ARRAY_SIZE(msm8226_functions),
+ .groups = msm8226_groups,
+ .ngroups = ARRAY_SIZE(msm8226_groups),
+ .ngpios = NUM_GPIO_PINGROUPS,
+};
+
+static int msm8226_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &msm8226_pinctrl);
+}
+
+static const struct of_device_id msm8226_pinctrl_of_match[] = {
+ { .compatible = "qcom,msm8226-pinctrl", },
+ { },
+};
+
+static struct platform_driver msm8226_pinctrl_driver = {
+ .driver = {
+ .name = "msm8226-pinctrl",
+ .of_match_table = msm8226_pinctrl_of_match,
+ },
+ .probe = msm8226_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init msm8226_pinctrl_init(void)
+{
+ return platform_driver_register(&msm8226_pinctrl_driver);
+}
+arch_initcall(msm8226_pinctrl_init);
+
+static void __exit msm8226_pinctrl_exit(void)
+{
+ platform_driver_unregister(&msm8226_pinctrl_driver);
+}
+module_exit(msm8226_pinctrl_exit);
+
+MODULE_AUTHOR("Bartosz Dudziak <bartosz.dudziak@snejp.pl>");
+MODULE_DESCRIPTION("Qualcomm MSM8226 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, msm8226_pinctrl_of_match);
+
--
2.25.1
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: pinctrl: qcom: Add msm8226 pinctrl bindings
From: Bartosz Dudziak @ 2020-07-16 20:55 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Bartosz Dudziak, Andy Gross, Linus Walleij, Rob Herring,
linux-arm-msm, linux-gpio, devicetree, linux-kernel
In-Reply-To: <20200716205530.22910-1-bartosz.dudziak@snejp.pl>
Add device tree binding Documentation details for Qualcomm msm8226
pinctrl driver.
- Bindings documentation was based on qcom,ipq6018-pinctrl.yaml added by
Sricharan R <sricharan@codeaurora.org> and then modified for msm8226
content
Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
---
.../pinctrl/qcom,msm8226-pinctrl.yaml | 132 ++++++++++++++++++
1 file changed, 132 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
new file mode 100644
index 0000000000..1f0f5757f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. MSM8226 TLMM block
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ MSM8226 platform.
+
+properties:
+ compatible:
+ const: qcom,msm8226-pinctrl
+
+ reg:
+ description: Specifies the base address and size of the TLMM register space
+ maxItems: 1
+
+ interrupts:
+ description: Specifies the TLMM summary IRQ
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ description: Specifies the PIN numbers and Flags, as defined in
+ include/dt-bindings/interrupt-controller/irq.h
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ gpio-reserved-ranges:
+ maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$"
+ - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
+ minItems: 1
+ maxItems: 36
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins. Functions are only valid for gpio pins.
+ enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
+ blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c5, blsp_spi1,
+ blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
+ blsp_uart3, blsp_uart5, cam_mclk0, cam_mclk1, wlan ]
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ msmgpio: pinctrl@fd510000 {
+ compatible = "qcom,msm8226-pinctrl";
+ reg = <0xfd510000 0x4000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&msmgpio 0 0 117>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+ serial-pins {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart3";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
--
2.25.1
^ permalink raw reply related
* [PATCH v2 0/2] Qualcomm MSM8226 TLMM binding and driver
From: Bartosz Dudziak @ 2020-07-16 20:55 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Bartosz Dudziak, Andy Gross, Linus Walleij, Rob Herring,
linux-arm-msm, linux-gpio, devicetree, linux-kernel
Binding and driver for the Qualcomm MSM8226 TLMM pinctrl block
Changes in v2:
- Changed node name pattern to '-pins$' in qcom,msm8226-pinctrl.yaml binding
- Expanded example in yaml binding with a 'serial-pins' node sample
Bartosz Dudziak (2):
dt-bindings: pinctrl: qcom: Add msm8226 pinctrl bindings
pinctrl: qcom: Add msm8226 pinctrl driver.
.../pinctrl/qcom,msm8226-pinctrl.yaml | 132 ++++
drivers/pinctrl/qcom/Kconfig | 9 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-msm8226.c | 631 ++++++++++++++++++
4 files changed, 773 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8226.c
--
2.25.1
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: pinctrl: qcom: Add msm8226 pinctrl bindings
From: Bartosz Dudziak @ 2020-07-16 21:29 UTC (permalink / raw)
To: Rob Herring
Cc: Bjorn Andersson, Andy Gross, Linus Walleij, linux-arm-msm,
linux-gpio, devicetree, linux-kernel
In-Reply-To: <20200715202413.GA755488@bogus>
On Wed, Jul 15, 2020 at 02:24:13PM -0600, Rob Herring wrote:
> On Sat, Jun 27, 2020 at 09:28:30PM +0200, Bartosz Dudziak wrote:
> > Add device tree binding Documentation details for Qualcomm msm8226
> > pinctrl driver.
> >
> > - Bindings documentation was based on qcom,sm8250-pinctrl.yaml by
> > Bjorn Andersson <bjorn.andersson@linaro.org> and then modified for
> > msm8226 content
> >
> > Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
> > ---
> > .../pinctrl/qcom,msm8226-pinctrl.yaml | 123 ++++++++++++++++++
> > 1 file changed, 123 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
> > new file mode 100644
> > index 0000000000..8d8dc15718
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
> > @@ -0,0 +1,123 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Qualcomm Technologies, Inc. MSM8226 TLMM block
> > +
> > +maintainers:
> > + - Bjorn Andersson <bjorn.andersson@linaro.org>
> > +
> > +description: |
> > + This binding describes the Top Level Mode Multiplexer block found in the
> > + MSM8226 platform.
> > +
> > +properties:
> > + compatible:
> > + const: qcom,msm8226-pinctrl
> > +
> > + reg:
> > + description: Specifies the base address and size of the TLMM register space
> > + maxItems: 1
> > +
> > + interrupts:
> > + description: Specifies the TLMM summary IRQ
> > + maxItems: 1
> > +
> > + interrupt-controller: true
> > +
> > + '#interrupt-cells':
> > + description: Specifies the PIN numbers and Flags, as defined in
> > + include/dt-bindings/interrupt-controller/irq.h
> > + const: 2
> > +
> > + gpio-controller: true
> > +
> > + '#gpio-cells':
> > + description: Specifying the pin number and flags, as defined in
> > + include/dt-bindings/gpio/gpio.h
> > + const: 2
> > +
> > + gpio-ranges:
> > + maxItems: 1
> > +
> > + gpio-reserved-ranges:
> > + maxItems: 1
> > +
> > +#PIN CONFIGURATION NODES
> > +patternProperties:
> > + '^.*$':
> > + if:
> > + type: object
>
> For new bindings, do '-pins$' for the node name pattern so we don't have
> to do this hack.
>
I have changed the name pattern and sent a v2 patch.
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: pinctrl: Add bindings for Actions S500 SoC
From: Cristian Ciocaltea @ 2020-07-16 21:26 UTC (permalink / raw)
To: Rob Herring
Cc: Andreas Färber, Manivannan Sadhasivam, Linus Walleij,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list:GPIO SUBSYSTEM, devicetree,
linux-kernel@vger.kernel.org, linux-actions
In-Reply-To: <CAL_Jsq+8bX5duv=116e=hve1L-h8a=5quqCHVtSAs4PjK6xc1w@mail.gmail.com>
On Thu, Jul 16, 2020 at 08:50:36AM -0600, Rob Herring wrote:
> On Thu, Jul 16, 2020 at 4:43 AM Cristian Ciocaltea
> <cristian.ciocaltea@gmail.com> wrote:
> >
> > On Wed, Jul 15, 2020 at 02:03:09PM -0600, Rob Herring wrote:
> > > On Thu, Jun 25, 2020 at 11:16:18PM +0300, Cristian Ciocaltea wrote:
> > > > Add pinctrl and gpio bindings for Actions Semi S500 SoC.
> > > >
> > > > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > > > ---
> > > > .../pinctrl/actions,s500-pinctrl.yaml | 228 ++++++++++++++++++
> > > > 1 file changed, 228 insertions(+)
> > > > create mode 100644 Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml
> > > > new file mode 100644
> > > > index 000000000000..856947c70844
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml
> > > > @@ -0,0 +1,228 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: Actions Semi S500 SoC pinmux & GPIO controller
> > > > +
> > > > +maintainers:
> > > > + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > > +
> > > > +description: |
> > > > + Pinmux & GPIO controller manages pin multiplexing & configuration including
> > > > + GPIO function selection & GPIO attributes configuration. Please refer to
> > > > + pinctrl-bindings.txt in this directory for common binding part and usage.
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + const: actions,s500-pinctrl
> > > > +
> > > > + reg:
> > > > + minItems: 1
> > > > + maxItems: 4
> > >
> > > Need to enumerate what each register range is.
> >
> > Hi Rob,
> >
> > Thanks for the review!
> >
> > Would the update below suffice?
> >
> > reg:
> > description: |
> > Specifies the memory region(s) associated with the pin-controller.
> > To improve granularity, up to four register ranges can be provided:
>
> What does 'improve granularity' mean:
Technically all the registers used by the driver could be specified via
a single contiguous range. However, there are a few unrelated registers
(i.e. PWM Output Control) which should be excluded in order to come up
with a more accurate specification. The 4 ranges below are basically
the result of this exclusion:
> > * GPIO Output + GPIO Input + GPIO Data
> > * Multiplexing Control
> > * PAD Pull Control + PAD Schmitt Trigger enable + PAD Control
> > * PAD Drive Capacity Select
>
> The h/w sometimes has these and sometimes doesn't?
No, the h/w is fixed, the only reason of this approach was to allow a
precise memory region specification, as explained above.
I'm not sure if this should be made mandatory or it's also fine to let
(a lazy) user provide combined ranges or just a contiguous one (like
in the example), with the drawback of loosing the accuracy, of course.
> If they do stay, then you want:
>
> items:
> - description: GPIO Output + GPIO Input + GPIO Data
> - description: ...
Would this be applicable even if we keep this flexible approach and
don't set 'minItems: 4'?
> >
> > > > +
> > > > + clocks:
> > > > + maxItems: 1
> > > > +
> > > > + gpio-controller: true
> > > > +
> > > > + gpio-ranges:
> > > > + maxItems: 1
> > > > +
> > > > + '#gpio-cells':
> > > > + description:
> > > > + Specifies the pin number and flags, as defined in
> > > > + include/dt-bindings/gpio/gpio.h
> > > > + const: 2
> > > > +
> > > > + interrupt-controller: true
> > > > +
> > > > + '#interrupt-cells':
> > > > + description:
> > > > + Specifies the pin number and flags, as defined in
> > > > + include/dt-bindings/interrupt-controller/irq.h
> > > > + const: 2
> > > > +
> > > > + interrupts:
> > > > + description:
> > > > + One interrupt per each of the 5 GPIO ports supported by the controller,
> > > > + sorted by port number ascending order.
> > > > + minItems: 5
> > > > + maxItems: 5
> > > > +
> > > > +patternProperties:
> > > > + '^.*$':
> > > > + if:
> > > > + type: object
> > >
> > > For a new binding, can you do '-pins$' for the node names so we don't
> > > need this if/then hack.
> >
> > Right, the idea was to be consistent with the existing bindings for
> > S700 and S900, which allow free node names, although they are not yet
> > converted to yaml format.
>
> If we want consistency, those should have their node names updated.
Fair enough, I have already updated the node names to use the '-pins'
suffix.
> >
> > > > + then:
> > > > + patternProperties:
> > > > + 'pinmux$':
> > >
> > > Is this really a pattern? Can't tell from the example.
> >
> > pinmux and pinconf subnodes may appear multiple times, that's why I
> > decided to match their names based on the suffix.
> >
> > The example is not complex enough, I will change it to the following:
> >
> > mmc0_default: mmc0_default {
> > pinmux {
> > groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
> > "sd0_cmd_mfp", "sd0_clk_mfp";
> > function = "sd0";
> > };
> >
> > drv_pinconf {
>
> drv-pinconf
>
> Make the pattern '-?pinconf' to enforce that. (that '-' may need escaping?)
Actually the pattern should be '^(.*-)?pinconf$', to restrict the names
to either 'pinconf' or '<label>-pinconf'.
I have just made some more validation tests and noticed I had missed an
'additionalProperties: false' line, for the 'pins' node. Should be fine
now!
Thanks,
Cristi
^ permalink raw reply
* Re: [gpio:ib-for-each-clump 4/4] include/linux/bitmap.h:639:45: sparse: sparse: shift too big (64) for type unsigned long
From: Andy Shevchenko @ 2020-07-16 21:25 UTC (permalink / raw)
To: kernel test robot
Cc: Syed Nayyar Waris, kbuild-all, open list:GPIO SUBSYSTEM,
Linus Walleij
In-Reply-To: <202007170339.nHjeGJBw%lkp@intel.com>
On Thu, Jul 16, 2020 at 11:13 PM kernel test robot <lkp@intel.com> wrote:
>
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git ib-for-each-clump
> head: 3358c938236d6a1be51124fbbb2698e50689d382
> commit: 3358c938236d6a1be51124fbbb2698e50689d382 [4/4] gpio: xilinx: Utilize generic bitmap_get_value and _set_value.
> config: alpha-randconfig-s031-20200716 (attached as .config)
> compiler: alpha-linux-gcc (GCC) 9.3.0
> reproduce:
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # apt-get install sparse
> # sparse version: v0.6.2-49-g707c5017-dirty
> git checkout 3358c938236d6a1be51124fbbb2698e50689d382
> # save the attached .config to linux build tree
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=alpha
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
>
> sparse warnings: (new ones prefixed by >>)
>
> >> include/linux/bitmap.h:639:45: sparse: sparse: shift too big (64) for type unsigned long
> >> include/linux/bitmap.h:639:45: sparse: sparse: shift too big (64) for type unsigned long
> include/linux/bitmap.h:594:63: sparse: sparse: shift too big (64) for type unsigned long
> >> include/linux/bitmap.h:639:45: sparse: sparse: shift too big (64) for type unsigned long
> >> include/linux/bitmap.h:638:17: sparse: sparse: invalid access past the end of 'old' (8 8)
>
> vim +639 include/linux/bitmap.h
>
> 169c474fb22d8a5 William Breathitt Gray 2019-12-04 613
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 614 /**
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 615 * bitmap_set_value - set n-bit value within a memory region
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 616 * @map: address to the bitmap memory region
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 617 * @value: value of nbits
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 618 * @start: bit offset of the n-bit value
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 619 * @nbits: size of value in bits
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 620 */
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 621 static inline void bitmap_set_value(unsigned long *map,
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 622 unsigned long value,
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 623 unsigned long start, unsigned long nbits)
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 624 {
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 625 const size_t index = BIT_WORD(start);
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 626 const unsigned long offset = start % BITS_PER_LONG;
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 627 const unsigned long ceiling = roundup(start + 1, BITS_PER_LONG);
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 628 const unsigned long space = ceiling - start;
If start == 0:
index = 0, offset = 0, ceiling = 64, space = 64
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 629
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 630 value &= GENMASK(nbits - 1, 0);
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 631
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 632 if (space >= nbits) {
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 633 map[index] &= ~(GENMASK(nbits + offset - 1, offset));
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 634 map[index] |= value << offset;
if nbits > space...
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 635 } else {
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 636 map[index] &= ~BITMAP_FIRST_WORD_MASK(start);
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 637 map[index] |= value << offset;
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 @638 map[index + 1] &= ~BITMAP_LAST_WORD_MASK(start + nbits);
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 @639 map[index + 1] |= (value >> space);
space = 64...
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 640 }
> e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 641 }
I don't see the test case for this. Can you provide one?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* [PATCH][next] pinctrl: single: Use fallthrough pseudo-keyword
From: Gustavo A. R. Silva @ 2020-07-16 21:23 UTC (permalink / raw)
To: Tony Lindgren, Haojian Zhuang, Linus Walleij
Cc: linux-arm-kernel, linux-omap, linux-gpio, linux-kernel,
Gustavo A. R. Silva
Replace the existing /* fall through */ comments and its variants with
the new pseudo-keyword macro fallthrough[1].
[1] https://www.kernel.org/doc/html/latest/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
---
drivers/pinctrl/pinctrl-single.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index e6d1cf25782c..132b36ef5d83 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -560,7 +560,7 @@ static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
case PIN_CONFIG_BIAS_PULL_UP:
if (arg)
pcs_pinconf_clear_bias(pctldev, pin);
- /* fall through */
+ fallthrough;
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
data &= ~func->conf[i].mask;
if (arg)
--
2.27.0
^ permalink raw reply related
* [PATCH][next] pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keyword
From: Gustavo A. R. Silva @ 2020-07-16 21:22 UTC (permalink / raw)
To: Bjorn Andersson, Andy Gross, Linus Walleij
Cc: linux-arm-msm, linux-gpio, linux-kernel, Gustavo A. R. Silva
Replace the existing /* fall through */ comments and its variants with
the new pseudo-keyword macro fallthrough[1].
[1] https://www.kernel.org/doc/html/latest/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
---
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 4 ++--
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
index 66cbcfe7950e..17441388ce8f 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
@@ -794,13 +794,13 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state,
switch (subtype) {
case PMIC_GPIO_SUBTYPE_GPIO_4CH:
pad->have_buffer = true;
- /* Fall through */
+ fallthrough;
case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
pad->num_sources = 4;
break;
case PMIC_GPIO_SUBTYPE_GPIO_8CH:
pad->have_buffer = true;
- /* Fall through */
+ fallthrough;
case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
pad->num_sources = 8;
break;
diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
index 338a15d08629..b5949f766a7a 100644
--- a/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
@@ -346,7 +346,7 @@ static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev,
return -EINVAL;
}
pin->pull_up_strength = arg;
- /* FALLTHROUGH */
+ fallthrough;
case PIN_CONFIG_BIAS_PULL_UP:
pin->bias = pin->pull_up_strength;
banks |= BIT(2);
--
2.27.0
^ permalink raw reply related
* [PATCH][next] pinctrl: lpc18xx: Use fallthrough pseudo-keyword
From: Gustavo A. R. Silva @ 2020-07-16 21:21 UTC (permalink / raw)
To: Linus Walleij, Vladimir Zapolskiy
Cc: linux-gpio, linux-arm-kernel, linux-kernel, Gustavo A. R. Silva
Replace the existing /* fall through */ comments and its variants with
the new pseudo-keyword macro fallthrough[1].
[1] https://www.kernel.org/doc/html/latest/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
---
drivers/pinctrl/pinctrl-lpc18xx.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c
index e4677546aec4..7b2f885e68bd 100644
--- a/drivers/pinctrl/pinctrl-lpc18xx.c
+++ b/drivers/pinctrl/pinctrl-lpc18xx.c
@@ -838,11 +838,11 @@ static int lpc18xx_pconf_get_pin(struct pinctrl_dev *pctldev, unsigned param,
*arg = (reg & LPC18XX_SCU_PIN_EHD_MASK) >> LPC18XX_SCU_PIN_EHD_POS;
switch (*arg) {
case 3: *arg += 5;
- /* fall through */
+ fallthrough;
case 2: *arg += 5;
- /* fall through */
+ fallthrough;
case 1: *arg += 3;
- /* fall through */
+ fallthrough;
case 0: *arg += 4;
}
break;
@@ -1057,11 +1057,11 @@ static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev, unsigned param,
switch (param_val) {
case 20: param_val -= 5;
- /* fall through */
+ fallthrough;
case 14: param_val -= 5;
- /* fall through */
+ fallthrough;
case 8: param_val -= 3;
- /* fall through */
+ fallthrough;
case 4: param_val -= 4;
break;
default:
--
2.27.0
^ permalink raw reply related
* [PATCH][next] pinctrl: baytrail: Use fallthrough pseudo-keyword
From: Gustavo A. R. Silva @ 2020-07-16 21:19 UTC (permalink / raw)
To: Mika Westerberg, Andy Shevchenko, Linus Walleij
Cc: linux-gpio, linux-kernel, Gustavo A. R. Silva
Replace the existing /* fall through */ comments and its variants with
the new pseudo-keyword macro fallthrough[1].
[1] https://www.kernel.org/doc/html/latest/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index a917a2df520e..d6e35cba3065 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -1372,13 +1372,13 @@ static void byt_irq_unmask(struct irq_data *d)
switch (irqd_get_trigger_type(d)) {
case IRQ_TYPE_LEVEL_HIGH:
value |= BYT_TRIG_LVL;
- /* fall through */
+ fallthrough;
case IRQ_TYPE_EDGE_RISING:
value |= BYT_TRIG_POS;
break;
case IRQ_TYPE_LEVEL_LOW:
value |= BYT_TRIG_LVL;
- /* fall through */
+ fallthrough;
case IRQ_TYPE_EDGE_FALLING:
value |= BYT_TRIG_NEG;
break;
--
2.27.0
^ permalink raw reply related
* [gpio:ib-for-each-clump 4/4] include/linux/bitmap.h:639:45: sparse: sparse: shift too big (64) for type unsigned long
From: kernel test robot @ 2020-07-16 19:48 UTC (permalink / raw)
To: Syed Nayyar Waris; +Cc: kbuild-all, linux-gpio, Linus Walleij
[-- Attachment #1: Type: text/plain, Size: 4449 bytes --]
tree: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git ib-for-each-clump
head: 3358c938236d6a1be51124fbbb2698e50689d382
commit: 3358c938236d6a1be51124fbbb2698e50689d382 [4/4] gpio: xilinx: Utilize generic bitmap_get_value and _set_value.
config: alpha-randconfig-s031-20200716 (attached as .config)
compiler: alpha-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.2-49-g707c5017-dirty
git checkout 3358c938236d6a1be51124fbbb2698e50689d382
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=alpha
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> include/linux/bitmap.h:639:45: sparse: sparse: shift too big (64) for type unsigned long
>> include/linux/bitmap.h:639:45: sparse: sparse: shift too big (64) for type unsigned long
include/linux/bitmap.h:594:63: sparse: sparse: shift too big (64) for type unsigned long
>> include/linux/bitmap.h:639:45: sparse: sparse: shift too big (64) for type unsigned long
>> include/linux/bitmap.h:638:17: sparse: sparse: invalid access past the end of 'old' (8 8)
vim +639 include/linux/bitmap.h
169c474fb22d8a5 William Breathitt Gray 2019-12-04 613
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 614 /**
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 615 * bitmap_set_value - set n-bit value within a memory region
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 616 * @map: address to the bitmap memory region
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 617 * @value: value of nbits
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 618 * @start: bit offset of the n-bit value
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 619 * @nbits: size of value in bits
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 620 */
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 621 static inline void bitmap_set_value(unsigned long *map,
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 622 unsigned long value,
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 623 unsigned long start, unsigned long nbits)
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 624 {
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 625 const size_t index = BIT_WORD(start);
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 626 const unsigned long offset = start % BITS_PER_LONG;
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 627 const unsigned long ceiling = roundup(start + 1, BITS_PER_LONG);
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 628 const unsigned long space = ceiling - start;
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 629
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 630 value &= GENMASK(nbits - 1, 0);
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 631
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 632 if (space >= nbits) {
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 633 map[index] &= ~(GENMASK(nbits + offset - 1, offset));
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 634 map[index] |= value << offset;
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 635 } else {
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 636 map[index] &= ~BITMAP_FIRST_WORD_MASK(start);
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 637 map[index] |= value << offset;
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 @638 map[index + 1] &= ~BITMAP_LAST_WORD_MASK(start + nbits);
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 @639 map[index + 1] |= (value >> space);
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 640 }
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 641 }
e77c9b6f35c4bdf Syed Nayyar Waris 2020-06-27 642
:::::: The code at line 639 was first introduced by commit
:::::: e77c9b6f35c4bdfa60c52f137a4b48c04ab87627 bitops: Introduce the for_each_set_clump macro
:::::: TO: Syed Nayyar Waris <syednwaris@gmail.com>
:::::: CC: Linus Walleij <linus.walleij@linaro.org>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 27345 bytes --]
^ permalink raw reply
* Re: [PATCH v2 5/8] dt-bindings: pinctrl: realtek: Add Realtek DHC SoC rtd1295
From: Rob Herring @ 2020-07-16 19:56 UTC (permalink / raw)
To: TY Chang
Cc: linux-realtek-soc, afaerber, linus.walleij, linux-gpio,
devicetree, linux-kernel
In-Reply-To: <20200716023338.14922-6-tychang@realtek.com>
On Thu, Jul 16, 2020 at 10:33:35AM +0800, TY Chang wrote:
> Add device tree binding Documentation for rtd1295
> pinctrl driver.
>
> Signed-off-by: TY Chang <tychang@realtek.com>
> ---
> .../pinctrl/realtek,rtd1295-pinctrl.yaml | 121 ++++++++++++++++++
> 1 file changed, 121 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/realtek,rtd1295-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1295-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1295-pinctrl.yaml
> new file mode 100644
> index 000000000000..8cd6cfa2282e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1295-pinctrl.yaml
> @@ -0,0 +1,121 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1295-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Realtek DHC RTD1295 pin control
> +
> +maintainers:
> + - Andreas Farber <afaerber@suse.de>
> +
> +properties:
> + compatible:
> + enum:
> + - realtek,rtd1295-iso-pinctrl
> + - realtek,rtd1295-sb2-pinctrl
> + - realtek,rtd1295-disp-pinctrl
> + - realtek,rtd1295-cr-pinctrl
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +#PIN CONFIGURATION NODES
> +patternProperties:
> + '-pins$':
> + type: object
> + description:
> + Pinctrl node's client devices use subnodes for desired pin configuration.
> + Client device subnodes use below standard properties.
> + allOf:
> + - $ref: "/schemas/pinctrl/pincfg-node.yaml"
> +
> + properties:
> + groups:
> + items:
> + enum: [ iso_gpio_0, iso_gpio_1, iso_gpio_2, iso_gpio_3, iso_gpio_4,
> + iso_gpio_5, hdmi_hpd, iso_gpio_7, ir_rx, ir_tx, ur0_rx,
> + ur0_tx, ur1_rx, ur1_tx, ur1_cts_n, ur1_rts_n, i2c_scl_0,
> + i2c_sda_0, i2c_scl_1, i2c_sda_1, i2c_scl_6, iso_gpio_21,
> + iso_gpio_22, iso_gpio_23, iso_gpio_24, iso_gpio_25,
> + i2c_sda_6, etn_led_link, etn_led_rxtx, nat_led_0,
> + nat_led_1, nat_led_2, nat_led_3, iso_gpio_33,
> + iso_gpio_34, pwm_23_loc0, pwm_01_loc0, pwm_23_loc1,
> + pwm_01_loc1, ejtag_avcpu_loc, ur2_loc, i2c0, i2c1,
> + i2c6, uart0, uart1, uart2_0, uart2_1, gpio_0, gpio_1,
> + gpio_2, gpio_3, gpio_4, gpio_5, gpio_6, gpio_7, gpio_8,
> + gpio_9, tp1_sync, i2c_scl_4, i2c_sda_4, i2c_scl_5,
> + i2c_sda_5, usb_id, sensor_cko_0, sensor_cko_1, sensor_rst,
> + sensor_stb_0, sensor_stb_1, tp0_data, tp0_clk, tp0_valid,
> + tp0_sync, tp1_data, tp1_clk, tp1_valid, rgmii0_txc,
> + rgmii0_tx_ctl,rgmii0_txd_0, rgmii0_txd_1, rgmii0_txd_2,
> + rgmii0_txd_3, rgmii0_rxc, rgmii0_rx_ctl, rgmii0_rxd_0,
> + rgmii0_rxd_1, rgmii0_rxd_2, rgmii0_rxd_3, rgmii0_mdio,
> + rgmii0_mdc, rgmii1_txc, rgmii1_tx_ctl, rgmii1_txd_0,
> + rgmii1_txd_1, rgmii1_txd_2, rgmii1_txd_3, rgmii1_rxc,
> + rgmii1_rx_ctl, rgmii1_rxd_0, rgmii1_rxd_1, rgmii1_rxd_2,
> + rgmii1_rxd_3, hif_loc, ejtag_scpu_loc, sf_en, tp0_loc,
> + tp1_loc, spdif, dmic_clk, dmic_data, ao_lrck, ao_bck,
> + aock, ao_sd_0, ao_sd_1, ao_sd_2, ao_sd_3, nf_cle,
> + nf_ale, nf_rd_n, nf_wr_n, nf_rdy, nf_dd_7, nf_dd_6,
> + nf_dd_5, nf_dd_4, nf_dd_3, nf_dd_2, nf_dd_1, nf_dd_0,
> + nf_dqs, nf_ce_n_0, nf_ce_n_1, emmc_dd_sb, mmc_cmd,
> + mmc_clk, mmc_wp, mmc_cd, mmc_data_0, mmc_data_1,
> + mmc_data_2, mmc_data_3, sdio_cmd, sdio_clk, sdio_data_0,
> + sdio_data_1, sdio_data_2, sdio_data_3, pcie_clkreq_0,
> + pcie_clkreq_1, prob_0, prob_1, prob_2, prob_3, sdio_loc ]
> + minItems: 1
> +
> + function:
> + enum: [ gpio, acpu_ejtag_loc_iso, edp_hpd, etn_led, i2c0, i2c1, i2c6,
> + ir_rx, ir_tx, nat_led, pwm_0, pwm_1, rtc, sc, standby_dbg,
> + uart0, uart1, uart2_0, uart2_1, pwm_01_loc0_normal,
> + pwm_23_loc0_normal, pwm_01_loc0_open_drain, pwm_23_loc0_open_drain,
> + pwm_01_loc1_normal, pwm_23_loc1_normal, pwm_01_loc1_open_drain,
> + pwm_23_loc1_open_drain, acpu_ejtag_loc_nf, ai, dc_fan_sensor,
> + eth_gpy, gspi, i2c2, i2c3, i2c4, i2c5, nand, rgmii, scpu_ejtag_loc_gpio,
> + sensor_cko_output, spi, test_loop_dis, tp0_loc_rgmii0_tx, tp0_loc_tp0,
> + tp0_loc_tp1, tp1_loc_rgmii0_rx, tp1_loc_tp0, tp1_loc_tp1,
> + usb_clock_output, hif_loc_misc, hif_loc_nf, scpu_ejtag_loc_cr, ao,
> + dmic, spdif_out, avcpu_ej, emmc, hif, nand, p2s, pcie, pll_test,
> + scpu_ejtag_loc_cr, sd_card, sdio_0, sdio_1 ]
> +
> + drive-strength:
> + enum: [2, 4, 8]
> +
> + bias-pull-down: true
> +
> + bias-pull-up: true
> +
> + bias-disable: true
> +
> + input-schmitt-disable: true
> +
> + input-schmitt-enable: true
> +
> + required:
> + - groups
> + - function
> +
> + additionalProperties: false
Also need top-level 'additionalProperties: false'.
With that,
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 4/8] dt-bindings: pinctrl: realtek: Add Realtek DHC SoC rtd1195
From: Rob Herring @ 2020-07-16 19:54 UTC (permalink / raw)
To: TY Chang
Cc: linux-realtek-soc, afaerber, linus.walleij, linux-gpio,
devicetree, linux-kernel
In-Reply-To: <20200716023338.14922-5-tychang@realtek.com>
On Thu, Jul 16, 2020 at 10:33:34AM +0800, TY Chang wrote:
> Add device tree binding Documentation for rtd1195
> pinctrl driver.
>
> Signed-off-by: TY Chang <tychang@realtek.com>
> ---
> .../pinctrl/realtek,rtd1195-pinctrl.yaml | 104 ++++++++++++++++++
> 1 file changed, 104 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/realtek,rtd1195-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1195-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1195-pinctrl.yaml
> new file mode 100644
> index 000000000000..50a95bc46e2b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1195-pinctrl.yaml
> @@ -0,0 +1,104 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1195-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Realtek DHC RTD1195 pin control
> +
> +maintainers:
> + - Andreas Farber <afaerber@suse.de>
> +
> +properties:
> + compatible:
> + enum:
> + - realtek,rtd1195-iso-pinctrl
> + - realtek,rtd1195-crt-pinctrl
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +#PIN CONFIGURATION NODES
> +patternProperties:
> + '-pins$':
> + type: object
> + description:
> + Pinctrl node's client devices use subnodes for desired pin configuration.
> + Client device subnodes use below standard properties.
> + allOf:
> + - $ref: "/schemas/pinctrl/pincfg-node.yaml"
> +
> + properties:
> + groups:
> + items:
> + enum: [ iso_gpio_0, iso_gpio_1, usb0, usb1, vfd_cs_n,
> + vfd_clk, vfd_d, ir_rx, ir_tx, ur0_rx, ur0_tx,
> + ur1_rx, ur1_tx, ur1_cts_n, ur1_rts_n, i2c_scl_0,
> + i2c_sda_0, etn_led_link, etn_led_rxtx,
> + i2c_scl_6, i2c_sda_6, ai_loc, ejtag_avcpu_loc,
> + ur1_loc, pwm_01_open_drain, pwm_23_open_drain,
> + gpio_0, gpio_1, gpio_2, gpio_3, gpio_4, gpio_5,
> + gpio_6, gpio_7, gpio_8, nf_dd_0, nf_dd_1,
> + nf_dd_2, nf_dd_3, nf_dd_4, nf_dd_5, nf_dd_6,
> + nf_dd_7, nf_rdy, nf_rd_n, nf_wr_n, nf_ale,
> + nf_cle, nf_ce_n_0, nf_ce_n_1, mmc_data_0,
> + mmc_data_1, mmc_data_2, mmc_data_3, mmc_clk,
> + mmc_cmd, mmc_wp, mmc_cd, sdio_clk, sdio_data_0,
> + sdio_data_1, sdio_data_2, sdio_data_3, sdio_cmd,
> + i2c_scl_5, i2c_sda_5, tp1_data, tp1_clk,
> + tp1_valid, tp1_sync, tp0_data, tp0_clk,
> + tp0_valid, tp0_sync, usb_id, hdmi_hpd, spdif,
> + i2c_scl_1, i2c_sda_1, i2c_scl_4, i2c_sda_4,
> + sensor_cko_0, sensor_cko_1, sensor_rst,
> + sensor_stb_0, sensor_stb_1, ejtag_scpu_loc,
> + hif_loc, ao_loc ]
> + minItems: 1
> +
> + function:
> + enum: [ gpio, ai_ur1, ai_vfd, avcpu_ejtag_iso,
> + avcpu_ejtag_misc_loc, etn_led, i2c0, i2c2,
> + i2c3, i2c6, ir_rx, ir_tx, pwm, standby_dbg,
> + uart0, uart1, ur1_misc, vfd, pwm_01_normal,
> + pwm_23_normal, pwm_01_open_drain, pwm_23_open_drain,
> + ao_tp0, ao_gpio, avcpu_ejtag_misc, cpu_loop, emmc,
> + gspi, hif_misc, hif_nf, i2c1, i2c2, i2c3,
> + i2c4, i2c5, mmc, nand, scpu_ejtag_gpio,
> + scpu_ejtag_cr, sdio, sensor, spdif, tp0, tp1,
> + uart1, usb ]
> +
> + drive-strength:
> + enum: [2, 4, 8]
> +
> + bias-pull-down: true
> +
> + bias-pull-up: true
> +
> + bias-disable: true
> +
> + input-schmitt-disable: true
> +
> + input-schmitt-enable: true
> +
> + required:
> + - groups
> + - function
> +
> + additionalProperties: false
Also need a top-level 'additionalProperties: false'
With that,
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH] gpio: max77620: Use helper variable and clarify
From: Dmitry Osipenko @ 2020-07-16 19:17 UTC (permalink / raw)
To: Linus Walleij, linux-gpio; +Cc: Bartosz Golaszewski
In-Reply-To: <20200716092835.69176-1-linus.walleij@linaro.org>
16.07.2020 12:28, Linus Walleij пишет:
> Most other drivers fill out the gpio_irq_chip using a
> struct gpio_irq_chip *girq helper variable for ease of
> reading.
>
> We also make a habit of explicitly assigning NULL and
> zero to the parent IRQs when using ordinary IRQ handlers
> in the driver, mostly for code readability and
> maintenance.
>
> Cc: Dmitry Osipenko <digetx@gmail.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> drivers/gpio/gpio-max77620.c | 16 +++++++++++-----
> 1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpio/gpio-max77620.c b/drivers/gpio/gpio-max77620.c
> index e090979659eb..7c0a9ef0b500 100644
> --- a/drivers/gpio/gpio-max77620.c
> +++ b/drivers/gpio/gpio-max77620.c
> @@ -288,6 +288,7 @@ static int max77620_gpio_probe(struct platform_device *pdev)
> {
> struct max77620_chip *chip = dev_get_drvdata(pdev->dev.parent);
> struct max77620_gpio *mgpio;
> + struct gpio_irq_chip *girq;
> unsigned int gpio_irq;
> int ret;
>
> @@ -316,11 +317,16 @@ static int max77620_gpio_probe(struct platform_device *pdev)
> mgpio->gpio_chip.can_sleep = 1;
> mgpio->gpio_chip.base = -1;
>
> - mgpio->gpio_chip.irq.chip = &max77620_gpio_irqchip;
> - mgpio->gpio_chip.irq.default_type = IRQ_TYPE_NONE;
> - mgpio->gpio_chip.irq.handler = handle_edge_irq;
> - mgpio->gpio_chip.irq.init_hw = max77620_gpio_irq_init_hw,
> - mgpio->gpio_chip.irq.threaded = true;
> + girq = &mgpio->gpio_chip.irq;
> + girq->chip = &max77620_gpio_irqchip;
> + /* This will let us handle the parent IRQ in the driver */
> + girq->parent_handler = NULL;
> + girq->num_parents = 0;
> + girq->parents = NULL;
> + girq->default_type = IRQ_TYPE_NONE;
> + girq->handler = handle_edge_irq;
> + girq->init_hw = max77620_gpio_irq_init_hw,
> + girq->threaded = true;
>
> platform_set_drvdata(pdev, mgpio);
>
>
Thanks :)
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
^ permalink raw reply
* Re: [PATCH v4 0/6] Improvements for MAX77620 GPIO driver
From: Dmitry Osipenko @ 2020-07-16 19:14 UTC (permalink / raw)
To: Linus Walleij
Cc: Thierry Reding, Jonathan Hunter, Laxman Dewangan,
Bartosz Golaszewski, Andy Shevchenko, linux-tegra,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org
In-Reply-To: <CACRpkdZNLDgsrPRenyvPZD6A+Wvj-P3AJBf5Ke-uY9=R9DyjxQ@mail.gmail.com>
16.07.2020 11:52, Linus Walleij пишет:
> On Thu, Jul 9, 2020 at 7:12 PM Dmitry Osipenko <digetx@gmail.com> wrote:
>
>> This series addresses a problem that I discovered on Nexus 7 device where
>> GPIO interrupts may be left enabled after bootloader and the driver isn't
>> prepared to this. It also makes a small improvements to the code, fixes the
>> non-released interrupt bug and converts driver to use irqchip template.
>>
>> Changelog:
>>
>> v4: - Added stable-tag to the patch "Fix missing release of interrupt".
>
> This v4 series applied, thanks a *LOT* for your patient work on this!
Hello, Linus! Thank you for applying the patches!
> I need to fix the USB port on my Nexus 7 so I can test how the
> mainline support is working these days!
Please notice that this should be a Nexus 7 2012, which is NVIDIA
Tegra30-based Nexus 7.
The mainline support just starting to emerge for the 2012 model,
although not much is missed in the upstream. There are couple patches
currently under review which are necessary for Nexus 7 2012 in order to
make it ready for everyday use, like a tiny patch for the touchscreen
support and DRM bridges/panel orientation improvements for the Tegra DRM
driver. We're pretty close! :)
^ permalink raw reply
* [pinctrl:devel 63/64] drivers/pinctrl/mediatek/pinctrl-mt6779.c:775:1: error: type defaults to 'int' in declaration of 'arch_initcall'
From: kernel test robot @ 2020-07-16 19:08 UTC (permalink / raw)
To: Hanks Chen; +Cc: kbuild-all, linux-gpio, Linus Walleij, Mars Cheng, Andy Teng
[-- Attachment #1: Type: text/plain, Size: 1929 bytes --]
tree: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
head: d9ce0e9fdfd37d45f669b831d0c084a7c9338ee8
commit: e6f744c6ad4fb3b7ac06d4e22b79e435578a6d54 [63/64] pinctrl: mediatek: add pinctrl support for MT6779 SoC
config: riscv-allmodconfig (attached as .config)
compiler: riscv64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout e6f744c6ad4fb3b7ac06d4e22b79e435578a6d54
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>):
>> drivers/pinctrl/mediatek/pinctrl-mt6779.c:775:1: warning: data definition has no type or storage class
775 | arch_initcall(mt6779_pinctrl_init);
| ^~~~~~~~~~~~~
>> drivers/pinctrl/mediatek/pinctrl-mt6779.c:775:1: error: type defaults to 'int' in declaration of 'arch_initcall' [-Werror=implicit-int]
>> drivers/pinctrl/mediatek/pinctrl-mt6779.c:775:1: warning: parameter names (without types) in function declaration
drivers/pinctrl/mediatek/pinctrl-mt6779.c:771:19: warning: 'mt6779_pinctrl_init' defined but not used [-Wunused-function]
771 | static int __init mt6779_pinctrl_init(void)
| ^~~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
vim +775 drivers/pinctrl/mediatek/pinctrl-mt6779.c
770
771 static int __init mt6779_pinctrl_init(void)
772 {
773 return platform_driver_register(&mt6779_pinctrl_driver);
774 }
> 775 arch_initcall(mt6779_pinctrl_init);
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 64867 bytes --]
^ permalink raw reply
* linusw/devel baseline: 86 runs, 4 regressions (gpio-v5.8-2-67-g761b5c30c206)
From: kernelci.org bot @ 2020-07-16 18:30 UTC (permalink / raw)
To: linux-gpio, fellows
linusw/devel baseline: 86 runs, 4 regressions (gpio-v5.8-2-67-g761b5c30c206)
Regressions Summary
-------------------
platform | arch | lab | compiler | defconfig | results
-----------------------------+-------+--------------+----------+--------------------+--------
at91-sama5d4_xplained | arm | lab-baylibre | gcc-8 | multi_v7_defconfig | 0/1
bcm2837-rpi-3-b | arm64 | lab-baylibre | gcc-8 | defconfig | 4/5
hifive-unleashed-a00 | riscv | lab-baylibre | gcc-8 | defconfig | 0/1
meson-gxl-s805x-libretech-ac | arm64 | lab-baylibre | gcc-8 | defconfig | 4/5
Details: https://kernelci.org/test/job/linusw/branch/devel/kernel/gpio-v5.8-2-67-g761b5c30c206/plan/baseline/
Test: baseline
Tree: linusw
Branch: devel
Describe: gpio-v5.8-2-67-g761b5c30c206
URL: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/
SHA: 761b5c30c206ba1788c6ceb23e5812f319548b52
Test Regressions
----------------
platform | arch | lab | compiler | defconfig | results
-----------------------------+-------+--------------+----------+--------------------+--------
at91-sama5d4_xplained | arm | lab-baylibre | gcc-8 | multi_v7_defconfig | 0/1
Details: https://kernelci.org/test/plan/id/5f109373afda954af085bbd2
Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: multi_v7_defconfig
Compiler: gcc-8 (arm-linux-gnueabihf-gcc (Debian 8.3.0-2) 8.3.0)
Plain log: https://storage.kernelci.org//linusw/devel/gpio-v5.8-2-67-g761b5c30c206/arm/multi_v7_defconfig/gcc-8/lab-baylibre/baseline-at91-sama5d4_xplained.txt
HTML log: https://storage.kernelci.org//linusw/devel/gpio-v5.8-2-67-g761b5c30c206/arm/multi_v7_defconfig/gcc-8/lab-baylibre/baseline-at91-sama5d4_xplained.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/kci-2020.05/armel/baseline/rootfs.cpio.gz
* baseline.login: https://kernelci.org/test/case/id/5f109373afda954af085bbd3
failing since 30 days (last pass: gpio-v5.8-1-1-gf6d984418ffd, first fail: v5.8-rc1)
platform | arch | lab | compiler | defconfig | results
-----------------------------+-------+--------------+----------+--------------------+--------
bcm2837-rpi-3-b | arm64 | lab-baylibre | gcc-8 | defconfig | 4/5
Details: https://kernelci.org/test/plan/id/5f1091f553d5468e3385bb24
Results: 4 PASS, 1 FAIL, 0 SKIP
Full config: defconfig
Compiler: gcc-8 (aarch64-linux-gnu-gcc (Debian 8.3.0-2) 8.3.0)
Plain log: https://storage.kernelci.org//linusw/devel/gpio-v5.8-2-67-g761b5c30c206/arm64/defconfig/gcc-8/lab-baylibre/baseline-bcm2837-rpi-3-b.txt
HTML log: https://storage.kernelci.org//linusw/devel/gpio-v5.8-2-67-g761b5c30c206/arm64/defconfig/gcc-8/lab-baylibre/baseline-bcm2837-rpi-3-b.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/kci-2020.05/arm64/baseline/rootfs.cpio.gz
* baseline.dmesg.crit: https://kernelci.org/test/case/id/5f1091f553d5468e3385bb27
new failure (last pass: gpio-v5.8-2-58-g1752911c6d10)
1 lines
platform | arch | lab | compiler | defconfig | results
-----------------------------+-------+--------------+----------+--------------------+--------
hifive-unleashed-a00 | riscv | lab-baylibre | gcc-8 | defconfig | 0/1
Details: https://kernelci.org/test/plan/id/5f108fabb237b4e7c685bb1b
Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig
Compiler: gcc-8 (riscv64-linux-gnu-gcc (Debian 8.3.0-2) 8.3.0)
Plain log: https://storage.kernelci.org//linusw/devel/gpio-v5.8-2-67-g761b5c30c206/riscv/defconfig/gcc-8/lab-baylibre/baseline-hifive-unleashed-a00.txt
HTML log: https://storage.kernelci.org//linusw/devel/gpio-v5.8-2-67-g761b5c30c206/riscv/defconfig/gcc-8/lab-baylibre/baseline-hifive-unleashed-a00.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/kci-2020.05/riscv/baseline/rootfs.cpio.gz
* baseline.login: https://kernelci.org/test/case/id/5f108fabb237b4e7c685bb1c
failing since 30 days (last pass: gpio-v5.8-1-1-gf6d984418ffd, first fail: v5.8-rc1)
platform | arch | lab | compiler | defconfig | results
-----------------------------+-------+--------------+----------+--------------------+--------
meson-gxl-s805x-libretech-ac | arm64 | lab-baylibre | gcc-8 | defconfig | 4/5
Details: https://kernelci.org/test/plan/id/5f10939fcbe0bd126985bb26
Results: 4 PASS, 1 FAIL, 0 SKIP
Full config: defconfig
Compiler: gcc-8 (aarch64-linux-gnu-gcc (Debian 8.3.0-2) 8.3.0)
Plain log: https://storage.kernelci.org//linusw/devel/gpio-v5.8-2-67-g761b5c30c206/arm64/defconfig/gcc-8/lab-baylibre/baseline-meson-gxl-s805x-libretech-ac.txt
HTML log: https://storage.kernelci.org//linusw/devel/gpio-v5.8-2-67-g761b5c30c206/arm64/defconfig/gcc-8/lab-baylibre/baseline-meson-gxl-s805x-libretech-ac.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/kci-2020.05/arm64/baseline/rootfs.cpio.gz
* baseline.dmesg.emerg: https://kernelci.org/test/case/id/5f10939fcbe0bd126985bb2b
new failure (last pass: gpio-v5.8-2-58-g1752911c6d10)
2 lines
^ permalink raw reply
* linusw/for-next baseline: 89 runs, 1 regressions (v5.8-rc5-68-geb211a587e18)
From: kernelci.org bot @ 2020-07-16 18:29 UTC (permalink / raw)
To: linux-gpio, fellows
linusw/for-next baseline: 89 runs, 1 regressions (v5.8-rc5-68-geb211a587e18)
Regressions Summary
-------------------
platform | arch | lab | compiler | defconfig | results
----------------+-------+--------------+----------+-----------+--------
bcm2837-rpi-3-b | arm64 | lab-baylibre | gcc-8 | defconfig | 4/5
Details: https://kernelci.org/test/job/linusw/branch/for-next/kernel/v5.8-rc5-68-geb211a587e18/plan/baseline/
Test: baseline
Tree: linusw
Branch: for-next
Describe: v5.8-rc5-68-geb211a587e18
URL: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/
SHA: eb211a587e18efb2a37250573492ae58126176eb
Test Regressions
----------------
platform | arch | lab | compiler | defconfig | results
----------------+-------+--------------+----------+-----------+--------
bcm2837-rpi-3-b | arm64 | lab-baylibre | gcc-8 | defconfig | 4/5
Details: https://kernelci.org/test/plan/id/5f1092ed404c0f611a85bb6d
Results: 4 PASS, 1 FAIL, 0 SKIP
Full config: defconfig
Compiler: gcc-8 (aarch64-linux-gnu-gcc (Debian 8.3.0-2) 8.3.0)
Plain log: https://storage.kernelci.org//linusw/for-next/v5.8-rc5-68-geb211a587e18/arm64/defconfig/gcc-8/lab-baylibre/baseline-bcm2837-rpi-3-b.txt
HTML log: https://storage.kernelci.org//linusw/for-next/v5.8-rc5-68-geb211a587e18/arm64/defconfig/gcc-8/lab-baylibre/baseline-bcm2837-rpi-3-b.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/kci-2020.05/arm64/baseline/rootfs.cpio.gz
* baseline.dmesg.crit: https://kernelci.org/test/case/id/5f1092ed404c0f611a85bb70
new failure (last pass: gpio-v5.8-2-58-g1752911c6d10)
2 lines
^ permalink raw reply
* linusw/devel build: 7 builds: 0 failed, 7 passed, 21 warnings (gpio-v5.8-2-67-g761b5c30c206)
From: kernelci.org bot @ 2020-07-16 17:45 UTC (permalink / raw)
To: linux-gpio, fellows
linusw/devel build: 7 builds: 0 failed, 7 passed, 21 warnings (gpio-v5.8-2-67-g761b5c30c206)
Full Build Summary: https://kernelci.org/build/linusw/branch/devel/kernel/gpio-v5.8-2-67-g761b5c30c206/
Tree: linusw
Branch: devel
Git Describe: gpio-v5.8-2-67-g761b5c30c206
Git Commit: 761b5c30c206ba1788c6ceb23e5812f319548b52
Git URL: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/
Built: 7 unique architectures
Warnings Detected:
arc:
arm64:
defconfig (gcc-8): 8 warnings
arm:
multi_v7_defconfig (gcc-8): 12 warnings
i386:
mips:
riscv:
defconfig (gcc-8): 1 warning
x86_64:
Warnings summary:
3 arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
3 arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
1 drivers/net/ethernet/intel/e1000e/netdev.c:137:13: warning: ‘e1000e_check_me’ defined but not used [-Wunused-function]
1 arch/arm64/boot/dts/qcom/ipq6018.dtsi:127.3-14: Warning (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
1 arch/arm64/boot/dts/qcom/ipq6018.dtsi:127.3-14: Warning (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
1 arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:161.3-30: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@300/ipmb7@10:reg: I2C address must be less than 10-bits, got "0x40000010"
1 arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:159.11-163.4: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@300/ipmb7@10: I2C bus unit address format error, expected "40000010"
1 arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:150.3-30: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@180/ipmb5@10:reg: I2C address must be less than 10-bits, got "0x40000010"
1 arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:148.11-152.4: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@180/ipmb5@10: I2C bus unit address format error, expected "40000010"
1 arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:139.3-30: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@100/ipmb3@10:reg: I2C address must be less than 10-bits, got "0x40000010"
1 arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:137.11-141.4: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@100/ipmb3@10: I2C bus unit address format error, expected "40000010"
1 arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:128.3-30: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@80/ipmb1@10:reg: I2C address must be less than 10-bits, got "0x40000010"
1 arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:126.11-130.4: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@80/ipmb1@10: I2C bus unit address format error, expected "40000010"
1 arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts:523.3-30: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@380/ipmb0@10:reg: I2C address must be less than 10-bits, got "0x40000010"
1 arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts:521.11-525.4: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@380/ipmb0@10: I2C bus unit address format error, expected "40000010"
1 arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts:437.3-30: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@140/ipmb0@10:reg: I2C address must be less than 10-bits, got "0x40000010"
1 arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts:435.11-439.4: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@140/ipmb0@10: I2C bus unit address format error, expected "40000010"
================================================================================
Detailed per-defconfig build reports:
--------------------------------------------------------------------------------
32r2el_defconfig (mips, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
--------------------------------------------------------------------------------
defconfig (riscv, gcc-8) — PASS, 0 errors, 1 warning, 0 section mismatches
Warnings:
drivers/net/ethernet/intel/e1000e/netdev.c:137:13: warning: ‘e1000e_check_me’ defined but not used [-Wunused-function]
--------------------------------------------------------------------------------
defconfig (arm64, gcc-8) — PASS, 0 errors, 8 warnings, 0 section mismatches
Warnings:
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
arch/arm64/boot/dts/qcom/ipq6018.dtsi:127.3-14: Warning (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
arch/arm64/boot/dts/qcom/ipq6018.dtsi:127.3-14: Warning (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
--------------------------------------------------------------------------------
haps_hs_smp_defconfig (arc, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
--------------------------------------------------------------------------------
i386_defconfig (i386, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
--------------------------------------------------------------------------------
multi_v7_defconfig (arm, gcc-8) — PASS, 0 errors, 12 warnings, 0 section mismatches
Warnings:
arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts:435.11-439.4: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@140/ipmb0@10: I2C bus unit address format error, expected "40000010"
arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts:437.3-30: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@140/ipmb0@10:reg: I2C address must be less than 10-bits, got "0x40000010"
arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts:521.11-525.4: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@380/ipmb0@10: I2C bus unit address format error, expected "40000010"
arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts:523.3-30: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@380/ipmb0@10:reg: I2C address must be less than 10-bits, got "0x40000010"
arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:126.11-130.4: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@80/ipmb1@10: I2C bus unit address format error, expected "40000010"
arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:128.3-30: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@80/ipmb1@10:reg: I2C address must be less than 10-bits, got "0x40000010"
arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:137.11-141.4: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@100/ipmb3@10: I2C bus unit address format error, expected "40000010"
arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:139.3-30: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@100/ipmb3@10:reg: I2C address must be less than 10-bits, got "0x40000010"
arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:148.11-152.4: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@180/ipmb5@10: I2C bus unit address format error, expected "40000010"
arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:150.3-30: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@180/ipmb5@10:reg: I2C address must be less than 10-bits, got "0x40000010"
arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:159.11-163.4: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@300/ipmb7@10: I2C bus unit address format error, expected "40000010"
arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts:161.3-30: Warning (i2c_bus_reg): /ahb/apb/bus@1e78a000/i2c-bus@300/ipmb7@10:reg: I2C address must be less than 10-bits, got "0x40000010"
--------------------------------------------------------------------------------
x86_64_defconfig (x86_64, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
---
For more info write to <info@kernelci.org>
^ permalink raw reply
* linusw/for-next build: 7 builds: 0 failed, 7 passed, 8 warnings (v5.8-rc5-68-geb211a587e18)
From: kernelci.org bot @ 2020-07-16 17:45 UTC (permalink / raw)
To: linux-gpio, fellows
linusw/for-next build: 7 builds: 0 failed, 7 passed, 8 warnings (v5.8-rc5-68-geb211a587e18)
Full Build Summary: https://kernelci.org/build/linusw/branch/for-next/kernel/v5.8-rc5-68-geb211a587e18/
Tree: linusw
Branch: for-next
Git Describe: v5.8-rc5-68-geb211a587e18
Git Commit: eb211a587e18efb2a37250573492ae58126176eb
Git URL: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/
Built: 7 unique architectures
Warnings Detected:
arc:
arm64:
defconfig (gcc-8): 8 warnings
arm:
i386:
mips:
riscv:
x86_64:
Warnings summary:
3 arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
3 arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
1 arch/arm64/boot/dts/qcom/ipq6018.dtsi:127.3-14: Warning (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
1 arch/arm64/boot/dts/qcom/ipq6018.dtsi:127.3-14: Warning (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
================================================================================
Detailed per-defconfig build reports:
--------------------------------------------------------------------------------
32r2el_defconfig (mips, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
--------------------------------------------------------------------------------
defconfig (riscv, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
--------------------------------------------------------------------------------
defconfig (arm64, gcc-8) — PASS, 0 errors, 8 warnings, 0 section mismatches
Warnings:
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
arch/arm64/boot/dts/qcom/ipq6018.dtsi:127.3-14: Warning (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
arch/arm64/boot/dts/qcom/ipq6018.dtsi:127.3-14: Warning (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
--------------------------------------------------------------------------------
haps_hs_smp_defconfig (arc, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
--------------------------------------------------------------------------------
i386_defconfig (i386, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
--------------------------------------------------------------------------------
multi_v7_defconfig (arm, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
--------------------------------------------------------------------------------
x86_64_defconfig (x86_64, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
---
For more info write to <info@kernelci.org>
^ permalink raw reply
* linusw/fixes build: 7 builds: 0 failed, 7 passed, 8 warnings (v5.8-rc5)
From: kernelci.org bot @ 2020-07-16 17:41 UTC (permalink / raw)
To: linux-gpio, fellows
linusw/fixes build: 7 builds: 0 failed, 7 passed, 8 warnings (v5.8-rc5)
Full Build Summary: https://kernelci.org/build/linusw/branch/fixes/kernel/v5.8-rc5/
Tree: linusw
Branch: fixes
Git Describe: v5.8-rc5
Git Commit: 11ba468877bb23f28956a35e896356252d63c983
Git URL: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/
Built: 7 unique architectures
Warnings Detected:
arc:
arm64:
defconfig (gcc-8): 8 warnings
arm:
i386:
mips:
riscv:
x86_64:
Warnings summary:
3 arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
3 arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
1 arch/arm64/boot/dts/qcom/ipq6018.dtsi:127.3-14: Warning (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
1 arch/arm64/boot/dts/qcom/ipq6018.dtsi:127.3-14: Warning (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
================================================================================
Detailed per-defconfig build reports:
--------------------------------------------------------------------------------
32r2el_defconfig (mips, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
--------------------------------------------------------------------------------
defconfig (riscv, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
--------------------------------------------------------------------------------
defconfig (arm64, gcc-8) — PASS, 0 errors, 8 warnings, 0 section mismatches
Warnings:
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi:7.3-14: Warning (dma_ranges_format): /usb:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
arch/arm64/boot/dts/qcom/ipq6018.dtsi:127.3-14: Warning (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but its #address-cells (1) differs from / (2)
arch/arm64/boot/dts/qcom/ipq6018.dtsi:127.3-14: Warning (dma_ranges_format): /soc:dma-ranges: empty "dma-ranges" property but its #size-cells (1) differs from / (2)
--------------------------------------------------------------------------------
haps_hs_smp_defconfig (arc, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
--------------------------------------------------------------------------------
i386_defconfig (i386, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
--------------------------------------------------------------------------------
multi_v7_defconfig (arm, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
--------------------------------------------------------------------------------
x86_64_defconfig (x86_64, gcc-8) — PASS, 0 errors, 0 warnings, 0 section mismatches
---
For more info write to <info@kernelci.org>
^ permalink raw reply
* Re: [PATCH 1/2] pinctrl: qcom: ipq4019: add open drain support
From: Brian Norris @ 2020-07-16 17:22 UTC (permalink / raw)
To: Linus Walleij, bjorn.andersson
Cc: Andy Gross, Rob Herring, MSM, open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Jaiganesh Narayanan
In-Reply-To: <CACRpkdar+aBBFn6SKJ1a90D-NT3F6qGvouzjt-jxaiR0VSuUOg@mail.gmail.com>
+ Bjorn for real
- Bjorn @mistyped-domain
On Thu, Jul 16, 2020 at 1:47 AM Linus Walleij <linus.walleij@linaro.org> wrote:
> On Fri, Jul 3, 2020 at 10:06 AM Brian Norris
> <computersforpeace@gmail.com> wrote:
>
> > From: Jaiganesh Narayanan <njaigane@codeaurora.org>
> >
> > Signed-off-by: Jaiganesh Narayanan <njaigane@codeaurora.org>
> > [ Brian: adapted from from the Chromium OS kernel used on IPQ4019-based
> > WiFi APs. ]
> > Signed-off-by: Brian Norris <computersforpeace@gmail.com>
>
> Patch applied because this looks innocent and Rob
> ACKed the binding.
Thanks!
> If Bjorn opposes, I will simply pull the patch out again.
Unfortunately, depending on his mail subscriptions and filters, Bjorn
may not have had much of a chance there. I failed to notice that I
deleted the "g" in ".org", so my mail didn't deliver to him.
Bjorn: for reference, here are archive links to the entire patch set:
https://lore.kernel.org/linux-gpio/20200703080646.23233-1-computersforpeace@gmail.com/
https://lore.kernel.org/linux-gpio/20200703080646.23233-2-computersforpeace@gmail.com/
Brian
^ permalink raw reply
* Re: [PATCH 1/2] pinctrl: imx: Support building SCU pinctrl driver as module
From: Daniel Baluta @ 2020-07-16 15:58 UTC (permalink / raw)
To: Anson Huang, Aisheng Dong, festevam@gmail.com,
shawnguo@kernel.org, stefan@agner.ch, kernel@pengutronix.de,
linus.walleij@linaro.org, s.hauer@pengutronix.de,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: dl-linux-imx
In-Reply-To: <DB3PR0402MB3916C9FE00C0F4FC62ACB711F57F0@DB3PR0402MB3916.eurprd04.prod.outlook.com>
On 7/16/20 6:21 PM, Anson Huang wrote:
> Hi, Daniel
>
>
>> Subject: Re: [PATCH 1/2] pinctrl: imx: Support building SCU pinctrl driver as
>> module
>>
>> Hi Anson,
>>
>> Few comments inline:
>>
>> On 7/16/20 6:06 PM, Anson Huang wrote:
>>> To support building i.MX SCU pinctrl driver as module, below things need to
>> be changed:
>>> - Export SCU related functions and use "IS_ENABLED" instead of
>>> "ifdef" to support SCU pinctrl driver user and itself to be
>>> built as module;
>>> - Use function callbacks for SCU related functions in pinctrl-imx.c
>>> in order to support the scenario of PINCTRL_IMX is built in
>>> while PINCTRL_IMX_SCU is built as module;
>>> - All drivers using SCU pinctrl driver need to initialize the
>>> SCU related function callback;
>>> - Change PINCTR_IMX_SCU to tristate;
>>> - Add module author, description and license.
>>>
>>> With above changes, i.MX SCU pinctrl driver can be built as module.
>>
>> There are a lot of changes here. I think it would be better to try to split them
>>
>> per functionality. One functional change per patch.
> Actually, I ever tried to split them, but the function will be broken. All the changes
> are just to support the module build. If split them, the bisect will have pinctrl
> build or function broken.
Hi Anson,
I see your point and I know that this is a very hard task to get it
right from
the first patches.
But let me suggest at least that:
- changes in drivers/pinctrl/freescale/pinctrl-imx.c (include file and
MODULE_ macros should go to a separate patch).
thanks
Daniel.
^ permalink raw reply
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