* [PATCH 02/13] pinctrl: rockchip: modify rockchip_pin_ctrl to const struct
From: Jianqun Xu @ 2020-07-17 1:48 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
The rockchip_pin_ctrl structure actually is soc data structure for
pinctrl on Rockchip SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 62 +++++++++++++++---------------
1 file changed, 31 insertions(+), 31 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index bc465da68f26..77c1e6744f6c 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -392,7 +392,7 @@ struct rockchip_pinctrl {
struct regmap *regmap_pull;
struct regmap *regmap_pmu;
struct device *dev;
- struct rockchip_pin_ctrl *ctrl;
+ const struct rockchip_pin_ctrl *ctrl;
struct pinctrl_desc pctl;
struct pinctrl_dev *pctl_dev;
struct rockchip_pin_group *groups;
@@ -779,7 +779,7 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
int *reg, u8 *bit, int *mask)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_mux_recalced_data *data;
int i;
@@ -1396,7 +1396,7 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
int mux, u32 *loc, u32 *reg, u32 *value)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_mux_route_data *data;
int i;
@@ -2112,7 +2112,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
int pin_num)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret;
u32 data, temp, rmask_bits;
@@ -2189,7 +2189,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
int pin_num, int strength)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret, i;
u32 data, rmask, rmask_bits, temp;
@@ -2297,7 +2297,7 @@ static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret, pull_type;
u8 bit;
@@ -2341,7 +2341,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
int pin_num, int pull)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret, i, pull_type;
u8 bit;
@@ -2427,7 +2427,7 @@ static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret;
u8 bit;
@@ -2449,7 +2449,7 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
int pin_num, int enable)
{
struct rockchip_pinctrl *info = bank->drvdata;
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct regmap *regmap;
int reg, ret;
u8 bit;
@@ -2621,7 +2621,7 @@ static const struct pinmux_ops rockchip_pmx_ops = {
* Pinconf_ops handling
*/
-static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
+static bool rockchip_pinconf_pull_valid(const struct rockchip_pin_ctrl *ctrl,
enum pin_config_param pull)
{
switch (ctrl->type) {
@@ -3366,7 +3366,7 @@ static void rockchip_irq_disable(struct irq_data *d)
static int rockchip_interrupts_register(struct platform_device *pdev,
struct rockchip_pinctrl *info)
{
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_pin_bank *bank = ctrl->pin_banks;
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct irq_chip_generic *gc;
@@ -3447,7 +3447,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
static int rockchip_gpiolib_register(struct platform_device *pdev,
struct rockchip_pinctrl *info)
{
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_pin_bank *bank = ctrl->pin_banks;
struct gpio_chip *gc;
int ret;
@@ -3493,7 +3493,7 @@ static int rockchip_gpiolib_register(struct platform_device *pdev,
static int rockchip_gpiolib_unregister(struct platform_device *pdev,
struct rockchip_pinctrl *info)
{
- struct rockchip_pin_ctrl *ctrl = info->ctrl;
+ const struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_pin_bank *bank = ctrl->pin_banks;
int i;
@@ -3563,20 +3563,20 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
static const struct of_device_id rockchip_pinctrl_dt_match[];
/* retrieve the soc specific data */
-static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
+static const struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
struct rockchip_pinctrl *d,
struct platform_device *pdev)
{
const struct of_device_id *match;
struct device_node *node = pdev->dev.of_node;
struct device_node *np;
- struct rockchip_pin_ctrl *ctrl;
+ const const struct rockchip_pin_ctrl *ctrl;
struct rockchip_pin_bank *bank;
int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
u32 nr_pins;
match = of_match_node(rockchip_pinctrl_dt_match, node);
- ctrl = (struct rockchip_pin_ctrl *)match->data;
+ ctrl = (const struct rockchip_pin_ctrl *)match->data;
for_each_child_of_node(node, np) {
if (!of_find_property(np, "gpio-controller", NULL))
@@ -3748,7 +3748,7 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
{
struct rockchip_pinctrl *info;
struct device *dev = &pdev->dev;
- struct rockchip_pin_ctrl *ctrl;
+ const const struct rockchip_pin_ctrl *ctrl;
struct device_node *np = pdev->dev.of_node, *node;
struct resource *res;
void __iomem *base;
@@ -3853,7 +3853,7 @@ static struct rockchip_pin_bank px30_pin_banks[] = {
),
};
-static struct rockchip_pin_ctrl px30_pin_ctrl = {
+static const struct rockchip_pin_ctrl px30_pin_ctrl = {
.pin_banks = px30_pin_banks,
.nr_banks = ARRAY_SIZE(px30_pin_banks),
.nr_pins = 128,
@@ -3878,7 +3878,7 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
};
-static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
+static const struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.pin_banks = rv1108_pin_banks,
.nr_banks = ARRAY_SIZE(rv1108_pin_banks),
.nr_pins = 128,
@@ -3900,7 +3900,7 @@ static struct rockchip_pin_bank rk2928_pin_banks[] = {
PIN_BANK(3, 32, "gpio3"),
};
-static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk2928_pin_ctrl = {
.pin_banks = rk2928_pin_banks,
.nr_banks = ARRAY_SIZE(rk2928_pin_banks),
.nr_pins = 128,
@@ -3916,7 +3916,7 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = {
PIN_BANK(2, 32, "gpio2"),
};
-static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3036_pin_ctrl = {
.pin_banks = rk3036_pin_banks,
.nr_banks = ARRAY_SIZE(rk3036_pin_banks),
.nr_pins = 96,
@@ -3935,7 +3935,7 @@ static struct rockchip_pin_bank rk3066a_pin_banks[] = {
PIN_BANK(6, 16, "gpio6"),
};
-static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
.pin_banks = rk3066a_pin_banks,
.nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
.nr_pins = 176,
@@ -3952,7 +3952,7 @@ static struct rockchip_pin_bank rk3066b_pin_banks[] = {
PIN_BANK(3, 32, "gpio3"),
};
-static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
.pin_banks = rk3066b_pin_banks,
.nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
.nr_pins = 128,
@@ -3968,7 +3968,7 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = {
PIN_BANK(3, 32, "gpio3"),
};
-static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3128_pin_ctrl = {
.pin_banks = rk3128_pin_banks,
.nr_banks = ARRAY_SIZE(rk3128_pin_banks),
.nr_pins = 128,
@@ -3989,7 +3989,7 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = {
PIN_BANK(3, 32, "gpio3"),
};
-static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3188_pin_ctrl = {
.pin_banks = rk3188_pin_banks,
.nr_banks = ARRAY_SIZE(rk3188_pin_banks),
.nr_pins = 128,
@@ -4008,7 +4008,7 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = {
PIN_BANK(3, 32, "gpio3"),
};
-static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3228_pin_ctrl = {
.pin_banks = rk3228_pin_banks,
.nr_banks = ARRAY_SIZE(rk3228_pin_banks),
.nr_pins = 128,
@@ -4053,7 +4053,7 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = {
PIN_BANK(8, 16, "gpio8"),
};
-static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3288_pin_ctrl = {
.pin_banks = rk3288_pin_banks,
.nr_banks = ARRAY_SIZE(rk3288_pin_banks),
.nr_pins = 264,
@@ -4090,7 +4090,7 @@ static struct rockchip_pin_bank rk3308_pin_banks[] = {
IOMUX_WIDTH_2BIT),
};
-static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3308_pin_ctrl = {
.pin_banks = rk3308_pin_banks,
.nr_banks = ARRAY_SIZE(rk3308_pin_banks),
.nr_pins = 160,
@@ -4120,7 +4120,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
0),
};
-static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3328_pin_ctrl = {
.pin_banks = rk3328_pin_banks,
.nr_banks = ARRAY_SIZE(rk3328_pin_banks),
.nr_pins = 128,
@@ -4147,7 +4147,7 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = {
PIN_BANK(3, 32, "gpio3"),
};
-static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3368_pin_ctrl = {
.pin_banks = rk3368_pin_banks,
.nr_banks = ARRAY_SIZE(rk3368_pin_banks),
.nr_pins = 128,
@@ -4212,7 +4212,7 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = {
),
};
-static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
+static const struct rockchip_pin_ctrl rk3399_pin_ctrl = {
.pin_banks = rk3399_pin_banks,
.nr_banks = ARRAY_SIZE(rk3399_pin_banks),
.nr_pins = 160,
--
2.17.1
^ permalink raw reply related
* [PATCH 08/13] pinctrl: rockchip: do codingstyle
From: Jianqun Xu @ 2020-07-17 1:53 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Add RK3308 definitions to separate from other SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 8e3fa9011165..44f051af97c6 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1952,6 +1952,9 @@ static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
}
#define RK3308_PULL_OFFSET 0xa0
+#define RK3308_PULL_BITS_PER_PIN 2
+#define RK3308_PULL_PINS_PER_REG 8
+#define RK3308_PULL_BANK_STRIDE 16
static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1961,14 +1964,17 @@ static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_base;
*reg = RK3308_PULL_OFFSET;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3308_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3308_PULL_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *bit = (pin_num % RK3308_PULL_PINS_PER_REG);
+ *bit *= RK3308_PULL_BITS_PER_PIN;
}
#define RK3308_DRV_GRF_OFFSET 0x100
+#define RK3308_DRV_BITS_PER_PIN 2
+#define RK3308_DRV_PINS_PER_REG 8
+#define RK3308_DRV_BANK_STRIDE 16
static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1978,11 +1984,11 @@ static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_base;
*reg = RK3308_DRV_GRF_OFFSET;
- *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
- *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3308_DRV_BANK_STRIDE;
+ *reg += ((pin_num / RK3308_DRV_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
- *bit *= RK3288_DRV_BITS_PER_PIN;
+ *bit = (pin_num % RK3308_DRV_PINS_PER_REG);
+ *bit *= RK3308_DRV_BITS_PER_PIN;
}
#define RK3368_PULL_GRF_OFFSET 0x100
--
2.17.1
^ permalink raw reply related
* [PATCH 05/13] pinctrl: rockchip: create irq mapping in gpio_to_irq
From: Jianqun Xu @ 2020-07-17 1:52 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Remove totally irq mappings create in probe, the gpio irq mapping will
be created when do
gpio_to_irq ->
rockchip_gpio_to_irq ->
irq_create_mapping
This patch can speed up system boot on, also abandon many unused irq
mappings' create.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 28 ++++++++++++----------------
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index d34fada39227..1be4627f3877 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3196,7 +3196,7 @@ static void rockchip_irq_demux(struct irq_desc *desc)
irq = __ffs(pend);
pend &= ~BIT(irq);
- virq = irq_linear_revmap(bank->domain, irq);
+ virq = irq_find_mapping(bank->domain, irq);
if (!virq) {
dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
@@ -3375,7 +3375,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct irq_chip_generic *gc;
int ret;
- int i, j;
+ int i;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
if (!bank->valid) {
@@ -3402,7 +3402,7 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
"rockchip_gpio_irq", handle_level_irq,
- clr, 0, IRQ_GC_INIT_MASK_CACHE);
+ clr, 0, 0);
if (ret) {
dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
bank->name);
@@ -3411,14 +3411,6 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
continue;
}
- /*
- * Linux assumes that all interrupts start out disabled/masked.
- * Our driver only uses the concept of masked and always keeps
- * things enabled, so for us that's all masked and all enabled.
- */
- writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
- writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
-
gc = irq_get_domain_generic_chip(bank->domain, 0);
gc->reg_base = bank->reg_base;
gc->private = bank;
@@ -3435,13 +3427,17 @@ static int rockchip_interrupts_register(struct platform_device *pdev,
gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
gc->wake_enabled = IRQ_MSK(bank->nr_pins);
+ /*
+ * Linux assumes that all interrupts start out disabled/masked.
+ * Our driver only uses the concept of masked and always keeps
+ * things enabled, so for us that's all masked and all enabled.
+ */
+ writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
+ writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
+ gc->mask_cache = 0xffffffff;
+
irq_set_chained_handler_and_data(bank->irq,
rockchip_irq_demux, bank);
-
- /* map the gpio irqs here, when the clock is still running */
- for (j = 0 ; j < 32 ; j++)
- irq_create_mapping(bank->domain, j);
-
clk_disable(bank->clk);
}
--
2.17.1
^ permalink raw reply related
* [PATCH 06/13] pinctrl: rockchip: do codingstyle
From: Jianqun Xu @ 2020-07-17 1:52 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Add RK3399 definitions to separate from other SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 1be4627f3877..71335ed003b3 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2050,6 +2050,9 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
#define RK3399_PULL_GRF_OFFSET 0xe040
#define RK3399_PULL_PMU_OFFSET 0x40
#define RK3399_DRV_3BITS_PER_PIN 3
+#define RK3399_PULL_BITS_PER_PIN 2
+#define RK3399_PULL_PINS_PER_REG 8
+#define RK3399_PULL_BANK_STRIDE 16
static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -2062,22 +2065,22 @@ static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3399_PULL_PMU_OFFSET;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+ *reg += bank->bank_num * RK3399_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
- *bit = pin_num % RK3188_PULL_PINS_PER_REG;
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *reg += ((pin_num / RK3399_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3399_PULL_PINS_PER_REG;
+ *bit *= RK3399_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3399_PULL_GRF_OFFSET;
/* correct the offset, as we're starting with the 3rd bank */
*reg -= 0x20;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3399_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3399_PULL_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *bit = (pin_num % RK3399_PULL_PINS_PER_REG);
+ *bit *= RK3399_PULL_BITS_PER_PIN;
}
}
--
2.17.1
^ permalink raw reply related
* [PATCH 11/13] pinctrl: rockchip: do codingstyle
From: Jianqun Xu @ 2020-07-17 1:53 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Add RK3128 definitions to separate from other SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 04e7027ec8e1..3b74455dcdb2 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1799,6 +1799,8 @@ static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
};
#define RK3128_PULL_OFFSET 0x118
+#define RK3128_PULL_PINS_PER_REG 16
+#define RK3128_PULL_BANK_STRIDE 8
static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1808,10 +1810,10 @@ static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_base;
*reg = RK3128_PULL_OFFSET;
- *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3128_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3128_PULL_PINS_PER_REG) * 4);
- *bit = pin_num % RK2928_PULL_PINS_PER_REG;
+ *bit = pin_num % RK3128_PULL_PINS_PER_REG;
}
#define RK3188_PULL_OFFSET 0x164
--
2.17.1
^ permalink raw reply related
* [PATCH 09/13] pinctrl: rockchip: do codingstyle
From: Jianqun Xu @ 2020-07-17 1:53 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Add RK3228 definitions to separate from other SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 44f051af97c6..ec6a1a08f8b1 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1918,6 +1918,9 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
}
#define RK3228_PULL_OFFSET 0x100
+#define RK3228_PULL_BITS_PER_PIN 2
+#define RK3228_PULL_PINS_PER_REG 8
+#define RK3228_PULL_BANK_STRIDE 16
static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1927,14 +1930,17 @@ static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_base;
*reg = RK3228_PULL_OFFSET;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3228_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3228_PULL_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *bit = (pin_num % RK3228_PULL_PINS_PER_REG);
+ *bit *= RK3228_PULL_BITS_PER_PIN;
}
#define RK3228_DRV_GRF_OFFSET 0x200
+#define RK3228_DRV_BITS_PER_PIN 2
+#define RK3228_DRV_PINS_PER_REG 8
+#define RK3228_DRV_BANK_STRIDE 16
static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1944,11 +1950,11 @@ static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_base;
*reg = RK3228_DRV_GRF_OFFSET;
- *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
- *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3228_DRV_BANK_STRIDE;
+ *reg += ((pin_num / RK3228_DRV_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
- *bit *= RK3288_DRV_BITS_PER_PIN;
+ *bit = (pin_num % RK3228_DRV_PINS_PER_REG);
+ *bit *= RK3228_DRV_BITS_PER_PIN;
}
#define RK3308_PULL_OFFSET 0xa0
--
2.17.1
^ permalink raw reply related
* [PATCH 06/13] pinctrl: rockchip: do codingstyle
From: Jianqun Xu @ 2020-07-17 1:52 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Add RK3399 definitions to separate from other SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 1be4627f3877..71335ed003b3 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -2050,6 +2050,9 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
#define RK3399_PULL_GRF_OFFSET 0xe040
#define RK3399_PULL_PMU_OFFSET 0x40
#define RK3399_DRV_3BITS_PER_PIN 3
+#define RK3399_PULL_BITS_PER_PIN 2
+#define RK3399_PULL_PINS_PER_REG 8
+#define RK3399_PULL_BANK_STRIDE 16
static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -2062,22 +2065,22 @@ static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3399_PULL_PMU_OFFSET;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
+ *reg += bank->bank_num * RK3399_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
- *bit = pin_num % RK3188_PULL_PINS_PER_REG;
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *reg += ((pin_num / RK3399_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3399_PULL_PINS_PER_REG;
+ *bit *= RK3399_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3399_PULL_GRF_OFFSET;
/* correct the offset, as we're starting with the 3rd bank */
*reg -= 0x20;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3399_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3399_PULL_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *bit = (pin_num % RK3399_PULL_PINS_PER_REG);
+ *bit *= RK3399_PULL_BITS_PER_PIN;
}
}
--
2.17.1
^ permalink raw reply related
* [PATCH 04/13] pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq
From: Jianqun Xu @ 2020-07-17 1:48 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
There need to enable pclk_gpio when do irq_create_mapping, since it will
do access to gpio controller.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index ec509ef8bd8d..d34fada39227 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3155,7 +3155,9 @@ static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
if (!bank->domain)
return -ENXIO;
+ clk_enable(bank->clk);
virq = irq_create_mapping(bank->domain, offset);
+ clk_disable(bank->clk);
return (virq) ? : -ENXIO;
}
--
2.17.1
^ permalink raw reply related
* [PATCH 13/13] pinctrl: rockchip: do codingstyle by adding mux route definitions
From: Jianqun Xu @ 2020-07-17 1:53 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Add MR_SAME/MR_GRF/MR_PMU definitions, and update data in mux route
structures.
This patch do nothing change, only do some codingstyle.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 674 +++++------------------------
1 file changed, 104 insertions(+), 570 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 71a367896297..50558ffcc05c 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -78,6 +78,9 @@ enum rockchip_pinctrl_type {
#define ROCKCHIP_DRV_3BITS_PER_PIN (3)
#define ROCKCHIP_DRV_BITS_PER_PIN (2)
+#define RK_GENMASK_VAL(h, l, v) \
+ (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
+
/**
* @type: iomux variant using IOMUX_* constants
* @offset: if initialized to -1 it will be autocalculated, by specifying
@@ -290,6 +293,25 @@ struct rockchip_pin_bank {
.pull_type[3] = pull3, \
}
+#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
+ { \
+ .bank_num = ID, \
+ .pin = PIN, \
+ .func = FUNC, \
+ .route_offset = REG, \
+ .route_val = VAL, \
+ .route_location = FLAG, \
+ }
+
+#define MR_SAME(ID, PIN, FUNC, REG, VAL) \
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
+
+#define MR_GRF(ID, PIN, FUNC, REG, VAL) \
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
+
+#define MR_PMU(ID, PIN, FUNC, REG, VAL) \
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
+
/**
* struct rockchip_mux_recalced_data: represent a pin iomux data.
* @num: bank number.
@@ -804,597 +826,109 @@ static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
}
static struct rockchip_mux_route_data px30_mux_route_data[] = {
- {
- /* cif-d2m0 */
- .bank_num = 2,
- .pin = 0,
- .func = 1,
- .route_offset = 0x184,
- .route_val = BIT(16 + 7),
- }, {
- /* cif-d2m1 */
- .bank_num = 3,
- .pin = 3,
- .func = 3,
- .route_offset = 0x184,
- .route_val = BIT(16 + 7) | BIT(7),
- }, {
- /* pdm-m0 */
- .bank_num = 3,
- .pin = 22,
- .func = 2,
- .route_offset = 0x184,
- .route_val = BIT(16 + 8),
- }, {
- /* pdm-m1 */
- .bank_num = 2,
- .pin = 22,
- .func = 1,
- .route_offset = 0x184,
- .route_val = BIT(16 + 8) | BIT(8),
- }, {
- /* uart2-rxm0 */
- .bank_num = 1,
- .pin = 27,
- .func = 2,
- .route_offset = 0x184,
- .route_val = BIT(16 + 10),
- }, {
- /* uart2-rxm1 */
- .bank_num = 2,
- .pin = 14,
- .func = 2,
- .route_offset = 0x184,
- .route_val = BIT(16 + 10) | BIT(10),
- }, {
- /* uart3-rxm0 */
- .bank_num = 0,
- .pin = 17,
- .func = 2,
- .route_offset = 0x184,
- .route_val = BIT(16 + 9),
- }, {
- /* uart3-rxm1 */
- .bank_num = 1,
- .pin = 15,
- .func = 2,
- .route_offset = 0x184,
- .route_val = BIT(16 + 9) | BIT(9),
- },
+ MR_SAME(2, 0, 1, 0x184, RK_GENMASK_VAL(7, 7, 0)), /* cif-d2m0 */
+ MR_SAME(3, 3, 3, 0x184, RK_GENMASK_VAL(7, 7, 1)), /* cif-d2m1 */
+ MR_SAME(3, 22, 2, 0x184, RK_GENMASK_VAL(8, 8, 0)), /* pdm-m0 */
+ MR_SAME(2, 22, 1, 0x184, RK_GENMASK_VAL(8, 8, 1)), /* pdm-m1 */
+ MR_SAME(0, 17, 2, 0x184, RK_GENMASK_VAL(9, 9, 0)), /* uart3-rxm0 */
+ MR_SAME(1, 15, 2, 0x184, RK_GENMASK_VAL(9, 9, 1)), /* uart3-rxm1 */
+ MR_SAME(1, 27, 2, 0x184, RK_GENMASK_VAL(10, 10, 0)), /* uart2-rxm0 */
+ MR_SAME(2, 14, 2, 0x184, RK_GENMASK_VAL(10, 10, 1)), /* uart2-rxm1 */
};
static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
- {
- /* spi-0 */
- .bank_num = 1,
- .pin = 10,
- .func = 1,
- .route_offset = 0x144,
- .route_val = BIT(16 + 3) | BIT(16 + 4),
- }, {
- /* spi-1 */
- .bank_num = 1,
- .pin = 27,
- .func = 3,
- .route_offset = 0x144,
- .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
- }, {
- /* spi-2 */
- .bank_num = 0,
- .pin = 13,
- .func = 2,
- .route_offset = 0x144,
- .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
- }, {
- /* i2s-0 */
- .bank_num = 1,
- .pin = 5,
- .func = 1,
- .route_offset = 0x144,
- .route_val = BIT(16 + 5),
- }, {
- /* i2s-1 */
- .bank_num = 0,
- .pin = 14,
- .func = 1,
- .route_offset = 0x144,
- .route_val = BIT(16 + 5) | BIT(5),
- }, {
- /* emmc-0 */
- .bank_num = 1,
- .pin = 22,
- .func = 2,
- .route_offset = 0x144,
- .route_val = BIT(16 + 6),
- }, {
- /* emmc-1 */
- .bank_num = 2,
- .pin = 4,
- .func = 2,
- .route_offset = 0x144,
- .route_val = BIT(16 + 6) | BIT(6),
- },
+ MR_SAME(1, 10, 1, 0x144, RK_GENMASK_VAL(4, 3, 0)), /* spi-0 */
+ MR_SAME(1, 27, 3, 0x144, RK_GENMASK_VAL(4, 3, 1)), /* spi-1 */
+ MR_SAME(0, 13, 2, 0x144, RK_GENMASK_VAL(4, 3, 2)), /* spi-2 */
+ MR_SAME(1, 5, 1, 0x144, RK_GENMASK_VAL(5, 5, 0)), /* i2s-0 */
+ MR_SAME(1, 14, 1, 0x144, RK_GENMASK_VAL(5, 5, 1)), /* i2s-1 */
+ MR_SAME(1, 22, 2, 0x144, RK_GENMASK_VAL(6, 6, 0)), /* emmc-0 */
+ MR_SAME(2, 4, 2, 0x144, RK_GENMASK_VAL(6, 6, 1)), /* emmc-1 */
};
static struct rockchip_mux_route_data rk3188_mux_route_data[] = {
- {
- /* non-iomuxed emmc/flash pins on flash-dqs */
- .bank_num = 0,
- .pin = 24,
- .func = 1,
- .route_location = ROCKCHIP_ROUTE_GRF,
- .route_offset = 0xa0,
- .route_val = BIT(16 + 11),
- }, {
- /* non-iomuxed emmc/flash pins on emmc-clk */
- .bank_num = 0,
- .pin = 24,
- .func = 2,
- .route_location = ROCKCHIP_ROUTE_GRF,
- .route_offset = 0xa0,
- .route_val = BIT(16 + 11) | BIT(11),
- },
+ /* non-iomuxed emmc/flash pins on flash-dqs */
+ MR_GRF(0, 24, 1, 0xa0, RK_GENMASK_VAL(11, 11, 0)),
+ /* non-iomuxed emmc/flash pins on emmc-clk */
+ MR_GRF(0, 24, 2, 0xa0, RK_GENMASK_VAL(11, 11, 1)),
};
static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
- {
- /* pwm0-0 */
- .bank_num = 0,
- .pin = 26,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16),
- }, {
- /* pwm0-1 */
- .bank_num = 3,
- .pin = 21,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16) | BIT(0),
- }, {
- /* pwm1-0 */
- .bank_num = 0,
- .pin = 27,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 1),
- }, {
- /* pwm1-1 */
- .bank_num = 0,
- .pin = 30,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 1) | BIT(1),
- }, {
- /* pwm2-0 */
- .bank_num = 0,
- .pin = 28,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 2),
- }, {
- /* pwm2-1 */
- .bank_num = 1,
- .pin = 12,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 2) | BIT(2),
- }, {
- /* pwm3-0 */
- .bank_num = 3,
- .pin = 26,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 3),
- }, {
- /* pwm3-1 */
- .bank_num = 1,
- .pin = 11,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 3) | BIT(3),
- }, {
- /* sdio-0_d0 */
- .bank_num = 1,
- .pin = 1,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 4),
- }, {
- /* sdio-1_d0 */
- .bank_num = 3,
- .pin = 2,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 4) | BIT(4),
- }, {
- /* spi-0_rx */
- .bank_num = 0,
- .pin = 13,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 5),
- }, {
- /* spi-1_rx */
- .bank_num = 2,
- .pin = 0,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 5) | BIT(5),
- }, {
- /* emmc-0_cmd */
- .bank_num = 1,
- .pin = 22,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 7),
- }, {
- /* emmc-1_cmd */
- .bank_num = 2,
- .pin = 4,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 7) | BIT(7),
- }, {
- /* uart2-0_rx */
- .bank_num = 1,
- .pin = 19,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 8),
- }, {
- /* uart2-1_rx */
- .bank_num = 1,
- .pin = 10,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 8) | BIT(8),
- }, {
- /* uart1-0_rx */
- .bank_num = 1,
- .pin = 10,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 11),
- }, {
- /* uart1-1_rx */
- .bank_num = 3,
- .pin = 13,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 11) | BIT(11),
- },
+ MR_SAME(0, 26, 1, 0x50, RK_GENMASK_VAL(0, 0, 0)), /* pwm0-0 */
+ MR_SAME(3, 21, 1, 0x50, RK_GENMASK_VAL(0, 0, 1)), /* pwm0-1 */
+ MR_SAME(0, 27, 1, 0x50, RK_GENMASK_VAL(1, 1, 0)), /* pwm1-0 */
+ MR_SAME(0, 30, 2, 0x50, RK_GENMASK_VAL(1, 1, 1)), /* pwm1-1 */
+ MR_SAME(0, 28, 1, 0x50, RK_GENMASK_VAL(2, 2, 0)), /* pwm2-0 */
+ MR_SAME(1, 12, 2, 0x50, RK_GENMASK_VAL(2, 2, 1)), /* pwm2-1 */
+ MR_SAME(3, 26, 1, 0x50, RK_GENMASK_VAL(3, 3, 0)), /* pwm3-0 */
+ MR_SAME(1, 11, 2, 0x50, RK_GENMASK_VAL(3, 3, 1)), /* pwm3-1 */
+ MR_SAME(1, 1, 1, 0x50, RK_GENMASK_VAL(4, 4, 0)), /* sdio-0_d0 */
+ MR_SAME(3, 2, 1, 0x50, RK_GENMASK_VAL(4, 4, 1)), /* sdio-1_d0 */
+ MR_SAME(0, 13, 2, 0x50, RK_GENMASK_VAL(5, 5, 0)), /* spi-0_rx */
+ MR_SAME(2, 0, 2, 0x50, RK_GENMASK_VAL(5, 5, 1)), /* spi-1_rx */
+ MR_SAME(1, 22, 2, 0x50, RK_GENMASK_VAL(7, 7, 0)), /* emmc-0_cmd */
+ MR_SAME(2, 4, 2, 0x50, RK_GENMASK_VAL(7, 7, 1)), /* emmc-1_cmd */
+ MR_SAME(1, 19, 2, 0x50, RK_GENMASK_VAL(8, 8, 0)), /* uart2-0_rx */
+ MR_SAME(1, 10, 2, 0x50, RK_GENMASK_VAL(8, 8, 1)), /* uart2-1_rx */
+ MR_SAME(1, 10, 1, 0x50, RK_GENMASK_VAL(11, 11, 0)), /* uart1-0_rx */
+ MR_SAME(3, 13, 1, 0x50, RK_GENMASK_VAL(11, 11, 1)), /* uart1-1_rx */
};
static struct rockchip_mux_route_data rk3288_mux_route_data[] = {
- {
- /* edphdmi_cecinoutt1 */
- .bank_num = 7,
- .pin = 16,
- .func = 2,
- .route_offset = 0x264,
- .route_val = BIT(16 + 12) | BIT(12),
- }, {
- /* edphdmi_cecinout */
- .bank_num = 7,
- .pin = 23,
- .func = 4,
- .route_offset = 0x264,
- .route_val = BIT(16 + 12),
- },
+ MR_SAME(7, 16, 2, 0x264, RK_GENMASK_VAL(12, 12, 1)), /* edphdmi_cecinoutt1 */
+ MR_SAME(7, 23, 4, 0x264, RK_GENMASK_VAL(12, 12, 0)), /* edphdmi_cecinout */
};
static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
- {
- /* rtc_clk */
- .bank_num = 0,
- .pin = 19,
- .func = 1,
- .route_offset = 0x314,
- .route_val = BIT(16 + 0) | BIT(0),
- }, {
- /* uart2_rxm0 */
- .bank_num = 1,
- .pin = 22,
- .func = 2,
- .route_offset = 0x314,
- .route_val = BIT(16 + 2) | BIT(16 + 3),
- }, {
- /* uart2_rxm1 */
- .bank_num = 4,
- .pin = 26,
- .func = 2,
- .route_offset = 0x314,
- .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
- }, {
- /* i2c3_sdam0 */
- .bank_num = 0,
- .pin = 15,
- .func = 2,
- .route_offset = 0x608,
- .route_val = BIT(16 + 8) | BIT(16 + 9),
- }, {
- /* i2c3_sdam1 */
- .bank_num = 3,
- .pin = 12,
- .func = 2,
- .route_offset = 0x608,
- .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
- }, {
- /* i2c3_sdam2 */
- .bank_num = 2,
- .pin = 0,
- .func = 3,
- .route_offset = 0x608,
- .route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9),
- }, {
- /* i2s-8ch-1-sclktxm0 */
- .bank_num = 1,
- .pin = 3,
- .func = 2,
- .route_offset = 0x308,
- .route_val = BIT(16 + 3),
- }, {
- /* i2s-8ch-1-sclkrxm0 */
- .bank_num = 1,
- .pin = 4,
- .func = 2,
- .route_offset = 0x308,
- .route_val = BIT(16 + 3),
- }, {
- /* i2s-8ch-1-sclktxm1 */
- .bank_num = 1,
- .pin = 13,
- .func = 2,
- .route_offset = 0x308,
- .route_val = BIT(16 + 3) | BIT(3),
- }, {
- /* i2s-8ch-1-sclkrxm1 */
- .bank_num = 1,
- .pin = 14,
- .func = 2,
- .route_offset = 0x308,
- .route_val = BIT(16 + 3) | BIT(3),
- }, {
- /* pdm-clkm0 */
- .bank_num = 1,
- .pin = 4,
- .func = 3,
- .route_offset = 0x308,
- .route_val = BIT(16 + 12) | BIT(16 + 13),
- }, {
- /* pdm-clkm1 */
- .bank_num = 1,
- .pin = 14,
- .func = 4,
- .route_offset = 0x308,
- .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
- }, {
- /* pdm-clkm2 */
- .bank_num = 2,
- .pin = 6,
- .func = 2,
- .route_offset = 0x308,
- .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
- }, {
- /* pdm-clkm-m2 */
- .bank_num = 2,
- .pin = 4,
- .func = 3,
- .route_offset = 0x600,
- .route_val = BIT(16 + 2) | BIT(2),
- }, {
- /* spi1_miso */
- .bank_num = 3,
- .pin = 10,
- .func = 3,
- .route_offset = 0x314,
- .route_val = BIT(16 + 9),
- }, {
- /* spi1_miso_m1 */
- .bank_num = 2,
- .pin = 4,
- .func = 2,
- .route_offset = 0x314,
- .route_val = BIT(16 + 9) | BIT(9),
- }, {
- /* owire_m0 */
- .bank_num = 0,
- .pin = 11,
- .func = 3,
- .route_offset = 0x314,
- .route_val = BIT(16 + 10) | BIT(16 + 11),
- }, {
- /* owire_m1 */
- .bank_num = 1,
- .pin = 22,
- .func = 7,
- .route_offset = 0x314,
- .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
- }, {
- /* owire_m2 */
- .bank_num = 2,
- .pin = 2,
- .func = 5,
- .route_offset = 0x314,
- .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
- }, {
- /* can_rxd_m0 */
- .bank_num = 0,
- .pin = 11,
- .func = 2,
- .route_offset = 0x314,
- .route_val = BIT(16 + 12) | BIT(16 + 13),
- }, {
- /* can_rxd_m1 */
- .bank_num = 1,
- .pin = 22,
- .func = 5,
- .route_offset = 0x314,
- .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
- }, {
- /* can_rxd_m2 */
- .bank_num = 2,
- .pin = 2,
- .func = 4,
- .route_offset = 0x314,
- .route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
- }, {
- /* mac_rxd0_m0 */
- .bank_num = 1,
- .pin = 20,
- .func = 3,
- .route_offset = 0x314,
- .route_val = BIT(16 + 14),
- }, {
- /* mac_rxd0_m1 */
- .bank_num = 4,
- .pin = 2,
- .func = 2,
- .route_offset = 0x314,
- .route_val = BIT(16 + 14) | BIT(14),
- }, {
- /* uart3_rx */
- .bank_num = 3,
- .pin = 12,
- .func = 4,
- .route_offset = 0x314,
- .route_val = BIT(16 + 15),
- }, {
- /* uart3_rx_m1 */
- .bank_num = 0,
- .pin = 17,
- .func = 3,
- .route_offset = 0x314,
- .route_val = BIT(16 + 15) | BIT(15),
- },
+ MR_SAME(0, 19, 1, 0x314, RK_GENMASK_VAL(0, 0, 1)), /* rtc_clk */
+ MR_SAME(1, 22, 2, 0x314, RK_GENMASK_VAL(3, 2, 0)), /* uart2_rxm0 */
+ MR_SAME(4, 26, 2, 0x314, RK_GENMASK_VAL(3, 2, 1)), /* uart2_rxm1 */
+ MR_SAME(0, 15, 2, 0x608, RK_GENMASK_VAL(9, 8, 0)), /* i2c3_sdam0 */
+ MR_SAME(3, 12, 2, 0x608, RK_GENMASK_VAL(9, 8, 1)), /* i2c3_sdam1 */
+ MR_SAME(2, 0, 3, 0x608, RK_GENMASK_VAL(9, 8, 2)), /* i2c3_sdam2 */
+ MR_SAME(1, 3, 2, 0x308, RK_GENMASK_VAL(3, 3, 0)), /* i2s-8ch-1-sclktxm0 */
+ MR_SAME(1, 4, 2, 0x308, RK_GENMASK_VAL(3, 3, 0)), /* i2s-8ch-1-sclkrxm0 */
+ MR_SAME(1, 13, 2, 0x308, RK_GENMASK_VAL(3, 3, 1)), /* i2s-8ch-1-sclktxm1 */
+ MR_SAME(1, 14, 2, 0x308, RK_GENMASK_VAL(3, 3, 1)), /* i2s-8ch-1-sclkrxm1 */
+ MR_SAME(1, 4, 3, 0x308, RK_GENMASK_VAL(13, 12, 0)), /* pdm-clkm0 */
+ MR_SAME(1, 14, 4, 0x308, RK_GENMASK_VAL(13, 12, 1)), /* pdm-clkm1 */
+ MR_SAME(2, 6, 2, 0x308, RK_GENMASK_VAL(13, 12, 2)), /* pdm-clkm2 */
+ MR_SAME(2, 4, 3, 0x600, RK_GENMASK_VAL(2, 2, 1)), /* pdm-clkm-m2 */
+ MR_SAME(3, 10, 3, 0x314, RK_GENMASK_VAL(9, 9, 0)), /* spi1_miso */
+ MR_SAME(2, 4, 2, 0x314, RK_GENMASK_VAL(9, 9, 1)), /* spi1_miso_m1 */
+ MR_SAME(0, 11, 3, 0x314, RK_GENMASK_VAL(11, 10, 0)), /* owire_m0 */
+ MR_SAME(1, 22, 7, 0x314, RK_GENMASK_VAL(11, 10, 1)), /* owire_m1 */
+ MR_SAME(2, 2, 5, 0x314, RK_GENMASK_VAL(11, 10, 2)), /* owire_m2 */
+ MR_SAME(0, 11, 2, 0x314, RK_GENMASK_VAL(13, 12, 0)), /* can_rxd_m0 */
+ MR_SAME(1, 22, 5, 0x314, RK_GENMASK_VAL(13, 12, 1)), /* can_rxd_m1 */
+ MR_SAME(2, 2, 4, 0x314, RK_GENMASK_VAL(13, 12, 2)), /* can_rxd_m2 */
+ MR_SAME(1, 20, 3, 0x314, RK_GENMASK_VAL(14, 14, 0)), /* mac_rxd0_m0 */
+ MR_SAME(4, 2, 2, 0x314, RK_GENMASK_VAL(14, 14, 1)), /* mac_rxd0_m1 */
+ MR_SAME(3, 12, 4, 0x314, RK_GENMASK_VAL(15, 15, 0)), /* uart3_rx */
+ MR_SAME(0, 17, 3, 0x314, RK_GENMASK_VAL(15, 15, 1)), /* uart3_rx_m1 */
};
static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
- {
- /* uart2dbg_rxm0 */
- .bank_num = 1,
- .pin = 1,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16) | BIT(16 + 1),
- }, {
- /* uart2dbg_rxm1 */
- .bank_num = 2,
- .pin = 1,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
- }, {
- /* gmac-m1_rxd0 */
- .bank_num = 1,
- .pin = 11,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 2) | BIT(2),
- }, {
- /* gmac-m1-optimized_rxd3 */
- .bank_num = 1,
- .pin = 14,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 10) | BIT(10),
- }, {
- /* pdm_sdi0m0 */
- .bank_num = 2,
- .pin = 19,
- .func = 2,
- .route_offset = 0x50,
- .route_val = BIT(16 + 3),
- }, {
- /* pdm_sdi0m1 */
- .bank_num = 1,
- .pin = 23,
- .func = 3,
- .route_offset = 0x50,
- .route_val = BIT(16 + 3) | BIT(3),
- }, {
- /* spi_rxdm2 */
- .bank_num = 3,
- .pin = 2,
- .func = 4,
- .route_offset = 0x50,
- .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
- }, {
- /* i2s2_sdim0 */
- .bank_num = 1,
- .pin = 24,
- .func = 1,
- .route_offset = 0x50,
- .route_val = BIT(16 + 6),
- }, {
- /* i2s2_sdim1 */
- .bank_num = 3,
- .pin = 2,
- .func = 6,
- .route_offset = 0x50,
- .route_val = BIT(16 + 6) | BIT(6),
- }, {
- /* card_iom1 */
- .bank_num = 2,
- .pin = 22,
- .func = 3,
- .route_offset = 0x50,
- .route_val = BIT(16 + 7) | BIT(7),
- }, {
- /* tsp_d5m1 */
- .bank_num = 2,
- .pin = 16,
- .func = 3,
- .route_offset = 0x50,
- .route_val = BIT(16 + 8) | BIT(8),
- }, {
- /* cif_data5m1 */
- .bank_num = 2,
- .pin = 16,
- .func = 4,
- .route_offset = 0x50,
- .route_val = BIT(16 + 9) | BIT(9),
- },
+ MR_SAME(1, 1, 2, 0x50, RK_GENMASK_VAL(1, 0, 0)), /* uart2dbg_rxm0 */
+ MR_SAME(2, 1, 1, 0x50, RK_GENMASK_VAL(1, 0, 1)), /* uart2dbg_rxm1 */
+ MR_SAME(1, 11, 2, 0x50, RK_GENMASK_VAL(2, 2, 1)), /* gmac-m1_rxd0 */
+ MR_SAME(1, 14, 2, 0x50, RK_GENMASK_VAL(10, 10, 1)), /* gmac-m1-optimized_rxd3 */
+ MR_SAME(2, 19, 2, 0x50, RK_GENMASK_VAL(3, 3, 0)), /* pdm_sdi0m0 */
+ MR_SAME(1, 23, 3, 0x50, RK_GENMASK_VAL(3, 3, 1)), /* pdm_sdi0m1 */
+ MR_SAME(3, 2, 4, 0x50, RK_GENMASK_VAL(5, 4, 2)), /* spi_rxdm2 */
+ MR_SAME(1, 24, 1, 0x50, RK_GENMASK_VAL(6, 6, 0)), /* i2s2_sdim0 */
+ MR_SAME(3, 2, 6, 0x50, RK_GENMASK_VAL(6, 6, 1)), /* i2s2_sdim1 */
+ MR_SAME(2, 22, 3, 0x50, RK_GENMASK_VAL(7, 7, 1)), /* card_iom1 */
+ MR_SAME(2, 16, 3, 0x50, RK_GENMASK_VAL(8, 8, 1)), /* tsp_d5m1 */
+ MR_SAME(2, 16, 4, 0x50, RK_GENMASK_VAL(9, 9, 1)), /* cif_data5m1 */
};
static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
- {
- /* uart2dbga_rx */
- .bank_num = 4,
- .pin = 8,
- .func = 2,
- .route_offset = 0xe21c,
- .route_val = BIT(16 + 10) | BIT(16 + 11),
- }, {
- /* uart2dbgb_rx */
- .bank_num = 4,
- .pin = 16,
- .func = 2,
- .route_offset = 0xe21c,
- .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
- }, {
- /* uart2dbgc_rx */
- .bank_num = 4,
- .pin = 19,
- .func = 1,
- .route_offset = 0xe21c,
- .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
- }, {
- /* pcie_clkreqn */
- .bank_num = 2,
- .pin = 26,
- .func = 2,
- .route_offset = 0xe21c,
- .route_val = BIT(16 + 14),
- }, {
- /* pcie_clkreqnb */
- .bank_num = 4,
- .pin = 24,
- .func = 1,
- .route_offset = 0xe21c,
- .route_val = BIT(16 + 14) | BIT(14),
- },
+ MR_SAME(4, 8, 2, 0xe21c, RK_GENMASK_VAL(11, 10, 0)), /* uart2dbga_rx */
+ MR_SAME(4, 16, 2, 0xe21c, RK_GENMASK_VAL(11, 10, 1)), /* uart2dbgb_rx */
+ MR_SAME(4, 19, 1, 0xe21c, RK_GENMASK_VAL(11, 10, 2)), /* uart2dbgc_rx */
+ MR_SAME(2, 26, 2, 0xe21c, RK_GENMASK_VAL(14, 14, 0)), /* pcie_clkreqn */
+ MR_SAME(4, 24, 1, 0xe21c, RK_GENMASK_VAL(14, 14, 1)), /* pcie_clkreqnb */
};
static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
--
2.17.1
^ permalink raw reply related
* [PATCH 12/13] pinctrl: rockchip: define common codes without special chip name
From: Jianqun Xu @ 2020-07-17 1:53 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Modify RK3399_DRV_3BITS_PER_PIN to ROCKCHIP_DRV_3BITS_PER_PIN, and
modify RK3288_DRV_BITS_PER_PIN to ROCKCHIP_DRV_BITS_PER_PIN.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 3b74455dcdb2..71a367896297 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -75,6 +75,9 @@ enum rockchip_pinctrl_type {
#define IOMUX_WIDTH_3BIT BIT(4)
#define IOMUX_WIDTH_2BIT BIT(5)
+#define ROCKCHIP_DRV_3BITS_PER_PIN (3)
+#define ROCKCHIP_DRV_BITS_PER_PIN (2)
+
/**
* @type: iomux variant using IOMUX_* constants
* @offset: if initialized to -1 it will be autocalculated, by specifying
@@ -2074,7 +2077,6 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
#define RK3399_PULL_GRF_OFFSET 0xe040
#define RK3399_PULL_PMU_OFFSET 0x40
-#define RK3399_DRV_3BITS_PER_PIN 3
#define RK3399_PULL_BITS_PER_PIN 2
#define RK3399_PULL_PINS_PER_REG 8
#define RK3399_PULL_BANK_STRIDE 16
@@ -2154,7 +2156,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
- rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+ rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
switch (bit) {
case 0 ... 12:
/* regular case, nothing to do */
@@ -2197,7 +2199,7 @@ static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
- rmask_bits = RK3288_DRV_BITS_PER_PIN;
+ rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
break;
default:
dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
@@ -2251,7 +2253,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
switch (drv_type) {
case DRV_TYPE_IO_1V8_3V0_AUTO:
case DRV_TYPE_IO_3V3_ONLY:
- rmask_bits = RK3399_DRV_3BITS_PER_PIN;
+ rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
switch (bit) {
case 0 ... 12:
/* regular case, nothing to do */
@@ -2291,7 +2293,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
case DRV_TYPE_IO_DEFAULT:
case DRV_TYPE_IO_1V8_OR_3V0:
case DRV_TYPE_IO_1V8_ONLY:
- rmask_bits = RK3288_DRV_BITS_PER_PIN;
+ rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
break;
default:
dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
--
2.17.1
^ permalink raw reply related
* [PATCH 10/13] pinctrl: rockchip: do codingstyle
From: Jianqun Xu @ 2020-07-17 1:53 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Add RK3288 definitons to separate from other SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index ec6a1a08f8b1..04e7027ec8e1 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1855,6 +1855,11 @@ static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
}
#define RK3288_PULL_OFFSET 0x140
+#define RK3288_PULL_PMU_OFFSET 0x64
+#define RK3288_PULL_BITS_PER_PIN 2
+#define RK3288_PULL_PINS_PER_REG 8
+#define RK3288_PULL_BANK_STRIDE 16
+
static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
@@ -1864,22 +1869,22 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
/* The first 24 pins of the first bank are located in PMU */
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
- *reg = RK3188_PULL_PMU_OFFSET;
+ *reg = RK3288_PULL_PMU_OFFSET;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
- *bit = pin_num % RK3188_PULL_PINS_PER_REG;
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *reg += ((pin_num / RK3288_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3288_PULL_PINS_PER_REG;
+ *bit *= RK3288_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3288_PULL_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3288_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3288_PULL_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *bit = (pin_num % RK3288_PULL_PINS_PER_REG);
+ *bit *= RK3288_PULL_BITS_PER_PIN;
}
}
--
2.17.1
^ permalink raw reply related
* [PATCH 07/13] pinctrl: rockchip: do codingstyle
From: Jianqun Xu @ 2020-07-17 1:53 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Add RK3368 definitions to separate from other SoCs.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 34 ++++++++++++++++++------------
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 71335ed003b3..8e3fa9011165 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1987,6 +1987,9 @@ static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
#define RK3368_PULL_GRF_OFFSET 0x100
#define RK3368_PULL_PMU_OFFSET 0x10
+#define RK3368_PULL_BITS_PER_PIN 2
+#define RK3368_PULL_PINS_PER_REG 8
+#define RK3368_PULL_BANK_STRIDE 16
static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -1999,25 +2002,28 @@ static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3368_PULL_PMU_OFFSET;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
- *bit = pin_num % RK3188_PULL_PINS_PER_REG;
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *reg += ((pin_num / RK3368_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3368_PULL_PINS_PER_REG;
+ *bit *= RK3368_PULL_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3368_PULL_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
- *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
- *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3368_PULL_BANK_STRIDE;
+ *reg += ((pin_num / RK3368_PULL_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
- *bit *= RK3188_PULL_BITS_PER_PIN;
+ *bit = (pin_num % RK3368_PULL_PINS_PER_REG);
+ *bit *= RK3368_PULL_BITS_PER_PIN;
}
}
#define RK3368_DRV_PMU_OFFSET 0x20
#define RK3368_DRV_GRF_OFFSET 0x200
+#define RK3368_DRV_BITS_PER_PIN 2
+#define RK3368_DRV_PINS_PER_REG 8
+#define RK3368_DRV_BANK_STRIDE 16
static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
@@ -2030,20 +2036,20 @@ static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*regmap = info->regmap_pmu;
*reg = RK3368_DRV_PMU_OFFSET;
- *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
- *bit = pin_num % RK3288_DRV_PINS_PER_REG;
- *bit *= RK3288_DRV_BITS_PER_PIN;
+ *reg += ((pin_num / RK3368_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3368_DRV_PINS_PER_REG;
+ *bit *= RK3368_DRV_BITS_PER_PIN;
} else {
*regmap = info->regmap_base;
*reg = RK3368_DRV_GRF_OFFSET;
/* correct the offset, as we're starting with the 2nd bank */
*reg -= 0x10;
- *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
- *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
+ *reg += bank->bank_num * RK3368_DRV_BANK_STRIDE;
+ *reg += ((pin_num / RK3368_DRV_PINS_PER_REG) * 4);
- *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
- *bit *= RK3288_DRV_BITS_PER_PIN;
+ *bit = (pin_num % RK3368_DRV_PINS_PER_REG);
+ *bit *= RK3368_DRV_BITS_PER_PIN;
}
}
--
2.17.1
^ permalink raw reply related
* [PATCH 01/13] pinctrl: rockchip: add nr_pins to rockchip_pin_ctrl
From: Jianqun Xu @ 2020-07-17 1:48 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Add nr_pins to rockchip_pin_ctrl by hand, instead of calculating during
driver probe. This patch is prepare work for making rockchip_pin_ctrl to
be const type.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/pinctrl-rockchip.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index c07324d1f265..bc465da68f26 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -3573,6 +3573,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
struct rockchip_pin_ctrl *ctrl;
struct rockchip_pin_bank *bank;
int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
+ u32 nr_pins;
match = of_match_node(rockchip_pinctrl_dt_match, node);
ctrl = (struct rockchip_pin_ctrl *)match->data;
@@ -3599,13 +3600,14 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
drv_pmu_offs = ctrl->pmu_drv_offset;
drv_grf_offs = ctrl->grf_drv_offset;
bank = ctrl->pin_banks;
+ nr_pins = 0;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
int bank_pins = 0;
raw_spin_lock_init(&bank->slock);
bank->drvdata = d;
- bank->pin_base = ctrl->nr_pins;
- ctrl->nr_pins += bank->nr_pins;
+ bank->pin_base = nr_pins;
+ nr_pins += bank->nr_pins;
/* calculate iomux and drv offsets */
for (j = 0; j < 4; j++) {
@@ -3692,6 +3694,8 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
}
}
+ WARN_ON(nr_pins != ctrl->nr_pins);
+
return ctrl;
}
@@ -3852,6 +3856,7 @@ static struct rockchip_pin_bank px30_pin_banks[] = {
static struct rockchip_pin_ctrl px30_pin_ctrl = {
.pin_banks = px30_pin_banks,
.nr_banks = ARRAY_SIZE(px30_pin_banks),
+ .nr_pins = 128,
.label = "PX30-GPIO",
.type = PX30,
.grf_mux_offset = 0x0,
@@ -3876,6 +3881,7 @@ static struct rockchip_pin_bank rv1108_pin_banks[] = {
static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.pin_banks = rv1108_pin_banks,
.nr_banks = ARRAY_SIZE(rv1108_pin_banks),
+ .nr_pins = 128,
.label = "RV1108-GPIO",
.type = RV1108,
.grf_mux_offset = 0x10,
@@ -3897,6 +3903,7 @@ static struct rockchip_pin_bank rk2928_pin_banks[] = {
static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
.pin_banks = rk2928_pin_banks,
.nr_banks = ARRAY_SIZE(rk2928_pin_banks),
+ .nr_pins = 128,
.label = "RK2928-GPIO",
.type = RK2928,
.grf_mux_offset = 0xa8,
@@ -3912,6 +3919,7 @@ static struct rockchip_pin_bank rk3036_pin_banks[] = {
static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
.pin_banks = rk3036_pin_banks,
.nr_banks = ARRAY_SIZE(rk3036_pin_banks),
+ .nr_pins = 96,
.label = "RK3036-GPIO",
.type = RK2928,
.grf_mux_offset = 0xa8,
@@ -3930,6 +3938,7 @@ static struct rockchip_pin_bank rk3066a_pin_banks[] = {
static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
.pin_banks = rk3066a_pin_banks,
.nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
+ .nr_pins = 176,
.label = "RK3066a-GPIO",
.type = RK2928,
.grf_mux_offset = 0xa8,
@@ -3946,6 +3955,7 @@ static struct rockchip_pin_bank rk3066b_pin_banks[] = {
static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
.pin_banks = rk3066b_pin_banks,
.nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
+ .nr_pins = 128,
.label = "RK3066b-GPIO",
.type = RK3066B,
.grf_mux_offset = 0x60,
@@ -3961,6 +3971,7 @@ static struct rockchip_pin_bank rk3128_pin_banks[] = {
static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
.pin_banks = rk3128_pin_banks,
.nr_banks = ARRAY_SIZE(rk3128_pin_banks),
+ .nr_pins = 128,
.label = "RK3128-GPIO",
.type = RK3128,
.grf_mux_offset = 0xa8,
@@ -3981,6 +3992,7 @@ static struct rockchip_pin_bank rk3188_pin_banks[] = {
static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
.pin_banks = rk3188_pin_banks,
.nr_banks = ARRAY_SIZE(rk3188_pin_banks),
+ .nr_pins = 128,
.label = "RK3188-GPIO",
.type = RK3188,
.grf_mux_offset = 0x60,
@@ -3999,6 +4011,7 @@ static struct rockchip_pin_bank rk3228_pin_banks[] = {
static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
.pin_banks = rk3228_pin_banks,
.nr_banks = ARRAY_SIZE(rk3228_pin_banks),
+ .nr_pins = 128,
.label = "RK3228-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
@@ -4043,6 +4056,7 @@ static struct rockchip_pin_bank rk3288_pin_banks[] = {
static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
.pin_banks = rk3288_pin_banks,
.nr_banks = ARRAY_SIZE(rk3288_pin_banks),
+ .nr_pins = 264,
.label = "RK3288-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
@@ -4079,6 +4093,7 @@ static struct rockchip_pin_bank rk3308_pin_banks[] = {
static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
.pin_banks = rk3308_pin_banks,
.nr_banks = ARRAY_SIZE(rk3308_pin_banks),
+ .nr_pins = 160,
.label = "RK3308-GPIO",
.type = RK3308,
.grf_mux_offset = 0x0,
@@ -4108,6 +4123,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
.pin_banks = rk3328_pin_banks,
.nr_banks = ARRAY_SIZE(rk3328_pin_banks),
+ .nr_pins = 128,
.label = "RK3328-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
@@ -4134,6 +4150,7 @@ static struct rockchip_pin_bank rk3368_pin_banks[] = {
static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
.pin_banks = rk3368_pin_banks,
.nr_banks = ARRAY_SIZE(rk3368_pin_banks),
+ .nr_pins = 128,
.label = "RK3368-GPIO",
.type = RK3368,
.grf_mux_offset = 0x0,
@@ -4198,6 +4215,7 @@ static struct rockchip_pin_bank rk3399_pin_banks[] = {
static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
.pin_banks = rk3399_pin_banks,
.nr_banks = ARRAY_SIZE(rk3399_pin_banks),
+ .nr_pins = 160,
.label = "RK3399-GPIO",
.type = RK3399,
.grf_mux_offset = 0xe000,
--
2.17.1
^ permalink raw reply related
* [PATCH 00/13] pinctrl: rockchip: prepare work for split driver
From: Jianqun Xu @ 2020-07-17 1:48 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
This serial patchs include 12 codingstyle patches and 1 bug fix (enable
gpio pclk for rockchip_gpio_to_irq).
Also it's prepare for split driver work.
Jianqun Xu (13):
pinctrl: rockchip: add nr_pins to rockchip_pin_ctrl
pinctrl: rockchip: modify rockchip_pin_ctrl to const struct
pinctrl: rockchip: make driver be tristate module
pinctrl: rockchip: enable gpio pclk for rockchip_gpio_to_irq
pinctrl: rockchip: create irq mapping in gpio_to_irq
pinctrl: rockchip: do codingstyle
pinctrl: rockchip: do codingstyle
pinctrl: rockchip: do codingstyle
pinctrl: rockchip: do codingstyle
pinctrl: rockchip: do codingstyle
pinctrl: rockchip: do codingstyle
pinctrl: rockchip: define common codes without special chip name
pinctrl: rockchip: do codingstyle by adding mux route definitions
drivers/pinctrl/Kconfig | 2 +-
drivers/pinctrl/pinctrl-rockchip.c | 933 ++++++++---------------------
2 files changed, 261 insertions(+), 674 deletions(-)
--
2.17.1
^ permalink raw reply
* [PATCH 03/13] pinctrl: rockchip: make driver be tristate module
From: Jianqun Xu @ 2020-07-17 1:48 UTC (permalink / raw)
To: heiko, linus.walleij
Cc: linux-gpio, linux-rockchip, linux-kernel, kever.yang, david.wu,
Jianqun Xu
In-Reply-To: <20200717014908.13914-1-jay.xu@rock-chips.com>
Make pinctrl-rockchip driver to be tristate module, support to build as
a module, this is useful for GKI.
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
---
drivers/pinctrl/Kconfig | 2 +-
drivers/pinctrl/pinctrl-rockchip.c | 7 +++++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8828613c4e0e..dd4874e2ac67 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -207,7 +207,7 @@ config PINCTRL_OXNAS
select MFD_SYSCON
config PINCTRL_ROCKCHIP
- bool
+ tristate "Rockchip gpio and pinctrl driver"
select PINMUX
select GENERIC_PINCONF
select GENERIC_IRQ_CHIP
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 77c1e6744f6c..ec509ef8bd8d 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -16,10 +16,12 @@
*/
#include <linux/init.h>
+#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
+#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/machine.h>
@@ -4259,6 +4261,7 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = &rk3399_pin_ctrl },
{},
};
+MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
static struct platform_driver rockchip_pinctrl_driver = {
.probe = rockchip_pinctrl_probe,
@@ -4274,3 +4277,7 @@ static int __init rockchip_pinctrl_drv_register(void)
return platform_driver_register(&rockchip_pinctrl_driver);
}
postcore_initcall(rockchip_pinctrl_drv_register);
+
+MODULE_DESCRIPTION("ROCKCHIP Pin Controller Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:pinctrl-rockchip");
--
2.17.1
^ permalink raw reply related
* Re: gpio-omap: handle bias flag for gpio line
From: Drew Fustini @ 2020-07-17 1:42 UTC (permalink / raw)
To: Tony Lindgren
Cc: Linus Walleij, Linux-OMAP, open list:GPIO SUBSYSTEM,
Jason Kridner, Robert Nelson
In-Reply-To: <20200713180519.GN5849@atomide.com>
On Mon, Jul 13, 2020 at 11:05:19AM -0700, Tony Lindgren wrote:
> * Drew Fustini <drew@beagleboard.org> [200713 17:47]:
> > Do you mean you would like to see the mapping added as a column in the pins file?
> >
> > debian@beaglebone:~$ sudo cat /sys/kernel/debug/pinctrl/44e10800.pinmux-pinctrl-single/pins |head
> > registered pins: 142
> > pin 0 (PIN0) 44e10800 00000027 pinctrl-single
> > pin 1 (PIN1) 44e10804 00000027 pinctrl-single
> > pin 2 (PIN2) 44e10808 00000027 pinctrl-single
> > pin 3 (PIN3) 44e1080c 00000027 pinctrl-single
> > pin 4 (PIN4) 44e10810 00000027 pinctrl-single
> > pin 5 (PIN5) 44e10814 00000027 pinctrl-single
> > pin 6 (PIN6) 44e10818 00000027 pinctrl-single
> > pin 7 (PIN7) 44e1081c 00000027 pinctrl-single
> > pin 8 (PIN8) 44e10820 00000027 pinctrl-single
> >
> > So that could be:
> >
> > debian@beaglebone:~$ sudo cat /sys/kernel/debug/pinctrl/44e10800.pinmux-pinctrl-single/pins |head
> > registered pins: 142
> > pin 0 (PIN0) 44e10800 00000027 pinctrl-single GPIO-32
> > pin 1 (PIN1) 44e10804 00000027 pinctrl-single GPIO-33
> > pin 2 (PIN2) 44e10808 00000027 pinctrl-single GPIO-34
> > pin 3 (PIN3) 44e1080c 00000027 pinctrl-single GPIO-35
> > pin 4 (PIN4) 44e10810 00000027 pinctrl-single GPIO-36
> > pin 5 (PIN5) 44e10814 00000027 pinctrl-single GPIO-37
> > pin 6 (PIN6) 44e10818 00000027 pinctrl-single GPIO-38
> > pin 7 (PIN7) 44e1081c 00000027 pinctrl-single GPIO-39
> > pin 8 (PIN8) 44e10820 00000027 pinctrl-single GPIO-22
>
> Yes that would make the debugfs output more understandable and
> easier to use.
I have posted a patch [0] to add the GPIO-xx column to the pins file.
Thanks,
Drew
[0] https://lore.kernel.org/linux-gpio/20200717013338.1741659-1-drew@beagleboard.org/
^ permalink raw reply
* [PATCH] pinctrl: single: print gpio number in pins debugfs file
From: Drew Fustini @ 2020-07-17 1:33 UTC (permalink / raw)
To: Tony Lindgren, Haojian Zhuang, Linus Walleij, linux-omap,
linux-gpio, Jason Kridner, Robert Nelson
Cc: Drew Fustini
If there is a gpio range mapping for the pin, then print out the gpio
number for the pin in the debugfs 'pins' file.
Here is an example on the BeagleBone Black:
$ cat /sys/kernel/debug/pinctrl/44e10800.pinmux-pinctrl-single/pins |head -20
registered pins: 142
pin 0 (PIN0) 44e10800 00000027 pinctrl-single GPIO-32
pin 1 (PIN1) 44e10804 00000027 pinctrl-single GPIO-33
pin 2 (PIN2) 44e10808 00000027 pinctrl-single GPIO-34
pin 3 (PIN3) 44e1080c 00000027 pinctrl-single GPIO-35
pin 4 (PIN4) 44e10810 00000027 pinctrl-single GPIO-36
pin 5 (PIN5) 44e10814 00000027 pinctrl-single GPIO-37
pin 6 (PIN6) 44e10818 00000027 pinctrl-single GPIO-38
pin 7 (PIN7) 44e1081c 00000027 pinctrl-single GPIO-39
pin 8 (PIN8) 44e10820 00000027 pinctrl-single GPIO-22
pin 9 (PIN9) 44e10824 00000030 pinctrl-single GPIO-23
pin 10 (PIN10) 44e10828 00000030 pinctrl-single GPIO-26
pin 11 (PIN11) 44e1082c 00000030 pinctrl-single GPIO-27
pin 12 (PIN12) 44e10830 00000030 pinctrl-single GPIO-44
pin 13 (PIN13) 44e10834 00000030 pinctrl-single GPIO-45
pin 14 (PIN14) 44e10838 00000030 pinctrl-single GPIO-46
pin 15 (PIN15) 44e1083c 00000030 pinctrl-single GPIO-47
pin 16 (PIN16) 44e10840 00000027 pinctrl-single GPIO-48
pin 17 (PIN17) 44e10844 00000027 pinctrl-single GPIO-49
pin 18 (PIN18) 44e10848 00000000 pinctrl-single GPIO-50
Signed-off-by: Drew Fustini <drew@beagleboard.org>
---
drivers/pinctrl/pinctrl-single.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index f3a8a465d27e..473fe0f61792 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -275,6 +275,14 @@ static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
unsigned val, mux_bytes;
unsigned long offset;
size_t pa;
+ struct pinctrl_gpio_range *range;
+ unsigned gpio_num = 0;
+
+ list_for_each_entry(range, &pctldev->gpio_ranges, node) {
+ if ((pin >= range->pin_base) &&
+ (pin < (range->pin_base + range->npins)))
+ gpio_num = range->base + (pin - range->pin_base);
+ }
pcs = pinctrl_dev_get_drvdata(pctldev);
@@ -283,7 +291,10 @@ static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
val = pcs->read(pcs->base + offset);
pa = pcs->res->start + offset;
- seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
+ if (gpio_num > 0)
+ seq_printf(s, "%zx %08x %s GPIO-%u", pa, val, DRIVER_NAME, gpio_num);
+ else
+ seq_printf(s, "%zx %08x %s", pa, val, DRIVER_NAME);
}
static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
--
2.25.1
^ permalink raw reply related
* [pinctrl:devel 63/64] drivers/pinctrl/mediatek/pinctrl-mt6779.c:775:15: error: a parameter list without types is only allowed in a function definition
From: kernel test robot @ 2020-07-17 0:46 UTC (permalink / raw)
To: Hanks Chen
Cc: kbuild-all, clang-built-linux, linux-gpio, Linus Walleij,
Mars Cheng, Andy Teng
[-- Attachment #1: Type: text/plain, Size: 1792 bytes --]
tree: https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git devel
head: d9ce0e9fdfd37d45f669b831d0c084a7c9338ee8
commit: e6f744c6ad4fb3b7ac06d4e22b79e435578a6d54 [63/64] pinctrl: mediatek: add pinctrl support for MT6779 SoC
config: x86_64-allmodconfig (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project ed6b578040a85977026c93bf4188f996148f3218)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
git checkout e6f744c6ad4fb3b7ac06d4e22b79e435578a6d54
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>):
>> drivers/pinctrl/mediatek/pinctrl-mt6779.c:775:1: warning: declaration specifier missing, defaulting to 'int'
arch_initcall(mt6779_pinctrl_init);
^
int
>> drivers/pinctrl/mediatek/pinctrl-mt6779.c:775:15: error: a parameter list without types is only allowed in a function definition
arch_initcall(mt6779_pinctrl_init);
^
1 warning and 1 error generated.
vim +775 drivers/pinctrl/mediatek/pinctrl-mt6779.c
770
771 static int __init mt6779_pinctrl_init(void)
772 {
773 return platform_driver_register(&mt6779_pinctrl_driver);
774 }
> 775 arch_initcall(mt6779_pinctrl_init);
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 75947 bytes --]
^ permalink raw reply
* Re: [PATCH v5 08/13] gpio: add support for the sl28cpld GPIO controller
From: kernel test robot @ 2020-07-17 0:25 UTC (permalink / raw)
To: Michael Walle, linux-gpio, devicetree, linux-kernel, linux-hwmon,
linux-pwm, linux-watchdog, linux-arm-kernel
Cc: kbuild-all, clang-built-linux, Linus Walleij, Bartosz Golaszewski,
Rob Herring
In-Reply-To: <20200706175353.16404-9-michael@walle.cc>
[-- Attachment #1: Type: text/plain, Size: 3895 bytes --]
Hi Michael,
I love your patch! Perhaps something to improve:
[auto build test WARNING on ljones-mfd/for-mfd-next]
[also build test WARNING on shawnguo/for-next v5.8-rc5]
[cannot apply to gpio/for-next hwmon/hwmon-next next-20200716]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Michael-Walle/Add-support-for-Kontron-sl28cpld/20200707-020034
base: https://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git for-mfd-next
config: x86_64-allyesconfig (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project ed6b578040a85977026c93bf4188f996148f3218)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpio/gpio-sl28cpld.c:121:29: warning: implicit conversion from 'unsigned long' to 'unsigned int' changes value from 18446744073709551615 to 4294967295 [-Wconstant-conversion]
config.reg_dir_out_base = GPIO_REGMAP_ADDR(base + GPIO_REG_DIR);
~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/gpio/regmap.h:12:44: note: expanded from macro 'GPIO_REGMAP_ADDR'
#define GPIO_REGMAP_ADDR(addr) ((addr) ? : GPIO_REGMAP_ADDR_ZERO)
^~~~~~~~~~~~~~~~~~~~~
include/linux/gpio/regmap.h:11:32: note: expanded from macro 'GPIO_REGMAP_ADDR_ZERO'
#define GPIO_REGMAP_ADDR_ZERO ((unsigned long)(-1))
^~~~~~~~~~~~~~~~~~~
1 warning generated.
vim +121 drivers/gpio/gpio-sl28cpld.c
88
89 static int sl28cpld_gpio_probe(struct platform_device *pdev)
90 {
91 struct gpio_regmap_config config = {0};
92 enum sl28cpld_gpio_type type;
93 struct regmap *regmap;
94 u32 base;
95 int ret;
96
97 if (!pdev->dev.parent)
98 return -ENODEV;
99
100 type = (uintptr_t)device_get_match_data(&pdev->dev);
101 if (!type)
102 return -ENODEV;
103
104 ret = device_property_read_u32(&pdev->dev, "reg", &base);
105 if (ret)
106 return -EINVAL;
107
108 regmap = dev_get_regmap(pdev->dev.parent, NULL);
109 if (!regmap)
110 return -ENODEV;
111
112 config.regmap = regmap;
113 config.parent = &pdev->dev;
114 config.ngpio = 8;
115
116 switch (type) {
117 case SL28CPLD_GPIO:
118 config.reg_dat_base = base + GPIO_REG_IN;
119 config.reg_set_base = base + GPIO_REG_OUT;
120 /* reg_dir_out_base might be zero */
> 121 config.reg_dir_out_base = GPIO_REGMAP_ADDR(base + GPIO_REG_DIR);
122
123 /* This type supports interrupts */
124 ret = sl28cpld_gpio_irq_init(pdev, base, &config);
125 if (ret)
126 return ret;
127 break;
128 case SL28CPLD_GPO:
129 config.reg_set_base = base + GPO_REG_OUT;
130 break;
131 case SL28CPLD_GPI:
132 config.reg_dat_base = base + GPI_REG_IN;
133 break;
134 default:
135 dev_err(&pdev->dev, "unknown type %d\n", type);
136 return -ENODEV;
137 }
138
139 return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(&pdev->dev, &config));
140 }
141
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 75399 bytes --]
^ permalink raw reply
* RE: [PATCH 1/2] pinctrl: imx: Support building SCU pinctrl driver as module
From: Anson Huang @ 2020-07-16 23:44 UTC (permalink / raw)
To: Daniel Baluta, Aisheng Dong, festevam@gmail.com,
shawnguo@kernel.org, stefan@agner.ch, kernel@pengutronix.de,
linus.walleij@linaro.org, s.hauer@pengutronix.de,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: dl-linux-imx
In-Reply-To: <5e2af0c3-c832-3978-017e-0b1649aac61c@nxp.com>
Hi, Daniel
> Subject: Re: [PATCH 1/2] pinctrl: imx: Support building SCU pinctrl driver as
> module
>
> On 7/16/20 6:21 PM, Anson Huang wrote:
> > Hi, Daniel
> >
> >
> >> Subject: Re: [PATCH 1/2] pinctrl: imx: Support building SCU pinctrl
> >> driver as module
> >>
> >> Hi Anson,
> >>
> >> Few comments inline:
> >>
> >> On 7/16/20 6:06 PM, Anson Huang wrote:
> >>> To support building i.MX SCU pinctrl driver as module, below things
> >>> need to
> >> be changed:
> >>> - Export SCU related functions and use "IS_ENABLED" instead of
> >>> "ifdef" to support SCU pinctrl driver user and itself to be
> >>> built as module;
> >>> - Use function callbacks for SCU related functions in pinctrl-imx.c
> >>> in order to support the scenario of PINCTRL_IMX is built in
> >>> while PINCTRL_IMX_SCU is built as module;
> >>> - All drivers using SCU pinctrl driver need to initialize the
> >>> SCU related function callback;
> >>> - Change PINCTR_IMX_SCU to tristate;
> >>> - Add module author, description and license.
> >>>
> >>> With above changes, i.MX SCU pinctrl driver can be built as module.
> >>
> >> There are a lot of changes here. I think it would be better to try to
> >> split them
> >>
> >> per functionality. One functional change per patch.
> > Actually, I ever tried to split them, but the function will be broken.
> > All the changes are just to support the module build. If split them,
> > the bisect will have pinctrl build or function broken.
>
> Hi Anson,
>
>
> I see your point and I know that this is a very hard task to get it right from
>
> the first patches.
>
> But let me suggest at least that:
>
> - changes in drivers/pinctrl/freescale/pinctrl-imx.c (include file and
> MODULE_ macros should go to a separate patch).
You meant in patch #2, the changes in Kconfig and the changes in .c file should
be split to 2 patches?
Thanks,
Anson
^ permalink raw reply
* [PATCH] dt-bindings: ingenic,pinctrl: Support pinmux/pinconf nodes
From: Paul Cercueil @ 2020-07-16 23:32 UTC (permalink / raw)
To: Rob Herring, Linus Walleij
Cc: od, linux-gpio, devicetree, linux-kernel, Paul Cercueil
Add YAML to describe the pinmux/pinconf sub-nodes of the pinctrl IP on
Ingenic SoCs.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
In-Reply-To: CAL_Jsq+nHZsbOMPpXC7NWp1etgVL57Q+o=gr6BJ6ijAq1pLJUw@mail.gmail.com
---
.../bindings/pinctrl/ingenic,pinctrl.yaml | 41 ++++++++++++++++++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
index adf462cc2737..9d374f55ebb1 100644
--- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
@@ -110,7 +110,46 @@ required:
- "#address-cells"
- "#size-cells"
-additionalProperties: false
+additionalProperties:
+ anyOf:
+ - type: object
+ allOf:
+ - $ref: pincfg-node.yaml#
+ - $ref: pinmux-node.yaml#
+
+ properties:
+ phandle: true
+ function: true
+ groups: true
+ pins: true
+ bias-disable: true
+ bias-pull-up: true
+ bias-pull-down: true
+ output-low: true
+ output-high: true
+ additionalProperties: false
+
+ - type: object
+ properties:
+ phandle: true
+ additionalProperties:
+ type: object
+ allOf:
+ - $ref: pincfg-node.yaml#
+ - $ref: pinmux-node.yaml#
+
+ properties:
+ phandle: true
+ function: true
+ groups: true
+ pins: true
+ bias-disable: true
+ bias-pull-up: true
+ bias-pull-down: true
+ output-low: true
+ output-high: true
+ additionalProperties: false
+
examples:
- |
--
2.27.0
^ permalink raw reply related
* Re: [PATCH v3 3/5] pinctrl: qcom: Use return value from irq_set_wake call
From: Doug Anderson @ 2020-07-16 21:51 UTC (permalink / raw)
To: Linus Walleij
Cc: Maulik Shah, Bjorn Andersson, Marc Zyngier, Stephen Boyd,
Evan Green, Matthias Kaehlcke, linux-kernel@vger.kernel.org, MSM,
open list:GPIO SUBSYSTEM, Andy Gross, Thomas Gleixner,
Jason Cooper, Rajendra Nayak, Lina Iyer,
open list:GPIO SUBSYSTEM <linux-gpio@vger.kernel.org>, Andy Gross <agross@kernel.org>, Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Doug Anderson <dianders@chromium.org>, Rajendra Nayak <rnayak@codeaurora.org>, Lina Iyer <ilina@codeaurora.org>,
In-Reply-To: <CACRpkdb-3Tf4s5=Gxjhy62GX=HUYkLOcPKZ6JWaLTQipz-0r6A@mail.gmail.com>
Hi,
On Thu, Jul 16, 2020 at 6:19 AM Linus Walleij <linus.walleij@linaro.org> wrote:
>
> On Mon, Jun 22, 2020 at 11:32 AM Maulik Shah <mkshah@codeaurora.org> wrote:
>
> > msmgpio irqchip is not using return value of irq_set_wake call.
> > Start using it.
> >
> > Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy")
> > Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
>
> Is this something that's causing regressions so I should apply it for
> fixes, or is it fine to keep this with the rest of the series for v5.9?
I would let Maulik comment more, but as far as I can tell the function
has been ignoring the return value of irq_set_irq_wake() for much
longer. Presumably one could logically say:
Fixes: 6aced33f4974 ("pinctrl: msm: drop wake_irqs bitmap")
...though when you get past the commit that Maulik tagged you need a
backport rather than a straight cherry-pick.
That would make me believe that there is no real hurry to land the fix here.
-Doug
^ permalink raw reply
* [PATCH v2 2/2] pinctrl: qcom: Add msm8226 pinctrl driver.
From: Bartosz Dudziak @ 2020-07-16 20:55 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Bartosz Dudziak, Andy Gross, Linus Walleij, Rob Herring,
linux-arm-msm, linux-gpio, devicetree, linux-kernel
In-Reply-To: <20200716205530.22910-1-bartosz.dudziak@snejp.pl>
Add initial Qualcomm msm8226 pinctrl driver to support pin configuration
with pinctrl framework for msm8226 SoC.
- Initial formatting and style was taken from the msm8x74 pinctrl driver
added by Björn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
---
drivers/pinctrl/qcom/Kconfig | 9 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-msm8226.c | 631 +++++++++++++++++++++++++
3 files changed, 641 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8226.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index ff1ee159dc..97ddc535fc 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -60,6 +60,15 @@ config PINCTRL_IPQ6018
Qualcomm Technologies Inc. IPQ6018 platform. Select this for
IPQ6018.
+config PINCTRL_MSM8226
+ tristate "Qualcomm 8226 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc MSM8226 platform.
+
config PINCTRL_MSM8660
tristate "Qualcomm 8660 pin controller driver"
depends on GPIOLIB && OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 061ec9fb65..9e3d9c91a4 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o
+obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o
obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c
new file mode 100644
index 0000000000..82010703c3
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c
@@ -0,0 +1,631 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+static const struct pinctrl_pin_desc msm8226_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+ PINCTRL_PIN(70, "GPIO_70"),
+ PINCTRL_PIN(71, "GPIO_71"),
+ PINCTRL_PIN(72, "GPIO_72"),
+ PINCTRL_PIN(73, "GPIO_73"),
+ PINCTRL_PIN(74, "GPIO_74"),
+ PINCTRL_PIN(75, "GPIO_75"),
+ PINCTRL_PIN(76, "GPIO_76"),
+ PINCTRL_PIN(77, "GPIO_77"),
+ PINCTRL_PIN(78, "GPIO_78"),
+ PINCTRL_PIN(79, "GPIO_79"),
+ PINCTRL_PIN(80, "GPIO_80"),
+ PINCTRL_PIN(81, "GPIO_81"),
+ PINCTRL_PIN(82, "GPIO_82"),
+ PINCTRL_PIN(83, "GPIO_83"),
+ PINCTRL_PIN(84, "GPIO_84"),
+ PINCTRL_PIN(85, "GPIO_85"),
+ PINCTRL_PIN(86, "GPIO_86"),
+ PINCTRL_PIN(87, "GPIO_87"),
+ PINCTRL_PIN(88, "GPIO_88"),
+ PINCTRL_PIN(89, "GPIO_89"),
+ PINCTRL_PIN(90, "GPIO_90"),
+ PINCTRL_PIN(91, "GPIO_91"),
+ PINCTRL_PIN(92, "GPIO_92"),
+ PINCTRL_PIN(93, "GPIO_93"),
+ PINCTRL_PIN(94, "GPIO_94"),
+ PINCTRL_PIN(95, "GPIO_95"),
+ PINCTRL_PIN(96, "GPIO_96"),
+ PINCTRL_PIN(97, "GPIO_97"),
+ PINCTRL_PIN(98, "GPIO_98"),
+ PINCTRL_PIN(99, "GPIO_99"),
+ PINCTRL_PIN(100, "GPIO_100"),
+ PINCTRL_PIN(101, "GPIO_101"),
+ PINCTRL_PIN(102, "GPIO_102"),
+ PINCTRL_PIN(103, "GPIO_103"),
+ PINCTRL_PIN(104, "GPIO_104"),
+ PINCTRL_PIN(105, "GPIO_105"),
+ PINCTRL_PIN(106, "GPIO_106"),
+ PINCTRL_PIN(107, "GPIO_107"),
+ PINCTRL_PIN(108, "GPIO_108"),
+ PINCTRL_PIN(109, "GPIO_109"),
+ PINCTRL_PIN(110, "GPIO_110"),
+ PINCTRL_PIN(111, "GPIO_111"),
+ PINCTRL_PIN(112, "GPIO_112"),
+ PINCTRL_PIN(113, "GPIO_113"),
+ PINCTRL_PIN(114, "GPIO_114"),
+ PINCTRL_PIN(115, "GPIO_115"),
+ PINCTRL_PIN(116, "GPIO_116"),
+
+ PINCTRL_PIN(117, "SDC1_CLK"),
+ PINCTRL_PIN(118, "SDC1_CMD"),
+ PINCTRL_PIN(119, "SDC1_DATA"),
+ PINCTRL_PIN(120, "SDC2_CLK"),
+ PINCTRL_PIN(121, "SDC2_CMD"),
+ PINCTRL_PIN(122, "SDC2_DATA"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+DECLARE_MSM_GPIO_PINS(65);
+DECLARE_MSM_GPIO_PINS(66);
+DECLARE_MSM_GPIO_PINS(67);
+DECLARE_MSM_GPIO_PINS(68);
+DECLARE_MSM_GPIO_PINS(69);
+DECLARE_MSM_GPIO_PINS(70);
+DECLARE_MSM_GPIO_PINS(71);
+DECLARE_MSM_GPIO_PINS(72);
+DECLARE_MSM_GPIO_PINS(73);
+DECLARE_MSM_GPIO_PINS(74);
+DECLARE_MSM_GPIO_PINS(75);
+DECLARE_MSM_GPIO_PINS(76);
+DECLARE_MSM_GPIO_PINS(77);
+DECLARE_MSM_GPIO_PINS(78);
+DECLARE_MSM_GPIO_PINS(79);
+DECLARE_MSM_GPIO_PINS(80);
+DECLARE_MSM_GPIO_PINS(81);
+DECLARE_MSM_GPIO_PINS(82);
+DECLARE_MSM_GPIO_PINS(83);
+DECLARE_MSM_GPIO_PINS(84);
+DECLARE_MSM_GPIO_PINS(85);
+DECLARE_MSM_GPIO_PINS(86);
+DECLARE_MSM_GPIO_PINS(87);
+DECLARE_MSM_GPIO_PINS(88);
+DECLARE_MSM_GPIO_PINS(89);
+DECLARE_MSM_GPIO_PINS(90);
+DECLARE_MSM_GPIO_PINS(91);
+DECLARE_MSM_GPIO_PINS(92);
+DECLARE_MSM_GPIO_PINS(93);
+DECLARE_MSM_GPIO_PINS(94);
+DECLARE_MSM_GPIO_PINS(95);
+DECLARE_MSM_GPIO_PINS(96);
+DECLARE_MSM_GPIO_PINS(97);
+DECLARE_MSM_GPIO_PINS(98);
+DECLARE_MSM_GPIO_PINS(99);
+DECLARE_MSM_GPIO_PINS(100);
+DECLARE_MSM_GPIO_PINS(101);
+DECLARE_MSM_GPIO_PINS(102);
+DECLARE_MSM_GPIO_PINS(103);
+DECLARE_MSM_GPIO_PINS(104);
+DECLARE_MSM_GPIO_PINS(105);
+DECLARE_MSM_GPIO_PINS(106);
+DECLARE_MSM_GPIO_PINS(107);
+DECLARE_MSM_GPIO_PINS(108);
+DECLARE_MSM_GPIO_PINS(109);
+DECLARE_MSM_GPIO_PINS(110);
+DECLARE_MSM_GPIO_PINS(111);
+DECLARE_MSM_GPIO_PINS(112);
+DECLARE_MSM_GPIO_PINS(113);
+DECLARE_MSM_GPIO_PINS(114);
+DECLARE_MSM_GPIO_PINS(115);
+DECLARE_MSM_GPIO_PINS(116);
+
+static const unsigned int sdc1_clk_pins[] = { 117 };
+static const unsigned int sdc1_cmd_pins[] = { 118 };
+static const unsigned int sdc1_data_pins[] = { 119 };
+static const unsigned int sdc2_clk_pins[] = { 120 };
+static const unsigned int sdc2_cmd_pins[] = { 121 };
+static const unsigned int sdc2_data_pins[] = { 122 };
+
+#define FUNCTION(fname) \
+ [MSM_MUX_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ MSM_MUX_gpio, \
+ MSM_MUX_##f1, \
+ MSM_MUX_##f2, \
+ MSM_MUX_##f3, \
+ MSM_MUX_##f4, \
+ MSM_MUX_##f5, \
+ MSM_MUX_##f6, \
+ MSM_MUX_##f7 \
+ }, \
+ .nfuncs = 8, \
+ .ctl_reg = 0x1000 + 0x10 * id, \
+ .io_reg = 0x1004 + 0x10 * id, \
+ .intr_cfg_reg = 0x1008 + 0x10 * id, \
+ .intr_status_reg = 0x100c + 0x10 * id, \
+ .intr_target_reg = 0x1008 + 0x10 * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 4, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_target_kpss_val = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
+/*
+ * TODO: Add the rest of the possible functions and fill out
+ * the pingroup table below.
+ */
+enum msm8226_functions {
+ MSM_MUX_gpio,
+ MSM_MUX_cci_i2c0,
+ MSM_MUX_blsp_i2c1,
+ MSM_MUX_blsp_i2c2,
+ MSM_MUX_blsp_i2c3,
+ MSM_MUX_blsp_i2c5,
+ MSM_MUX_blsp_spi1,
+ MSM_MUX_blsp_spi2,
+ MSM_MUX_blsp_spi3,
+ MSM_MUX_blsp_spi5,
+ MSM_MUX_blsp_uart1,
+ MSM_MUX_blsp_uart2,
+ MSM_MUX_blsp_uart3,
+ MSM_MUX_blsp_uart5,
+ MSM_MUX_blsp_uim1,
+ MSM_MUX_blsp_uim2,
+ MSM_MUX_blsp_uim3,
+ MSM_MUX_blsp_uim5,
+ MSM_MUX_cam_mclk0,
+ MSM_MUX_cam_mclk1,
+ MSM_MUX_wlan,
+ MSM_MUX_NA,
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
+ "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
+ "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
+ "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
+ "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
+};
+
+static const char * const blsp_uart1_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3"
+};
+
+static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" };
+static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" };
+static const char * const blsp_spi1_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3"
+};
+
+static const char * const blsp_uart2_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7"
+};
+
+static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" };
+static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" };
+static const char * const blsp_spi2_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7"
+};
+
+static const char * const blsp_uart3_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+
+static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" };
+static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" };
+static const char * const blsp_spi3_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11"
+};
+
+static const char * const blsp_uart5_groups[] = {
+ "gpio16", "gpio17", "gpio18", "gpio19"
+};
+
+static const char * const blsp_uim5_groups[] = { "gpio16", "gpio17" };
+static const char * const blsp_i2c5_groups[] = { "gpio18", "gpio19" };
+static const char * const blsp_spi5_groups[] = {
+ "gpio16", "gpio17", "gpio18", "gpio19"
+};
+
+static const char * const cci_i2c0_groups[] = { "gpio29", "gpio30" };
+
+static const char * const cam_mclk0_groups[] = { "gpio26" };
+static const char * const cam_mclk1_groups[] = { "gpio27" };
+
+static const char * const wlan_groups[] = {
+ "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"
+};
+
+static const struct msm_function msm8226_functions[] = {
+ FUNCTION(gpio),
+ FUNCTION(cci_i2c0),
+ FUNCTION(blsp_uim1),
+ FUNCTION(blsp_uim2),
+ FUNCTION(blsp_uim3),
+ FUNCTION(blsp_uim5),
+ FUNCTION(blsp_i2c1),
+ FUNCTION(blsp_i2c2),
+ FUNCTION(blsp_i2c3),
+ FUNCTION(blsp_i2c5),
+ FUNCTION(blsp_spi1),
+ FUNCTION(blsp_spi2),
+ FUNCTION(blsp_spi3),
+ FUNCTION(blsp_spi5),
+ FUNCTION(blsp_uart1),
+ FUNCTION(blsp_uart2),
+ FUNCTION(blsp_uart3),
+ FUNCTION(blsp_uart5),
+ FUNCTION(cam_mclk0),
+ FUNCTION(cam_mclk1),
+ FUNCTION(wlan),
+};
+
+static const struct msm_pingroup msm8226_groups[] = {
+ PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
+ PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
+ PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
+ PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
+ PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
+ PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
+ PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
+ PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
+ PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, NA, NA, NA, NA),
+ PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, NA, NA, NA, NA),
+ PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
+ PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
+ PINGROUP(12, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(13, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(14, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(15, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(16, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
+ PINGROUP(17, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
+ PINGROUP(18, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
+ PINGROUP(19, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
+ PINGROUP(20, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(21, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(22, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(23, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(24, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(25, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(26, cam_mclk0, NA, NA, NA, NA, NA, NA),
+ PINGROUP(27, cam_mclk1, NA, NA, NA, NA, NA, NA),
+ PINGROUP(28, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(29, cci_i2c0, NA, NA, NA, NA, NA, NA),
+ PINGROUP(30, cci_i2c0, NA, NA, NA, NA, NA, NA),
+ PINGROUP(31, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(32, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(33, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(34, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(35, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(36, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(37, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(38, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(39, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(40, wlan, NA, NA, NA, NA, NA, NA),
+ PINGROUP(41, wlan, NA, NA, NA, NA, NA, NA),
+ PINGROUP(42, wlan, NA, NA, NA, NA, NA, NA),
+ PINGROUP(43, wlan, NA, NA, NA, NA, NA, NA),
+ PINGROUP(44, wlan, NA, NA, NA, NA, NA, NA),
+ PINGROUP(45, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(46, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(47, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(48, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(49, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(50, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(51, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(52, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(53, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(54, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(55, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(56, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(57, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(58, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(59, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(60, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(61, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(62, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(63, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(64, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(65, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(66, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(67, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(68, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(69, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(70, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(71, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(72, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(73, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(74, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(75, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(76, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(77, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(78, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(79, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(80, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(81, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(82, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(83, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(84, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(85, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(86, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(87, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(88, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(89, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(90, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(91, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(92, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(93, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(94, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(95, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(96, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(97, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(98, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(99, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(100, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(101, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(102, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(103, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(104, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(105, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(106, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(107, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(108, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(109, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(110, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(111, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(112, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(113, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(114, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(115, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(116, NA, NA, NA, NA, NA, NA, NA),
+ SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6),
+ SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3),
+ SDC_PINGROUP(sdc1_data, 0x2044, 9, 0),
+ SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6),
+ SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3),
+ SDC_PINGROUP(sdc2_data, 0x2048, 9, 0),
+};
+
+#define NUM_GPIO_PINGROUPS 117
+
+static const struct msm_pinctrl_soc_data msm8226_pinctrl = {
+ .pins = msm8226_pins,
+ .npins = ARRAY_SIZE(msm8226_pins),
+ .functions = msm8226_functions,
+ .nfunctions = ARRAY_SIZE(msm8226_functions),
+ .groups = msm8226_groups,
+ .ngroups = ARRAY_SIZE(msm8226_groups),
+ .ngpios = NUM_GPIO_PINGROUPS,
+};
+
+static int msm8226_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &msm8226_pinctrl);
+}
+
+static const struct of_device_id msm8226_pinctrl_of_match[] = {
+ { .compatible = "qcom,msm8226-pinctrl", },
+ { },
+};
+
+static struct platform_driver msm8226_pinctrl_driver = {
+ .driver = {
+ .name = "msm8226-pinctrl",
+ .of_match_table = msm8226_pinctrl_of_match,
+ },
+ .probe = msm8226_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init msm8226_pinctrl_init(void)
+{
+ return platform_driver_register(&msm8226_pinctrl_driver);
+}
+arch_initcall(msm8226_pinctrl_init);
+
+static void __exit msm8226_pinctrl_exit(void)
+{
+ platform_driver_unregister(&msm8226_pinctrl_driver);
+}
+module_exit(msm8226_pinctrl_exit);
+
+MODULE_AUTHOR("Bartosz Dudziak <bartosz.dudziak@snejp.pl>");
+MODULE_DESCRIPTION("Qualcomm MSM8226 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, msm8226_pinctrl_of_match);
+
--
2.25.1
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: pinctrl: qcom: Add msm8226 pinctrl bindings
From: Bartosz Dudziak @ 2020-07-16 20:55 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Bartosz Dudziak, Andy Gross, Linus Walleij, Rob Herring,
linux-arm-msm, linux-gpio, devicetree, linux-kernel
In-Reply-To: <20200716205530.22910-1-bartosz.dudziak@snejp.pl>
Add device tree binding Documentation details for Qualcomm msm8226
pinctrl driver.
- Bindings documentation was based on qcom,ipq6018-pinctrl.yaml added by
Sricharan R <sricharan@codeaurora.org> and then modified for msm8226
content
Signed-off-by: Bartosz Dudziak <bartosz.dudziak@snejp.pl>
---
.../pinctrl/qcom,msm8226-pinctrl.yaml | 132 ++++++++++++++++++
1 file changed, 132 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
new file mode 100644
index 0000000000..1f0f5757f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. MSM8226 TLMM block
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer block found in the
+ MSM8226 platform.
+
+properties:
+ compatible:
+ const: qcom,msm8226-pinctrl
+
+ reg:
+ description: Specifies the base address and size of the TLMM register space
+ maxItems: 1
+
+ interrupts:
+ description: Specifies the TLMM summary IRQ
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ description: Specifies the PIN numbers and Flags, as defined in
+ include/dt-bindings/interrupt-controller/irq.h
+ const: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ description: Specifying the pin number and flags, as defined in
+ include/dt-bindings/gpio/gpio.h
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ gpio-reserved-ranges:
+ maxItems: 1
+
+#PIN CONFIGURATION NODES
+patternProperties:
+ '-pins$':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: "/schemas/pinctrl/pincfg-node.yaml"
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$"
+ - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
+ minItems: 1
+ maxItems: 36
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins. Functions are only valid for gpio pins.
+ enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
+ blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c5, blsp_spi1,
+ blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
+ blsp_uart3, blsp_uart5, cam_mclk0, cam_mclk1, wlan ]
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ default: 2
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ bias-pull-down: true
+
+ bias-pull-up: true
+
+ bias-disable: true
+
+ output-high: true
+
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ msmgpio: pinctrl@fd510000 {
+ compatible = "qcom,msm8226-pinctrl";
+ reg = <0xfd510000 0x4000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&msmgpio 0 0 117>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+
+ serial-pins {
+ pins = "gpio8", "gpio9";
+ function = "blsp_uart3";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
--
2.25.1
^ permalink raw reply related
* [PATCH v2 0/2] Qualcomm MSM8226 TLMM binding and driver
From: Bartosz Dudziak @ 2020-07-16 20:55 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Bartosz Dudziak, Andy Gross, Linus Walleij, Rob Herring,
linux-arm-msm, linux-gpio, devicetree, linux-kernel
Binding and driver for the Qualcomm MSM8226 TLMM pinctrl block
Changes in v2:
- Changed node name pattern to '-pins$' in qcom,msm8226-pinctrl.yaml binding
- Expanded example in yaml binding with a 'serial-pins' node sample
Bartosz Dudziak (2):
dt-bindings: pinctrl: qcom: Add msm8226 pinctrl bindings
pinctrl: qcom: Add msm8226 pinctrl driver.
.../pinctrl/qcom,msm8226-pinctrl.yaml | 132 ++++
drivers/pinctrl/qcom/Kconfig | 9 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-msm8226.c | 631 ++++++++++++++++++
4 files changed, 773 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8226.c
--
2.25.1
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox