From: sashiko-bot@kernel.org
To: "Xilin Wu" <sophon@radxa.com>
Cc: linux-pci@vger.kernel.org, dri-devel@lists.freedesktop.org,
devicetree@vger.kernel.org, linux-gpio@vger.kernel.org,
robh@kernel.org, conor+dt@kernel.org
Subject: Re: [PATCH v3 3/4] arm64: dts: qcom: sc8280xp: add Radxa Dragon Q8B
Date: Thu, 29 Oct 2026 09:58:23 +0000 [thread overview]
Message-ID: <sashiko-outbox-189075@kernel.org> (raw)
In-Reply-To: <20261029-q8b-dts-v3-3-655696dfec45@radxa.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] arm64: dts: qcom: missing pinctrl properties on uart2 in dragon-q8b
--
commit 806aef47629e5a5fdf23480747e829d1b21764d6
Author: Xilin Wu <sophon@radxa.com>
arm64: dts: qcom: sc8280xp: add Radxa Dragon Q8B
This commit adds initial device tree support for the Radxa Dragon Q8B
single-board computer based on the Qualcomm Snapdragon 8cx Gen 3 SC8280XP
platform.
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-radxa-dragon-q8b.dts b/arch/arm64/boot/dts/qcom/sc8280xp-radxa-dragon-q8b.dts
> new file mode 100644
> index 0000000000000..fd1e29ce83b27
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-radxa-dragon-q8b.dts
> @@ -0,0 +1,2049 @@
[ ... ]
> +/* E-key Bluetooth */
> +&uart2 {
> + uart-has-rtscts;
> + status = "okay";
> +
> + port {
> + uart2_ep: endpoint {
> + remote-endpoint = <&wlan_uart_ep>;
> + };
> + };
> +};
[Severity: Medium]
Should the &uart2 node in arch/arm64/boot/dts/qcom/sc8280xp-radxa-dragon-q8b.dts
include pinctrl-0 and pinctrl-names properties?
In arch/arm64/boot/dts/qcom/sc8280xp.dtsi, the base uart2: serial@988000 node
does not define default pinctrl properties:
uart2: serial@988000 {
compatible = "qcom,geni-uart";
reg = <0 0x00988000 0 0x4000>;
...
status = "disabled";
};
Instead, the pin configuration state qup_uart2_default (for gpio121 CTS,
gpio122 RTS, gpio123 TX, and gpio124 RX) is defined separately under &tlmm in
sc8280xp.dtsi for board device trees to reference.
When qcom_geni_serial probes uart2 for the M.2 E-key Bluetooth interface and
activates resources via pinctrl_bind_pins() and geni_se_resources_on() ->
pinctrl_pm_select_default_state(), the TLMM pins for UART2 will not be muxed
to the qup2 function or configured by Linux without:
pinctrl-0 = <&qup_uart2_default>;
pinctrl-names = "default";
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261029-q8b-dts-v3-0-655696dfec45@radxa.com?part=3
next prev parent reply other threads:[~2026-10-29 9:58 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-29 9:44 [PATCH v3 0/4] arm64: dts: qcom: Add support for Radxa Dragon Q8B Xilin Wu
2026-10-29 9:44 ` [PATCH v3 1/4] arm64: dts: qcom: sc8280xp: enable PCIe ECAM and 64-bit memory Xilin Wu
2026-10-29 9:58 ` sashiko-bot
2026-10-29 9:44 ` [PATCH v3 2/4] dt-bindings: arm: qcom: document Radxa Dragon Q8B Xilin Wu
2026-10-29 9:44 ` [PATCH v3 3/4] arm64: dts: qcom: sc8280xp: add " Xilin Wu
2026-10-29 9:58 ` sashiko-bot [this message]
2026-10-29 9:44 ` [PATCH v3 4/4] firmware: qcom: scm: Allow QSEECOM for " Xilin Wu
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