From: sashiko-bot@kernel.org
To: "Bartosz Golaszewski" <bartosz.golaszewski@oss.qualcomm.com>
Cc: linux-gpio@vger.kernel.org
Subject: Re: [PATCH] pinctrl: qcom: check the return value of qcom_scm_io_readl()
Date: Thu, 05 Nov 2026 16:28:00 +0000 [thread overview]
Message-ID: <sashiko-outbox-199495@kernel.org> (raw)
In-Reply-To: <20261105-pinctrl-qcom-scm-fail-v1-1-a23f96c6b313@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] pinctrl: qcom: premature dual_edge_irqs update in msm_gpio_irq_set_type()
--
commit 95e665aa134824797beb0596c04a8bbf7fde94f2
Author: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
pinctrl: qcom: check the return value of qcom_scm_io_readl()
This commit checks the return value of qcom_scm_io_readl() in
msm_gpio_irq_set_type() and bails out on failure to avoid writing an
uninitialized value to hardware registers.
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
> index 32aa7b919e24a..0053d1d927dc1 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
> @@ -1117,7 +1117,12 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
> u32 addr = pctrl->phys_base[0] + reg;
> int ret;
>
> - qcom_scm_io_readl(addr, &val);
> + ret = qcom_scm_io_readl(addr, &val);
> + if (ret) {
> + raw_spin_unlock_irqrestore(&pctrl->lock, flags);
> + return ret;
> + }
[Severity: Medium]
Just above this block in msm_gpio_irq_set_type(), pctrl->dual_edge_irqs is
updated for the new trigger type before qcom_scm_io_readl() is called:
if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
set_bit(d->hwirq, pctrl->dual_edge_irqs);
else
clear_bit(d->hwirq, pctrl->dual_edge_irqs);
On platforms like IPQ8064 where pctrl->intr_target_use_scm is set and
g->intr_detection_width is 1, if qcom_scm_io_readl() fails and returns early
here, msm_writel_intr_cfg() and msm_gpio_update_dual_edge_pos() are skipped
while pctrl->dual_edge_irqs retains the updated bit for the failed transition.
When __irq_set_trigger() then restores the IRQ state on error, wouldn't
pctrl->dual_edge_irqs be out of sync with the hardware interrupt configuration
inspected by msm_gpio_irq_ack()? Should the pctrl->dual_edge_irqs update be
moved after the qcom_scm_io_readl() check succeeds?
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261105-pinctrl-qcom-scm-fail-v1-1-a23f96c6b313@oss.qualcomm.com?part=1
prev parent reply other threads:[~2026-11-05 16:28 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-05 16:18 [PATCH] pinctrl: qcom: check the return value of qcom_scm_io_readl() Bartosz Golaszewski
2026-11-05 16:28 ` sashiko-bot [this message]
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